2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
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14 * substantially similar to the "NO WARRANTY" disclaimer below
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16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
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19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
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37 * POSSIBILITY OF SUCH DAMAGES.
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
45 static struct scsi_transport_template *pm8001_stt;
48 * chip info structure to identify chip key functionality as
49 * encryption available/not, no of ports, hw specific function ref
51 static const struct pm8001_chip_info pm8001_chips[] = {
52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
60 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
61 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
62 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
68 struct workqueue_struct *pm8001_wq;
71 * The main structure which LLDD must register for scsi core.
73 static struct scsi_host_template pm8001_sht = {
74 .module = THIS_MODULE,
76 .queuecommand = sas_queuecommand,
77 .target_alloc = sas_target_alloc,
78 .slave_configure = sas_slave_configure,
79 .scan_finished = pm8001_scan_finished,
80 .scan_start = pm8001_scan_start,
81 .change_queue_depth = sas_change_queue_depth,
82 .bios_param = sas_bios_param,
85 .sg_tablesize = SG_ALL,
86 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
87 .use_clustering = ENABLE_CLUSTERING,
88 .eh_device_reset_handler = sas_eh_device_reset_handler,
89 .eh_target_reset_handler = sas_eh_target_reset_handler,
90 .slave_alloc = sas_slave_alloc,
91 .target_destroy = sas_target_destroy,
93 .shost_attrs = pm8001_host_attrs,
94 .track_queue_depth = 1,
98 * Sas layer call this function to execute specific task.
100 static struct sas_domain_function_template pm8001_transport_ops = {
101 .lldd_dev_found = pm8001_dev_found,
102 .lldd_dev_gone = pm8001_dev_gone,
104 .lldd_execute_task = pm8001_queue_command,
105 .lldd_control_phy = pm8001_phy_control,
107 .lldd_abort_task = pm8001_abort_task,
108 .lldd_abort_task_set = pm8001_abort_task_set,
109 .lldd_clear_aca = pm8001_clear_aca,
110 .lldd_clear_task_set = pm8001_clear_task_set,
111 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
112 .lldd_lu_reset = pm8001_lu_reset,
113 .lldd_query_task = pm8001_query_task,
117 *pm8001_phy_init - initiate our adapter phys
118 *@pm8001_ha: our hba structure.
121 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
123 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
124 struct asd_sas_phy *sas_phy = &phy->sas_phy;
126 phy->pm8001_ha = pm8001_ha;
127 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
128 sas_phy->class = SAS;
129 sas_phy->iproto = SAS_PROTOCOL_ALL;
131 sas_phy->type = PHY_TYPE_PHYSICAL;
132 sas_phy->role = PHY_ROLE_INITIATOR;
133 sas_phy->oob_mode = OOB_NOT_CONNECTED;
134 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
135 sas_phy->id = phy_id;
136 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
137 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
138 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
139 sas_phy->lldd_phy = phy;
143 *pm8001_free - free hba
144 *@pm8001_ha: our hba structure.
147 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
154 for (i = 0; i < USI_MAX_MEMCNT; i++) {
155 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
156 pci_free_consistent(pm8001_ha->pdev,
157 (pm8001_ha->memoryMap.region[i].total_len +
158 pm8001_ha->memoryMap.region[i].alignment),
159 pm8001_ha->memoryMap.region[i].virt_ptr,
160 pm8001_ha->memoryMap.region[i].phys_addr);
163 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
164 flush_workqueue(pm8001_wq);
165 kfree(pm8001_ha->tags);
169 #ifdef PM8001_USE_TASKLET
172 * tasklet for 64 msi-x interrupt handler
173 * @opaque: the passed general host adapter struct
174 * Note: pm8001_tasklet is common for pm8001 & pm80xx
176 static void pm8001_tasklet(unsigned long opaque)
178 struct pm8001_hba_info *pm8001_ha;
179 struct isr_param *irq_vector;
181 irq_vector = (struct isr_param *)opaque;
182 pm8001_ha = irq_vector->drv_inst;
183 if (unlikely(!pm8001_ha))
185 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
190 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
191 * It obtains the vector number and calls the equivalent bottom
192 * half or services directly.
193 * @opaque: the passed outbound queue/vector. Host structure is
194 * retrieved from the same.
196 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
198 struct isr_param *irq_vector;
199 struct pm8001_hba_info *pm8001_ha;
200 irqreturn_t ret = IRQ_HANDLED;
201 irq_vector = (struct isr_param *)opaque;
202 pm8001_ha = irq_vector->drv_inst;
204 if (unlikely(!pm8001_ha))
206 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
208 #ifdef PM8001_USE_TASKLET
209 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
211 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
217 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
218 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
221 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
223 struct pm8001_hba_info *pm8001_ha;
224 irqreturn_t ret = IRQ_HANDLED;
225 struct sas_ha_struct *sha = dev_id;
226 pm8001_ha = sha->lldd_ha;
227 if (unlikely(!pm8001_ha))
229 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
232 #ifdef PM8001_USE_TASKLET
233 tasklet_schedule(&pm8001_ha->tasklet[0]);
235 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
241 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
242 * @pm8001_ha:our hba structure.
245 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
246 const struct pci_device_id *ent)
249 spin_lock_init(&pm8001_ha->lock);
250 spin_lock_init(&pm8001_ha->bitmap_lock);
251 PM8001_INIT_DBG(pm8001_ha,
252 pm8001_printk("pm8001_alloc: PHY:%x\n",
253 pm8001_ha->chip->n_phy));
254 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
255 pm8001_phy_init(pm8001_ha, i);
256 pm8001_ha->port[i].wide_port_phymap = 0;
257 pm8001_ha->port[i].port_attached = 0;
258 pm8001_ha->port[i].port_state = 0;
259 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
262 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
263 if (!pm8001_ha->tags)
265 /* MPI Memory region 1 for AAP Event Log for fw */
266 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
267 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
268 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
269 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
271 /* MPI Memory region 2 for IOP Event Log for fw */
272 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
273 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
274 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
275 pm8001_ha->memoryMap.region[IOP].alignment = 32;
277 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
278 /* MPI Memory region 3 for consumer Index of inbound queues */
279 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
280 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
281 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
282 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
284 if ((ent->driver_data) != chip_8001) {
285 /* MPI Memory region 5 inbound queues */
286 pm8001_ha->memoryMap.region[IB+i].num_elements =
288 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
289 pm8001_ha->memoryMap.region[IB+i].total_len =
290 PM8001_MPI_QUEUE * 128;
291 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
293 pm8001_ha->memoryMap.region[IB+i].num_elements =
295 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
296 pm8001_ha->memoryMap.region[IB+i].total_len =
297 PM8001_MPI_QUEUE * 64;
298 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
302 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303 /* MPI Memory region 4 for producer Index of outbound queues */
304 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
305 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
306 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
307 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
309 if (ent->driver_data != chip_8001) {
310 /* MPI Memory region 6 Outbound queues */
311 pm8001_ha->memoryMap.region[OB+i].num_elements =
313 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
314 pm8001_ha->memoryMap.region[OB+i].total_len =
315 PM8001_MPI_QUEUE * 128;
316 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
318 /* MPI Memory region 6 Outbound queues */
319 pm8001_ha->memoryMap.region[OB+i].num_elements =
321 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
322 pm8001_ha->memoryMap.region[OB+i].total_len =
323 PM8001_MPI_QUEUE * 64;
324 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
328 /* Memory region write DMA*/
329 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
330 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
331 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
332 /* Memory region for devices*/
333 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
334 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
335 sizeof(struct pm8001_device);
336 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
337 sizeof(struct pm8001_device);
339 /* Memory region for ccb_info*/
340 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
341 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
342 sizeof(struct pm8001_ccb_info);
343 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
344 sizeof(struct pm8001_ccb_info);
346 /* Memory region for fw flash */
347 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
349 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
350 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
351 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
352 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
353 for (i = 0; i < USI_MAX_MEMCNT; i++) {
354 if (pm8001_mem_alloc(pm8001_ha->pdev,
355 &pm8001_ha->memoryMap.region[i].virt_ptr,
356 &pm8001_ha->memoryMap.region[i].phys_addr,
357 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
358 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
359 pm8001_ha->memoryMap.region[i].total_len,
360 pm8001_ha->memoryMap.region[i].alignment) != 0) {
361 PM8001_FAIL_DBG(pm8001_ha,
362 pm8001_printk("Mem%d alloc failed\n",
368 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
369 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
370 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
371 pm8001_ha->devices[i].id = i;
372 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
373 pm8001_ha->devices[i].running_req = 0;
375 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
376 for (i = 0; i < PM8001_MAX_CCB; i++) {
377 pm8001_ha->ccb_info[i].ccb_dma_handle =
378 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
379 i * sizeof(struct pm8001_ccb_info);
380 pm8001_ha->ccb_info[i].task = NULL;
381 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
382 pm8001_ha->ccb_info[i].device = NULL;
383 ++pm8001_ha->tags_num;
385 pm8001_ha->flags = PM8001F_INIT_TIME;
386 /* Initialize tags */
387 pm8001_tag_init(pm8001_ha);
394 * pm8001_ioremap - remap the pci high physical address to kernal virtual
395 * address so that we can access them.
396 * @pm8001_ha:our hba structure.
398 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
402 struct pci_dev *pdev;
404 pdev = pm8001_ha->pdev;
405 /* map pci mem (PMC pci base 0-3)*/
406 for (bar = 0; bar < 6; bar++) {
408 ** logical BARs for SPC:
409 ** bar 0 and 1 - logical BAR0
410 ** bar 2 and 3 - logical BAR1
411 ** bar4 - logical BAR2
412 ** bar5 - logical BAR3
413 ** Skip the appropriate assignments:
415 if ((bar == 1) || (bar == 3))
417 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
418 pm8001_ha->io_mem[logicalBar].membase =
419 pci_resource_start(pdev, bar);
420 pm8001_ha->io_mem[logicalBar].memsize =
421 pci_resource_len(pdev, bar);
422 pm8001_ha->io_mem[logicalBar].memvirtaddr =
423 ioremap(pm8001_ha->io_mem[logicalBar].membase,
424 pm8001_ha->io_mem[logicalBar].memsize);
425 PM8001_INIT_DBG(pm8001_ha,
426 pm8001_printk("PCI: bar %d, logicalBar %d ",
428 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
429 "base addr %llx virt_addr=%llx len=%d\n",
430 (u64)pm8001_ha->io_mem[logicalBar].membase,
432 pm8001_ha->io_mem[logicalBar].memvirtaddr,
433 pm8001_ha->io_mem[logicalBar].memsize));
435 pm8001_ha->io_mem[logicalBar].membase = 0;
436 pm8001_ha->io_mem[logicalBar].memsize = 0;
437 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
445 * pm8001_pci_alloc - initialize our ha card structure
448 * @shost: scsi host struct which has been initialized before.
450 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
451 const struct pci_device_id *ent,
452 struct Scsi_Host *shost)
455 struct pm8001_hba_info *pm8001_ha;
456 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
459 pm8001_ha = sha->lldd_ha;
463 pm8001_ha->pdev = pdev;
464 pm8001_ha->dev = &pdev->dev;
465 pm8001_ha->chip_id = ent->driver_data;
466 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
467 pm8001_ha->irq = pdev->irq;
468 pm8001_ha->sas = sha;
469 pm8001_ha->shost = shost;
470 pm8001_ha->id = pm8001_id++;
471 pm8001_ha->logging_level = 0x01;
472 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
473 /* IOMB size is 128 for 8088/89 controllers */
474 if (pm8001_ha->chip_id != chip_8001)
475 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
477 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
479 #ifdef PM8001_USE_TASKLET
480 /* Tasklet for non msi-x interrupt handler */
481 if ((!pdev->msix_cap || !pci_msi_enabled())
482 || (pm8001_ha->chip_id == chip_8001))
483 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
484 (unsigned long)&(pm8001_ha->irq_vector[0]));
486 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
487 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
488 (unsigned long)&(pm8001_ha->irq_vector[j]));
490 pm8001_ioremap(pm8001_ha);
491 if (!pm8001_alloc(pm8001_ha, ent))
493 pm8001_free(pm8001_ha);
498 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
501 static int pci_go_44(struct pci_dev *pdev)
505 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
506 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
508 rc = pci_set_consistent_dma_mask(pdev,
511 dev_printk(KERN_ERR, &pdev->dev,
512 "44-bit DMA enable failed\n");
517 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
519 dev_printk(KERN_ERR, &pdev->dev,
520 "32-bit DMA enable failed\n");
523 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
525 dev_printk(KERN_ERR, &pdev->dev,
526 "32-bit consistent DMA enable failed\n");
534 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
535 * @shost: scsi host which has been allocated outside.
536 * @chip_info: our ha struct.
538 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
539 const struct pm8001_chip_info *chip_info)
542 struct asd_sas_phy **arr_phy;
543 struct asd_sas_port **arr_port;
544 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
546 phy_nr = chip_info->n_phy;
548 memset(sha, 0x00, sizeof(*sha));
549 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
552 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
556 sha->sas_phy = arr_phy;
557 sha->sas_port = arr_port;
558 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
562 shost->transportt = pm8001_stt;
563 shost->max_id = PM8001_MAX_DEVICES;
565 shost->max_channel = 0;
566 shost->unique_id = pm8001_id;
567 shost->max_cmd_len = 16;
568 shost->can_queue = PM8001_CAN_QUEUE;
569 shost->cmd_per_lun = 32;
580 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
581 * @shost: scsi host which has been allocated outside
582 * @chip_info: our ha struct.
584 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
585 const struct pm8001_chip_info *chip_info)
588 struct pm8001_hba_info *pm8001_ha;
589 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591 pm8001_ha = sha->lldd_ha;
592 for (i = 0; i < chip_info->n_phy; i++) {
593 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
594 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
595 sha->sas_phy[i]->sas_addr =
596 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
598 sha->sas_ha_name = DRV_NAME;
599 sha->dev = pm8001_ha->dev;
600 sha->strict_wide_ports = 1;
601 sha->lldd_module = THIS_MODULE;
602 sha->sas_addr = &pm8001_ha->sas_addr[0];
603 sha->num_phys = chip_info->n_phy;
604 sha->core.shost = shost;
608 * pm8001_init_sas_add - initialize sas address
609 * @chip_info: our ha struct.
611 * Currently we just set the fixed SAS address to our HBA,for manufacture,
612 * it should read from the EEPROM
614 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
618 #ifdef PM8001_READ_VPD
619 /* For new SPC controllers WWN is stored in flash vpd
620 * For SPC/SPCve controllers WWN is stored in EEPROM
621 * For Older SPC WWN is stored in NVMD
623 DECLARE_COMPLETION_ONSTACK(completion);
624 struct pm8001_ioctl_payload payload;
628 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
629 pm8001_ha->nvmd_completion = &completion;
631 if (pm8001_ha->chip_id == chip_8001) {
632 if (deviceid == 0x8081 || deviceid == 0x0042) {
633 payload.minor_function = 4;
634 payload.length = 4096;
636 payload.minor_function = 0;
637 payload.length = 128;
639 } else if ((pm8001_ha->chip_id == chip_8070 ||
640 pm8001_ha->chip_id == chip_8072) &&
641 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
642 payload.minor_function = 4;
643 payload.length = 4096;
645 payload.minor_function = 1;
646 payload.length = 4096;
649 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
650 if (!payload.func_specific) {
651 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
654 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
656 kfree(payload.func_specific);
657 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
660 wait_for_completion(&completion);
662 for (i = 0, j = 0; i <= 7; i++, j++) {
663 if (pm8001_ha->chip_id == chip_8001) {
664 if (deviceid == 0x8081)
665 pm8001_ha->sas_addr[j] =
666 payload.func_specific[0x704 + i];
667 else if (deviceid == 0x0042)
668 pm8001_ha->sas_addr[j] =
669 payload.func_specific[0x010 + i];
670 } else if ((pm8001_ha->chip_id == chip_8070 ||
671 pm8001_ha->chip_id == chip_8072) &&
672 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
673 pm8001_ha->sas_addr[j] =
674 payload.func_specific[0x010 + i];
676 pm8001_ha->sas_addr[j] =
677 payload.func_specific[0x804 + i];
679 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
680 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
681 if (i && ((i % 4) == 0))
682 sas_add[7] = sas_add[7] + 4;
683 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
684 sas_add, SAS_ADDR_SIZE);
685 PM8001_INIT_DBG(pm8001_ha,
686 pm8001_printk("phy %d sas_addr = %016llx\n", i,
687 pm8001_ha->phy[i].dev_sas_addr));
689 kfree(payload.func_specific);
691 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
692 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
693 pm8001_ha->phy[i].dev_sas_addr =
695 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
697 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
703 * pm8001_get_phy_settings_info : Read phy setting values.
704 * @pm8001_ha : our hba.
706 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
709 #ifdef PM8001_READ_VPD
710 /*OPTION ROM FLASH read for the SPC cards */
711 DECLARE_COMPLETION_ONSTACK(completion);
712 struct pm8001_ioctl_payload payload;
715 pm8001_ha->nvmd_completion = &completion;
716 /* SAS ADDRESS read from flash / EEPROM */
717 payload.minor_function = 6;
719 payload.length = 4096;
720 payload.func_specific = kzalloc(4096, GFP_KERNEL);
721 if (!payload.func_specific)
723 /* Read phy setting values from flash */
724 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
726 kfree(payload.func_specific);
727 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
730 wait_for_completion(&completion);
731 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
732 kfree(payload.func_specific);
737 struct pm8001_mpi3_phy_pg_trx_config {
750 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
751 * @pm8001_ha : our adapter
752 * @phycfg : PHY config page to populate
755 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
756 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
758 phycfg->LaneLosCfg = 0x00000132;
759 phycfg->LanePgaCfg1 = 0x00203949;
760 phycfg->LanePisoCfg1 = 0x000000FF;
761 phycfg->LanePisoCfg2 = 0xFF000001;
762 phycfg->LanePisoCfg3 = 0xE7011300;
763 phycfg->LanePisoCfg4 = 0x631C40C0;
764 phycfg->LanePisoCfg5 = 0xF8102036;
765 phycfg->LanePisoCfg6 = 0xF74A1000;
766 phycfg->LaneBctCtrl = 0x00FB33F8;
770 * pm8001_get_external_phy_settings : Retrieves the external PHY settings
771 * @pm8001_ha : our adapter
772 * @phycfg : PHY config page to populate
775 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
776 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
778 phycfg->LaneLosCfg = 0x00000132;
779 phycfg->LanePgaCfg1 = 0x00203949;
780 phycfg->LanePisoCfg1 = 0x000000FF;
781 phycfg->LanePisoCfg2 = 0xFF000001;
782 phycfg->LanePisoCfg3 = 0xE7011300;
783 phycfg->LanePisoCfg4 = 0x63349140;
784 phycfg->LanePisoCfg5 = 0xF8102036;
785 phycfg->LanePisoCfg6 = 0xF80D9300;
786 phycfg->LaneBctCtrl = 0x00FB33F8;
790 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
791 * @pm8001_ha : our adapter
792 * @phymask : The PHY mask
795 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
797 switch (pm8001_ha->pdev->subsystem_device) {
798 case 0x0070: /* H1280 - 8 external 0 internal */
799 case 0x0072: /* H12F0 - 16 external 0 internal */
803 case 0x0071: /* H1208 - 0 external 8 internal */
804 case 0x0073: /* H120F - 0 external 16 internal */
808 case 0x0080: /* H1244 - 4 external 4 internal */
812 case 0x0081: /* H1248 - 4 external 8 internal */
816 case 0x0082: /* H1288 - 8 external 8 internal */
821 PM8001_INIT_DBG(pm8001_ha,
822 pm8001_printk("Unknown subsystem device=0x%.04x",
823 pm8001_ha->pdev->subsystem_device));
828 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
829 * @pm8001_ha : our adapter
832 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
834 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
835 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
839 memset(&phycfg_int, 0, sizeof(phycfg_int));
840 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
842 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
843 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
844 pm8001_get_phy_mask(pm8001_ha, &phymask);
846 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
847 if (phymask & (1 << i)) {/* Internal PHY */
848 pm8001_set_phy_profile_single(pm8001_ha, i,
849 sizeof(phycfg_int) / sizeof(u32),
852 } else { /* External PHY */
853 pm8001_set_phy_profile_single(pm8001_ha, i,
854 sizeof(phycfg_ext) / sizeof(u32),
863 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
864 * @pm8001_ha : our hba.
866 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
868 switch (pm8001_ha->pdev->subsystem_vendor) {
869 case PCI_VENDOR_ID_ATTO:
870 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
873 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
875 case PCI_VENDOR_ID_ADAPTEC2:
880 return pm8001_get_phy_settings_info(pm8001_ha);
884 #ifdef PM8001_USE_MSIX
886 * pm8001_setup_msix - enable MSI-X interrupt
887 * @chip_info: our ha struct.
888 * @irq_handler: irq_handler
890 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
896 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
898 /* SPCv controllers supports 64 msi-x */
899 if (pm8001_ha->chip_id == chip_8001) {
902 number_of_intr = PM8001_MAX_MSIX_VEC;
903 flag &= ~IRQF_SHARED;
906 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
907 number_of_intr, PCI_IRQ_MSIX);
910 pm8001_ha->number_of_intr = number_of_intr;
912 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
913 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
914 rc, pm8001_ha->number_of_intr));
916 for (i = 0; i < number_of_intr; i++) {
917 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
919 pm8001_ha->irq_vector[i].irq_id = i;
920 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
922 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
923 pm8001_interrupt_handler_msix, flag,
924 intr_drvname[i], &(pm8001_ha->irq_vector[i]));
926 for (j = 0; j < i; j++) {
927 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
928 &(pm8001_ha->irq_vector[i]));
930 pci_free_irq_vectors(pm8001_ha->pdev);
940 * pm8001_request_irq - register interrupt
941 * @chip_info: our ha struct.
943 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
945 struct pci_dev *pdev;
948 pdev = pm8001_ha->pdev;
950 #ifdef PM8001_USE_MSIX
951 if (pdev->msix_cap && pci_msi_enabled())
952 return pm8001_setup_msix(pm8001_ha);
954 PM8001_INIT_DBG(pm8001_ha,
955 pm8001_printk("MSIX not supported!!!\n"));
961 /* initialize the INT-X interrupt */
962 pm8001_ha->irq_vector[0].irq_id = 0;
963 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
964 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
965 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
970 * pm8001_pci_probe - probe supported device
971 * @pdev: pci device which kernel has been prepared for.
972 * @ent: pci device id
974 * This function is the main initialization function, when register a new
975 * pci driver it is invoked, all struct an hardware initilization should be done
976 * here, also, register interrupt
978 static int pm8001_pci_probe(struct pci_dev *pdev,
979 const struct pci_device_id *ent)
984 struct pm8001_hba_info *pm8001_ha;
985 struct Scsi_Host *shost = NULL;
986 const struct pm8001_chip_info *chip;
988 dev_printk(KERN_INFO, &pdev->dev,
989 "pm80xx: driver version %s\n", DRV_VERSION);
990 rc = pci_enable_device(pdev);
993 pci_set_master(pdev);
995 * Enable pci slot busmaster by setting pci command register.
996 * This is required by FW for Cyclone card.
999 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1001 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1002 rc = pci_request_regions(pdev, DRV_NAME);
1004 goto err_out_disable;
1005 rc = pci_go_44(pdev);
1007 goto err_out_regions;
1009 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1012 goto err_out_regions;
1014 chip = &pm8001_chips[ent->driver_data];
1015 SHOST_TO_SAS_HA(shost) =
1016 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1017 if (!SHOST_TO_SAS_HA(shost)) {
1019 goto err_out_free_host;
1022 rc = pm8001_prep_sas_ha_init(shost, chip);
1027 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1028 /* ent->driver variable is used to differentiate between controllers */
1029 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1034 list_add_tail(&pm8001_ha->list, &hba_list);
1035 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1036 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1038 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1039 "chip_init failed [ret: %d]\n", rc));
1040 goto err_out_ha_free;
1043 rc = scsi_add_host(shost, &pdev->dev);
1045 goto err_out_ha_free;
1046 rc = pm8001_request_irq(pm8001_ha);
1048 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1049 "pm8001_request_irq failed [ret: %d]\n", rc));
1053 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1054 if (pm8001_ha->chip_id != chip_8001) {
1055 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1056 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1057 /* setup thermal configuration. */
1058 pm80xx_set_thermal_config(pm8001_ha);
1061 pm8001_init_sas_add(pm8001_ha);
1062 /* phy setting support for motherboard controller */
1063 rc = pm8001_configure_phy_settings(pm8001_ha);
1067 pm8001_post_sas_ha_init(shost, chip);
1068 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1071 scsi_scan_host(pm8001_ha->shost);
1075 scsi_remove_host(pm8001_ha->shost);
1077 pm8001_free(pm8001_ha);
1079 kfree(SHOST_TO_SAS_HA(shost));
1081 scsi_host_put(shost);
1083 pci_release_regions(pdev);
1085 pci_disable_device(pdev);
1090 static void pm8001_pci_remove(struct pci_dev *pdev)
1092 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1093 struct pm8001_hba_info *pm8001_ha;
1095 pm8001_ha = sha->lldd_ha;
1096 sas_unregister_ha(sha);
1097 sas_remove_host(pm8001_ha->shost);
1098 list_del(&pm8001_ha->list);
1099 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1100 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1102 #ifdef PM8001_USE_MSIX
1103 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1104 synchronize_irq(pci_irq_vector(pdev, i));
1105 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1106 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1107 pci_free_irq_vectors(pdev);
1109 free_irq(pm8001_ha->irq, sha);
1111 #ifdef PM8001_USE_TASKLET
1112 /* For non-msix and msix interrupts */
1113 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1114 (pm8001_ha->chip_id == chip_8001))
1115 tasklet_kill(&pm8001_ha->tasklet[0]);
1117 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1118 tasklet_kill(&pm8001_ha->tasklet[j]);
1120 scsi_host_put(pm8001_ha->shost);
1121 pm8001_free(pm8001_ha);
1122 kfree(sha->sas_phy);
1123 kfree(sha->sas_port);
1125 pci_release_regions(pdev);
1126 pci_disable_device(pdev);
1130 * pm8001_pci_suspend - power management suspend main entry point
1131 * @pdev: PCI device struct
1132 * @state: PM state change to (usually PCI_D3)
1134 * Returns 0 success, anything else error.
1136 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1138 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1139 struct pm8001_hba_info *pm8001_ha;
1142 pm8001_ha = sha->lldd_ha;
1143 sas_suspend_ha(sha);
1144 flush_workqueue(pm8001_wq);
1145 scsi_block_requests(pm8001_ha->shost);
1146 if (!pdev->pm_cap) {
1147 dev_err(&pdev->dev, " PCI PM not supported\n");
1150 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1151 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1152 #ifdef PM8001_USE_MSIX
1153 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1154 synchronize_irq(pci_irq_vector(pdev, i));
1155 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1156 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1157 pci_free_irq_vectors(pdev);
1159 free_irq(pm8001_ha->irq, sha);
1161 #ifdef PM8001_USE_TASKLET
1162 /* For non-msix and msix interrupts */
1163 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1164 (pm8001_ha->chip_id == chip_8001))
1165 tasklet_kill(&pm8001_ha->tasklet[0]);
1167 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1168 tasklet_kill(&pm8001_ha->tasklet[j]);
1170 device_state = pci_choose_state(pdev, state);
1171 pm8001_printk("pdev=0x%p, slot=%s, entering "
1172 "operating state [D%d]\n", pdev,
1173 pm8001_ha->name, device_state);
1174 pci_save_state(pdev);
1175 pci_disable_device(pdev);
1176 pci_set_power_state(pdev, device_state);
1181 * pm8001_pci_resume - power management resume main entry point
1182 * @pdev: PCI device struct
1184 * Returns 0 success, anything else error.
1186 static int pm8001_pci_resume(struct pci_dev *pdev)
1188 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1189 struct pm8001_hba_info *pm8001_ha;
1193 DECLARE_COMPLETION_ONSTACK(completion);
1194 pm8001_ha = sha->lldd_ha;
1195 device_state = pdev->current_state;
1197 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1198 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1200 pci_set_power_state(pdev, PCI_D0);
1201 pci_enable_wake(pdev, PCI_D0, 0);
1202 pci_restore_state(pdev);
1203 rc = pci_enable_device(pdev);
1205 pm8001_printk("slot=%s Enable device failed during resume\n",
1207 goto err_out_enable;
1210 pci_set_master(pdev);
1211 rc = pci_go_44(pdev);
1213 goto err_out_disable;
1214 sas_prep_resume_ha(sha);
1215 /* chip soft rst only for spc */
1216 if (pm8001_ha->chip_id == chip_8001) {
1217 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1218 PM8001_INIT_DBG(pm8001_ha,
1219 pm8001_printk("chip soft reset successful\n"));
1221 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1223 goto err_out_disable;
1225 /* disable all the interrupt bits */
1226 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1228 rc = pm8001_request_irq(pm8001_ha);
1230 goto err_out_disable;
1231 #ifdef PM8001_USE_TASKLET
1232 /* Tasklet for non msi-x interrupt handler */
1233 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1234 (pm8001_ha->chip_id == chip_8001))
1235 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1236 (unsigned long)&(pm8001_ha->irq_vector[0]));
1238 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1239 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1240 (unsigned long)&(pm8001_ha->irq_vector[j]));
1242 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1243 if (pm8001_ha->chip_id != chip_8001) {
1244 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1245 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1248 /* Chip documentation for the 8070 and 8072 SPCv */
1249 /* states that a 500ms minimum delay is required */
1250 /* before issuing commands. Otherwise, the firmware */
1251 /* will enter an unrecoverable state. */
1253 if (pm8001_ha->chip_id == chip_8070 ||
1254 pm8001_ha->chip_id == chip_8072) {
1258 /* Spin up the PHYs */
1260 pm8001_ha->flags = PM8001F_RUN_TIME;
1261 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1262 pm8001_ha->phy[i].enable_completion = &completion;
1263 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1264 wait_for_completion(&completion);
1270 scsi_remove_host(pm8001_ha->shost);
1271 pci_disable_device(pdev);
1276 /* update of pci device, vendor id and driver data with
1277 * unique value for each of the controller
1279 static struct pci_device_id pm8001_pci_table[] = {
1280 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1281 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1282 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1283 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1284 /* Support for SPC/SPCv/SPCve controllers */
1285 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1286 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1287 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1288 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1289 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1290 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1291 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1292 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1293 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1294 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1295 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1296 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1297 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1298 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1299 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1300 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1301 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1302 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1303 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1304 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1305 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1306 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1307 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1308 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1309 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1310 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1311 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1312 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1313 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1314 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1315 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1316 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1317 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1318 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1319 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1320 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1321 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1322 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1323 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1324 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1325 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1326 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1327 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1328 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1329 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1330 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1331 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1332 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1333 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1334 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1335 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1336 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1337 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1338 { PCI_VENDOR_ID_ATTO, 0x8070,
1339 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1340 { PCI_VENDOR_ID_ATTO, 0x8070,
1341 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1342 { PCI_VENDOR_ID_ATTO, 0x8072,
1343 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1344 { PCI_VENDOR_ID_ATTO, 0x8072,
1345 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1346 { PCI_VENDOR_ID_ATTO, 0x8070,
1347 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1348 { PCI_VENDOR_ID_ATTO, 0x8072,
1349 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1350 { PCI_VENDOR_ID_ATTO, 0x8072,
1351 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1352 {} /* terminate list */
1355 static struct pci_driver pm8001_pci_driver = {
1357 .id_table = pm8001_pci_table,
1358 .probe = pm8001_pci_probe,
1359 .remove = pm8001_pci_remove,
1360 .suspend = pm8001_pci_suspend,
1361 .resume = pm8001_pci_resume,
1365 * pm8001_init - initialize scsi transport template
1367 static int __init pm8001_init(void)
1371 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1376 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1379 rc = pci_register_driver(&pm8001_pci_driver);
1385 sas_release_transport(pm8001_stt);
1387 destroy_workqueue(pm8001_wq);
1392 static void __exit pm8001_exit(void)
1394 pci_unregister_driver(&pm8001_pci_driver);
1395 sas_release_transport(pm8001_stt);
1396 destroy_workqueue(pm8001_wq);
1399 module_init(pm8001_init);
1400 module_exit(pm8001_exit);
1402 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1403 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1404 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1405 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1407 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1408 "SAS/SATA controller driver");
1409 MODULE_VERSION(DRV_VERSION);
1410 MODULE_LICENSE("GPL");
1411 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);