drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
  47 module_param(logging_level, ulong, 0644);
  48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  49
  50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  51 module_param(link_rate, ulong, 0644);
  52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  53                 " 1: Link rate 1.5G\n"
  54                 " 2: Link rate 3.0G\n"
  55                 " 4: Link rate 6.0G\n"
  56                 " 8: Link rate 12.0G\n");
  57
  58 static struct scsi_transport_template *pm8001_stt;
  59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
  60
  61 /*
  62  * chip info structure to identify chip key functionality as
  63  * encryption available/not, no of ports, hw specific function ref
  64  */
  65 static const struct pm8001_chip_info pm8001_chips[] = {
  66         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  67         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  68         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  69         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  70         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  71         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  72         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  73         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  75         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  76         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  77 };
  78 static int pm8001_id;
  79
  80 LIST_HEAD(hba_list);
  81
  82 struct workqueue_struct *pm8001_wq;
  83
  84 /*
  85  * The main structure which LLDD must register for scsi core.
  86  */
  87 static struct scsi_host_template pm8001_sht = {
  88         .module                 = THIS_MODULE,
  89         .name                   = DRV_NAME,
  90         .queuecommand           = sas_queuecommand,
  91         .dma_need_drain         = ata_scsi_dma_need_drain,
  92         .target_alloc           = sas_target_alloc,
  93         .slave_configure        = sas_slave_configure,
  94         .scan_finished          = pm8001_scan_finished,
  95         .scan_start             = pm8001_scan_start,
  96         .change_queue_depth     = sas_change_queue_depth,
  97         .bios_param             = sas_bios_param,
  98         .can_queue              = 1,
  99         .this_id                = -1,
 100         .sg_tablesize           = PM8001_MAX_DMA_SG,
 101         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 102         .eh_device_reset_handler = sas_eh_device_reset_handler,
 103         .eh_target_reset_handler = sas_eh_target_reset_handler,
 104         .slave_alloc            = sas_slave_alloc,
 105         .target_destroy         = sas_target_destroy,
 106         .ioctl                  = sas_ioctl,
 107 #ifdef CONFIG_COMPAT
 108         .compat_ioctl           = sas_ioctl,
 109 #endif
 110         .shost_attrs            = pm8001_host_attrs,
 111         .track_queue_depth      = 1,
 112 };
 113
 114 /*
 115  * Sas layer call this function to execute specific task.
 116  */
 117 static struct sas_domain_function_template pm8001_transport_ops = {
 118         .lldd_dev_found         = pm8001_dev_found,
 119         .lldd_dev_gone          = pm8001_dev_gone,
 120
 121         .lldd_execute_task      = pm8001_queue_command,
 122         .lldd_control_phy       = pm8001_phy_control,
 123
 124         .lldd_abort_task        = pm8001_abort_task,
 125         .lldd_abort_task_set    = pm8001_abort_task_set,
 126         .lldd_clear_aca         = pm8001_clear_aca,
 127         .lldd_clear_task_set    = pm8001_clear_task_set,
 128         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 129         .lldd_lu_reset          = pm8001_lu_reset,
 130         .lldd_query_task        = pm8001_query_task,
 131 };
 132
 133 /**
 134  * pm8001_phy_init - initiate our adapter phys
 135  * @pm8001_ha: our hba structure.
 136  * @phy_id: phy id.
 137  */
 138 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 139 {
 140         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 141         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 142         phy->phy_state = PHY_LINK_DISABLE;
 143         phy->pm8001_ha = pm8001_ha;
 144         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 145         sas_phy->class = SAS;
 146         sas_phy->iproto = SAS_PROTOCOL_ALL;
 147         sas_phy->tproto = 0;
 148         sas_phy->type = PHY_TYPE_PHYSICAL;
 149         sas_phy->role = PHY_ROLE_INITIATOR;
 150         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 151         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 152         sas_phy->id = phy_id;
 153         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 154         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 155         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 156         sas_phy->lldd_phy = phy;
 157 }
 158
 159 /**
 160  * pm8001_free - free hba
 161  * @pm8001_ha:  our hba structure.
 162  */
 163 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 164 {
 165         int i;
 166
 167         if (!pm8001_ha)
 168                 return;
 169
 170         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 171                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 172                         dma_free_coherent(&pm8001_ha->pdev->dev,
 173                                 (pm8001_ha->memoryMap.region[i].total_len +
 174                                 pm8001_ha->memoryMap.region[i].alignment),
 175                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 176                                 pm8001_ha->memoryMap.region[i].phys_addr);
 177                         }
 178         }
 179         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 180         flush_workqueue(pm8001_wq);
 181         kfree(pm8001_ha->tags);
 182         kfree(pm8001_ha);
 183 }
 184
 185 #ifdef PM8001_USE_TASKLET
 186
 187 /**
 188  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
 189  * @opaque: the passed general host adapter struct
 190  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 191  */
 192 static void pm8001_tasklet(unsigned long opaque)
 193 {
 194         struct pm8001_hba_info *pm8001_ha;
 195         struct isr_param *irq_vector;
 196
 197         irq_vector = (struct isr_param *)opaque;
 198         pm8001_ha = irq_vector->drv_inst;
 199         if (unlikely(!pm8001_ha))
 200                 BUG_ON(1);
 201         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 202 }
 203 #endif
 204
 205 /**
 206  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 207  * It obtains the vector number and calls the equivalent bottom
 208  * half or services directly.
 209  * @irq: interrupt number
 210  * @opaque: the passed outbound queue/vector. Host structure is
 211  * retrieved from the same.
 212  */
 213 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 214 {
 215         struct isr_param *irq_vector;
 216         struct pm8001_hba_info *pm8001_ha;
 217         irqreturn_t ret = IRQ_HANDLED;
 218         irq_vector = (struct isr_param *)opaque;
 219         pm8001_ha = irq_vector->drv_inst;
 220
 221         if (unlikely(!pm8001_ha))
 222                 return IRQ_NONE;
 223         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 224                 return IRQ_NONE;
 225 #ifdef PM8001_USE_TASKLET
 226         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 227 #else
 228         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 229 #endif
 230         return ret;
 231 }
 232
 233 /**
 234  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 235  * @irq: interrupt number
 236  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
 237  */
 238
 239 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 240 {
 241         struct pm8001_hba_info *pm8001_ha;
 242         irqreturn_t ret = IRQ_HANDLED;
 243         struct sas_ha_struct *sha = dev_id;
 244         pm8001_ha = sha->lldd_ha;
 245         if (unlikely(!pm8001_ha))
 246                 return IRQ_NONE;
 247         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 248                 return IRQ_NONE;
 249
 250 #ifdef PM8001_USE_TASKLET
 251         tasklet_schedule(&pm8001_ha->tasklet[0]);
 252 #else
 253         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 254 #endif
 255         return ret;
 256 }
 257
 258 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 259 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 260
 261 /**
 262  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 263  * @pm8001_ha: our hba structure.
 264  * @ent: PCI device ID structure to match on
 265  */
 266 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 267                         const struct pci_device_id *ent)
 268 {
 269         int i, count = 0, rc = 0;
 270         u32 ci_offset, ib_offset, ob_offset, pi_offset;
 271         struct inbound_queue_table *ibq;
 272         struct outbound_queue_table *obq;
 273
 274         spin_lock_init(&pm8001_ha->lock);
 275         spin_lock_init(&pm8001_ha->bitmap_lock);
 276         pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
 277                    pm8001_ha->chip->n_phy);
 278
 279         /* Setup Interrupt */
 280         rc = pm8001_setup_irq(pm8001_ha);
 281         if (rc) {
 282                 pm8001_dbg(pm8001_ha, FAIL,
 283                            "pm8001_setup_irq failed [ret: %d]\n", rc);
 284                 goto err_out;
 285         }
 286         /* Request Interrupt */
 287         rc = pm8001_request_irq(pm8001_ha);
 288         if (rc)
 289                 goto err_out;
 290
 291         count = pm8001_ha->max_q_num;
 292         /* Queues are chosen based on the number of cores/msix availability */
 293         ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
 294         ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
 295         ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
 296         pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
 297         pm8001_ha->max_memcnt = pi_offset + count;
 298
 299         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 300                 pm8001_phy_init(pm8001_ha, i);
 301                 pm8001_ha->port[i].wide_port_phymap = 0;
 302                 pm8001_ha->port[i].port_attached = 0;
 303                 pm8001_ha->port[i].port_state = 0;
 304                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 305         }
 306
 307         /* MPI Memory region 1 for AAP Event Log for fw */
 308         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 309         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 310         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 311         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 312
 313         /* MPI Memory region 2 for IOP Event Log for fw */
 314         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 315         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 316         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 317         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 318
 319         for (i = 0; i < count; i++) {
 320                 ibq = &pm8001_ha->inbnd_q_tbl[i];
 321                 spin_lock_init(&ibq->iq_lock);
 322                 /* MPI Memory region 3 for consumer Index of inbound queues */
 323                 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
 324                 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
 325                 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
 326                 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
 327
 328                 if ((ent->driver_data) != chip_8001) {
 329                         /* MPI Memory region 5 inbound queues */
 330                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 331                                                 PM8001_MPI_QUEUE;
 332                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 333                                                                 = 128;
 334                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 335                                                 PM8001_MPI_QUEUE * 128;
 336                         pm8001_ha->memoryMap.region[ib_offset+i].alignment
 337                                                                 = 128;
 338                 } else {
 339                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 340                                                 PM8001_MPI_QUEUE;
 341                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 342                                                                 = 64;
 343                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 344                                                 PM8001_MPI_QUEUE * 64;
 345                         pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
 346                 }
 347         }
 348
 349         for (i = 0; i < count; i++) {
 350                 obq = &pm8001_ha->outbnd_q_tbl[i];
 351                 spin_lock_init(&obq->oq_lock);
 352                 /* MPI Memory region 4 for producer Index of outbound queues */
 353                 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
 354                 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
 355                 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
 356                 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
 357
 358                 if (ent->driver_data != chip_8001) {
 359                         /* MPI Memory region 6 Outbound queues */
 360                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 361                                                 PM8001_MPI_QUEUE;
 362                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 363                                                                 = 128;
 364                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 365                                                 PM8001_MPI_QUEUE * 128;
 366                         pm8001_ha->memoryMap.region[ob_offset+i].alignment
 367                                                                 = 128;
 368                 } else {
 369                         /* MPI Memory region 6 Outbound queues */
 370                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 371                                                 PM8001_MPI_QUEUE;
 372                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 373                                                                 = 64;
 374                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 375                                                 PM8001_MPI_QUEUE * 64;
 376                         pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
 377                 }
 378
 379         }
 380         /* Memory region write DMA*/
 381         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 382         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 383         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 384
 385         /* Memory region for fw flash */
 386         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 387
 388         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 389         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 390         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 391         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 392         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 393                 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
 394
 395                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 396                                      &region->virt_ptr,
 397                                      &region->phys_addr,
 398                                      &region->phys_addr_hi,
 399                                      &region->phys_addr_lo,
 400                                      region->total_len,
 401                                      region->alignment) != 0) {
 402                         pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
 403                         goto err_out;
 404                 }
 405         }
 406
 407         /* Memory region for devices*/
 408         pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
 409                                 * sizeof(struct pm8001_device), GFP_KERNEL);
 410         if (!pm8001_ha->devices) {
 411                 rc = -ENOMEM;
 412                 goto err_out_nodev;
 413         }
 414         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 415                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 416                 pm8001_ha->devices[i].id = i;
 417                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 418                 atomic_set(&pm8001_ha->devices[i].running_req, 0);
 419         }
 420         pm8001_ha->flags = PM8001F_INIT_TIME;
 421         /* Initialize tags */
 422         pm8001_tag_init(pm8001_ha);
 423         return 0;
 424
 425 err_out_nodev:
 426         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 427                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 428                         dma_free_coherent(&pm8001_ha->pdev->dev,
 429                                 (pm8001_ha->memoryMap.region[i].total_len +
 430                                 pm8001_ha->memoryMap.region[i].alignment),
 431                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 432                                 pm8001_ha->memoryMap.region[i].phys_addr);
 433                 }
 434         }
 435 err_out:
 436         return 1;
 437 }
 438
 439 /**
 440  * pm8001_ioremap - remap the pci high physical address to kernel virtual
 441  * address so that we can access them.
 442  * @pm8001_ha: our hba structure.
 443  */
 444 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 445 {
 446         u32 bar;
 447         u32 logicalBar = 0;
 448         struct pci_dev *pdev;
 449
 450         pdev = pm8001_ha->pdev;
 451         /* map pci mem (PMC pci base 0-3)*/
 452         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 453                 /*
 454                 ** logical BARs for SPC:
 455                 ** bar 0 and 1 - logical BAR0
 456                 ** bar 2 and 3 - logical BAR1
 457                 ** bar4 - logical BAR2
 458                 ** bar5 - logical BAR3
 459                 ** Skip the appropriate assignments:
 460                 */
 461                 if ((bar == 1) || (bar == 3))
 462                         continue;
 463                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 464                         pm8001_ha->io_mem[logicalBar].membase =
 465                                 pci_resource_start(pdev, bar);
 466                         pm8001_ha->io_mem[logicalBar].memsize =
 467                                 pci_resource_len(pdev, bar);
 468                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 469                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 470                                 pm8001_ha->io_mem[logicalBar].memsize);
 471                         if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
 472                                 pm8001_dbg(pm8001_ha, INIT,
 473                                         "Failed to ioremap bar %d, logicalBar %d",
 474                                    bar, logicalBar);
 475                                 return -ENOMEM;
 476                         }
 477                         pm8001_dbg(pm8001_ha, INIT,
 478                                    "base addr %llx virt_addr=%llx len=%d\n",
 479                                    (u64)pm8001_ha->io_mem[logicalBar].membase,
 480                                    (u64)(unsigned long)
 481                                    pm8001_ha->io_mem[logicalBar].memvirtaddr,
 482                                    pm8001_ha->io_mem[logicalBar].memsize);
 483                 } else {
 484                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 485                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 486                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 487                 }
 488                 logicalBar++;
 489         }
 490         return 0;
 491 }
 492
 493 /**
 494  * pm8001_pci_alloc - initialize our ha card structure
 495  * @pdev: pci device.
 496  * @ent: ent
 497  * @shost: scsi host struct which has been initialized before.
 498  */
 499 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 500                                  const struct pci_device_id *ent,
 501                                 struct Scsi_Host *shost)
 502
 503 {
 504         struct pm8001_hba_info *pm8001_ha;
 505         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 506         int j;
 507
 508         pm8001_ha = sha->lldd_ha;
 509         if (!pm8001_ha)
 510                 return NULL;
 511
 512         pm8001_ha->pdev = pdev;
 513         pm8001_ha->dev = &pdev->dev;
 514         pm8001_ha->chip_id = ent->driver_data;
 515         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 516         pm8001_ha->irq = pdev->irq;
 517         pm8001_ha->sas = sha;
 518         pm8001_ha->shost = shost;
 519         pm8001_ha->id = pm8001_id++;
 520         pm8001_ha->logging_level = logging_level;
 521         pm8001_ha->non_fatal_count = 0;
 522         if (link_rate >= 1 && link_rate <= 15)
 523                 pm8001_ha->link_rate = (link_rate << 8);
 524         else {
 525                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 526                         LINKRATE_60 | LINKRATE_120;
 527                 pm8001_dbg(pm8001_ha, FAIL,
 528                            "Setting link rate to default value\n");
 529         }
 530         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 531         /* IOMB size is 128 for 8088/89 controllers */
 532         if (pm8001_ha->chip_id != chip_8001)
 533                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 534         else
 535                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 536
 537 #ifdef PM8001_USE_TASKLET
 538         /* Tasklet for non msi-x interrupt handler */
 539         if ((!pdev->msix_cap || !pci_msi_enabled())
 540             || (pm8001_ha->chip_id == chip_8001))
 541                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 542                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 543         else
 544                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 545                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 546                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 547 #endif
 548         if (pm8001_ioremap(pm8001_ha))
 549                 goto failed_pci_alloc;
 550         if (!pm8001_alloc(pm8001_ha, ent))
 551                 return pm8001_ha;
 552 failed_pci_alloc:
 553         pm8001_free(pm8001_ha);
 554         return NULL;
 555 }
 556
 557 /**
 558  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 559  * @pdev: pci device.
 560  */
 561 static int pci_go_44(struct pci_dev *pdev)
 562 {
 563         int rc;
 564
 565         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 566         if (rc) {
 567                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 568                 if (rc)
 569                         dev_printk(KERN_ERR, &pdev->dev,
 570                                 "32-bit DMA enable failed\n");
 571         }
 572         return rc;
 573 }
 574
 575 /**
 576  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 577  * @shost: scsi host which has been allocated outside.
 578  * @chip_info: our ha struct.
 579  */
 580 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 581                                    const struct pm8001_chip_info *chip_info)
 582 {
 583         int phy_nr, port_nr;
 584         struct asd_sas_phy **arr_phy;
 585         struct asd_sas_port **arr_port;
 586         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 587
 588         phy_nr = chip_info->n_phy;
 589         port_nr = phy_nr;
 590         memset(sha, 0x00, sizeof(*sha));
 591         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 592         if (!arr_phy)
 593                 goto exit;
 594         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 595         if (!arr_port)
 596                 goto exit_free2;
 597
 598         sha->sas_phy = arr_phy;
 599         sha->sas_port = arr_port;
 600         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 601         if (!sha->lldd_ha)
 602                 goto exit_free1;
 603
 604         shost->transportt = pm8001_stt;
 605         shost->max_id = PM8001_MAX_DEVICES;
 606         shost->max_lun = 8;
 607         shost->max_channel = 0;
 608         shost->unique_id = pm8001_id;
 609         shost->max_cmd_len = 16;
 610         shost->can_queue = PM8001_CAN_QUEUE;
 611         shost->cmd_per_lun = 32;
 612         return 0;
 613 exit_free1:
 614         kfree(arr_port);
 615 exit_free2:
 616         kfree(arr_phy);
 617 exit:
 618         return -1;
 619 }
 620
 621 /**
 622  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 623  * @shost: scsi host which has been allocated outside
 624  * @chip_info: our ha struct.
 625  */
 626 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 627                                      const struct pm8001_chip_info *chip_info)
 628 {
 629         int i = 0;
 630         struct pm8001_hba_info *pm8001_ha;
 631         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 632
 633         pm8001_ha = sha->lldd_ha;
 634         for (i = 0; i < chip_info->n_phy; i++) {
 635                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 636                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 637                 sha->sas_phy[i]->sas_addr =
 638                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 639         }
 640         sha->sas_ha_name = DRV_NAME;
 641         sha->dev = pm8001_ha->dev;
 642         sha->strict_wide_ports = 1;
 643         sha->lldd_module = THIS_MODULE;
 644         sha->sas_addr = &pm8001_ha->sas_addr[0];
 645         sha->num_phys = chip_info->n_phy;
 646         sha->core.shost = shost;
 647 }
 648
 649 /**
 650  * pm8001_init_sas_add - initialize sas address
 651  * @pm8001_ha: our ha struct.
 652  *
 653  * Currently we just set the fixed SAS address to our HBA, for manufacture,
 654  * it should read from the EEPROM
 655  */
 656 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 657 {
 658         u8 i, j;
 659         u8 sas_add[8];
 660 #ifdef PM8001_READ_VPD
 661         /* For new SPC controllers WWN is stored in flash vpd
 662         *  For SPC/SPCve controllers WWN is stored in EEPROM
 663         *  For Older SPC WWN is stored in NVMD
 664         */
 665         DECLARE_COMPLETION_ONSTACK(completion);
 666         struct pm8001_ioctl_payload payload;
 667         u16 deviceid;
 668         int rc;
 669
 670         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 671         pm8001_ha->nvmd_completion = &completion;
 672
 673         if (pm8001_ha->chip_id == chip_8001) {
 674                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 675                         payload.minor_function = 4;
 676                         payload.rd_length = 4096;
 677                 } else {
 678                         payload.minor_function = 0;
 679                         payload.rd_length = 128;
 680                 }
 681         } else if ((pm8001_ha->chip_id == chip_8070 ||
 682                         pm8001_ha->chip_id == chip_8072) &&
 683                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 684                 payload.minor_function = 4;
 685                 payload.rd_length = 4096;
 686         } else {
 687                 payload.minor_function = 1;
 688                 payload.rd_length = 4096;
 689         }
 690         payload.offset = 0;
 691         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 692         if (!payload.func_specific) {
 693                 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
 694                 return;
 695         }
 696         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 697         if (rc) {
 698                 kfree(payload.func_specific);
 699                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 700                 return;
 701         }
 702         wait_for_completion(&completion);
 703
 704         for (i = 0, j = 0; i <= 7; i++, j++) {
 705                 if (pm8001_ha->chip_id == chip_8001) {
 706                         if (deviceid == 0x8081)
 707                                 pm8001_ha->sas_addr[j] =
 708                                         payload.func_specific[0x704 + i];
 709                         else if (deviceid == 0x0042)
 710                                 pm8001_ha->sas_addr[j] =
 711                                         payload.func_specific[0x010 + i];
 712                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 713                                 pm8001_ha->chip_id == chip_8072) &&
 714                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 715                         pm8001_ha->sas_addr[j] =
 716                                         payload.func_specific[0x010 + i];
 717                 } else
 718                         pm8001_ha->sas_addr[j] =
 719                                         payload.func_specific[0x804 + i];
 720         }
 721         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 722         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 723                 if (i && ((i % 4) == 0))
 724                         sas_add[7] = sas_add[7] + 4;
 725                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 726                         sas_add, SAS_ADDR_SIZE);
 727                 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
 728                            pm8001_ha->phy[i].dev_sas_addr);
 729         }
 730         kfree(payload.func_specific);
 731 #else
 732         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 733                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 734                 pm8001_ha->phy[i].dev_sas_addr =
 735                         cpu_to_be64((u64)
 736                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 737         }
 738         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 739                 SAS_ADDR_SIZE);
 740 #endif
 741 }
 742
 743 /*
 744  * pm8001_get_phy_settings_info : Read phy setting values.
 745  * @pm8001_ha : our hba.
 746  */
 747 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 748 {
 749
 750 #ifdef PM8001_READ_VPD
 751         /*OPTION ROM FLASH read for the SPC cards */
 752         DECLARE_COMPLETION_ONSTACK(completion);
 753         struct pm8001_ioctl_payload payload;
 754         int rc;
 755
 756         pm8001_ha->nvmd_completion = &completion;
 757         /* SAS ADDRESS read from flash / EEPROM */
 758         payload.minor_function = 6;
 759         payload.offset = 0;
 760         payload.rd_length = 4096;
 761         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 762         if (!payload.func_specific)
 763                 return -ENOMEM;
 764         /* Read phy setting values from flash */
 765         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 766         if (rc) {
 767                 kfree(payload.func_specific);
 768                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 769                 return -ENOMEM;
 770         }
 771         wait_for_completion(&completion);
 772         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 773         kfree(payload.func_specific);
 774 #endif
 775         return 0;
 776 }
 777
 778 struct pm8001_mpi3_phy_pg_trx_config {
 779         u32 LaneLosCfg;
 780         u32 LanePgaCfg1;
 781         u32 LanePisoCfg1;
 782         u32 LanePisoCfg2;
 783         u32 LanePisoCfg3;
 784         u32 LanePisoCfg4;
 785         u32 LanePisoCfg5;
 786         u32 LanePisoCfg6;
 787         u32 LaneBctCtrl;
 788 };
 789
 790 /**
 791  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
 792  * @pm8001_ha : our adapter
 793  * @phycfg : PHY config page to populate
 794  */
 795 static
 796 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 797                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 798 {
 799         phycfg->LaneLosCfg   = 0x00000132;
 800         phycfg->LanePgaCfg1  = 0x00203949;
 801         phycfg->LanePisoCfg1 = 0x000000FF;
 802         phycfg->LanePisoCfg2 = 0xFF000001;
 803         phycfg->LanePisoCfg3 = 0xE7011300;
 804         phycfg->LanePisoCfg4 = 0x631C40C0;
 805         phycfg->LanePisoCfg5 = 0xF8102036;
 806         phycfg->LanePisoCfg6 = 0xF74A1000;
 807         phycfg->LaneBctCtrl  = 0x00FB33F8;
 808 }
 809
 810 /**
 811  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
 812  * @pm8001_ha : our adapter
 813  * @phycfg : PHY config page to populate
 814  */
 815 static
 816 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 817                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 818 {
 819         phycfg->LaneLosCfg   = 0x00000132;
 820         phycfg->LanePgaCfg1  = 0x00203949;
 821         phycfg->LanePisoCfg1 = 0x000000FF;
 822         phycfg->LanePisoCfg2 = 0xFF000001;
 823         phycfg->LanePisoCfg3 = 0xE7011300;
 824         phycfg->LanePisoCfg4 = 0x63349140;
 825         phycfg->LanePisoCfg5 = 0xF8102036;
 826         phycfg->LanePisoCfg6 = 0xF80D9300;
 827         phycfg->LaneBctCtrl  = 0x00FB33F8;
 828 }
 829
 830 /**
 831  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
 832  * @pm8001_ha : our adapter
 833  * @phymask : The PHY mask
 834  */
 835 static
 836 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 837 {
 838         switch (pm8001_ha->pdev->subsystem_device) {
 839         case 0x0070: /* H1280 - 8 external 0 internal */
 840         case 0x0072: /* H12F0 - 16 external 0 internal */
 841                 *phymask = 0x0000;
 842                 break;
 843
 844         case 0x0071: /* H1208 - 0 external 8 internal */
 845         case 0x0073: /* H120F - 0 external 16 internal */
 846                 *phymask = 0xFFFF;
 847                 break;
 848
 849         case 0x0080: /* H1244 - 4 external 4 internal */
 850                 *phymask = 0x00F0;
 851                 break;
 852
 853         case 0x0081: /* H1248 - 4 external 8 internal */
 854                 *phymask = 0x0FF0;
 855                 break;
 856
 857         case 0x0082: /* H1288 - 8 external 8 internal */
 858                 *phymask = 0xFF00;
 859                 break;
 860
 861         default:
 862                 pm8001_dbg(pm8001_ha, INIT,
 863                            "Unknown subsystem device=0x%.04x\n",
 864                            pm8001_ha->pdev->subsystem_device);
 865         }
 866 }
 867
 868 /**
 869  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
 870  * @pm8001_ha : our adapter
 871  */
 872 static
 873 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 874 {
 875         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 876         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 877         int phymask = 0;
 878         int i = 0;
 879
 880         memset(&phycfg_int, 0, sizeof(phycfg_int));
 881         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 882
 883         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 884         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 885         pm8001_get_phy_mask(pm8001_ha, &phymask);
 886
 887         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 888                 if (phymask & (1 << i)) {/* Internal PHY */
 889                         pm8001_set_phy_profile_single(pm8001_ha, i,
 890                                         sizeof(phycfg_int) / sizeof(u32),
 891                                         (u32 *)&phycfg_int);
 892
 893                 } else { /* External PHY */
 894                         pm8001_set_phy_profile_single(pm8001_ha, i,
 895                                         sizeof(phycfg_ext) / sizeof(u32),
 896                                         (u32 *)&phycfg_ext);
 897                 }
 898         }
 899
 900         return 0;
 901 }
 902
 903 /**
 904  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
 905  * @pm8001_ha : our hba.
 906  */
 907 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 908 {
 909         switch (pm8001_ha->pdev->subsystem_vendor) {
 910         case PCI_VENDOR_ID_ATTO:
 911                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 912                         return 0;
 913                 else
 914                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 915
 916         case PCI_VENDOR_ID_ADAPTEC2:
 917         case 0:
 918                 return 0;
 919
 920         default:
 921                 return pm8001_get_phy_settings_info(pm8001_ha);
 922         }
 923 }
 924
 925 #ifdef PM8001_USE_MSIX
 926 /**
 927  * pm8001_setup_msix - enable MSI-X interrupt
 928  * @pm8001_ha: our ha struct.
 929  */
 930 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 931 {
 932         u32 number_of_intr;
 933         int rc, cpu_online_count;
 934         unsigned int allocated_irq_vectors;
 935
 936         /* SPCv controllers supports 64 msi-x */
 937         if (pm8001_ha->chip_id == chip_8001) {
 938                 number_of_intr = 1;
 939         } else {
 940                 number_of_intr = PM8001_MAX_MSIX_VEC;
 941         }
 942
 943         cpu_online_count = num_online_cpus();
 944         number_of_intr = min_t(int, cpu_online_count, number_of_intr);
 945         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 946                         number_of_intr, PCI_IRQ_MSIX);
 947         allocated_irq_vectors = rc;
 948         if (rc < 0)
 949                 return rc;
 950
 951         /* Assigns the number of interrupts */
 952         number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
 953         pm8001_ha->number_of_intr = number_of_intr;
 954
 955         /* Maximum queue number updating in HBA structure */
 956         pm8001_ha->max_q_num = number_of_intr;
 957
 958         pm8001_dbg(pm8001_ha, INIT,
 959                    "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 960                    rc, pm8001_ha->number_of_intr);
 961         return 0;
 962 }
 963
 964 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 965 {
 966         u32 i = 0, j = 0;
 967         int flag = 0, rc = 0;
 968         int nr_irqs = pm8001_ha->number_of_intr;
 969
 970         if (pm8001_ha->chip_id != chip_8001)
 971                 flag &= ~IRQF_SHARED;
 972
 973         pm8001_dbg(pm8001_ha, INIT,
 974                    "pci_enable_msix request number of intr %d\n",
 975                    pm8001_ha->number_of_intr);
 976
 977         if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
 978                 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
 979
 980         for (i = 0; i < nr_irqs; i++) {
 981                 snprintf(pm8001_ha->intr_drvname[i],
 982                         sizeof(pm8001_ha->intr_drvname[0]),
 983                         "%s-%d", pm8001_ha->name, i);
 984                 pm8001_ha->irq_vector[i].irq_id = i;
 985                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 986
 987                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 988                         pm8001_interrupt_handler_msix, flag,
 989                         pm8001_ha->intr_drvname[i],
 990                         &(pm8001_ha->irq_vector[i]));
 991                 if (rc) {
 992                         for (j = 0; j < i; j++) {
 993                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 994                                         &(pm8001_ha->irq_vector[i]));
 995                         }
 996                         pci_free_irq_vectors(pm8001_ha->pdev);
 997                         break;
 998                 }
 999         }
1000
1001         return rc;
1002 }
1003 #endif
1004
1005 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1006 {
1007         struct pci_dev *pdev;
1008
1009         pdev = pm8001_ha->pdev;
1010
1011 #ifdef PM8001_USE_MSIX
1012         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1013                 return pm8001_setup_msix(pm8001_ha);
1014         pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1015 #endif
1016         return 0;
1017 }
1018
1019 /**
1020  * pm8001_request_irq - register interrupt
1021  * @pm8001_ha: our ha struct.
1022  */
1023 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1024 {
1025         struct pci_dev *pdev;
1026         int rc;
1027
1028         pdev = pm8001_ha->pdev;
1029
1030 #ifdef PM8001_USE_MSIX
1031         if (pdev->msix_cap && pci_msi_enabled())
1032                 return pm8001_request_msix(pm8001_ha);
1033         else {
1034                 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1035                 goto intx;
1036         }
1037 #endif
1038
1039 intx:
1040         /* initialize the INT-X interrupt */
1041         pm8001_ha->irq_vector[0].irq_id = 0;
1042         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1043         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1044                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1045         return rc;
1046 }
1047
1048 /**
1049  * pm8001_pci_probe - probe supported device
1050  * @pdev: pci device which kernel has been prepared for.
1051  * @ent: pci device id
1052  *
1053  * This function is the main initialization function, when register a new
1054  * pci driver it is invoked, all struct and hardware initialization should be
1055  * done here, also, register interrupt.
1056  */
1057 static int pm8001_pci_probe(struct pci_dev *pdev,
1058                             const struct pci_device_id *ent)
1059 {
1060         unsigned int rc;
1061         u32     pci_reg;
1062         u8      i = 0;
1063         struct pm8001_hba_info *pm8001_ha;
1064         struct Scsi_Host *shost = NULL;
1065         const struct pm8001_chip_info *chip;
1066         struct sas_ha_struct *sha;
1067
1068         dev_printk(KERN_INFO, &pdev->dev,
1069                 "pm80xx: driver version %s\n", DRV_VERSION);
1070         rc = pci_enable_device(pdev);
1071         if (rc)
1072                 goto err_out_enable;
1073         pci_set_master(pdev);
1074         /*
1075          * Enable pci slot busmaster by setting pci command register.
1076          * This is required by FW for Cyclone card.
1077          */
1078
1079         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1080         pci_reg |= 0x157;
1081         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1082         rc = pci_request_regions(pdev, DRV_NAME);
1083         if (rc)
1084                 goto err_out_disable;
1085         rc = pci_go_44(pdev);
1086         if (rc)
1087                 goto err_out_regions;
1088
1089         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1090         if (!shost) {
1091                 rc = -ENOMEM;
1092                 goto err_out_regions;
1093         }
1094         chip = &pm8001_chips[ent->driver_data];
1095         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1096         if (!sha) {
1097                 rc = -ENOMEM;
1098                 goto err_out_free_host;
1099         }
1100         SHOST_TO_SAS_HA(shost) = sha;
1101
1102         rc = pm8001_prep_sas_ha_init(shost, chip);
1103         if (rc) {
1104                 rc = -ENOMEM;
1105                 goto err_out_free;
1106         }
1107         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1108         /* ent->driver variable is used to differentiate between controllers */
1109         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1110         if (!pm8001_ha) {
1111                 rc = -ENOMEM;
1112                 goto err_out_free;
1113         }
1114
1115         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1116         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1117         if (rc) {
1118                 pm8001_dbg(pm8001_ha, FAIL,
1119                            "chip_init failed [ret: %d]\n", rc);
1120                 goto err_out_ha_free;
1121         }
1122
1123         rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1124         if (rc)
1125                 goto err_out_enable;
1126
1127         rc = scsi_add_host(shost, &pdev->dev);
1128         if (rc)
1129                 goto err_out_ha_free;
1130
1131         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1132         if (pm8001_ha->chip_id != chip_8001) {
1133                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1134                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1135                 /* setup thermal configuration. */
1136                 pm80xx_set_thermal_config(pm8001_ha);
1137         }
1138
1139         pm8001_init_sas_add(pm8001_ha);
1140         /* phy setting support for motherboard controller */
1141         rc = pm8001_configure_phy_settings(pm8001_ha);
1142         if (rc)
1143                 goto err_out_shost;
1144
1145         pm8001_post_sas_ha_init(shost, chip);
1146         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1147         if (rc) {
1148                 pm8001_dbg(pm8001_ha, FAIL,
1149                            "sas_register_ha failed [ret: %d]\n", rc);
1150                 goto err_out_shost;
1151         }
1152         list_add_tail(&pm8001_ha->list, &hba_list);
1153         pm8001_ha->flags = PM8001F_RUN_TIME;
1154         scsi_scan_host(pm8001_ha->shost);
1155         return 0;
1156
1157 err_out_shost:
1158         scsi_remove_host(pm8001_ha->shost);
1159 err_out_ha_free:
1160         pm8001_free(pm8001_ha);
1161 err_out_free:
1162         kfree(sha);
1163 err_out_free_host:
1164         scsi_host_put(shost);
1165 err_out_regions:
1166         pci_release_regions(pdev);
1167 err_out_disable:
1168         pci_disable_device(pdev);
1169 err_out_enable:
1170         return rc;
1171 }
1172
1173 /**
1174  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1175  * @pm8001_ha: our hba card information.
1176  * @shost: scsi host which has been allocated outside.
1177  * @pdev: pci device.
1178  */
1179 static int
1180 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1181                         struct pci_dev *pdev)
1182 {
1183         int i = 0;
1184         u32 max_out_io, ccb_count;
1185         u32 can_queue;
1186
1187         max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1188         ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1189
1190         /* Update to the scsi host*/
1191         can_queue = ccb_count - PM8001_RESERVE_SLOT;
1192         shost->can_queue = can_queue;
1193
1194         pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1195         if (!pm8001_ha->tags)
1196                 goto err_out;
1197
1198         /* Memory region for ccb_info*/
1199         pm8001_ha->ccb_count = ccb_count;
1200         pm8001_ha->ccb_info =
1201                 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1202         if (!pm8001_ha->ccb_info) {
1203                 pm8001_dbg(pm8001_ha, FAIL,
1204                            "Unable to allocate memory for ccb\n");
1205                 goto err_out_noccb;
1206         }
1207         for (i = 0; i < ccb_count; i++) {
1208                 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev,
1209                                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1210                                 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1211                                 GFP_KERNEL);
1212                 if (!pm8001_ha->ccb_info[i].buf_prd) {
1213                         pm8001_dbg(pm8001_ha, FAIL,
1214                                    "ccb prd memory allocation error\n");
1215                         goto err_out;
1216                 }
1217                 pm8001_ha->ccb_info[i].task = NULL;
1218                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1219                 pm8001_ha->ccb_info[i].device = NULL;
1220                 ++pm8001_ha->tags_num;
1221         }
1222         return 0;
1223
1224 err_out_noccb:
1225         kfree(pm8001_ha->devices);
1226 err_out:
1227         return -ENOMEM;
1228 }
1229
1230 static void pm8001_pci_remove(struct pci_dev *pdev)
1231 {
1232         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1233         struct pm8001_hba_info *pm8001_ha;
1234         int i, j;
1235         pm8001_ha = sha->lldd_ha;
1236         sas_unregister_ha(sha);
1237         sas_remove_host(pm8001_ha->shost);
1238         list_del(&pm8001_ha->list);
1239         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1240         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1241
1242 #ifdef PM8001_USE_MSIX
1243         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1244                 synchronize_irq(pci_irq_vector(pdev, i));
1245         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1246                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1247         pci_free_irq_vectors(pdev);
1248 #else
1249         free_irq(pm8001_ha->irq, sha);
1250 #endif
1251 #ifdef PM8001_USE_TASKLET
1252         /* For non-msix and msix interrupts */
1253         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1254             (pm8001_ha->chip_id == chip_8001))
1255                 tasklet_kill(&pm8001_ha->tasklet[0]);
1256         else
1257                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1258                         tasklet_kill(&pm8001_ha->tasklet[j]);
1259 #endif
1260         scsi_host_put(pm8001_ha->shost);
1261
1262         for (i = 0; i < pm8001_ha->ccb_count; i++) {
1263                 dma_free_coherent(&pm8001_ha->pdev->dev,
1264                         sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1265                         pm8001_ha->ccb_info[i].buf_prd,
1266                         pm8001_ha->ccb_info[i].ccb_dma_handle);
1267         }
1268         kfree(pm8001_ha->ccb_info);
1269         kfree(pm8001_ha->devices);
1270
1271         pm8001_free(pm8001_ha);
1272         kfree(sha->sas_phy);
1273         kfree(sha->sas_port);
1274         kfree(sha);
1275         pci_release_regions(pdev);
1276         pci_disable_device(pdev);
1277 }
1278
1279 /**
1280  * pm8001_pci_suspend - power management suspend main entry point
1281  * @dev: Device struct
1282  *
1283  * Return: 0 on success, anything else on error.
1284  */
1285 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1286 {
1287         struct pci_dev *pdev = to_pci_dev(dev);
1288         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1289         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1290         int  i, j;
1291         sas_suspend_ha(sha);
1292         flush_workqueue(pm8001_wq);
1293         scsi_block_requests(pm8001_ha->shost);
1294         if (!pdev->pm_cap) {
1295                 dev_err(dev, " PCI PM not supported\n");
1296                 return -ENODEV;
1297         }
1298         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1299         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1300 #ifdef PM8001_USE_MSIX
1301         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1302                 synchronize_irq(pci_irq_vector(pdev, i));
1303         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1304                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1305         pci_free_irq_vectors(pdev);
1306 #else
1307         free_irq(pm8001_ha->irq, sha);
1308 #endif
1309 #ifdef PM8001_USE_TASKLET
1310         /* For non-msix and msix interrupts */
1311         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1312             (pm8001_ha->chip_id == chip_8001))
1313                 tasklet_kill(&pm8001_ha->tasklet[0]);
1314         else
1315                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1316                         tasklet_kill(&pm8001_ha->tasklet[j]);
1317 #endif
1318         pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1319                       "suspended state\n", pdev,
1320                       pm8001_ha->name);
1321         return 0;
1322 }
1323
1324 /**
1325  * pm8001_pci_resume - power management resume main entry point
1326  * @dev: Device struct
1327  *
1328  * Return: 0 on success, anything else on error.
1329  */
1330 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1331 {
1332         struct pci_dev *pdev = to_pci_dev(dev);
1333         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1334         struct pm8001_hba_info *pm8001_ha;
1335         int rc;
1336         u8 i = 0, j;
1337         u32 device_state;
1338         DECLARE_COMPLETION_ONSTACK(completion);
1339         pm8001_ha = sha->lldd_ha;
1340         device_state = pdev->current_state;
1341
1342         pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1343                       pdev, pm8001_ha->name, device_state);
1344
1345         rc = pci_go_44(pdev);
1346         if (rc)
1347                 goto err_out_disable;
1348         sas_prep_resume_ha(sha);
1349         /* chip soft rst only for spc */
1350         if (pm8001_ha->chip_id == chip_8001) {
1351                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1352                 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1353         }
1354         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1355         if (rc)
1356                 goto err_out_disable;
1357
1358         /* disable all the interrupt bits */
1359         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1360
1361         rc = pm8001_request_irq(pm8001_ha);
1362         if (rc)
1363                 goto err_out_disable;
1364 #ifdef PM8001_USE_TASKLET
1365         /*  Tasklet for non msi-x interrupt handler */
1366         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1367             (pm8001_ha->chip_id == chip_8001))
1368                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1369                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1370         else
1371                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1372                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1373                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1374 #endif
1375         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1376         if (pm8001_ha->chip_id != chip_8001) {
1377                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1378                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1379         }
1380
1381         /* Chip documentation for the 8070 and 8072 SPCv    */
1382         /* states that a 500ms minimum delay is required    */
1383         /* before issuing commands. Otherwise, the firmware */
1384         /* will enter an unrecoverable state.               */
1385
1386         if (pm8001_ha->chip_id == chip_8070 ||
1387                 pm8001_ha->chip_id == chip_8072) {
1388                 mdelay(500);
1389         }
1390
1391         /* Spin up the PHYs */
1392
1393         pm8001_ha->flags = PM8001F_RUN_TIME;
1394         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1395                 pm8001_ha->phy[i].enable_completion = &completion;
1396                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1397                 wait_for_completion(&completion);
1398         }
1399         sas_resume_ha(sha);
1400         return 0;
1401
1402 err_out_disable:
1403         scsi_remove_host(pm8001_ha->shost);
1404
1405         return rc;
1406 }
1407
1408 /* update of pci device, vendor id and driver data with
1409  * unique value for each of the controller
1410  */
1411 static struct pci_device_id pm8001_pci_table[] = {
1412         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1413         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1414         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1415         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1416         /* Support for SPC/SPCv/SPCve controllers */
1417         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1418         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1419         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1420         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1421         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1422         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1423         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1424         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1425         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1426         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1427         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1428         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1429         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1430         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1431         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1432         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1433                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1434         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1435                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1436         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1437                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1438         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1439                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1440         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1441                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1442         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1443                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1444         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1445                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1446         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1447                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1448         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1449                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1450         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1451                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1452         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1453                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1454         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1455                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1456         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1457                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1458         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1459                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1460         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1461                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1462         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1463                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1464         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1465                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1466         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1467                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1468         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1469                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1470         { PCI_VENDOR_ID_ATTO, 0x8070,
1471                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1472         { PCI_VENDOR_ID_ATTO, 0x8070,
1473                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1474         { PCI_VENDOR_ID_ATTO, 0x8072,
1475                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1476         { PCI_VENDOR_ID_ATTO, 0x8072,
1477                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1478         { PCI_VENDOR_ID_ATTO, 0x8070,
1479                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1480         { PCI_VENDOR_ID_ATTO, 0x8072,
1481                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1482         { PCI_VENDOR_ID_ATTO, 0x8072,
1483                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1484         {} /* terminate list */
1485 };
1486
1487 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1488                          pm8001_pci_suspend,
1489                          pm8001_pci_resume);
1490
1491 static struct pci_driver pm8001_pci_driver = {
1492         .name           = DRV_NAME,
1493         .id_table       = pm8001_pci_table,
1494         .probe          = pm8001_pci_probe,
1495         .remove         = pm8001_pci_remove,
1496         .driver.pm      = &pm8001_pci_pm_ops,
1497 };
1498
1499 /**
1500  *      pm8001_init - initialize scsi transport template
1501  */
1502 static int __init pm8001_init(void)
1503 {
1504         int rc = -ENOMEM;
1505
1506         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1507         if (!pm8001_wq)
1508                 goto err;
1509
1510         pm8001_id = 0;
1511         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1512         if (!pm8001_stt)
1513                 goto err_wq;
1514         rc = pci_register_driver(&pm8001_pci_driver);
1515         if (rc)
1516                 goto err_tp;
1517         return 0;
1518
1519 err_tp:
1520         sas_release_transport(pm8001_stt);
1521 err_wq:
1522         destroy_workqueue(pm8001_wq);
1523 err:
1524         return rc;
1525 }
1526
1527 static void __exit pm8001_exit(void)
1528 {
1529         pci_unregister_driver(&pm8001_pci_driver);
1530         sas_release_transport(pm8001_stt);
1531         destroy_workqueue(pm8001_wq);
1532 }
1533
1534 module_init(pm8001_init);
1535 module_exit(pm8001_exit);
1536
1537 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1538 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1539 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1540 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1541 MODULE_DESCRIPTION(
1542                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1543                 "SAS/SATA controller driver");
1544 MODULE_VERSION(DRV_VERSION);
1545 MODULE_LICENSE("GPL");
1546 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1547