drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
  47 module_param(logging_level, ulong, 0644);
  48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  49
  50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  51 module_param(link_rate, ulong, 0644);
  52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  53                 " 1: Link rate 1.5G\n"
  54                 " 2: Link rate 3.0G\n"
  55                 " 4: Link rate 6.0G\n"
  56                 " 8: Link rate 12.0G\n");
  57
  58 static struct scsi_transport_template *pm8001_stt;
  59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
  60
  61 /*
  62  * chip info structure to identify chip key functionality as
  63  * encryption available/not, no of ports, hw specific function ref
  64  */
  65 static const struct pm8001_chip_info pm8001_chips[] = {
  66         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  67         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  68         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  69         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  70         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  71         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  72         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  73         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  75         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  76         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  77 };
  78 static int pm8001_id;
  79
  80 LIST_HEAD(hba_list);
  81
  82 struct workqueue_struct *pm8001_wq;
  83
  84 /*
  85  * The main structure which LLDD must register for scsi core.
  86  */
  87 static struct scsi_host_template pm8001_sht = {
  88         .module                 = THIS_MODULE,
  89         .name                   = DRV_NAME,
  90         .queuecommand           = sas_queuecommand,
  91         .dma_need_drain         = ata_scsi_dma_need_drain,
  92         .target_alloc           = sas_target_alloc,
  93         .slave_configure        = sas_slave_configure,
  94         .scan_finished          = pm8001_scan_finished,
  95         .scan_start             = pm8001_scan_start,
  96         .change_queue_depth     = sas_change_queue_depth,
  97         .bios_param             = sas_bios_param,
  98         .can_queue              = 1,
  99         .this_id                = -1,
 100         .sg_tablesize           = PM8001_MAX_DMA_SG,
 101         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 102         .eh_device_reset_handler = sas_eh_device_reset_handler,
 103         .eh_target_reset_handler = sas_eh_target_reset_handler,
 104         .slave_alloc            = sas_slave_alloc,
 105         .target_destroy         = sas_target_destroy,
 106         .ioctl                  = sas_ioctl,
 107 #ifdef CONFIG_COMPAT
 108         .compat_ioctl           = sas_ioctl,
 109 #endif
 110         .shost_groups           = pm8001_host_groups,
 111         .track_queue_depth      = 1,
 112 };
 113
 114 /*
 115  * Sas layer call this function to execute specific task.
 116  */
 117 static struct sas_domain_function_template pm8001_transport_ops = {
 118         .lldd_dev_found         = pm8001_dev_found,
 119         .lldd_dev_gone          = pm8001_dev_gone,
 120
 121         .lldd_execute_task      = pm8001_queue_command,
 122         .lldd_control_phy       = pm8001_phy_control,
 123
 124         .lldd_abort_task        = pm8001_abort_task,
 125         .lldd_abort_task_set    = sas_abort_task_set,
 126         .lldd_clear_task_set    = pm8001_clear_task_set,
 127         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 128         .lldd_lu_reset          = pm8001_lu_reset,
 129         .lldd_query_task        = pm8001_query_task,
 130         .lldd_port_formed       = pm8001_port_formed,
 131         .lldd_tmf_exec_complete = pm8001_setds_completion,
 132         .lldd_tmf_aborted       = pm8001_tmf_aborted,
 133 };
 134
 135 /**
 136  * pm8001_phy_init - initiate our adapter phys
 137  * @pm8001_ha: our hba structure.
 138  * @phy_id: phy id.
 139  */
 140 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 141 {
 142         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 143         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 144         phy->phy_state = PHY_LINK_DISABLE;
 145         phy->pm8001_ha = pm8001_ha;
 146         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 147         sas_phy->class = SAS;
 148         sas_phy->iproto = SAS_PROTOCOL_ALL;
 149         sas_phy->tproto = 0;
 150         sas_phy->type = PHY_TYPE_PHYSICAL;
 151         sas_phy->role = PHY_ROLE_INITIATOR;
 152         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 153         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 154         sas_phy->id = phy_id;
 155         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 156         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 157         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 158         sas_phy->lldd_phy = phy;
 159 }
 160
 161 /**
 162  * pm8001_free - free hba
 163  * @pm8001_ha:  our hba structure.
 164  */
 165 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 166 {
 167         int i;
 168
 169         if (!pm8001_ha)
 170                 return;
 171
 172         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 173                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 174                         dma_free_coherent(&pm8001_ha->pdev->dev,
 175                                 (pm8001_ha->memoryMap.region[i].total_len +
 176                                 pm8001_ha->memoryMap.region[i].alignment),
 177                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 178                                 pm8001_ha->memoryMap.region[i].phys_addr);
 179                         }
 180         }
 181         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 182         flush_workqueue(pm8001_wq);
 183         bitmap_free(pm8001_ha->tags);
 184         kfree(pm8001_ha);
 185 }
 186
 187 #ifdef PM8001_USE_TASKLET
 188
 189 /**
 190  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
 191  * @opaque: the passed general host adapter struct
 192  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 193  */
 194 static void pm8001_tasklet(unsigned long opaque)
 195 {
 196         struct pm8001_hba_info *pm8001_ha;
 197         struct isr_param *irq_vector;
 198
 199         irq_vector = (struct isr_param *)opaque;
 200         pm8001_ha = irq_vector->drv_inst;
 201         if (unlikely(!pm8001_ha))
 202                 BUG_ON(1);
 203         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 204 }
 205 #endif
 206
 207 /**
 208  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 209  * It obtains the vector number and calls the equivalent bottom
 210  * half or services directly.
 211  * @irq: interrupt number
 212  * @opaque: the passed outbound queue/vector. Host structure is
 213  * retrieved from the same.
 214  */
 215 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 216 {
 217         struct isr_param *irq_vector;
 218         struct pm8001_hba_info *pm8001_ha;
 219         irqreturn_t ret = IRQ_HANDLED;
 220         irq_vector = (struct isr_param *)opaque;
 221         pm8001_ha = irq_vector->drv_inst;
 222
 223         if (unlikely(!pm8001_ha))
 224                 return IRQ_NONE;
 225         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 226                 return IRQ_NONE;
 227 #ifdef PM8001_USE_TASKLET
 228         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 229 #else
 230         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 231 #endif
 232         return ret;
 233 }
 234
 235 /**
 236  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 237  * @irq: interrupt number
 238  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
 239  */
 240
 241 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 242 {
 243         struct pm8001_hba_info *pm8001_ha;
 244         irqreturn_t ret = IRQ_HANDLED;
 245         struct sas_ha_struct *sha = dev_id;
 246         pm8001_ha = sha->lldd_ha;
 247         if (unlikely(!pm8001_ha))
 248                 return IRQ_NONE;
 249         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 250                 return IRQ_NONE;
 251
 252 #ifdef PM8001_USE_TASKLET
 253         tasklet_schedule(&pm8001_ha->tasklet[0]);
 254 #else
 255         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 256 #endif
 257         return ret;
 258 }
 259
 260 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 261 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 262
 263 /**
 264  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 265  * @pm8001_ha: our hba structure.
 266  * @ent: PCI device ID structure to match on
 267  */
 268 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 269                         const struct pci_device_id *ent)
 270 {
 271         int i, count = 0, rc = 0;
 272         u32 ci_offset, ib_offset, ob_offset, pi_offset;
 273         struct inbound_queue_table *ibq;
 274         struct outbound_queue_table *obq;
 275
 276         spin_lock_init(&pm8001_ha->lock);
 277         spin_lock_init(&pm8001_ha->bitmap_lock);
 278         pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
 279                    pm8001_ha->chip->n_phy);
 280
 281         /* Setup Interrupt */
 282         rc = pm8001_setup_irq(pm8001_ha);
 283         if (rc) {
 284                 pm8001_dbg(pm8001_ha, FAIL,
 285                            "pm8001_setup_irq failed [ret: %d]\n", rc);
 286                 goto err_out;
 287         }
 288         /* Request Interrupt */
 289         rc = pm8001_request_irq(pm8001_ha);
 290         if (rc)
 291                 goto err_out;
 292
 293         count = pm8001_ha->max_q_num;
 294         /* Queues are chosen based on the number of cores/msix availability */
 295         ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
 296         ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
 297         ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
 298         pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
 299         pm8001_ha->max_memcnt = pi_offset + count;
 300
 301         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 302                 pm8001_phy_init(pm8001_ha, i);
 303                 pm8001_ha->port[i].wide_port_phymap = 0;
 304                 pm8001_ha->port[i].port_attached = 0;
 305                 pm8001_ha->port[i].port_state = 0;
 306                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 307         }
 308
 309         /* MPI Memory region 1 for AAP Event Log for fw */
 310         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 311         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 312         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 313         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 314
 315         /* MPI Memory region 2 for IOP Event Log for fw */
 316         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 317         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 318         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 319         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 320
 321         for (i = 0; i < count; i++) {
 322                 ibq = &pm8001_ha->inbnd_q_tbl[i];
 323                 spin_lock_init(&ibq->iq_lock);
 324                 /* MPI Memory region 3 for consumer Index of inbound queues */
 325                 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
 326                 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
 327                 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
 328                 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
 329
 330                 if ((ent->driver_data) != chip_8001) {
 331                         /* MPI Memory region 5 inbound queues */
 332                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 333                                                 PM8001_MPI_QUEUE;
 334                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 335                                                                 = 128;
 336                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 337                                                 PM8001_MPI_QUEUE * 128;
 338                         pm8001_ha->memoryMap.region[ib_offset+i].alignment
 339                                                                 = 128;
 340                 } else {
 341                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 342                                                 PM8001_MPI_QUEUE;
 343                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 344                                                                 = 64;
 345                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 346                                                 PM8001_MPI_QUEUE * 64;
 347                         pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
 348                 }
 349         }
 350
 351         for (i = 0; i < count; i++) {
 352                 obq = &pm8001_ha->outbnd_q_tbl[i];
 353                 spin_lock_init(&obq->oq_lock);
 354                 /* MPI Memory region 4 for producer Index of outbound queues */
 355                 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
 356                 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
 357                 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
 358                 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
 359
 360                 if (ent->driver_data != chip_8001) {
 361                         /* MPI Memory region 6 Outbound queues */
 362                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 363                                                 PM8001_MPI_QUEUE;
 364                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 365                                                                 = 128;
 366                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 367                                                 PM8001_MPI_QUEUE * 128;
 368                         pm8001_ha->memoryMap.region[ob_offset+i].alignment
 369                                                                 = 128;
 370                 } else {
 371                         /* MPI Memory region 6 Outbound queues */
 372                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 373                                                 PM8001_MPI_QUEUE;
 374                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 375                                                                 = 64;
 376                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 377                                                 PM8001_MPI_QUEUE * 64;
 378                         pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
 379                 }
 380
 381         }
 382         /* Memory region write DMA*/
 383         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 384         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 385         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 386
 387         /* Memory region for fw flash */
 388         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 389
 390         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 391         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 392         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 393         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 394         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 395                 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
 396
 397                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 398                                      &region->virt_ptr,
 399                                      &region->phys_addr,
 400                                      &region->phys_addr_hi,
 401                                      &region->phys_addr_lo,
 402                                      region->total_len,
 403                                      region->alignment) != 0) {
 404                         pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
 405                         goto err_out;
 406                 }
 407         }
 408
 409         /* Memory region for devices*/
 410         pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
 411                                 * sizeof(struct pm8001_device), GFP_KERNEL);
 412         if (!pm8001_ha->devices) {
 413                 rc = -ENOMEM;
 414                 goto err_out_nodev;
 415         }
 416         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 417                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 418                 pm8001_ha->devices[i].id = i;
 419                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 420                 atomic_set(&pm8001_ha->devices[i].running_req, 0);
 421         }
 422         pm8001_ha->flags = PM8001F_INIT_TIME;
 423         /* Initialize tags */
 424         pm8001_tag_init(pm8001_ha);
 425         return 0;
 426
 427 err_out_nodev:
 428         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 429                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 430                         dma_free_coherent(&pm8001_ha->pdev->dev,
 431                                 (pm8001_ha->memoryMap.region[i].total_len +
 432                                 pm8001_ha->memoryMap.region[i].alignment),
 433                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 434                                 pm8001_ha->memoryMap.region[i].phys_addr);
 435                 }
 436         }
 437 err_out:
 438         return 1;
 439 }
 440
 441 /**
 442  * pm8001_ioremap - remap the pci high physical address to kernel virtual
 443  * address so that we can access them.
 444  * @pm8001_ha: our hba structure.
 445  */
 446 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 447 {
 448         u32 bar;
 449         u32 logicalBar = 0;
 450         struct pci_dev *pdev;
 451
 452         pdev = pm8001_ha->pdev;
 453         /* map pci mem (PMC pci base 0-3)*/
 454         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 455                 /*
 456                 ** logical BARs for SPC:
 457                 ** bar 0 and 1 - logical BAR0
 458                 ** bar 2 and 3 - logical BAR1
 459                 ** bar4 - logical BAR2
 460                 ** bar5 - logical BAR3
 461                 ** Skip the appropriate assignments:
 462                 */
 463                 if ((bar == 1) || (bar == 3))
 464                         continue;
 465                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 466                         pm8001_ha->io_mem[logicalBar].membase =
 467                                 pci_resource_start(pdev, bar);
 468                         pm8001_ha->io_mem[logicalBar].memsize =
 469                                 pci_resource_len(pdev, bar);
 470                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 471                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 472                                 pm8001_ha->io_mem[logicalBar].memsize);
 473                         if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
 474                                 pm8001_dbg(pm8001_ha, INIT,
 475                                         "Failed to ioremap bar %d, logicalBar %d",
 476                                    bar, logicalBar);
 477                                 return -ENOMEM;
 478                         }
 479                         pm8001_dbg(pm8001_ha, INIT,
 480                                    "base addr %llx virt_addr=%llx len=%d\n",
 481                                    (u64)pm8001_ha->io_mem[logicalBar].membase,
 482                                    (u64)(unsigned long)
 483                                    pm8001_ha->io_mem[logicalBar].memvirtaddr,
 484                                    pm8001_ha->io_mem[logicalBar].memsize);
 485                 } else {
 486                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 487                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 488                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 489                 }
 490                 logicalBar++;
 491         }
 492         return 0;
 493 }
 494
 495 /**
 496  * pm8001_pci_alloc - initialize our ha card structure
 497  * @pdev: pci device.
 498  * @ent: ent
 499  * @shost: scsi host struct which has been initialized before.
 500  */
 501 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 502                                  const struct pci_device_id *ent,
 503                                 struct Scsi_Host *shost)
 504
 505 {
 506         struct pm8001_hba_info *pm8001_ha;
 507         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 508         int j;
 509
 510         pm8001_ha = sha->lldd_ha;
 511         if (!pm8001_ha)
 512                 return NULL;
 513
 514         pm8001_ha->pdev = pdev;
 515         pm8001_ha->dev = &pdev->dev;
 516         pm8001_ha->chip_id = ent->driver_data;
 517         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 518         pm8001_ha->irq = pdev->irq;
 519         pm8001_ha->sas = sha;
 520         pm8001_ha->shost = shost;
 521         pm8001_ha->id = pm8001_id++;
 522         pm8001_ha->logging_level = logging_level;
 523         pm8001_ha->non_fatal_count = 0;
 524         if (link_rate >= 1 && link_rate <= 15)
 525                 pm8001_ha->link_rate = (link_rate << 8);
 526         else {
 527                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 528                         LINKRATE_60 | LINKRATE_120;
 529                 pm8001_dbg(pm8001_ha, FAIL,
 530                            "Setting link rate to default value\n");
 531         }
 532         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 533         /* IOMB size is 128 for 8088/89 controllers */
 534         if (pm8001_ha->chip_id != chip_8001)
 535                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 536         else
 537                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 538
 539 #ifdef PM8001_USE_TASKLET
 540         /* Tasklet for non msi-x interrupt handler */
 541         if ((!pdev->msix_cap || !pci_msi_enabled())
 542             || (pm8001_ha->chip_id == chip_8001))
 543                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 544                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 545         else
 546                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 547                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 548                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 549 #endif
 550         if (pm8001_ioremap(pm8001_ha))
 551                 goto failed_pci_alloc;
 552         if (!pm8001_alloc(pm8001_ha, ent))
 553                 return pm8001_ha;
 554 failed_pci_alloc:
 555         pm8001_free(pm8001_ha);
 556         return NULL;
 557 }
 558
 559 /**
 560  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 561  * @pdev: pci device.
 562  */
 563 static int pci_go_44(struct pci_dev *pdev)
 564 {
 565         int rc;
 566
 567         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 568         if (rc) {
 569                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 570                 if (rc)
 571                         dev_printk(KERN_ERR, &pdev->dev,
 572                                 "32-bit DMA enable failed\n");
 573         }
 574         return rc;
 575 }
 576
 577 /**
 578  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 579  * @shost: scsi host which has been allocated outside.
 580  * @chip_info: our ha struct.
 581  */
 582 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 583                                    const struct pm8001_chip_info *chip_info)
 584 {
 585         int phy_nr, port_nr;
 586         struct asd_sas_phy **arr_phy;
 587         struct asd_sas_port **arr_port;
 588         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 589
 590         phy_nr = chip_info->n_phy;
 591         port_nr = phy_nr;
 592         memset(sha, 0x00, sizeof(*sha));
 593         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 594         if (!arr_phy)
 595                 goto exit;
 596         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 597         if (!arr_port)
 598                 goto exit_free2;
 599
 600         sha->sas_phy = arr_phy;
 601         sha->sas_port = arr_port;
 602         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 603         if (!sha->lldd_ha)
 604                 goto exit_free1;
 605
 606         shost->transportt = pm8001_stt;
 607         shost->max_id = PM8001_MAX_DEVICES;
 608         shost->max_lun = 8;
 609         shost->max_channel = 0;
 610         shost->unique_id = pm8001_id;
 611         shost->max_cmd_len = 16;
 612         shost->can_queue = PM8001_CAN_QUEUE;
 613         shost->cmd_per_lun = 32;
 614         return 0;
 615 exit_free1:
 616         kfree(arr_port);
 617 exit_free2:
 618         kfree(arr_phy);
 619 exit:
 620         return -1;
 621 }
 622
 623 /**
 624  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 625  * @shost: scsi host which has been allocated outside
 626  * @chip_info: our ha struct.
 627  */
 628 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 629                                      const struct pm8001_chip_info *chip_info)
 630 {
 631         int i = 0;
 632         struct pm8001_hba_info *pm8001_ha;
 633         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 634
 635         pm8001_ha = sha->lldd_ha;
 636         for (i = 0; i < chip_info->n_phy; i++) {
 637                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 638                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 639                 sha->sas_phy[i]->sas_addr =
 640                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 641         }
 642         sha->sas_ha_name = DRV_NAME;
 643         sha->dev = pm8001_ha->dev;
 644         sha->strict_wide_ports = 1;
 645         sha->lldd_module = THIS_MODULE;
 646         sha->sas_addr = &pm8001_ha->sas_addr[0];
 647         sha->num_phys = chip_info->n_phy;
 648         sha->core.shost = shost;
 649 }
 650
 651 /**
 652  * pm8001_init_sas_add - initialize sas address
 653  * @pm8001_ha: our ha struct.
 654  *
 655  * Currently we just set the fixed SAS address to our HBA, for manufacture,
 656  * it should read from the EEPROM
 657  */
 658 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 659 {
 660         u8 i, j;
 661         u8 sas_add[8];
 662 #ifdef PM8001_READ_VPD
 663         /* For new SPC controllers WWN is stored in flash vpd
 664         *  For SPC/SPCve controllers WWN is stored in EEPROM
 665         *  For Older SPC WWN is stored in NVMD
 666         */
 667         DECLARE_COMPLETION_ONSTACK(completion);
 668         struct pm8001_ioctl_payload payload;
 669         u16 deviceid;
 670         int rc;
 671
 672         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 673         pm8001_ha->nvmd_completion = &completion;
 674
 675         if (pm8001_ha->chip_id == chip_8001) {
 676                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 677                         payload.minor_function = 4;
 678                         payload.rd_length = 4096;
 679                 } else {
 680                         payload.minor_function = 0;
 681                         payload.rd_length = 128;
 682                 }
 683         } else if ((pm8001_ha->chip_id == chip_8070 ||
 684                         pm8001_ha->chip_id == chip_8072) &&
 685                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 686                 payload.minor_function = 4;
 687                 payload.rd_length = 4096;
 688         } else {
 689                 payload.minor_function = 1;
 690                 payload.rd_length = 4096;
 691         }
 692         payload.offset = 0;
 693         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 694         if (!payload.func_specific) {
 695                 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
 696                 return;
 697         }
 698         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 699         if (rc) {
 700                 kfree(payload.func_specific);
 701                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 702                 return;
 703         }
 704         wait_for_completion(&completion);
 705
 706         for (i = 0, j = 0; i <= 7; i++, j++) {
 707                 if (pm8001_ha->chip_id == chip_8001) {
 708                         if (deviceid == 0x8081)
 709                                 pm8001_ha->sas_addr[j] =
 710                                         payload.func_specific[0x704 + i];
 711                         else if (deviceid == 0x0042)
 712                                 pm8001_ha->sas_addr[j] =
 713                                         payload.func_specific[0x010 + i];
 714                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 715                                 pm8001_ha->chip_id == chip_8072) &&
 716                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 717                         pm8001_ha->sas_addr[j] =
 718                                         payload.func_specific[0x010 + i];
 719                 } else
 720                         pm8001_ha->sas_addr[j] =
 721                                         payload.func_specific[0x804 + i];
 722         }
 723         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 724         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 725                 if (i && ((i % 4) == 0))
 726                         sas_add[7] = sas_add[7] + 4;
 727                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 728                         sas_add, SAS_ADDR_SIZE);
 729                 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
 730                            pm8001_ha->phy[i].dev_sas_addr);
 731         }
 732         kfree(payload.func_specific);
 733 #else
 734         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 735                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 736                 pm8001_ha->phy[i].dev_sas_addr =
 737                         cpu_to_be64((u64)
 738                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 739         }
 740         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 741                 SAS_ADDR_SIZE);
 742 #endif
 743 }
 744
 745 /*
 746  * pm8001_get_phy_settings_info : Read phy setting values.
 747  * @pm8001_ha : our hba.
 748  */
 749 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 750 {
 751
 752 #ifdef PM8001_READ_VPD
 753         /*OPTION ROM FLASH read for the SPC cards */
 754         DECLARE_COMPLETION_ONSTACK(completion);
 755         struct pm8001_ioctl_payload payload;
 756         int rc;
 757
 758         pm8001_ha->nvmd_completion = &completion;
 759         /* SAS ADDRESS read from flash / EEPROM */
 760         payload.minor_function = 6;
 761         payload.offset = 0;
 762         payload.rd_length = 4096;
 763         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 764         if (!payload.func_specific)
 765                 return -ENOMEM;
 766         /* Read phy setting values from flash */
 767         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 768         if (rc) {
 769                 kfree(payload.func_specific);
 770                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 771                 return -ENOMEM;
 772         }
 773         wait_for_completion(&completion);
 774         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 775         kfree(payload.func_specific);
 776 #endif
 777         return 0;
 778 }
 779
 780 struct pm8001_mpi3_phy_pg_trx_config {
 781         u32 LaneLosCfg;
 782         u32 LanePgaCfg1;
 783         u32 LanePisoCfg1;
 784         u32 LanePisoCfg2;
 785         u32 LanePisoCfg3;
 786         u32 LanePisoCfg4;
 787         u32 LanePisoCfg5;
 788         u32 LanePisoCfg6;
 789         u32 LaneBctCtrl;
 790 };
 791
 792 /**
 793  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
 794  * @pm8001_ha : our adapter
 795  * @phycfg : PHY config page to populate
 796  */
 797 static
 798 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 799                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 800 {
 801         phycfg->LaneLosCfg   = 0x00000132;
 802         phycfg->LanePgaCfg1  = 0x00203949;
 803         phycfg->LanePisoCfg1 = 0x000000FF;
 804         phycfg->LanePisoCfg2 = 0xFF000001;
 805         phycfg->LanePisoCfg3 = 0xE7011300;
 806         phycfg->LanePisoCfg4 = 0x631C40C0;
 807         phycfg->LanePisoCfg5 = 0xF8102036;
 808         phycfg->LanePisoCfg6 = 0xF74A1000;
 809         phycfg->LaneBctCtrl  = 0x00FB33F8;
 810 }
 811
 812 /**
 813  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
 814  * @pm8001_ha : our adapter
 815  * @phycfg : PHY config page to populate
 816  */
 817 static
 818 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 819                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 820 {
 821         phycfg->LaneLosCfg   = 0x00000132;
 822         phycfg->LanePgaCfg1  = 0x00203949;
 823         phycfg->LanePisoCfg1 = 0x000000FF;
 824         phycfg->LanePisoCfg2 = 0xFF000001;
 825         phycfg->LanePisoCfg3 = 0xE7011300;
 826         phycfg->LanePisoCfg4 = 0x63349140;
 827         phycfg->LanePisoCfg5 = 0xF8102036;
 828         phycfg->LanePisoCfg6 = 0xF80D9300;
 829         phycfg->LaneBctCtrl  = 0x00FB33F8;
 830 }
 831
 832 /**
 833  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
 834  * @pm8001_ha : our adapter
 835  * @phymask : The PHY mask
 836  */
 837 static
 838 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 839 {
 840         switch (pm8001_ha->pdev->subsystem_device) {
 841         case 0x0070: /* H1280 - 8 external 0 internal */
 842         case 0x0072: /* H12F0 - 16 external 0 internal */
 843                 *phymask = 0x0000;
 844                 break;
 845
 846         case 0x0071: /* H1208 - 0 external 8 internal */
 847         case 0x0073: /* H120F - 0 external 16 internal */
 848                 *phymask = 0xFFFF;
 849                 break;
 850
 851         case 0x0080: /* H1244 - 4 external 4 internal */
 852                 *phymask = 0x00F0;
 853                 break;
 854
 855         case 0x0081: /* H1248 - 4 external 8 internal */
 856                 *phymask = 0x0FF0;
 857                 break;
 858
 859         case 0x0082: /* H1288 - 8 external 8 internal */
 860                 *phymask = 0xFF00;
 861                 break;
 862
 863         default:
 864                 pm8001_dbg(pm8001_ha, INIT,
 865                            "Unknown subsystem device=0x%.04x\n",
 866                            pm8001_ha->pdev->subsystem_device);
 867         }
 868 }
 869
 870 /**
 871  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
 872  * @pm8001_ha : our adapter
 873  */
 874 static
 875 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 876 {
 877         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 878         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 879         int phymask = 0;
 880         int i = 0;
 881
 882         memset(&phycfg_int, 0, sizeof(phycfg_int));
 883         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 884
 885         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 886         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 887         pm8001_get_phy_mask(pm8001_ha, &phymask);
 888
 889         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 890                 if (phymask & (1 << i)) {/* Internal PHY */
 891                         pm8001_set_phy_profile_single(pm8001_ha, i,
 892                                         sizeof(phycfg_int) / sizeof(u32),
 893                                         (u32 *)&phycfg_int);
 894
 895                 } else { /* External PHY */
 896                         pm8001_set_phy_profile_single(pm8001_ha, i,
 897                                         sizeof(phycfg_ext) / sizeof(u32),
 898                                         (u32 *)&phycfg_ext);
 899                 }
 900         }
 901
 902         return 0;
 903 }
 904
 905 /**
 906  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
 907  * @pm8001_ha : our hba.
 908  */
 909 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 910 {
 911         switch (pm8001_ha->pdev->subsystem_vendor) {
 912         case PCI_VENDOR_ID_ATTO:
 913                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 914                         return 0;
 915                 else
 916                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 917
 918         case PCI_VENDOR_ID_ADAPTEC2:
 919         case 0:
 920                 return 0;
 921
 922         default:
 923                 return pm8001_get_phy_settings_info(pm8001_ha);
 924         }
 925 }
 926
 927 #ifdef PM8001_USE_MSIX
 928 /**
 929  * pm8001_setup_msix - enable MSI-X interrupt
 930  * @pm8001_ha: our ha struct.
 931  */
 932 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 933 {
 934         u32 number_of_intr;
 935         int rc, cpu_online_count;
 936         unsigned int allocated_irq_vectors;
 937
 938         /* SPCv controllers supports 64 msi-x */
 939         if (pm8001_ha->chip_id == chip_8001) {
 940                 number_of_intr = 1;
 941         } else {
 942                 number_of_intr = PM8001_MAX_MSIX_VEC;
 943         }
 944
 945         cpu_online_count = num_online_cpus();
 946         number_of_intr = min_t(int, cpu_online_count, number_of_intr);
 947         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 948                         number_of_intr, PCI_IRQ_MSIX);
 949         allocated_irq_vectors = rc;
 950         if (rc < 0)
 951                 return rc;
 952
 953         /* Assigns the number of interrupts */
 954         number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
 955         pm8001_ha->number_of_intr = number_of_intr;
 956
 957         /* Maximum queue number updating in HBA structure */
 958         pm8001_ha->max_q_num = number_of_intr;
 959
 960         pm8001_dbg(pm8001_ha, INIT,
 961                    "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 962                    rc, pm8001_ha->number_of_intr);
 963         return 0;
 964 }
 965
 966 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 967 {
 968         u32 i = 0, j = 0;
 969         int flag = 0, rc = 0;
 970         int nr_irqs = pm8001_ha->number_of_intr;
 971
 972         if (pm8001_ha->chip_id != chip_8001)
 973                 flag &= ~IRQF_SHARED;
 974
 975         pm8001_dbg(pm8001_ha, INIT,
 976                    "pci_enable_msix request number of intr %d\n",
 977                    pm8001_ha->number_of_intr);
 978
 979         if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
 980                 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
 981
 982         for (i = 0; i < nr_irqs; i++) {
 983                 snprintf(pm8001_ha->intr_drvname[i],
 984                         sizeof(pm8001_ha->intr_drvname[0]),
 985                         "%s-%d", pm8001_ha->name, i);
 986                 pm8001_ha->irq_vector[i].irq_id = i;
 987                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 988
 989                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 990                         pm8001_interrupt_handler_msix, flag,
 991                         pm8001_ha->intr_drvname[i],
 992                         &(pm8001_ha->irq_vector[i]));
 993                 if (rc) {
 994                         for (j = 0; j < i; j++) {
 995                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 996                                         &(pm8001_ha->irq_vector[i]));
 997                         }
 998                         pci_free_irq_vectors(pm8001_ha->pdev);
 999                         break;
1000                 }
1001         }
1002
1003         return rc;
1004 }
1005 #endif
1006
1007 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1008 {
1009         struct pci_dev *pdev;
1010
1011         pdev = pm8001_ha->pdev;
1012
1013 #ifdef PM8001_USE_MSIX
1014         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1015                 return pm8001_setup_msix(pm8001_ha);
1016         pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1017 #endif
1018         return 0;
1019 }
1020
1021 /**
1022  * pm8001_request_irq - register interrupt
1023  * @pm8001_ha: our ha struct.
1024  */
1025 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1026 {
1027         struct pci_dev *pdev;
1028         int rc;
1029
1030         pdev = pm8001_ha->pdev;
1031
1032 #ifdef PM8001_USE_MSIX
1033         if (pdev->msix_cap && pci_msi_enabled())
1034                 return pm8001_request_msix(pm8001_ha);
1035         else {
1036                 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1037                 goto intx;
1038         }
1039 #endif
1040
1041 intx:
1042         /* initialize the INT-X interrupt */
1043         pm8001_ha->irq_vector[0].irq_id = 0;
1044         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1045         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1046                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1047         return rc;
1048 }
1049
1050 /**
1051  * pm8001_pci_probe - probe supported device
1052  * @pdev: pci device which kernel has been prepared for.
1053  * @ent: pci device id
1054  *
1055  * This function is the main initialization function, when register a new
1056  * pci driver it is invoked, all struct and hardware initialization should be
1057  * done here, also, register interrupt.
1058  */
1059 static int pm8001_pci_probe(struct pci_dev *pdev,
1060                             const struct pci_device_id *ent)
1061 {
1062         unsigned int rc;
1063         u32     pci_reg;
1064         u8      i = 0;
1065         struct pm8001_hba_info *pm8001_ha;
1066         struct Scsi_Host *shost = NULL;
1067         const struct pm8001_chip_info *chip;
1068         struct sas_ha_struct *sha;
1069
1070         dev_printk(KERN_INFO, &pdev->dev,
1071                 "pm80xx: driver version %s\n", DRV_VERSION);
1072         rc = pci_enable_device(pdev);
1073         if (rc)
1074                 goto err_out_enable;
1075         pci_set_master(pdev);
1076         /*
1077          * Enable pci slot busmaster by setting pci command register.
1078          * This is required by FW for Cyclone card.
1079          */
1080
1081         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1082         pci_reg |= 0x157;
1083         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1084         rc = pci_request_regions(pdev, DRV_NAME);
1085         if (rc)
1086                 goto err_out_disable;
1087         rc = pci_go_44(pdev);
1088         if (rc)
1089                 goto err_out_regions;
1090
1091         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1092         if (!shost) {
1093                 rc = -ENOMEM;
1094                 goto err_out_regions;
1095         }
1096         chip = &pm8001_chips[ent->driver_data];
1097         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1098         if (!sha) {
1099                 rc = -ENOMEM;
1100                 goto err_out_free_host;
1101         }
1102         SHOST_TO_SAS_HA(shost) = sha;
1103
1104         rc = pm8001_prep_sas_ha_init(shost, chip);
1105         if (rc) {
1106                 rc = -ENOMEM;
1107                 goto err_out_free;
1108         }
1109         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1110         /* ent->driver variable is used to differentiate between controllers */
1111         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1112         if (!pm8001_ha) {
1113                 rc = -ENOMEM;
1114                 goto err_out_free;
1115         }
1116
1117         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1118         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1119         if (rc) {
1120                 pm8001_dbg(pm8001_ha, FAIL,
1121                            "chip_init failed [ret: %d]\n", rc);
1122                 goto err_out_ha_free;
1123         }
1124
1125         rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1126         if (rc)
1127                 goto err_out_enable;
1128
1129         rc = scsi_add_host(shost, &pdev->dev);
1130         if (rc)
1131                 goto err_out_ha_free;
1132
1133         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1134         if (pm8001_ha->chip_id != chip_8001) {
1135                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1136                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1137                 /* setup thermal configuration. */
1138                 pm80xx_set_thermal_config(pm8001_ha);
1139         }
1140
1141         pm8001_init_sas_add(pm8001_ha);
1142         /* phy setting support for motherboard controller */
1143         rc = pm8001_configure_phy_settings(pm8001_ha);
1144         if (rc)
1145                 goto err_out_shost;
1146
1147         pm8001_post_sas_ha_init(shost, chip);
1148         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1149         if (rc) {
1150                 pm8001_dbg(pm8001_ha, FAIL,
1151                            "sas_register_ha failed [ret: %d]\n", rc);
1152                 goto err_out_shost;
1153         }
1154         list_add_tail(&pm8001_ha->list, &hba_list);
1155         pm8001_ha->flags = PM8001F_RUN_TIME;
1156         scsi_scan_host(pm8001_ha->shost);
1157         return 0;
1158
1159 err_out_shost:
1160         scsi_remove_host(pm8001_ha->shost);
1161 err_out_ha_free:
1162         pm8001_free(pm8001_ha);
1163 err_out_free:
1164         kfree(sha);
1165 err_out_free_host:
1166         scsi_host_put(shost);
1167 err_out_regions:
1168         pci_release_regions(pdev);
1169 err_out_disable:
1170         pci_disable_device(pdev);
1171 err_out_enable:
1172         return rc;
1173 }
1174
1175 /**
1176  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1177  * @pm8001_ha: our hba card information.
1178  * @shost: scsi host which has been allocated outside.
1179  * @pdev: pci device.
1180  */
1181 static int
1182 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1183                         struct pci_dev *pdev)
1184 {
1185         int i = 0;
1186         u32 max_out_io, ccb_count;
1187         u32 can_queue;
1188
1189         max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1190         ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1191
1192         /* Update to the scsi host*/
1193         can_queue = ccb_count - PM8001_RESERVE_SLOT;
1194         shost->can_queue = can_queue;
1195
1196         pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL);
1197         if (!pm8001_ha->tags)
1198                 goto err_out;
1199
1200         /* Memory region for ccb_info*/
1201         pm8001_ha->ccb_count = ccb_count;
1202         pm8001_ha->ccb_info =
1203                 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1204         if (!pm8001_ha->ccb_info) {
1205                 pm8001_dbg(pm8001_ha, FAIL,
1206                            "Unable to allocate memory for ccb\n");
1207                 goto err_out_noccb;
1208         }
1209         for (i = 0; i < ccb_count; i++) {
1210                 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev,
1211                                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1212                                 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1213                                 GFP_KERNEL);
1214                 if (!pm8001_ha->ccb_info[i].buf_prd) {
1215                         pm8001_dbg(pm8001_ha, FAIL,
1216                                    "ccb prd memory allocation error\n");
1217                         goto err_out;
1218                 }
1219                 pm8001_ha->ccb_info[i].task = NULL;
1220                 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1221                 pm8001_ha->ccb_info[i].device = NULL;
1222                 ++pm8001_ha->tags_num;
1223         }
1224
1225         return 0;
1226
1227 err_out_noccb:
1228         kfree(pm8001_ha->devices);
1229 err_out:
1230         return -ENOMEM;
1231 }
1232
1233 static void pm8001_pci_remove(struct pci_dev *pdev)
1234 {
1235         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1236         struct pm8001_hba_info *pm8001_ha;
1237         int i, j;
1238         pm8001_ha = sha->lldd_ha;
1239         sas_unregister_ha(sha);
1240         sas_remove_host(pm8001_ha->shost);
1241         list_del(&pm8001_ha->list);
1242         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1243         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1244
1245 #ifdef PM8001_USE_MSIX
1246         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1247                 synchronize_irq(pci_irq_vector(pdev, i));
1248         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1249                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1250         pci_free_irq_vectors(pdev);
1251 #else
1252         free_irq(pm8001_ha->irq, sha);
1253 #endif
1254 #ifdef PM8001_USE_TASKLET
1255         /* For non-msix and msix interrupts */
1256         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1257             (pm8001_ha->chip_id == chip_8001))
1258                 tasklet_kill(&pm8001_ha->tasklet[0]);
1259         else
1260                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1261                         tasklet_kill(&pm8001_ha->tasklet[j]);
1262 #endif
1263         scsi_host_put(pm8001_ha->shost);
1264
1265         for (i = 0; i < pm8001_ha->ccb_count; i++) {
1266                 dma_free_coherent(&pm8001_ha->pdev->dev,
1267                         sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1268                         pm8001_ha->ccb_info[i].buf_prd,
1269                         pm8001_ha->ccb_info[i].ccb_dma_handle);
1270         }
1271         kfree(pm8001_ha->ccb_info);
1272         kfree(pm8001_ha->devices);
1273
1274         pm8001_free(pm8001_ha);
1275         kfree(sha->sas_phy);
1276         kfree(sha->sas_port);
1277         kfree(sha);
1278         pci_release_regions(pdev);
1279         pci_disable_device(pdev);
1280 }
1281
1282 /**
1283  * pm8001_pci_suspend - power management suspend main entry point
1284  * @dev: Device struct
1285  *
1286  * Return: 0 on success, anything else on error.
1287  */
1288 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1289 {
1290         struct pci_dev *pdev = to_pci_dev(dev);
1291         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1292         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1293         int  i, j;
1294         sas_suspend_ha(sha);
1295         flush_workqueue(pm8001_wq);
1296         scsi_block_requests(pm8001_ha->shost);
1297         if (!pdev->pm_cap) {
1298                 dev_err(dev, " PCI PM not supported\n");
1299                 return -ENODEV;
1300         }
1301         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1302         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1303 #ifdef PM8001_USE_MSIX
1304         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1305                 synchronize_irq(pci_irq_vector(pdev, i));
1306         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1307                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1308         pci_free_irq_vectors(pdev);
1309 #else
1310         free_irq(pm8001_ha->irq, sha);
1311 #endif
1312 #ifdef PM8001_USE_TASKLET
1313         /* For non-msix and msix interrupts */
1314         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1315             (pm8001_ha->chip_id == chip_8001))
1316                 tasklet_kill(&pm8001_ha->tasklet[0]);
1317         else
1318                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1319                         tasklet_kill(&pm8001_ha->tasklet[j]);
1320 #endif
1321         pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1322                       "suspended state\n", pdev,
1323                       pm8001_ha->name);
1324         return 0;
1325 }
1326
1327 /**
1328  * pm8001_pci_resume - power management resume main entry point
1329  * @dev: Device struct
1330  *
1331  * Return: 0 on success, anything else on error.
1332  */
1333 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1334 {
1335         struct pci_dev *pdev = to_pci_dev(dev);
1336         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1337         struct pm8001_hba_info *pm8001_ha;
1338         int rc;
1339         u8 i = 0, j;
1340         DECLARE_COMPLETION_ONSTACK(completion);
1341
1342         pm8001_ha = sha->lldd_ha;
1343
1344         pm8001_info(pm8001_ha,
1345                     "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1346                     pdev, pm8001_ha->name, pdev->current_state);
1347
1348         rc = pci_go_44(pdev);
1349         if (rc)
1350                 goto err_out_disable;
1351         sas_prep_resume_ha(sha);
1352         /* chip soft rst only for spc */
1353         if (pm8001_ha->chip_id == chip_8001) {
1354                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1355                 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1356         }
1357         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1358         if (rc)
1359                 goto err_out_disable;
1360
1361         /* disable all the interrupt bits */
1362         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1363
1364         rc = pm8001_request_irq(pm8001_ha);
1365         if (rc)
1366                 goto err_out_disable;
1367 #ifdef PM8001_USE_TASKLET
1368         /*  Tasklet for non msi-x interrupt handler */
1369         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1370             (pm8001_ha->chip_id == chip_8001))
1371                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1372                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1373         else
1374                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1375                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1376                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1377 #endif
1378         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1379         if (pm8001_ha->chip_id != chip_8001) {
1380                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1381                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1382         }
1383
1384         /* Chip documentation for the 8070 and 8072 SPCv    */
1385         /* states that a 500ms minimum delay is required    */
1386         /* before issuing commands. Otherwise, the firmware */
1387         /* will enter an unrecoverable state.               */
1388
1389         if (pm8001_ha->chip_id == chip_8070 ||
1390                 pm8001_ha->chip_id == chip_8072) {
1391                 mdelay(500);
1392         }
1393
1394         /* Spin up the PHYs */
1395
1396         pm8001_ha->flags = PM8001F_RUN_TIME;
1397         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1398                 pm8001_ha->phy[i].enable_completion = &completion;
1399                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1400                 wait_for_completion(&completion);
1401         }
1402         sas_resume_ha(sha);
1403         return 0;
1404
1405 err_out_disable:
1406         scsi_remove_host(pm8001_ha->shost);
1407
1408         return rc;
1409 }
1410
1411 /* update of pci device, vendor id and driver data with
1412  * unique value for each of the controller
1413  */
1414 static struct pci_device_id pm8001_pci_table[] = {
1415         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1416         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1417         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1418         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1419         /* Support for SPC/SPCv/SPCve controllers */
1420         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1421         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1422         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1423         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1424         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1425         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1426         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1427         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1428         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1429         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1430         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1431         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1432         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1433         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1434         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1435         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1436                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1437         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1438                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1439         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1440                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1441         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1442                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1443         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1444                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1445         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1446                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1447         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1448                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1449         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1450                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1451         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1452                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1453         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1454                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1455         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1456                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1457         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1458                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1459         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1460                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1461         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1462                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1463         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1464                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1465         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1466                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1467         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1468                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1469         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1470                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1471         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1472                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1473         { PCI_VENDOR_ID_ATTO, 0x8070,
1474                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1475         { PCI_VENDOR_ID_ATTO, 0x8070,
1476                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1477         { PCI_VENDOR_ID_ATTO, 0x8072,
1478                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1479         { PCI_VENDOR_ID_ATTO, 0x8072,
1480                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1481         { PCI_VENDOR_ID_ATTO, 0x8070,
1482                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1483         { PCI_VENDOR_ID_ATTO, 0x8072,
1484                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1485         { PCI_VENDOR_ID_ATTO, 0x8072,
1486                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1487         {} /* terminate list */
1488 };
1489
1490 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1491                          pm8001_pci_suspend,
1492                          pm8001_pci_resume);
1493
1494 static struct pci_driver pm8001_pci_driver = {
1495         .name           = DRV_NAME,
1496         .id_table       = pm8001_pci_table,
1497         .probe          = pm8001_pci_probe,
1498         .remove         = pm8001_pci_remove,
1499         .driver.pm      = &pm8001_pci_pm_ops,
1500 };
1501
1502 /**
1503  *      pm8001_init - initialize scsi transport template
1504  */
1505 static int __init pm8001_init(void)
1506 {
1507         int rc = -ENOMEM;
1508
1509         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1510         if (!pm8001_wq)
1511                 goto err;
1512
1513         pm8001_id = 0;
1514         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1515         if (!pm8001_stt)
1516                 goto err_wq;
1517         rc = pci_register_driver(&pm8001_pci_driver);
1518         if (rc)
1519                 goto err_tp;
1520         return 0;
1521
1522 err_tp:
1523         sas_release_transport(pm8001_stt);
1524 err_wq:
1525         destroy_workqueue(pm8001_wq);
1526 err:
1527         return rc;
1528 }
1529
1530 static void __exit pm8001_exit(void)
1531 {
1532         pci_unregister_driver(&pm8001_pci_driver);
1533         sas_release_transport(pm8001_stt);
1534         destroy_workqueue(pm8001_wq);
1535 }
1536
1537 module_init(pm8001_init);
1538 module_exit(pm8001_exit);
1539
1540 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1541 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1542 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1543 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1544 MODULE_DESCRIPTION(
1545                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1546                 "SAS/SATA controller driver");
1547 MODULE_VERSION(DRV_VERSION);
1548 MODULE_LICENSE("GPL");
1549 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1550