drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44
  45 static struct scsi_transport_template *pm8001_stt;
  46
  47 /**
  48  * chip info structure to identify chip key functionality as
  49  * encryption available/not, no of ports, hw specific function ref
  50  */
  51 static const struct pm8001_chip_info pm8001_chips[] = {
  52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  60         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  61         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  62         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  63 };
  64 static int pm8001_id;
  65
  66 LIST_HEAD(hba_list);
  67
  68 struct workqueue_struct *pm8001_wq;
  69
  70 /**
  71  * The main structure which LLDD must register for scsi core.
  72  */
  73 static struct scsi_host_template pm8001_sht = {
  74         .module                 = THIS_MODULE,
  75         .name                   = DRV_NAME,
  76         .queuecommand           = sas_queuecommand,
  77         .target_alloc           = sas_target_alloc,
  78         .slave_configure        = sas_slave_configure,
  79         .scan_finished          = pm8001_scan_finished,
  80         .scan_start             = pm8001_scan_start,
  81         .change_queue_depth     = sas_change_queue_depth,
  82         .bios_param             = sas_bios_param,
  83         .can_queue              = 1,
  84         .this_id                = -1,
  85         .sg_tablesize           = SG_ALL,
  86         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  87         .use_clustering         = ENABLE_CLUSTERING,
  88         .eh_device_reset_handler = sas_eh_device_reset_handler,
  89         .eh_target_reset_handler = sas_eh_target_reset_handler,
  90         .slave_alloc            = sas_slave_alloc,
  91         .target_destroy         = sas_target_destroy,
  92         .ioctl                  = sas_ioctl,
  93         .shost_attrs            = pm8001_host_attrs,
  94         .track_queue_depth      = 1,
  95 };
  96
  97 /**
  98  * Sas layer call this function to execute specific task.
  99  */
 100 static struct sas_domain_function_template pm8001_transport_ops = {
 101         .lldd_dev_found         = pm8001_dev_found,
 102         .lldd_dev_gone          = pm8001_dev_gone,
 103
 104         .lldd_execute_task      = pm8001_queue_command,
 105         .lldd_control_phy       = pm8001_phy_control,
 106
 107         .lldd_abort_task        = pm8001_abort_task,
 108         .lldd_abort_task_set    = pm8001_abort_task_set,
 109         .lldd_clear_aca         = pm8001_clear_aca,
 110         .lldd_clear_task_set    = pm8001_clear_task_set,
 111         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 112         .lldd_lu_reset          = pm8001_lu_reset,
 113         .lldd_query_task        = pm8001_query_task,
 114 };
 115
 116 /**
 117  *pm8001_phy_init - initiate our adapter phys
 118  *@pm8001_ha: our hba structure.
 119  *@phy_id: phy id.
 120  */
 121 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 122 {
 123         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 124         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 125         phy->phy_state = 0;
 126         phy->pm8001_ha = pm8001_ha;
 127         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 128         sas_phy->class = SAS;
 129         sas_phy->iproto = SAS_PROTOCOL_ALL;
 130         sas_phy->tproto = 0;
 131         sas_phy->type = PHY_TYPE_PHYSICAL;
 132         sas_phy->role = PHY_ROLE_INITIATOR;
 133         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 134         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 135         sas_phy->id = phy_id;
 136         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 137         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 138         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 139         sas_phy->lldd_phy = phy;
 140 }
 141
 142 /**
 143  *pm8001_free - free hba
 144  *@pm8001_ha:   our hba structure.
 145  *
 146  */
 147 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 148 {
 149         int i;
 150
 151         if (!pm8001_ha)
 152                 return;
 153
 154         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 155                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 156                         pci_free_consistent(pm8001_ha->pdev,
 157                                 (pm8001_ha->memoryMap.region[i].total_len +
 158                                 pm8001_ha->memoryMap.region[i].alignment),
 159                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 160                                 pm8001_ha->memoryMap.region[i].phys_addr);
 161                         }
 162         }
 163         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 164         flush_workqueue(pm8001_wq);
 165         kfree(pm8001_ha->tags);
 166         kfree(pm8001_ha);
 167 }
 168
 169 #ifdef PM8001_USE_TASKLET
 170
 171 /**
 172  * tasklet for 64 msi-x interrupt handler
 173  * @opaque: the passed general host adapter struct
 174  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 175  */
 176 static void pm8001_tasklet(unsigned long opaque)
 177 {
 178         struct pm8001_hba_info *pm8001_ha;
 179         struct isr_param *irq_vector;
 180
 181         irq_vector = (struct isr_param *)opaque;
 182         pm8001_ha = irq_vector->drv_inst;
 183         if (unlikely(!pm8001_ha))
 184                 BUG_ON(1);
 185         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 186 }
 187 #endif
 188
 189 /**
 190  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 191  * It obtains the vector number and calls the equivalent bottom
 192  * half or services directly.
 193  * @opaque: the passed outbound queue/vector. Host structure is
 194  * retrieved from the same.
 195  */
 196 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 197 {
 198         struct isr_param *irq_vector;
 199         struct pm8001_hba_info *pm8001_ha;
 200         irqreturn_t ret = IRQ_HANDLED;
 201         irq_vector = (struct isr_param *)opaque;
 202         pm8001_ha = irq_vector->drv_inst;
 203
 204         if (unlikely(!pm8001_ha))
 205                 return IRQ_NONE;
 206         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 207                 return IRQ_NONE;
 208 #ifdef PM8001_USE_TASKLET
 209         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 210 #else
 211         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 212 #endif
 213         return ret;
 214 }
 215
 216 /**
 217  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 218  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 219  */
 220
 221 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 222 {
 223         struct pm8001_hba_info *pm8001_ha;
 224         irqreturn_t ret = IRQ_HANDLED;
 225         struct sas_ha_struct *sha = dev_id;
 226         pm8001_ha = sha->lldd_ha;
 227         if (unlikely(!pm8001_ha))
 228                 return IRQ_NONE;
 229         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 230                 return IRQ_NONE;
 231
 232 #ifdef PM8001_USE_TASKLET
 233         tasklet_schedule(&pm8001_ha->tasklet[0]);
 234 #else
 235         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 236 #endif
 237         return ret;
 238 }
 239
 240 /**
 241  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 242  * @pm8001_ha:our hba structure.
 243  *
 244  */
 245 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 246                         const struct pci_device_id *ent)
 247 {
 248         int i;
 249         spin_lock_init(&pm8001_ha->lock);
 250         spin_lock_init(&pm8001_ha->bitmap_lock);
 251         PM8001_INIT_DBG(pm8001_ha,
 252                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 253                                 pm8001_ha->chip->n_phy));
 254         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 255                 pm8001_phy_init(pm8001_ha, i);
 256                 pm8001_ha->port[i].wide_port_phymap = 0;
 257                 pm8001_ha->port[i].port_attached = 0;
 258                 pm8001_ha->port[i].port_state = 0;
 259                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 260         }
 261
 262         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
 263         if (!pm8001_ha->tags)
 264                 goto err_out;
 265         /* MPI Memory region 1 for AAP Event Log for fw */
 266         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 267         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 268         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 269         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 270
 271         /* MPI Memory region 2 for IOP Event Log for fw */
 272         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 273         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 274         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 275         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 276
 277         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 278                 /* MPI Memory region 3 for consumer Index of inbound queues */
 279                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
 280                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
 281                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
 282                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
 283
 284                 if ((ent->driver_data) != chip_8001) {
 285                         /* MPI Memory region 5 inbound queues */
 286                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 287                                                 PM8001_MPI_QUEUE;
 288                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
 289                         pm8001_ha->memoryMap.region[IB+i].total_len =
 290                                                 PM8001_MPI_QUEUE * 128;
 291                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
 292                 } else {
 293                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 294                                                 PM8001_MPI_QUEUE;
 295                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
 296                         pm8001_ha->memoryMap.region[IB+i].total_len =
 297                                                 PM8001_MPI_QUEUE * 64;
 298                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
 299                 }
 300         }
 301
 302         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 303                 /* MPI Memory region 4 for producer Index of outbound queues */
 304                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
 305                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
 306                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
 307                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
 308
 309                 if (ent->driver_data != chip_8001) {
 310                         /* MPI Memory region 6 Outbound queues */
 311                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 312                                                 PM8001_MPI_QUEUE;
 313                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
 314                         pm8001_ha->memoryMap.region[OB+i].total_len =
 315                                                 PM8001_MPI_QUEUE * 128;
 316                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
 317                 } else {
 318                         /* MPI Memory region 6 Outbound queues */
 319                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 320                                                 PM8001_MPI_QUEUE;
 321                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
 322                         pm8001_ha->memoryMap.region[OB+i].total_len =
 323                                                 PM8001_MPI_QUEUE * 64;
 324                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
 325                 }
 326
 327         }
 328         /* Memory region write DMA*/
 329         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 330         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 331         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 332         /* Memory region for devices*/
 333         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
 334         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
 335                 sizeof(struct pm8001_device);
 336         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
 337                 sizeof(struct pm8001_device);
 338
 339         /* Memory region for ccb_info*/
 340         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
 341         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
 342                 sizeof(struct pm8001_ccb_info);
 343         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
 344                 sizeof(struct pm8001_ccb_info);
 345
 346         /* Memory region for fw flash */
 347         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 348
 349         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 350         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 351         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 352         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 353         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 354                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 355                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 356                         &pm8001_ha->memoryMap.region[i].phys_addr,
 357                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 358                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 359                         pm8001_ha->memoryMap.region[i].total_len,
 360                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 361                                 PM8001_FAIL_DBG(pm8001_ha,
 362                                         pm8001_printk("Mem%d alloc failed\n",
 363                                         i));
 364                                 goto err_out;
 365                 }
 366         }
 367
 368         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
 369         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 370                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 371                 pm8001_ha->devices[i].id = i;
 372                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 373                 pm8001_ha->devices[i].running_req = 0;
 374         }
 375         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
 376         for (i = 0; i < PM8001_MAX_CCB; i++) {
 377                 pm8001_ha->ccb_info[i].ccb_dma_handle =
 378                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
 379                         i * sizeof(struct pm8001_ccb_info);
 380                 pm8001_ha->ccb_info[i].task = NULL;
 381                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
 382                 pm8001_ha->ccb_info[i].device = NULL;
 383                 ++pm8001_ha->tags_num;
 384         }
 385         pm8001_ha->flags = PM8001F_INIT_TIME;
 386         /* Initialize tags */
 387         pm8001_tag_init(pm8001_ha);
 388         return 0;
 389 err_out:
 390         return 1;
 391 }
 392
 393 /**
 394  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 395  * address so that we can access them.
 396  * @pm8001_ha:our hba structure.
 397  */
 398 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 399 {
 400         u32 bar;
 401         u32 logicalBar = 0;
 402         struct pci_dev *pdev;
 403
 404         pdev = pm8001_ha->pdev;
 405         /* map pci mem (PMC pci base 0-3)*/
 406         for (bar = 0; bar < 6; bar++) {
 407                 /*
 408                 ** logical BARs for SPC:
 409                 ** bar 0 and 1 - logical BAR0
 410                 ** bar 2 and 3 - logical BAR1
 411                 ** bar4 - logical BAR2
 412                 ** bar5 - logical BAR3
 413                 ** Skip the appropriate assignments:
 414                 */
 415                 if ((bar == 1) || (bar == 3))
 416                         continue;
 417                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 418                         pm8001_ha->io_mem[logicalBar].membase =
 419                                 pci_resource_start(pdev, bar);
 420                         pm8001_ha->io_mem[logicalBar].memsize =
 421                                 pci_resource_len(pdev, bar);
 422                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 423                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 424                                 pm8001_ha->io_mem[logicalBar].memsize);
 425                         PM8001_INIT_DBG(pm8001_ha,
 426                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 427                                 bar, logicalBar));
 428                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 429                                 "base addr %llx virt_addr=%llx len=%d\n",
 430                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 431                                 (u64)(unsigned long)
 432                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 433                                 pm8001_ha->io_mem[logicalBar].memsize));
 434                 } else {
 435                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 436                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 437                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
 438                 }
 439                 logicalBar++;
 440         }
 441         return 0;
 442 }
 443
 444 /**
 445  * pm8001_pci_alloc - initialize our ha card structure
 446  * @pdev: pci device.
 447  * @ent: ent
 448  * @shost: scsi host struct which has been initialized before.
 449  */
 450 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 451                                  const struct pci_device_id *ent,
 452                                 struct Scsi_Host *shost)
 453
 454 {
 455         struct pm8001_hba_info *pm8001_ha;
 456         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 457         int j;
 458
 459         pm8001_ha = sha->lldd_ha;
 460         if (!pm8001_ha)
 461                 return NULL;
 462
 463         pm8001_ha->pdev = pdev;
 464         pm8001_ha->dev = &pdev->dev;
 465         pm8001_ha->chip_id = ent->driver_data;
 466         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 467         pm8001_ha->irq = pdev->irq;
 468         pm8001_ha->sas = sha;
 469         pm8001_ha->shost = shost;
 470         pm8001_ha->id = pm8001_id++;
 471         pm8001_ha->logging_level = 0x01;
 472         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 473         /* IOMB size is 128 for 8088/89 controllers */
 474         if (pm8001_ha->chip_id != chip_8001)
 475                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 476         else
 477                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 478
 479 #ifdef PM8001_USE_TASKLET
 480         /* Tasklet for non msi-x interrupt handler */
 481         if ((!pdev->msix_cap || !pci_msi_enabled())
 482             || (pm8001_ha->chip_id == chip_8001))
 483                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 484                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 485         else
 486                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 487                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 488                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 489 #endif
 490         pm8001_ioremap(pm8001_ha);
 491         if (!pm8001_alloc(pm8001_ha, ent))
 492                 return pm8001_ha;
 493         pm8001_free(pm8001_ha);
 494         return NULL;
 495 }
 496
 497 /**
 498  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 499  * @pdev: pci device.
 500  */
 501 static int pci_go_44(struct pci_dev *pdev)
 502 {
 503         int rc;
 504
 505         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
 506                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
 507                 if (rc) {
 508                         rc = pci_set_consistent_dma_mask(pdev,
 509                                 DMA_BIT_MASK(32));
 510                         if (rc) {
 511                                 dev_printk(KERN_ERR, &pdev->dev,
 512                                         "44-bit DMA enable failed\n");
 513                                 return rc;
 514                         }
 515                 }
 516         } else {
 517                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 518                 if (rc) {
 519                         dev_printk(KERN_ERR, &pdev->dev,
 520                                 "32-bit DMA enable failed\n");
 521                         return rc;
 522                 }
 523                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 524                 if (rc) {
 525                         dev_printk(KERN_ERR, &pdev->dev,
 526                                 "32-bit consistent DMA enable failed\n");
 527                         return rc;
 528                 }
 529         }
 530         return rc;
 531 }
 532
 533 /**
 534  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 535  * @shost: scsi host which has been allocated outside.
 536  * @chip_info: our ha struct.
 537  */
 538 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 539                                    const struct pm8001_chip_info *chip_info)
 540 {
 541         int phy_nr, port_nr;
 542         struct asd_sas_phy **arr_phy;
 543         struct asd_sas_port **arr_port;
 544         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 545
 546         phy_nr = chip_info->n_phy;
 547         port_nr = phy_nr;
 548         memset(sha, 0x00, sizeof(*sha));
 549         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 550         if (!arr_phy)
 551                 goto exit;
 552         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 553         if (!arr_port)
 554                 goto exit_free2;
 555
 556         sha->sas_phy = arr_phy;
 557         sha->sas_port = arr_port;
 558         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 559         if (!sha->lldd_ha)
 560                 goto exit_free1;
 561
 562         shost->transportt = pm8001_stt;
 563         shost->max_id = PM8001_MAX_DEVICES;
 564         shost->max_lun = 8;
 565         shost->max_channel = 0;
 566         shost->unique_id = pm8001_id;
 567         shost->max_cmd_len = 16;
 568         shost->can_queue = PM8001_CAN_QUEUE;
 569         shost->cmd_per_lun = 32;
 570         return 0;
 571 exit_free1:
 572         kfree(arr_port);
 573 exit_free2:
 574         kfree(arr_phy);
 575 exit:
 576         return -1;
 577 }
 578
 579 /**
 580  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 581  * @shost: scsi host which has been allocated outside
 582  * @chip_info: our ha struct.
 583  */
 584 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 585                                      const struct pm8001_chip_info *chip_info)
 586 {
 587         int i = 0;
 588         struct pm8001_hba_info *pm8001_ha;
 589         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 590
 591         pm8001_ha = sha->lldd_ha;
 592         for (i = 0; i < chip_info->n_phy; i++) {
 593                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 594                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 595                 sha->sas_phy[i]->sas_addr =
 596                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 597         }
 598         sha->sas_ha_name = DRV_NAME;
 599         sha->dev = pm8001_ha->dev;
 600         sha->strict_wide_ports = 1;
 601         sha->lldd_module = THIS_MODULE;
 602         sha->sas_addr = &pm8001_ha->sas_addr[0];
 603         sha->num_phys = chip_info->n_phy;
 604         sha->core.shost = shost;
 605 }
 606
 607 /**
 608  * pm8001_init_sas_add - initialize sas address
 609  * @chip_info: our ha struct.
 610  *
 611  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 612  * it should read from the EEPROM
 613  */
 614 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 615 {
 616         u8 i, j;
 617         u8 sas_add[8];
 618 #ifdef PM8001_READ_VPD
 619         /* For new SPC controllers WWN is stored in flash vpd
 620         *  For SPC/SPCve controllers WWN is stored in EEPROM
 621         *  For Older SPC WWN is stored in NVMD
 622         */
 623         DECLARE_COMPLETION_ONSTACK(completion);
 624         struct pm8001_ioctl_payload payload;
 625         u16 deviceid;
 626         int rc;
 627
 628         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 629         pm8001_ha->nvmd_completion = &completion;
 630
 631         if (pm8001_ha->chip_id == chip_8001) {
 632                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 633                         payload.minor_function = 4;
 634                         payload.length = 4096;
 635                 } else {
 636                         payload.minor_function = 0;
 637                         payload.length = 128;
 638                 }
 639         } else if ((pm8001_ha->chip_id == chip_8070 ||
 640                         pm8001_ha->chip_id == chip_8072) &&
 641                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 642                 payload.minor_function = 4;
 643                 payload.length = 4096;
 644         } else {
 645                 payload.minor_function = 1;
 646                 payload.length = 4096;
 647         }
 648         payload.offset = 0;
 649         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
 650         if (!payload.func_specific) {
 651                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
 652                 return;
 653         }
 654         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 655         if (rc) {
 656                 kfree(payload.func_specific);
 657                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 658                 return;
 659         }
 660         wait_for_completion(&completion);
 661
 662         for (i = 0, j = 0; i <= 7; i++, j++) {
 663                 if (pm8001_ha->chip_id == chip_8001) {
 664                         if (deviceid == 0x8081)
 665                                 pm8001_ha->sas_addr[j] =
 666                                         payload.func_specific[0x704 + i];
 667                         else if (deviceid == 0x0042)
 668                                 pm8001_ha->sas_addr[j] =
 669                                         payload.func_specific[0x010 + i];
 670                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 671                                 pm8001_ha->chip_id == chip_8072) &&
 672                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 673                         pm8001_ha->sas_addr[j] =
 674                                         payload.func_specific[0x010 + i];
 675                 } else
 676                         pm8001_ha->sas_addr[j] =
 677                                         payload.func_specific[0x804 + i];
 678         }
 679         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 680         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 681                 if (i && ((i % 4) == 0))
 682                         sas_add[7] = sas_add[7] + 4;
 683                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 684                         sas_add, SAS_ADDR_SIZE);
 685                 PM8001_INIT_DBG(pm8001_ha,
 686                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 687                         pm8001_ha->phy[i].dev_sas_addr));
 688         }
 689         kfree(payload.func_specific);
 690 #else
 691         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 692                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 693                 pm8001_ha->phy[i].dev_sas_addr =
 694                         cpu_to_be64((u64)
 695                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 696         }
 697         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 698                 SAS_ADDR_SIZE);
 699 #endif
 700 }
 701
 702 /*
 703  * pm8001_get_phy_settings_info : Read phy setting values.
 704  * @pm8001_ha : our hba.
 705  */
 706 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 707 {
 708
 709 #ifdef PM8001_READ_VPD
 710         /*OPTION ROM FLASH read for the SPC cards */
 711         DECLARE_COMPLETION_ONSTACK(completion);
 712         struct pm8001_ioctl_payload payload;
 713         int rc;
 714
 715         pm8001_ha->nvmd_completion = &completion;
 716         /* SAS ADDRESS read from flash / EEPROM */
 717         payload.minor_function = 6;
 718         payload.offset = 0;
 719         payload.length = 4096;
 720         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 721         if (!payload.func_specific)
 722                 return -ENOMEM;
 723         /* Read phy setting values from flash */
 724         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 725         if (rc) {
 726                 kfree(payload.func_specific);
 727                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 728                 return -ENOMEM;
 729         }
 730         wait_for_completion(&completion);
 731         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 732         kfree(payload.func_specific);
 733 #endif
 734         return 0;
 735 }
 736
 737 struct pm8001_mpi3_phy_pg_trx_config {
 738         u32 LaneLosCfg;
 739         u32 LanePgaCfg1;
 740         u32 LanePisoCfg1;
 741         u32 LanePisoCfg2;
 742         u32 LanePisoCfg3;
 743         u32 LanePisoCfg4;
 744         u32 LanePisoCfg5;
 745         u32 LanePisoCfg6;
 746         u32 LaneBctCtrl;
 747 };
 748
 749 /**
 750  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
 751  * @pm8001_ha : our adapter
 752  * @phycfg : PHY config page to populate
 753  */
 754 static
 755 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 756                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 757 {
 758         phycfg->LaneLosCfg   = 0x00000132;
 759         phycfg->LanePgaCfg1  = 0x00203949;
 760         phycfg->LanePisoCfg1 = 0x000000FF;
 761         phycfg->LanePisoCfg2 = 0xFF000001;
 762         phycfg->LanePisoCfg3 = 0xE7011300;
 763         phycfg->LanePisoCfg4 = 0x631C40C0;
 764         phycfg->LanePisoCfg5 = 0xF8102036;
 765         phycfg->LanePisoCfg6 = 0xF74A1000;
 766         phycfg->LaneBctCtrl  = 0x00FB33F8;
 767 }
 768
 769 /**
 770  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
 771  * @pm8001_ha : our adapter
 772  * @phycfg : PHY config page to populate
 773  */
 774 static
 775 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 776                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 777 {
 778         phycfg->LaneLosCfg   = 0x00000132;
 779         phycfg->LanePgaCfg1  = 0x00203949;
 780         phycfg->LanePisoCfg1 = 0x000000FF;
 781         phycfg->LanePisoCfg2 = 0xFF000001;
 782         phycfg->LanePisoCfg3 = 0xE7011300;
 783         phycfg->LanePisoCfg4 = 0x63349140;
 784         phycfg->LanePisoCfg5 = 0xF8102036;
 785         phycfg->LanePisoCfg6 = 0xF80D9300;
 786         phycfg->LaneBctCtrl  = 0x00FB33F8;
 787 }
 788
 789 /**
 790  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
 791  * @pm8001_ha : our adapter
 792  * @phymask : The PHY mask
 793  */
 794 static
 795 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 796 {
 797         switch (pm8001_ha->pdev->subsystem_device) {
 798         case 0x0070: /* H1280 - 8 external 0 internal */
 799         case 0x0072: /* H12F0 - 16 external 0 internal */
 800                 *phymask = 0x0000;
 801                 break;
 802
 803         case 0x0071: /* H1208 - 0 external 8 internal */
 804         case 0x0073: /* H120F - 0 external 16 internal */
 805                 *phymask = 0xFFFF;
 806                 break;
 807
 808         case 0x0080: /* H1244 - 4 external 4 internal */
 809                 *phymask = 0x00F0;
 810                 break;
 811
 812         case 0x0081: /* H1248 - 4 external 8 internal */
 813                 *phymask = 0x0FF0;
 814                 break;
 815
 816         case 0x0082: /* H1288 - 8 external 8 internal */
 817                 *phymask = 0xFF00;
 818                 break;
 819
 820         default:
 821                 PM8001_INIT_DBG(pm8001_ha,
 822                         pm8001_printk("Unknown subsystem device=0x%.04x",
 823                                 pm8001_ha->pdev->subsystem_device));
 824         }
 825 }
 826
 827 /**
 828  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
 829  * @pm8001_ha : our adapter
 830  */
 831 static
 832 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 833 {
 834         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 835         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 836         int phymask = 0;
 837         int i = 0;
 838
 839         memset(&phycfg_int, 0, sizeof(phycfg_int));
 840         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 841
 842         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 843         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 844         pm8001_get_phy_mask(pm8001_ha, &phymask);
 845
 846         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 847                 if (phymask & (1 << i)) {/* Internal PHY */
 848                         pm8001_set_phy_profile_single(pm8001_ha, i,
 849                                         sizeof(phycfg_int) / sizeof(u32),
 850                                         (u32 *)&phycfg_int);
 851
 852                 } else { /* External PHY */
 853                         pm8001_set_phy_profile_single(pm8001_ha, i,
 854                                         sizeof(phycfg_ext) / sizeof(u32),
 855                                         (u32 *)&phycfg_ext);
 856                 }
 857         }
 858
 859         return 0;
 860 }
 861
 862 /**
 863  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 864  * @pm8001_ha : our hba.
 865  */
 866 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 867 {
 868         switch (pm8001_ha->pdev->subsystem_vendor) {
 869         case PCI_VENDOR_ID_ATTO:
 870                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 871                         return 0;
 872                 else
 873                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 874
 875         case PCI_VENDOR_ID_ADAPTEC2:
 876         case 0:
 877                 return 0;
 878
 879         default:
 880                 return pm8001_get_phy_settings_info(pm8001_ha);
 881         }
 882 }
 883
 884 #ifdef PM8001_USE_MSIX
 885 /**
 886  * pm8001_setup_msix - enable MSI-X interrupt
 887  * @chip_info: our ha struct.
 888  * @irq_handler: irq_handler
 889  */
 890 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 891 {
 892         u32 i = 0, j = 0;
 893         u32 number_of_intr;
 894         int flag = 0;
 895         int rc;
 896         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
 897
 898         /* SPCv controllers supports 64 msi-x */
 899         if (pm8001_ha->chip_id == chip_8001) {
 900                 number_of_intr = 1;
 901         } else {
 902                 number_of_intr = PM8001_MAX_MSIX_VEC;
 903                 flag &= ~IRQF_SHARED;
 904         }
 905
 906         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 907                         number_of_intr, PCI_IRQ_MSIX);
 908         if (rc < 0)
 909                 return rc;
 910         pm8001_ha->number_of_intr = number_of_intr;
 911
 912         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 913                 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 914                                 rc, pm8001_ha->number_of_intr));
 915
 916         for (i = 0; i < number_of_intr; i++) {
 917                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
 918                                 DRV_NAME"%d", i);
 919                 pm8001_ha->irq_vector[i].irq_id = i;
 920                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 921
 922                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 923                         pm8001_interrupt_handler_msix, flag,
 924                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
 925                 if (rc) {
 926                         for (j = 0; j < i; j++) {
 927                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 928                                         &(pm8001_ha->irq_vector[i]));
 929                         }
 930                         pci_free_irq_vectors(pm8001_ha->pdev);
 931                         break;
 932                 }
 933         }
 934
 935         return rc;
 936 }
 937 #endif
 938
 939 /**
 940  * pm8001_request_irq - register interrupt
 941  * @chip_info: our ha struct.
 942  */
 943 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 944 {
 945         struct pci_dev *pdev;
 946         int rc;
 947
 948         pdev = pm8001_ha->pdev;
 949
 950 #ifdef PM8001_USE_MSIX
 951         if (pdev->msix_cap && pci_msi_enabled())
 952                 return pm8001_setup_msix(pm8001_ha);
 953         else {
 954                 PM8001_INIT_DBG(pm8001_ha,
 955                         pm8001_printk("MSIX not supported!!!\n"));
 956                 goto intx;
 957         }
 958 #endif
 959
 960 intx:
 961         /* initialize the INT-X interrupt */
 962         pm8001_ha->irq_vector[0].irq_id = 0;
 963         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
 964         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
 965                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
 966         return rc;
 967 }
 968
 969 /**
 970  * pm8001_pci_probe - probe supported device
 971  * @pdev: pci device which kernel has been prepared for.
 972  * @ent: pci device id
 973  *
 974  * This function is the main initialization function, when register a new
 975  * pci driver it is invoked, all struct an hardware initilization should be done
 976  * here, also, register interrupt
 977  */
 978 static int pm8001_pci_probe(struct pci_dev *pdev,
 979                             const struct pci_device_id *ent)
 980 {
 981         unsigned int rc;
 982         u32     pci_reg;
 983         u8      i = 0;
 984         struct pm8001_hba_info *pm8001_ha;
 985         struct Scsi_Host *shost = NULL;
 986         const struct pm8001_chip_info *chip;
 987
 988         dev_printk(KERN_INFO, &pdev->dev,
 989                 "pm80xx: driver version %s\n", DRV_VERSION);
 990         rc = pci_enable_device(pdev);
 991         if (rc)
 992                 goto err_out_enable;
 993         pci_set_master(pdev);
 994         /*
 995          * Enable pci slot busmaster by setting pci command register.
 996          * This is required by FW for Cyclone card.
 997          */
 998
 999         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1000         pci_reg |= 0x157;
1001         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1002         rc = pci_request_regions(pdev, DRV_NAME);
1003         if (rc)
1004                 goto err_out_disable;
1005         rc = pci_go_44(pdev);
1006         if (rc)
1007                 goto err_out_regions;
1008
1009         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1010         if (!shost) {
1011                 rc = -ENOMEM;
1012                 goto err_out_regions;
1013         }
1014         chip = &pm8001_chips[ent->driver_data];
1015         SHOST_TO_SAS_HA(shost) =
1016                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1017         if (!SHOST_TO_SAS_HA(shost)) {
1018                 rc = -ENOMEM;
1019                 goto err_out_free_host;
1020         }
1021
1022         rc = pm8001_prep_sas_ha_init(shost, chip);
1023         if (rc) {
1024                 rc = -ENOMEM;
1025                 goto err_out_free;
1026         }
1027         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1028         /* ent->driver variable is used to differentiate between controllers */
1029         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1030         if (!pm8001_ha) {
1031                 rc = -ENOMEM;
1032                 goto err_out_free;
1033         }
1034         list_add_tail(&pm8001_ha->list, &hba_list);
1035         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1036         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1037         if (rc) {
1038                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1039                         "chip_init failed [ret: %d]\n", rc));
1040                 goto err_out_ha_free;
1041         }
1042
1043         rc = scsi_add_host(shost, &pdev->dev);
1044         if (rc)
1045                 goto err_out_ha_free;
1046         rc = pm8001_request_irq(pm8001_ha);
1047         if (rc) {
1048                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1049                         "pm8001_request_irq failed [ret: %d]\n", rc));
1050                 goto err_out_shost;
1051         }
1052
1053         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1054         if (pm8001_ha->chip_id != chip_8001) {
1055                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1056                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1057                 /* setup thermal configuration. */
1058                 pm80xx_set_thermal_config(pm8001_ha);
1059         }
1060
1061         pm8001_init_sas_add(pm8001_ha);
1062         /* phy setting support for motherboard controller */
1063         rc = pm8001_configure_phy_settings(pm8001_ha);
1064         if (rc)
1065                 goto err_out_shost;
1066
1067         pm8001_post_sas_ha_init(shost, chip);
1068         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1069         if (rc)
1070                 goto err_out_shost;
1071         scsi_scan_host(pm8001_ha->shost);
1072         return 0;
1073
1074 err_out_shost:
1075         scsi_remove_host(pm8001_ha->shost);
1076 err_out_ha_free:
1077         pm8001_free(pm8001_ha);
1078 err_out_free:
1079         kfree(SHOST_TO_SAS_HA(shost));
1080 err_out_free_host:
1081         scsi_host_put(shost);
1082 err_out_regions:
1083         pci_release_regions(pdev);
1084 err_out_disable:
1085         pci_disable_device(pdev);
1086 err_out_enable:
1087         return rc;
1088 }
1089
1090 static void pm8001_pci_remove(struct pci_dev *pdev)
1091 {
1092         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1093         struct pm8001_hba_info *pm8001_ha;
1094         int i, j;
1095         pm8001_ha = sha->lldd_ha;
1096         sas_unregister_ha(sha);
1097         sas_remove_host(pm8001_ha->shost);
1098         list_del(&pm8001_ha->list);
1099         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1100         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1101
1102 #ifdef PM8001_USE_MSIX
1103         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1104                 synchronize_irq(pci_irq_vector(pdev, i));
1105         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1106                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1107         pci_free_irq_vectors(pdev);
1108 #else
1109         free_irq(pm8001_ha->irq, sha);
1110 #endif
1111 #ifdef PM8001_USE_TASKLET
1112         /* For non-msix and msix interrupts */
1113         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1114             (pm8001_ha->chip_id == chip_8001))
1115                 tasklet_kill(&pm8001_ha->tasklet[0]);
1116         else
1117                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1118                         tasklet_kill(&pm8001_ha->tasklet[j]);
1119 #endif
1120         scsi_host_put(pm8001_ha->shost);
1121         pm8001_free(pm8001_ha);
1122         kfree(sha->sas_phy);
1123         kfree(sha->sas_port);
1124         kfree(sha);
1125         pci_release_regions(pdev);
1126         pci_disable_device(pdev);
1127 }
1128
1129 /**
1130  * pm8001_pci_suspend - power management suspend main entry point
1131  * @pdev: PCI device struct
1132  * @state: PM state change to (usually PCI_D3)
1133  *
1134  * Returns 0 success, anything else error.
1135  */
1136 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1137 {
1138         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1139         struct pm8001_hba_info *pm8001_ha;
1140         int  i, j;
1141         u32 device_state;
1142         pm8001_ha = sha->lldd_ha;
1143         sas_suspend_ha(sha);
1144         flush_workqueue(pm8001_wq);
1145         scsi_block_requests(pm8001_ha->shost);
1146         if (!pdev->pm_cap) {
1147                 dev_err(&pdev->dev, " PCI PM not supported\n");
1148                 return -ENODEV;
1149         }
1150         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1151         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1152 #ifdef PM8001_USE_MSIX
1153         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1154                 synchronize_irq(pci_irq_vector(pdev, i));
1155         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1156                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1157         pci_free_irq_vectors(pdev);
1158 #else
1159         free_irq(pm8001_ha->irq, sha);
1160 #endif
1161 #ifdef PM8001_USE_TASKLET
1162         /* For non-msix and msix interrupts */
1163         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1164             (pm8001_ha->chip_id == chip_8001))
1165                 tasklet_kill(&pm8001_ha->tasklet[0]);
1166         else
1167                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1168                         tasklet_kill(&pm8001_ha->tasklet[j]);
1169 #endif
1170         device_state = pci_choose_state(pdev, state);
1171         pm8001_printk("pdev=0x%p, slot=%s, entering "
1172                       "operating state [D%d]\n", pdev,
1173                       pm8001_ha->name, device_state);
1174         pci_save_state(pdev);
1175         pci_disable_device(pdev);
1176         pci_set_power_state(pdev, device_state);
1177         return 0;
1178 }
1179
1180 /**
1181  * pm8001_pci_resume - power management resume main entry point
1182  * @pdev: PCI device struct
1183  *
1184  * Returns 0 success, anything else error.
1185  */
1186 static int pm8001_pci_resume(struct pci_dev *pdev)
1187 {
1188         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1189         struct pm8001_hba_info *pm8001_ha;
1190         int rc;
1191         u8 i = 0, j;
1192         u32 device_state;
1193         DECLARE_COMPLETION_ONSTACK(completion);
1194         pm8001_ha = sha->lldd_ha;
1195         device_state = pdev->current_state;
1196
1197         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1198                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1199
1200         pci_set_power_state(pdev, PCI_D0);
1201         pci_enable_wake(pdev, PCI_D0, 0);
1202         pci_restore_state(pdev);
1203         rc = pci_enable_device(pdev);
1204         if (rc) {
1205                 pm8001_printk("slot=%s Enable device failed during resume\n",
1206                               pm8001_ha->name);
1207                 goto err_out_enable;
1208         }
1209
1210         pci_set_master(pdev);
1211         rc = pci_go_44(pdev);
1212         if (rc)
1213                 goto err_out_disable;
1214         sas_prep_resume_ha(sha);
1215         /* chip soft rst only for spc */
1216         if (pm8001_ha->chip_id == chip_8001) {
1217                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1218                 PM8001_INIT_DBG(pm8001_ha,
1219                         pm8001_printk("chip soft reset successful\n"));
1220         }
1221         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1222         if (rc)
1223                 goto err_out_disable;
1224
1225         /* disable all the interrupt bits */
1226         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1227
1228         rc = pm8001_request_irq(pm8001_ha);
1229         if (rc)
1230                 goto err_out_disable;
1231 #ifdef PM8001_USE_TASKLET
1232         /*  Tasklet for non msi-x interrupt handler */
1233         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1234             (pm8001_ha->chip_id == chip_8001))
1235                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1236                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1237         else
1238                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1239                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1240                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1241 #endif
1242         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1243         if (pm8001_ha->chip_id != chip_8001) {
1244                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1245                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1246         }
1247
1248         /* Chip documentation for the 8070 and 8072 SPCv    */
1249         /* states that a 500ms minimum delay is required    */
1250         /* before issuing commands. Otherwise, the firmware */
1251         /* will enter an unrecoverable state.               */
1252
1253         if (pm8001_ha->chip_id == chip_8070 ||
1254                 pm8001_ha->chip_id == chip_8072) {
1255                 mdelay(500);
1256         }
1257
1258         /* Spin up the PHYs */
1259
1260         pm8001_ha->flags = PM8001F_RUN_TIME;
1261         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1262                 pm8001_ha->phy[i].enable_completion = &completion;
1263                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1264                 wait_for_completion(&completion);
1265         }
1266         sas_resume_ha(sha);
1267         return 0;
1268
1269 err_out_disable:
1270         scsi_remove_host(pm8001_ha->shost);
1271         pci_disable_device(pdev);
1272 err_out_enable:
1273         return rc;
1274 }
1275
1276 /* update of pci device, vendor id and driver data with
1277  * unique value for each of the controller
1278  */
1279 static struct pci_device_id pm8001_pci_table[] = {
1280         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1281         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1282         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1283         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1284         /* Support for SPC/SPCv/SPCve controllers */
1285         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1286         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1287         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1288         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1289         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1290         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1291         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1292         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1293         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1294         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1295         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1296         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1297         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1298         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1299         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1300         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1301                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1302         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1303                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1304         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1305                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1306         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1307                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1308         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1309                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1310         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1311                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1312         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1313                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1314         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1315                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1316         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1317                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1318         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1319                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1320         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1321                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1322         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1323                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1324         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1325                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1326         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1327                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1328         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1329                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1330         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1331                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1332         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1333                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1334         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1335                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1336         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1337                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1338         { PCI_VENDOR_ID_ATTO, 0x8070,
1339                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1340         { PCI_VENDOR_ID_ATTO, 0x8070,
1341                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1342         { PCI_VENDOR_ID_ATTO, 0x8072,
1343                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1344         { PCI_VENDOR_ID_ATTO, 0x8072,
1345                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1346         { PCI_VENDOR_ID_ATTO, 0x8070,
1347                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1348         { PCI_VENDOR_ID_ATTO, 0x8072,
1349                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1350         { PCI_VENDOR_ID_ATTO, 0x8072,
1351                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1352         {} /* terminate list */
1353 };
1354
1355 static struct pci_driver pm8001_pci_driver = {
1356         .name           = DRV_NAME,
1357         .id_table       = pm8001_pci_table,
1358         .probe          = pm8001_pci_probe,
1359         .remove         = pm8001_pci_remove,
1360         .suspend        = pm8001_pci_suspend,
1361         .resume         = pm8001_pci_resume,
1362 };
1363
1364 /**
1365  *      pm8001_init - initialize scsi transport template
1366  */
1367 static int __init pm8001_init(void)
1368 {
1369         int rc = -ENOMEM;
1370
1371         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1372         if (!pm8001_wq)
1373                 goto err;
1374
1375         pm8001_id = 0;
1376         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1377         if (!pm8001_stt)
1378                 goto err_wq;
1379         rc = pci_register_driver(&pm8001_pci_driver);
1380         if (rc)
1381                 goto err_tp;
1382         return 0;
1383
1384 err_tp:
1385         sas_release_transport(pm8001_stt);
1386 err_wq:
1387         destroy_workqueue(pm8001_wq);
1388 err:
1389         return rc;
1390 }
1391
1392 static void __exit pm8001_exit(void)
1393 {
1394         pci_unregister_driver(&pm8001_pci_driver);
1395         sas_release_transport(pm8001_stt);
1396         destroy_workqueue(pm8001_wq);
1397 }
1398
1399 module_init(pm8001_init);
1400 module_exit(pm8001_exit);
1401
1402 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1403 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1404 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1405 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1406 MODULE_DESCRIPTION(
1407                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1408                 "SAS/SATA controller driver");
1409 MODULE_VERSION(DRV_VERSION);
1410 MODULE_LICENSE("GPL");
1411 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1412