drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
  47 module_param(logging_level, ulong, 0644);
  48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  49
  50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  51 module_param(link_rate, ulong, 0644);
  52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  53                 " 1: Link rate 1.5G\n"
  54                 " 2: Link rate 3.0G\n"
  55                 " 4: Link rate 6.0G\n"
  56                 " 8: Link rate 12.0G\n");
  57
  58 static struct scsi_transport_template *pm8001_stt;
  59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
  60
  61 /*
  62  * chip info structure to identify chip key functionality as
  63  * encryption available/not, no of ports, hw specific function ref
  64  */
  65 static const struct pm8001_chip_info pm8001_chips[] = {
  66         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  67         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  68         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  69         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  70         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  71         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  72         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  73         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  75         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  76         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  77 };
  78 static int pm8001_id;
  79
  80 LIST_HEAD(hba_list);
  81
  82 struct workqueue_struct *pm8001_wq;
  83
  84 /*
  85  * The main structure which LLDD must register for scsi core.
  86  */
  87 static struct scsi_host_template pm8001_sht = {
  88         .module                 = THIS_MODULE,
  89         .name                   = DRV_NAME,
  90         .queuecommand           = sas_queuecommand,
  91         .dma_need_drain         = ata_scsi_dma_need_drain,
  92         .target_alloc           = sas_target_alloc,
  93         .slave_configure        = sas_slave_configure,
  94         .scan_finished          = pm8001_scan_finished,
  95         .scan_start             = pm8001_scan_start,
  96         .change_queue_depth     = sas_change_queue_depth,
  97         .bios_param             = sas_bios_param,
  98         .can_queue              = 1,
  99         .this_id                = -1,
 100         .sg_tablesize           = PM8001_MAX_DMA_SG,
 101         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 102         .eh_device_reset_handler = sas_eh_device_reset_handler,
 103         .eh_target_reset_handler = sas_eh_target_reset_handler,
 104         .slave_alloc            = sas_slave_alloc,
 105         .target_destroy         = sas_target_destroy,
 106         .ioctl                  = sas_ioctl,
 107 #ifdef CONFIG_COMPAT
 108         .compat_ioctl           = sas_ioctl,
 109 #endif
 110         .shost_attrs            = pm8001_host_attrs,
 111         .track_queue_depth      = 1,
 112 };
 113
 114 /*
 115  * Sas layer call this function to execute specific task.
 116  */
 117 static struct sas_domain_function_template pm8001_transport_ops = {
 118         .lldd_dev_found         = pm8001_dev_found,
 119         .lldd_dev_gone          = pm8001_dev_gone,
 120
 121         .lldd_execute_task      = pm8001_queue_command,
 122         .lldd_control_phy       = pm8001_phy_control,
 123
 124         .lldd_abort_task        = pm8001_abort_task,
 125         .lldd_abort_task_set    = pm8001_abort_task_set,
 126         .lldd_clear_aca         = pm8001_clear_aca,
 127         .lldd_clear_task_set    = pm8001_clear_task_set,
 128         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 129         .lldd_lu_reset          = pm8001_lu_reset,
 130         .lldd_query_task        = pm8001_query_task,
 131 };
 132
 133 /**
 134  * pm8001_phy_init - initiate our adapter phys
 135  * @pm8001_ha: our hba structure.
 136  * @phy_id: phy id.
 137  */
 138 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 139 {
 140         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 141         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 142         phy->phy_state = PHY_LINK_DISABLE;
 143         phy->pm8001_ha = pm8001_ha;
 144         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 145         sas_phy->class = SAS;
 146         sas_phy->iproto = SAS_PROTOCOL_ALL;
 147         sas_phy->tproto = 0;
 148         sas_phy->type = PHY_TYPE_PHYSICAL;
 149         sas_phy->role = PHY_ROLE_INITIATOR;
 150         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 151         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 152         sas_phy->id = phy_id;
 153         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 154         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 155         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 156         sas_phy->lldd_phy = phy;
 157 }
 158
 159 /**
 160  * pm8001_free - free hba
 161  * @pm8001_ha:  our hba structure.
 162  */
 163 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 164 {
 165         int i;
 166
 167         if (!pm8001_ha)
 168                 return;
 169
 170         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 171                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 172                         dma_free_coherent(&pm8001_ha->pdev->dev,
 173                                 (pm8001_ha->memoryMap.region[i].total_len +
 174                                 pm8001_ha->memoryMap.region[i].alignment),
 175                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 176                                 pm8001_ha->memoryMap.region[i].phys_addr);
 177                         }
 178         }
 179         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 180         flush_workqueue(pm8001_wq);
 181         kfree(pm8001_ha->tags);
 182         kfree(pm8001_ha);
 183 }
 184
 185 #ifdef PM8001_USE_TASKLET
 186
 187 /**
 188  * tasklet for 64 msi-x interrupt handler
 189  * @opaque: the passed general host adapter struct
 190  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 191  */
 192 static void pm8001_tasklet(unsigned long opaque)
 193 {
 194         struct pm8001_hba_info *pm8001_ha;
 195         struct isr_param *irq_vector;
 196
 197         irq_vector = (struct isr_param *)opaque;
 198         pm8001_ha = irq_vector->drv_inst;
 199         if (unlikely(!pm8001_ha))
 200                 BUG_ON(1);
 201         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 202 }
 203 #endif
 204
 205 /**
 206  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 207  * It obtains the vector number and calls the equivalent bottom
 208  * half or services directly.
 209  * @irq: interrupt number
 210  * @opaque: the passed outbound queue/vector. Host structure is
 211  * retrieved from the same.
 212  */
 213 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 214 {
 215         struct isr_param *irq_vector;
 216         struct pm8001_hba_info *pm8001_ha;
 217         irqreturn_t ret = IRQ_HANDLED;
 218         irq_vector = (struct isr_param *)opaque;
 219         pm8001_ha = irq_vector->drv_inst;
 220
 221         if (unlikely(!pm8001_ha))
 222                 return IRQ_NONE;
 223         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 224                 return IRQ_NONE;
 225 #ifdef PM8001_USE_TASKLET
 226         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 227 #else
 228         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 229 #endif
 230         return ret;
 231 }
 232
 233 /**
 234  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 235  * @irq: interrupt number
 236  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 237  */
 238
 239 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 240 {
 241         struct pm8001_hba_info *pm8001_ha;
 242         irqreturn_t ret = IRQ_HANDLED;
 243         struct sas_ha_struct *sha = dev_id;
 244         pm8001_ha = sha->lldd_ha;
 245         if (unlikely(!pm8001_ha))
 246                 return IRQ_NONE;
 247         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 248                 return IRQ_NONE;
 249
 250 #ifdef PM8001_USE_TASKLET
 251         tasklet_schedule(&pm8001_ha->tasklet[0]);
 252 #else
 253         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 254 #endif
 255         return ret;
 256 }
 257
 258 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 259 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 260
 261 /**
 262  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 263  * @pm8001_ha: our hba structure.
 264  * @ent: PCI device ID structure to match on
 265  */
 266 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 267                         const struct pci_device_id *ent)
 268 {
 269         int i, count = 0, rc = 0;
 270         u32 ci_offset, ib_offset, ob_offset, pi_offset;
 271         struct inbound_queue_table *circularQ;
 272
 273         spin_lock_init(&pm8001_ha->lock);
 274         spin_lock_init(&pm8001_ha->bitmap_lock);
 275         pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
 276                    pm8001_ha->chip->n_phy);
 277
 278         /* Setup Interrupt */
 279         rc = pm8001_setup_irq(pm8001_ha);
 280         if (rc) {
 281                 pm8001_dbg(pm8001_ha, FAIL,
 282                            "pm8001_setup_irq failed [ret: %d]\n", rc);
 283                 goto err_out;
 284         }
 285         /* Request Interrupt */
 286         rc = pm8001_request_irq(pm8001_ha);
 287         if (rc)
 288                 goto err_out;
 289
 290         count = pm8001_ha->max_q_num;
 291         /* Queues are chosen based on the number of cores/msix availability */
 292         ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
 293         ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
 294         ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
 295         pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
 296         pm8001_ha->max_memcnt = pi_offset + count;
 297
 298         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 299                 pm8001_phy_init(pm8001_ha, i);
 300                 pm8001_ha->port[i].wide_port_phymap = 0;
 301                 pm8001_ha->port[i].port_attached = 0;
 302                 pm8001_ha->port[i].port_state = 0;
 303                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 304         }
 305
 306         /* MPI Memory region 1 for AAP Event Log for fw */
 307         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 308         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 309         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 310         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 311
 312         /* MPI Memory region 2 for IOP Event Log for fw */
 313         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 314         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 315         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 316         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 317
 318         for (i = 0; i < count; i++) {
 319                 circularQ = &pm8001_ha->inbnd_q_tbl[i];
 320                 spin_lock_init(&circularQ->iq_lock);
 321                 /* MPI Memory region 3 for consumer Index of inbound queues */
 322                 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
 323                 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
 324                 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
 325                 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
 326
 327                 if ((ent->driver_data) != chip_8001) {
 328                         /* MPI Memory region 5 inbound queues */
 329                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 330                                                 PM8001_MPI_QUEUE;
 331                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 332                                                                 = 128;
 333                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 334                                                 PM8001_MPI_QUEUE * 128;
 335                         pm8001_ha->memoryMap.region[ib_offset+i].alignment
 336                                                                 = 128;
 337                 } else {
 338                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 339                                                 PM8001_MPI_QUEUE;
 340                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 341                                                                 = 64;
 342                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 343                                                 PM8001_MPI_QUEUE * 64;
 344                         pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
 345                 }
 346         }
 347
 348         for (i = 0; i < count; i++) {
 349                 /* MPI Memory region 4 for producer Index of outbound queues */
 350                 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
 351                 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
 352                 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
 353                 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
 354
 355                 if (ent->driver_data != chip_8001) {
 356                         /* MPI Memory region 6 Outbound queues */
 357                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 358                                                 PM8001_MPI_QUEUE;
 359                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 360                                                                 = 128;
 361                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 362                                                 PM8001_MPI_QUEUE * 128;
 363                         pm8001_ha->memoryMap.region[ob_offset+i].alignment
 364                                                                 = 128;
 365                 } else {
 366                         /* MPI Memory region 6 Outbound queues */
 367                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 368                                                 PM8001_MPI_QUEUE;
 369                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 370                                                                 = 64;
 371                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 372                                                 PM8001_MPI_QUEUE * 64;
 373                         pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
 374                 }
 375
 376         }
 377         /* Memory region write DMA*/
 378         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 379         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 380         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 381
 382         /* Memory region for fw flash */
 383         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 384
 385         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 386         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 387         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 388         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 389         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 390                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 391                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 392                         &pm8001_ha->memoryMap.region[i].phys_addr,
 393                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 394                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 395                         pm8001_ha->memoryMap.region[i].total_len,
 396                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 397                         pm8001_dbg(pm8001_ha, FAIL,
 398                                    "Mem%d alloc failed\n",
 399                                    i);
 400                                 goto err_out;
 401                 }
 402         }
 403
 404         /* Memory region for devices*/
 405         pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
 406                                 * sizeof(struct pm8001_device), GFP_KERNEL);
 407         if (!pm8001_ha->devices) {
 408                 rc = -ENOMEM;
 409                 goto err_out_nodev;
 410         }
 411         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 412                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 413                 pm8001_ha->devices[i].id = i;
 414                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 415                 atomic_set(&pm8001_ha->devices[i].running_req, 0);
 416         }
 417         pm8001_ha->flags = PM8001F_INIT_TIME;
 418         /* Initialize tags */
 419         pm8001_tag_init(pm8001_ha);
 420         return 0;
 421
 422 err_out_nodev:
 423         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 424                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 425                         pci_free_consistent(pm8001_ha->pdev,
 426                                 (pm8001_ha->memoryMap.region[i].total_len +
 427                                 pm8001_ha->memoryMap.region[i].alignment),
 428                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 429                                 pm8001_ha->memoryMap.region[i].phys_addr);
 430                 }
 431         }
 432 err_out:
 433         return 1;
 434 }
 435
 436 /**
 437  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 438  * address so that we can access them.
 439  * @pm8001_ha:our hba structure.
 440  */
 441 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 442 {
 443         u32 bar;
 444         u32 logicalBar = 0;
 445         struct pci_dev *pdev;
 446
 447         pdev = pm8001_ha->pdev;
 448         /* map pci mem (PMC pci base 0-3)*/
 449         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 450                 /*
 451                 ** logical BARs for SPC:
 452                 ** bar 0 and 1 - logical BAR0
 453                 ** bar 2 and 3 - logical BAR1
 454                 ** bar4 - logical BAR2
 455                 ** bar5 - logical BAR3
 456                 ** Skip the appropriate assignments:
 457                 */
 458                 if ((bar == 1) || (bar == 3))
 459                         continue;
 460                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 461                         pm8001_ha->io_mem[logicalBar].membase =
 462                                 pci_resource_start(pdev, bar);
 463                         pm8001_ha->io_mem[logicalBar].memsize =
 464                                 pci_resource_len(pdev, bar);
 465                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 466                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 467                                 pm8001_ha->io_mem[logicalBar].memsize);
 468                         pm8001_dbg(pm8001_ha, INIT,
 469                                    "PCI: bar %d, logicalBar %d\n",
 470                                    bar, logicalBar);
 471                         pm8001_dbg(pm8001_ha, INIT,
 472                                    "base addr %llx virt_addr=%llx len=%d\n",
 473                                    (u64)pm8001_ha->io_mem[logicalBar].membase,
 474                                    (u64)(unsigned long)
 475                                    pm8001_ha->io_mem[logicalBar].memvirtaddr,
 476                                    pm8001_ha->io_mem[logicalBar].memsize);
 477                 } else {
 478                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 479                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 480                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 481                 }
 482                 logicalBar++;
 483         }
 484         return 0;
 485 }
 486
 487 /**
 488  * pm8001_pci_alloc - initialize our ha card structure
 489  * @pdev: pci device.
 490  * @ent: ent
 491  * @shost: scsi host struct which has been initialized before.
 492  */
 493 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 494                                  const struct pci_device_id *ent,
 495                                 struct Scsi_Host *shost)
 496
 497 {
 498         struct pm8001_hba_info *pm8001_ha;
 499         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 500         int j;
 501
 502         pm8001_ha = sha->lldd_ha;
 503         if (!pm8001_ha)
 504                 return NULL;
 505
 506         pm8001_ha->pdev = pdev;
 507         pm8001_ha->dev = &pdev->dev;
 508         pm8001_ha->chip_id = ent->driver_data;
 509         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 510         pm8001_ha->irq = pdev->irq;
 511         pm8001_ha->sas = sha;
 512         pm8001_ha->shost = shost;
 513         pm8001_ha->id = pm8001_id++;
 514         pm8001_ha->logging_level = logging_level;
 515         pm8001_ha->non_fatal_count = 0;
 516         if (link_rate >= 1 && link_rate <= 15)
 517                 pm8001_ha->link_rate = (link_rate << 8);
 518         else {
 519                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 520                         LINKRATE_60 | LINKRATE_120;
 521                 pm8001_dbg(pm8001_ha, FAIL,
 522                            "Setting link rate to default value\n");
 523         }
 524         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 525         /* IOMB size is 128 for 8088/89 controllers */
 526         if (pm8001_ha->chip_id != chip_8001)
 527                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 528         else
 529                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 530
 531 #ifdef PM8001_USE_TASKLET
 532         /* Tasklet for non msi-x interrupt handler */
 533         if ((!pdev->msix_cap || !pci_msi_enabled())
 534             || (pm8001_ha->chip_id == chip_8001))
 535                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 536                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 537         else
 538                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 539                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 540                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 541 #endif
 542         pm8001_ioremap(pm8001_ha);
 543         if (!pm8001_alloc(pm8001_ha, ent))
 544                 return pm8001_ha;
 545         pm8001_free(pm8001_ha);
 546         return NULL;
 547 }
 548
 549 /**
 550  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 551  * @pdev: pci device.
 552  */
 553 static int pci_go_44(struct pci_dev *pdev)
 554 {
 555         int rc;
 556
 557         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 558         if (rc) {
 559                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 560                 if (rc)
 561                         dev_printk(KERN_ERR, &pdev->dev,
 562                                 "32-bit DMA enable failed\n");
 563         }
 564         return rc;
 565 }
 566
 567 /**
 568  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 569  * @shost: scsi host which has been allocated outside.
 570  * @chip_info: our ha struct.
 571  */
 572 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 573                                    const struct pm8001_chip_info *chip_info)
 574 {
 575         int phy_nr, port_nr;
 576         struct asd_sas_phy **arr_phy;
 577         struct asd_sas_port **arr_port;
 578         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 579
 580         phy_nr = chip_info->n_phy;
 581         port_nr = phy_nr;
 582         memset(sha, 0x00, sizeof(*sha));
 583         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 584         if (!arr_phy)
 585                 goto exit;
 586         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 587         if (!arr_port)
 588                 goto exit_free2;
 589
 590         sha->sas_phy = arr_phy;
 591         sha->sas_port = arr_port;
 592         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 593         if (!sha->lldd_ha)
 594                 goto exit_free1;
 595
 596         shost->transportt = pm8001_stt;
 597         shost->max_id = PM8001_MAX_DEVICES;
 598         shost->max_lun = 8;
 599         shost->max_channel = 0;
 600         shost->unique_id = pm8001_id;
 601         shost->max_cmd_len = 16;
 602         shost->can_queue = PM8001_CAN_QUEUE;
 603         shost->cmd_per_lun = 32;
 604         return 0;
 605 exit_free1:
 606         kfree(arr_port);
 607 exit_free2:
 608         kfree(arr_phy);
 609 exit:
 610         return -1;
 611 }
 612
 613 /**
 614  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 615  * @shost: scsi host which has been allocated outside
 616  * @chip_info: our ha struct.
 617  */
 618 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 619                                      const struct pm8001_chip_info *chip_info)
 620 {
 621         int i = 0;
 622         struct pm8001_hba_info *pm8001_ha;
 623         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 624
 625         pm8001_ha = sha->lldd_ha;
 626         for (i = 0; i < chip_info->n_phy; i++) {
 627                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 628                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 629                 sha->sas_phy[i]->sas_addr =
 630                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 631         }
 632         sha->sas_ha_name = DRV_NAME;
 633         sha->dev = pm8001_ha->dev;
 634         sha->strict_wide_ports = 1;
 635         sha->lldd_module = THIS_MODULE;
 636         sha->sas_addr = &pm8001_ha->sas_addr[0];
 637         sha->num_phys = chip_info->n_phy;
 638         sha->core.shost = shost;
 639 }
 640
 641 /**
 642  * pm8001_init_sas_add - initialize sas address
 643  * @pm8001_ha: our ha struct.
 644  *
 645  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 646  * it should read from the EEPROM
 647  */
 648 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 649 {
 650         u8 i, j;
 651         u8 sas_add[8];
 652 #ifdef PM8001_READ_VPD
 653         /* For new SPC controllers WWN is stored in flash vpd
 654         *  For SPC/SPCve controllers WWN is stored in EEPROM
 655         *  For Older SPC WWN is stored in NVMD
 656         */
 657         DECLARE_COMPLETION_ONSTACK(completion);
 658         struct pm8001_ioctl_payload payload;
 659         u16 deviceid;
 660         int rc;
 661
 662         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 663         pm8001_ha->nvmd_completion = &completion;
 664
 665         if (pm8001_ha->chip_id == chip_8001) {
 666                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 667                         payload.minor_function = 4;
 668                         payload.rd_length = 4096;
 669                 } else {
 670                         payload.minor_function = 0;
 671                         payload.rd_length = 128;
 672                 }
 673         } else if ((pm8001_ha->chip_id == chip_8070 ||
 674                         pm8001_ha->chip_id == chip_8072) &&
 675                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 676                 payload.minor_function = 4;
 677                 payload.rd_length = 4096;
 678         } else {
 679                 payload.minor_function = 1;
 680                 payload.rd_length = 4096;
 681         }
 682         payload.offset = 0;
 683         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 684         if (!payload.func_specific) {
 685                 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
 686                 return;
 687         }
 688         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 689         if (rc) {
 690                 kfree(payload.func_specific);
 691                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 692                 return;
 693         }
 694         wait_for_completion(&completion);
 695
 696         for (i = 0, j = 0; i <= 7; i++, j++) {
 697                 if (pm8001_ha->chip_id == chip_8001) {
 698                         if (deviceid == 0x8081)
 699                                 pm8001_ha->sas_addr[j] =
 700                                         payload.func_specific[0x704 + i];
 701                         else if (deviceid == 0x0042)
 702                                 pm8001_ha->sas_addr[j] =
 703                                         payload.func_specific[0x010 + i];
 704                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 705                                 pm8001_ha->chip_id == chip_8072) &&
 706                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 707                         pm8001_ha->sas_addr[j] =
 708                                         payload.func_specific[0x010 + i];
 709                 } else
 710                         pm8001_ha->sas_addr[j] =
 711                                         payload.func_specific[0x804 + i];
 712         }
 713         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 714         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 715                 if (i && ((i % 4) == 0))
 716                         sas_add[7] = sas_add[7] + 4;
 717                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 718                         sas_add, SAS_ADDR_SIZE);
 719                 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
 720                            pm8001_ha->phy[i].dev_sas_addr);
 721         }
 722         kfree(payload.func_specific);
 723 #else
 724         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 725                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 726                 pm8001_ha->phy[i].dev_sas_addr =
 727                         cpu_to_be64((u64)
 728                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 729         }
 730         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 731                 SAS_ADDR_SIZE);
 732 #endif
 733 }
 734
 735 /*
 736  * pm8001_get_phy_settings_info : Read phy setting values.
 737  * @pm8001_ha : our hba.
 738  */
 739 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 740 {
 741
 742 #ifdef PM8001_READ_VPD
 743         /*OPTION ROM FLASH read for the SPC cards */
 744         DECLARE_COMPLETION_ONSTACK(completion);
 745         struct pm8001_ioctl_payload payload;
 746         int rc;
 747
 748         pm8001_ha->nvmd_completion = &completion;
 749         /* SAS ADDRESS read from flash / EEPROM */
 750         payload.minor_function = 6;
 751         payload.offset = 0;
 752         payload.rd_length = 4096;
 753         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 754         if (!payload.func_specific)
 755                 return -ENOMEM;
 756         /* Read phy setting values from flash */
 757         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 758         if (rc) {
 759                 kfree(payload.func_specific);
 760                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 761                 return -ENOMEM;
 762         }
 763         wait_for_completion(&completion);
 764         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 765         kfree(payload.func_specific);
 766 #endif
 767         return 0;
 768 }
 769
 770 struct pm8001_mpi3_phy_pg_trx_config {
 771         u32 LaneLosCfg;
 772         u32 LanePgaCfg1;
 773         u32 LanePisoCfg1;
 774         u32 LanePisoCfg2;
 775         u32 LanePisoCfg3;
 776         u32 LanePisoCfg4;
 777         u32 LanePisoCfg5;
 778         u32 LanePisoCfg6;
 779         u32 LaneBctCtrl;
 780 };
 781
 782 /**
 783  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
 784  * @pm8001_ha : our adapter
 785  * @phycfg : PHY config page to populate
 786  */
 787 static
 788 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 789                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 790 {
 791         phycfg->LaneLosCfg   = 0x00000132;
 792         phycfg->LanePgaCfg1  = 0x00203949;
 793         phycfg->LanePisoCfg1 = 0x000000FF;
 794         phycfg->LanePisoCfg2 = 0xFF000001;
 795         phycfg->LanePisoCfg3 = 0xE7011300;
 796         phycfg->LanePisoCfg4 = 0x631C40C0;
 797         phycfg->LanePisoCfg5 = 0xF8102036;
 798         phycfg->LanePisoCfg6 = 0xF74A1000;
 799         phycfg->LaneBctCtrl  = 0x00FB33F8;
 800 }
 801
 802 /**
 803  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
 804  * @pm8001_ha : our adapter
 805  * @phycfg : PHY config page to populate
 806  */
 807 static
 808 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 809                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 810 {
 811         phycfg->LaneLosCfg   = 0x00000132;
 812         phycfg->LanePgaCfg1  = 0x00203949;
 813         phycfg->LanePisoCfg1 = 0x000000FF;
 814         phycfg->LanePisoCfg2 = 0xFF000001;
 815         phycfg->LanePisoCfg3 = 0xE7011300;
 816         phycfg->LanePisoCfg4 = 0x63349140;
 817         phycfg->LanePisoCfg5 = 0xF8102036;
 818         phycfg->LanePisoCfg6 = 0xF80D9300;
 819         phycfg->LaneBctCtrl  = 0x00FB33F8;
 820 }
 821
 822 /**
 823  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
 824  * @pm8001_ha : our adapter
 825  * @phymask : The PHY mask
 826  */
 827 static
 828 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 829 {
 830         switch (pm8001_ha->pdev->subsystem_device) {
 831         case 0x0070: /* H1280 - 8 external 0 internal */
 832         case 0x0072: /* H12F0 - 16 external 0 internal */
 833                 *phymask = 0x0000;
 834                 break;
 835
 836         case 0x0071: /* H1208 - 0 external 8 internal */
 837         case 0x0073: /* H120F - 0 external 16 internal */
 838                 *phymask = 0xFFFF;
 839                 break;
 840
 841         case 0x0080: /* H1244 - 4 external 4 internal */
 842                 *phymask = 0x00F0;
 843                 break;
 844
 845         case 0x0081: /* H1248 - 4 external 8 internal */
 846                 *phymask = 0x0FF0;
 847                 break;
 848
 849         case 0x0082: /* H1288 - 8 external 8 internal */
 850                 *phymask = 0xFF00;
 851                 break;
 852
 853         default:
 854                 pm8001_dbg(pm8001_ha, INIT,
 855                            "Unknown subsystem device=0x%.04x\n",
 856                            pm8001_ha->pdev->subsystem_device);
 857         }
 858 }
 859
 860 /**
 861  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
 862  * @pm8001_ha : our adapter
 863  */
 864 static
 865 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 866 {
 867         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 868         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 869         int phymask = 0;
 870         int i = 0;
 871
 872         memset(&phycfg_int, 0, sizeof(phycfg_int));
 873         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 874
 875         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 876         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 877         pm8001_get_phy_mask(pm8001_ha, &phymask);
 878
 879         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 880                 if (phymask & (1 << i)) {/* Internal PHY */
 881                         pm8001_set_phy_profile_single(pm8001_ha, i,
 882                                         sizeof(phycfg_int) / sizeof(u32),
 883                                         (u32 *)&phycfg_int);
 884
 885                 } else { /* External PHY */
 886                         pm8001_set_phy_profile_single(pm8001_ha, i,
 887                                         sizeof(phycfg_ext) / sizeof(u32),
 888                                         (u32 *)&phycfg_ext);
 889                 }
 890         }
 891
 892         return 0;
 893 }
 894
 895 /**
 896  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 897  * @pm8001_ha : our hba.
 898  */
 899 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 900 {
 901         switch (pm8001_ha->pdev->subsystem_vendor) {
 902         case PCI_VENDOR_ID_ATTO:
 903                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 904                         return 0;
 905                 else
 906                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 907
 908         case PCI_VENDOR_ID_ADAPTEC2:
 909         case 0:
 910                 return 0;
 911
 912         default:
 913                 return pm8001_get_phy_settings_info(pm8001_ha);
 914         }
 915 }
 916
 917 #ifdef PM8001_USE_MSIX
 918 /**
 919  * pm8001_setup_msix - enable MSI-X interrupt
 920  * @pm8001_ha: our ha struct.
 921  */
 922 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 923 {
 924         u32 number_of_intr;
 925         int rc, cpu_online_count;
 926         unsigned int allocated_irq_vectors;
 927
 928         /* SPCv controllers supports 64 msi-x */
 929         if (pm8001_ha->chip_id == chip_8001) {
 930                 number_of_intr = 1;
 931         } else {
 932                 number_of_intr = PM8001_MAX_MSIX_VEC;
 933         }
 934
 935         cpu_online_count = num_online_cpus();
 936         number_of_intr = min_t(int, cpu_online_count, number_of_intr);
 937         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 938                         number_of_intr, PCI_IRQ_MSIX);
 939         allocated_irq_vectors = rc;
 940         if (rc < 0)
 941                 return rc;
 942
 943         /* Assigns the number of interrupts */
 944         number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
 945         pm8001_ha->number_of_intr = number_of_intr;
 946
 947         /* Maximum queue number updating in HBA structure */
 948         pm8001_ha->max_q_num = number_of_intr;
 949
 950         pm8001_dbg(pm8001_ha, INIT,
 951                    "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 952                    rc, pm8001_ha->number_of_intr);
 953         return 0;
 954 }
 955
 956 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 957 {
 958         u32 i = 0, j = 0;
 959         int flag = 0, rc = 0;
 960
 961         if (pm8001_ha->chip_id != chip_8001)
 962                 flag &= ~IRQF_SHARED;
 963
 964         pm8001_dbg(pm8001_ha, INIT,
 965                    "pci_enable_msix request number of intr %d\n",
 966                    pm8001_ha->number_of_intr);
 967
 968         for (i = 0; i < pm8001_ha->number_of_intr; i++) {
 969                 snprintf(pm8001_ha->intr_drvname[i],
 970                         sizeof(pm8001_ha->intr_drvname[0]),
 971                         "%s-%d", pm8001_ha->name, i);
 972                 pm8001_ha->irq_vector[i].irq_id = i;
 973                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 974
 975                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 976                         pm8001_interrupt_handler_msix, flag,
 977                         pm8001_ha->intr_drvname[i],
 978                         &(pm8001_ha->irq_vector[i]));
 979                 if (rc) {
 980                         for (j = 0; j < i; j++) {
 981                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 982                                         &(pm8001_ha->irq_vector[i]));
 983                         }
 984                         pci_free_irq_vectors(pm8001_ha->pdev);
 985                         break;
 986                 }
 987         }
 988
 989         return rc;
 990 }
 991 #endif
 992
 993 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
 994 {
 995         struct pci_dev *pdev;
 996
 997         pdev = pm8001_ha->pdev;
 998
 999 #ifdef PM8001_USE_MSIX
1000         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1001                 return pm8001_setup_msix(pm8001_ha);
1002         pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1003 #endif
1004         return 0;
1005 }
1006
1007 /**
1008  * pm8001_request_irq - register interrupt
1009  * @pm8001_ha: our ha struct.
1010  */
1011 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1012 {
1013         struct pci_dev *pdev;
1014         int rc;
1015
1016         pdev = pm8001_ha->pdev;
1017
1018 #ifdef PM8001_USE_MSIX
1019         if (pdev->msix_cap && pci_msi_enabled())
1020                 return pm8001_request_msix(pm8001_ha);
1021         else {
1022                 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1023                 goto intx;
1024         }
1025 #endif
1026
1027 intx:
1028         /* initialize the INT-X interrupt */
1029         pm8001_ha->irq_vector[0].irq_id = 0;
1030         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1031         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1032                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1033         return rc;
1034 }
1035
1036 /**
1037  * pm8001_pci_probe - probe supported device
1038  * @pdev: pci device which kernel has been prepared for.
1039  * @ent: pci device id
1040  *
1041  * This function is the main initialization function, when register a new
1042  * pci driver it is invoked, all struct an hardware initilization should be done
1043  * here, also, register interrupt
1044  */
1045 static int pm8001_pci_probe(struct pci_dev *pdev,
1046                             const struct pci_device_id *ent)
1047 {
1048         unsigned int rc;
1049         u32     pci_reg;
1050         u8      i = 0;
1051         struct pm8001_hba_info *pm8001_ha;
1052         struct Scsi_Host *shost = NULL;
1053         const struct pm8001_chip_info *chip;
1054         struct sas_ha_struct *sha;
1055
1056         dev_printk(KERN_INFO, &pdev->dev,
1057                 "pm80xx: driver version %s\n", DRV_VERSION);
1058         rc = pci_enable_device(pdev);
1059         if (rc)
1060                 goto err_out_enable;
1061         pci_set_master(pdev);
1062         /*
1063          * Enable pci slot busmaster by setting pci command register.
1064          * This is required by FW for Cyclone card.
1065          */
1066
1067         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1068         pci_reg |= 0x157;
1069         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1070         rc = pci_request_regions(pdev, DRV_NAME);
1071         if (rc)
1072                 goto err_out_disable;
1073         rc = pci_go_44(pdev);
1074         if (rc)
1075                 goto err_out_regions;
1076
1077         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1078         if (!shost) {
1079                 rc = -ENOMEM;
1080                 goto err_out_regions;
1081         }
1082         chip = &pm8001_chips[ent->driver_data];
1083         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1084         if (!sha) {
1085                 rc = -ENOMEM;
1086                 goto err_out_free_host;
1087         }
1088         SHOST_TO_SAS_HA(shost) = sha;
1089
1090         rc = pm8001_prep_sas_ha_init(shost, chip);
1091         if (rc) {
1092                 rc = -ENOMEM;
1093                 goto err_out_free;
1094         }
1095         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1096         /* ent->driver variable is used to differentiate between controllers */
1097         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1098         if (!pm8001_ha) {
1099                 rc = -ENOMEM;
1100                 goto err_out_free;
1101         }
1102
1103         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1104         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1105         if (rc) {
1106                 pm8001_dbg(pm8001_ha, FAIL,
1107                            "chip_init failed [ret: %d]\n", rc);
1108                 goto err_out_ha_free;
1109         }
1110
1111         rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1112         if (rc)
1113                 goto err_out_enable;
1114
1115         rc = scsi_add_host(shost, &pdev->dev);
1116         if (rc)
1117                 goto err_out_ha_free;
1118
1119         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1120         if (pm8001_ha->chip_id != chip_8001) {
1121                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1122                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1123                 /* setup thermal configuration. */
1124                 pm80xx_set_thermal_config(pm8001_ha);
1125         }
1126
1127         pm8001_init_sas_add(pm8001_ha);
1128         /* phy setting support for motherboard controller */
1129         rc = pm8001_configure_phy_settings(pm8001_ha);
1130         if (rc)
1131                 goto err_out_shost;
1132
1133         pm8001_post_sas_ha_init(shost, chip);
1134         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1135         if (rc) {
1136                 pm8001_dbg(pm8001_ha, FAIL,
1137                            "sas_register_ha failed [ret: %d]\n", rc);
1138                 goto err_out_shost;
1139         }
1140         list_add_tail(&pm8001_ha->list, &hba_list);
1141         pm8001_ha->flags = PM8001F_RUN_TIME;
1142         scsi_scan_host(pm8001_ha->shost);
1143         return 0;
1144
1145 err_out_shost:
1146         scsi_remove_host(pm8001_ha->shost);
1147 err_out_ha_free:
1148         pm8001_free(pm8001_ha);
1149 err_out_free:
1150         kfree(sha);
1151 err_out_free_host:
1152         scsi_host_put(shost);
1153 err_out_regions:
1154         pci_release_regions(pdev);
1155 err_out_disable:
1156         pci_disable_device(pdev);
1157 err_out_enable:
1158         return rc;
1159 }
1160
1161 /*
1162  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1163  * @pm8001_ha: our hba card information.
1164  * @shost: scsi host which has been allocated outside.
1165  */
1166 static int
1167 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1168                         struct pci_dev *pdev)
1169 {
1170         int i = 0;
1171         u32 max_out_io, ccb_count;
1172         u32 can_queue;
1173
1174         max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1175         ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1176
1177         /* Update to the scsi host*/
1178         can_queue = ccb_count - PM8001_RESERVE_SLOT;
1179         shost->can_queue = can_queue;
1180
1181         pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1182         if (!pm8001_ha->tags)
1183                 goto err_out;
1184
1185         /* Memory region for ccb_info*/
1186         pm8001_ha->ccb_info = (struct pm8001_ccb_info *)
1187                 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1188         if (!pm8001_ha->ccb_info) {
1189                 pm8001_dbg(pm8001_ha, FAIL,
1190                            "Unable to allocate memory for ccb\n");
1191                 goto err_out_noccb;
1192         }
1193         for (i = 0; i < ccb_count; i++) {
1194                 pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev,
1195                                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1196                                 &pm8001_ha->ccb_info[i].ccb_dma_handle);
1197                 if (!pm8001_ha->ccb_info[i].buf_prd) {
1198                         pm8001_dbg(pm8001_ha, FAIL,
1199                                    "pm80xx: ccb prd memory allocation error\n");
1200                         goto err_out;
1201                 }
1202                 pm8001_ha->ccb_info[i].task = NULL;
1203                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1204                 pm8001_ha->ccb_info[i].device = NULL;
1205                 ++pm8001_ha->tags_num;
1206         }
1207         return 0;
1208
1209 err_out_noccb:
1210         kfree(pm8001_ha->devices);
1211 err_out:
1212         return -ENOMEM;
1213 }
1214
1215 static void pm8001_pci_remove(struct pci_dev *pdev)
1216 {
1217         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1218         struct pm8001_hba_info *pm8001_ha;
1219         int i, j;
1220         pm8001_ha = sha->lldd_ha;
1221         sas_unregister_ha(sha);
1222         sas_remove_host(pm8001_ha->shost);
1223         list_del(&pm8001_ha->list);
1224         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1225         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1226
1227 #ifdef PM8001_USE_MSIX
1228         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1229                 synchronize_irq(pci_irq_vector(pdev, i));
1230         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1231                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1232         pci_free_irq_vectors(pdev);
1233 #else
1234         free_irq(pm8001_ha->irq, sha);
1235 #endif
1236 #ifdef PM8001_USE_TASKLET
1237         /* For non-msix and msix interrupts */
1238         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1239             (pm8001_ha->chip_id == chip_8001))
1240                 tasklet_kill(&pm8001_ha->tasklet[0]);
1241         else
1242                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1243                         tasklet_kill(&pm8001_ha->tasklet[j]);
1244 #endif
1245         scsi_host_put(pm8001_ha->shost);
1246         pm8001_free(pm8001_ha);
1247         kfree(sha->sas_phy);
1248         kfree(sha->sas_port);
1249         kfree(sha);
1250         pci_release_regions(pdev);
1251         pci_disable_device(pdev);
1252 }
1253
1254 /**
1255  * pm8001_pci_suspend - power management suspend main entry point
1256  * @pdev: PCI device struct
1257  * @state: PM state change to (usually PCI_D3)
1258  *
1259  * Returns 0 success, anything else error.
1260  */
1261 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1262 {
1263         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1264         struct pm8001_hba_info *pm8001_ha;
1265         int  i, j;
1266         u32 device_state;
1267         pm8001_ha = sha->lldd_ha;
1268         sas_suspend_ha(sha);
1269         flush_workqueue(pm8001_wq);
1270         scsi_block_requests(pm8001_ha->shost);
1271         if (!pdev->pm_cap) {
1272                 dev_err(&pdev->dev, " PCI PM not supported\n");
1273                 return -ENODEV;
1274         }
1275         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1276         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1277 #ifdef PM8001_USE_MSIX
1278         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1279                 synchronize_irq(pci_irq_vector(pdev, i));
1280         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1281                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1282         pci_free_irq_vectors(pdev);
1283 #else
1284         free_irq(pm8001_ha->irq, sha);
1285 #endif
1286 #ifdef PM8001_USE_TASKLET
1287         /* For non-msix and msix interrupts */
1288         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1289             (pm8001_ha->chip_id == chip_8001))
1290                 tasklet_kill(&pm8001_ha->tasklet[0]);
1291         else
1292                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1293                         tasklet_kill(&pm8001_ha->tasklet[j]);
1294 #endif
1295         device_state = pci_choose_state(pdev, state);
1296         pm8001_printk("pdev=0x%p, slot=%s, entering "
1297                       "operating state [D%d]\n", pdev,
1298                       pm8001_ha->name, device_state);
1299         pci_save_state(pdev);
1300         pci_disable_device(pdev);
1301         pci_set_power_state(pdev, device_state);
1302         return 0;
1303 }
1304
1305 /**
1306  * pm8001_pci_resume - power management resume main entry point
1307  * @pdev: PCI device struct
1308  *
1309  * Returns 0 success, anything else error.
1310  */
1311 static int pm8001_pci_resume(struct pci_dev *pdev)
1312 {
1313         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1314         struct pm8001_hba_info *pm8001_ha;
1315         int rc;
1316         u8 i = 0, j;
1317         u32 device_state;
1318         DECLARE_COMPLETION_ONSTACK(completion);
1319         pm8001_ha = sha->lldd_ha;
1320         device_state = pdev->current_state;
1321
1322         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1323                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1324
1325         pci_set_power_state(pdev, PCI_D0);
1326         pci_enable_wake(pdev, PCI_D0, 0);
1327         pci_restore_state(pdev);
1328         rc = pci_enable_device(pdev);
1329         if (rc) {
1330                 pm8001_printk("slot=%s Enable device failed during resume\n",
1331                               pm8001_ha->name);
1332                 goto err_out_enable;
1333         }
1334
1335         pci_set_master(pdev);
1336         rc = pci_go_44(pdev);
1337         if (rc)
1338                 goto err_out_disable;
1339         sas_prep_resume_ha(sha);
1340         /* chip soft rst only for spc */
1341         if (pm8001_ha->chip_id == chip_8001) {
1342                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1343                 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1344         }
1345         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1346         if (rc)
1347                 goto err_out_disable;
1348
1349         /* disable all the interrupt bits */
1350         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1351
1352         rc = pm8001_request_irq(pm8001_ha);
1353         if (rc)
1354                 goto err_out_disable;
1355 #ifdef PM8001_USE_TASKLET
1356         /*  Tasklet for non msi-x interrupt handler */
1357         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1358             (pm8001_ha->chip_id == chip_8001))
1359                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1360                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1361         else
1362                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1363                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1364                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1365 #endif
1366         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1367         if (pm8001_ha->chip_id != chip_8001) {
1368                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1369                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1370         }
1371
1372         /* Chip documentation for the 8070 and 8072 SPCv    */
1373         /* states that a 500ms minimum delay is required    */
1374         /* before issuing commands. Otherwise, the firmware */
1375         /* will enter an unrecoverable state.               */
1376
1377         if (pm8001_ha->chip_id == chip_8070 ||
1378                 pm8001_ha->chip_id == chip_8072) {
1379                 mdelay(500);
1380         }
1381
1382         /* Spin up the PHYs */
1383
1384         pm8001_ha->flags = PM8001F_RUN_TIME;
1385         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1386                 pm8001_ha->phy[i].enable_completion = &completion;
1387                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1388                 wait_for_completion(&completion);
1389         }
1390         sas_resume_ha(sha);
1391         return 0;
1392
1393 err_out_disable:
1394         scsi_remove_host(pm8001_ha->shost);
1395         pci_disable_device(pdev);
1396 err_out_enable:
1397         return rc;
1398 }
1399
1400 /* update of pci device, vendor id and driver data with
1401  * unique value for each of the controller
1402  */
1403 static struct pci_device_id pm8001_pci_table[] = {
1404         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1405         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1406         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1407         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1408         /* Support for SPC/SPCv/SPCve controllers */
1409         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1410         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1411         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1412         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1413         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1414         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1415         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1416         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1417         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1418         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1419         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1420         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1421         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1422         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1423         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1424         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1425                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1426         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1427                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1428         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1429                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1430         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1431                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1432         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1433                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1434         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1435                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1436         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1437                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1438         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1439                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1440         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1441                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1442         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1443                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1444         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1445                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1446         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1447                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1448         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1449                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1450         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1451                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1452         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1453                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1454         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1455                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1456         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1457                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1458         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1459                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1460         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1461                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1462         { PCI_VENDOR_ID_ATTO, 0x8070,
1463                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1464         { PCI_VENDOR_ID_ATTO, 0x8070,
1465                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1466         { PCI_VENDOR_ID_ATTO, 0x8072,
1467                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1468         { PCI_VENDOR_ID_ATTO, 0x8072,
1469                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1470         { PCI_VENDOR_ID_ATTO, 0x8070,
1471                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1472         { PCI_VENDOR_ID_ATTO, 0x8072,
1473                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1474         { PCI_VENDOR_ID_ATTO, 0x8072,
1475                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1476         {} /* terminate list */
1477 };
1478
1479 static struct pci_driver pm8001_pci_driver = {
1480         .name           = DRV_NAME,
1481         .id_table       = pm8001_pci_table,
1482         .probe          = pm8001_pci_probe,
1483         .remove         = pm8001_pci_remove,
1484         .suspend        = pm8001_pci_suspend,
1485         .resume         = pm8001_pci_resume,
1486 };
1487
1488 /**
1489  *      pm8001_init - initialize scsi transport template
1490  */
1491 static int __init pm8001_init(void)
1492 {
1493         int rc = -ENOMEM;
1494
1495         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1496         if (!pm8001_wq)
1497                 goto err;
1498
1499         pm8001_id = 0;
1500         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1501         if (!pm8001_stt)
1502                 goto err_wq;
1503         rc = pci_register_driver(&pm8001_pci_driver);
1504         if (rc)
1505                 goto err_tp;
1506         return 0;
1507
1508 err_tp:
1509         sas_release_transport(pm8001_stt);
1510 err_wq:
1511         destroy_workqueue(pm8001_wq);
1512 err:
1513         return rc;
1514 }
1515
1516 static void __exit pm8001_exit(void)
1517 {
1518         pci_unregister_driver(&pm8001_pci_driver);
1519         sas_release_transport(pm8001_stt);
1520         destroy_workqueue(pm8001_wq);
1521 }
1522
1523 module_init(pm8001_init);
1524 module_exit(pm8001_exit);
1525
1526 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1527 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1528 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1529 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1530 MODULE_DESCRIPTION(
1531                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1532                 "SAS/SATA controller driver");
1533 MODULE_VERSION(DRV_VERSION);
1534 MODULE_LICENSE("GPL");
1535 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1536