drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192         u32 ib_offset = pm8001_ha->ib_offset;
 193         u32 ob_offset = pm8001_ha->ob_offset;
 194         u32 ci_offset = pm8001_ha->ci_offset;
 195         u32 pi_offset = pm8001_ha->pi_offset;
 196
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 199         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 201         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 203                                                                          0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 205                                                                          0;
 206         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 208         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 210
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 212                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 214                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 215         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 216                 PM8001_EVENT_LOG_SIZE;
 217         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 219                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 221                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 222         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 223                 PM8001_EVENT_LOG_SIZE;
 224         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 225         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 226         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 227                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 228                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 229                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 230                         pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
 231                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 232                 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
 233                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 234                   (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
 235                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 236                         pm8001_ha->memoryMap.region[ib_offset + i].total_len;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 238                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
 239                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 240                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
 241                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 242                         pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
 243                 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
 244                 offsetib = i * 0x20;
 245                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 246                         get_pci_bar_index(pm8001_mr32(addressib,
 247                                 (offsetib + 0x14)));
 248                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 249                         pm8001_mr32(addressib, (offsetib + 0x18));
 250                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 251                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 252         }
 253         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 254                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 255                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 256                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 257                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
 258                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 259                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
 260                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 261                   (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
 262                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 263                         pm8001_ha->memoryMap.region[ob_offset + i].total_len;
 264                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 265                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
 266                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 267                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
 268                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 269                         0 | (10 << 16) | (i << 24);
 270                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 271                         pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
 272                 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
 273                 offsetob = i * 0x24;
 274                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 275                         get_pci_bar_index(pm8001_mr32(addressob,
 276                         offsetob + 0x14));
 277                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 278                         pm8001_mr32(addressob, (offsetob + 0x18));
 279                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 280                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 281         }
 282 }
 283
 284 /**
 285  * update_main_config_table - update the main default table to the HBA.
 286  * @pm8001_ha: our hba card information
 287  */
 288 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 289 {
 290         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 291         pm8001_mw32(address, 0x24,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 293         pm8001_mw32(address, 0x28,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 295         pm8001_mw32(address, 0x2C,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 297         pm8001_mw32(address, 0x30,
 298                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 299         pm8001_mw32(address, 0x34,
 300                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 301         pm8001_mw32(address, 0x38,
 302                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                         outbound_tgt_ITNexus_event_pid0_3);
 304         pm8001_mw32(address, 0x3C,
 305                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                         outbound_tgt_ITNexus_event_pid4_7);
 307         pm8001_mw32(address, 0x40,
 308                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                         outbound_tgt_ssp_event_pid0_3);
 310         pm8001_mw32(address, 0x44,
 311                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                         outbound_tgt_ssp_event_pid4_7);
 313         pm8001_mw32(address, 0x48,
 314                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 315                                         outbound_tgt_smp_event_pid0_3);
 316         pm8001_mw32(address, 0x4C,
 317                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 318                                         outbound_tgt_smp_event_pid4_7);
 319         pm8001_mw32(address, 0x50,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 321         pm8001_mw32(address, 0x54,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 323         pm8001_mw32(address, 0x58,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 325         pm8001_mw32(address, 0x5C,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 327         pm8001_mw32(address, 0x60,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 329         pm8001_mw32(address, 0x64,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 331         pm8001_mw32(address, 0x68,
 332                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 333         pm8001_mw32(address, 0x6C,
 334                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 335         pm8001_mw32(address, 0x70,
 336                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 337 }
 338
 339 /**
 340  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 341  * @pm8001_ha: our hba card information
 342  * @number: entry in the queue
 343  */
 344 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 345                                      int number)
 346 {
 347         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 348         u16 offset = number * 0x20;
 349         pm8001_mw32(address, offset + 0x00,
 350                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 351         pm8001_mw32(address, offset + 0x04,
 352                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 353         pm8001_mw32(address, offset + 0x08,
 354                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 355         pm8001_mw32(address, offset + 0x0C,
 356                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 357         pm8001_mw32(address, offset + 0x10,
 358                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 359 }
 360
 361 /**
 362  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 363  * @pm8001_ha: our hba card information
 364  * @number: entry in the queue
 365  */
 366 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 367                                       int number)
 368 {
 369         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 370         u16 offset = number * 0x24;
 371         pm8001_mw32(address, offset + 0x00,
 372                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 373         pm8001_mw32(address, offset + 0x04,
 374                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 375         pm8001_mw32(address, offset + 0x08,
 376                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 377         pm8001_mw32(address, offset + 0x0C,
 378                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 379         pm8001_mw32(address, offset + 0x10,
 380                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 381         pm8001_mw32(address, offset + 0x1C,
 382                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 383 }
 384
 385 /**
 386  * pm8001_bar4_shift - function is called to shift BAR base address
 387  * @pm8001_ha : our hba card information
 388  * @shiftValue : shifting value in memory bar.
 389  */
 390 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 391 {
 392         u32 regVal;
 393         unsigned long start;
 394
 395         /* program the inbound AXI translation Lower Address */
 396         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 397
 398         /* confirm the setting is written */
 399         start = jiffies + HZ; /* 1 sec */
 400         do {
 401                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 402         } while ((regVal != shiftValue) && time_before(jiffies, start));
 403
 404         if (regVal != shiftValue) {
 405                 pm8001_dbg(pm8001_ha, INIT,
 406                            "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
 407                            regVal);
 408                 return -1;
 409         }
 410         return 0;
 411 }
 412
 413 /**
 414  * mpi_set_phys_g3_with_ssc
 415  * @pm8001_ha: our hba card information
 416  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 417  */
 418 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 419                                      u32 SSCbit)
 420 {
 421         u32 offset, i;
 422         unsigned long flags;
 423
 424 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 425 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 426 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 427 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 428 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 429 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 430 #define SNW3_PHY_CAPABILITIES_PARITY 31
 431
 432    /*
 433     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 434     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 435     */
 436         spin_lock_irqsave(&pm8001_ha->lock, flags);
 437         if (-1 == pm8001_bar4_shift(pm8001_ha,
 438                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 439                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 440                 return;
 441         }
 442
 443         for (i = 0; i < 4; i++) {
 444                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 445                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 446         }
 447         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 448         if (-1 == pm8001_bar4_shift(pm8001_ha,
 449                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 450                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 451                 return;
 452         }
 453         for (i = 4; i < 8; i++) {
 454                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 455                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 456         }
 457         /*************************************************************
 458         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 459         Device MABC SMOD0 Controls
 460         Address: (via MEMBASE-III):
 461         Using shifted destination address 0x0_0000: with Offset 0xD8
 462
 463         31:28 R/W Reserved Do not change
 464         27:24 R/W SAS_SMOD_SPRDUP 0000
 465         23:20 R/W SAS_SMOD_SPRDDN 0000
 466         19:0  R/W  Reserved Do not change
 467         Upon power-up this register will read as 0x8990c016,
 468         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 469         so that the written value will be 0x8090c016.
 470         This will ensure only down-spreading SSC is enabled on the SPC.
 471         *************************************************************/
 472         pm8001_cr32(pm8001_ha, 2, 0xd8);
 473         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 474
 475         /*set the shifted destination address to 0x0 to avoid error operation */
 476         pm8001_bar4_shift(pm8001_ha, 0x0);
 477         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 478         return;
 479 }
 480
 481 /**
 482  * mpi_set_open_retry_interval_reg
 483  * @pm8001_ha: our hba card information
 484  * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 485  */
 486 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 487                                             u32 interval)
 488 {
 489         u32 offset;
 490         u32 value;
 491         u32 i;
 492         unsigned long flags;
 493
 494 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 495 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 496 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 497 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 498 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 499
 500         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 501         spin_lock_irqsave(&pm8001_ha->lock, flags);
 502         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 503         if (-1 == pm8001_bar4_shift(pm8001_ha,
 504                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 505                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 506                 return;
 507         }
 508         for (i = 0; i < 4; i++) {
 509                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 510                 pm8001_cw32(pm8001_ha, 2, offset, value);
 511         }
 512
 513         if (-1 == pm8001_bar4_shift(pm8001_ha,
 514                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 515                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 516                 return;
 517         }
 518         for (i = 4; i < 8; i++) {
 519                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 520                 pm8001_cw32(pm8001_ha, 2, offset, value);
 521         }
 522         /*set the shifted destination address to 0x0 to avoid error operation */
 523         pm8001_bar4_shift(pm8001_ha, 0x0);
 524         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 525         return;
 526 }
 527
 528 /**
 529  * mpi_init_check - check firmware initialization status.
 530  * @pm8001_ha: our hba card information
 531  */
 532 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 533 {
 534         u32 max_wait_count;
 535         u32 value;
 536         u32 gst_len_mpistate;
 537         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 538         table is updated */
 539         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 540         /* wait until Inbound DoorBell Clear Register toggled */
 541         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 542         do {
 543                 udelay(1);
 544                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 545                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 546         } while ((value != 0) && (--max_wait_count));
 547
 548         if (!max_wait_count)
 549                 return -1;
 550         /* check the MPI-State for initialization */
 551         gst_len_mpistate =
 552                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 553                 GST_GSTLEN_MPIS_OFFSET);
 554         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 555                 return -1;
 556         /* check MPI Initialization error */
 557         gst_len_mpistate = gst_len_mpistate >> 16;
 558         if (0x0000 != gst_len_mpistate)
 559                 return -1;
 560         return 0;
 561 }
 562
 563 /**
 564  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 565  * @pm8001_ha: our hba card information
 566  */
 567 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 568 {
 569         u32 value, value1;
 570         u32 max_wait_count;
 571         /* check error state */
 572         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 573         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 574         /* check AAP error */
 575         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 576                 /* error state */
 577                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 578                 return -1;
 579         }
 580
 581         /* check IOP error */
 582         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 583                 /* error state */
 584                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 585                 return -1;
 586         }
 587
 588         /* bit 4-31 of scratch pad1 should be zeros if it is not
 589         in error state*/
 590         if (value & SCRATCH_PAD1_STATE_MASK) {
 591                 /* error case */
 592                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 593                 return -1;
 594         }
 595
 596         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 597         in error state */
 598         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 599                 /* error case */
 600                 return -1;
 601         }
 602
 603         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 604
 605         /* wait until scratch pad 1 and 2 registers in ready state  */
 606         do {
 607                 udelay(1);
 608                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 609                         & SCRATCH_PAD1_RDY;
 610                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 611                         & SCRATCH_PAD2_RDY;
 612                 if ((--max_wait_count) == 0)
 613                         return -1;
 614         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 615         return 0;
 616 }
 617
 618 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 619 {
 620         void __iomem *base_addr;
 621         u32     value;
 622         u32     offset;
 623         u32     pcibar;
 624         u32     pcilogic;
 625
 626         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 627         offset = value & 0x03FFFFFF;
 628         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
 629         pcilogic = (value & 0xFC000000) >> 26;
 630         pcibar = get_pci_bar_index(pcilogic);
 631         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
 632         pm8001_ha->main_cfg_tbl_addr = base_addr =
 633                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 634         pm8001_ha->general_stat_tbl_addr =
 635                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 636         pm8001_ha->inbnd_q_tbl_addr =
 637                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 638         pm8001_ha->outbnd_q_tbl_addr =
 639                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 640 }
 641
 642 /**
 643  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 644  * @pm8001_ha: our hba card information
 645  */
 646 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 647 {
 648         u32 i = 0;
 649         u16 deviceid;
 650         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 651         /* 8081 controllers need BAR shift to access MPI space
 652         * as this is shared with BIOS data */
 653         if (deviceid == 0x8081 || deviceid == 0x0042) {
 654                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 655                         pm8001_dbg(pm8001_ha, FAIL,
 656                                    "Shift Bar4 to 0x%x failed\n",
 657                                    GSM_SM_BASE);
 658                         return -1;
 659                 }
 660         }
 661         /* check the firmware status */
 662         if (-1 == check_fw_ready(pm8001_ha)) {
 663                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
 664                 return -EBUSY;
 665         }
 666
 667         /* Initialize pci space address eg: mpi offset */
 668         init_pci_device_addresses(pm8001_ha);
 669         init_default_table_values(pm8001_ha);
 670         read_main_config_table(pm8001_ha);
 671         read_general_status_table(pm8001_ha);
 672         read_inbnd_queue_table(pm8001_ha);
 673         read_outbnd_queue_table(pm8001_ha);
 674         /* update main config table ,inbound table and outbound table */
 675         update_main_config_table(pm8001_ha);
 676         for (i = 0; i < pm8001_ha->max_q_num; i++)
 677                 update_inbnd_queue_table(pm8001_ha, i);
 678         for (i = 0; i < pm8001_ha->max_q_num; i++)
 679                 update_outbnd_queue_table(pm8001_ha, i);
 680         /* 8081 controller donot require these operations */
 681         if (deviceid != 0x8081 && deviceid != 0x0042) {
 682                 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 683                 /* 7->130ms, 34->500ms, 119->1.5s */
 684                 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 685         }
 686         /* notify firmware update finished and check initialization status */
 687         if (0 == mpi_init_check(pm8001_ha)) {
 688                 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
 689         } else
 690                 return -EBUSY;
 691         /*This register is a 16-bit timer with a resolution of 1us. This is the
 692         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 693         Zero is not a valid value. A value of 1 in the register will cause the
 694         interrupts to be normal. A value greater than 1 will cause coalescing
 695         delays.*/
 696         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 697         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 698         return 0;
 699 }
 700
 701 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 702 {
 703         u32 max_wait_count;
 704         u32 value;
 705         u32 gst_len_mpistate;
 706         u16 deviceid;
 707         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 708         if (deviceid == 0x8081 || deviceid == 0x0042) {
 709                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 710                         pm8001_dbg(pm8001_ha, FAIL,
 711                                    "Shift Bar4 to 0x%x failed\n",
 712                                    GSM_SM_BASE);
 713                         return -1;
 714                 }
 715         }
 716         init_pci_device_addresses(pm8001_ha);
 717         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 718         table is stop */
 719         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 720
 721         /* wait until Inbound DoorBell Clear Register toggled */
 722         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 723         do {
 724                 udelay(1);
 725                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 726                 value &= SPC_MSGU_CFG_TABLE_RESET;
 727         } while ((value != 0) && (--max_wait_count));
 728
 729         if (!max_wait_count) {
 730                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
 731                            value);
 732                 return -1;
 733         }
 734
 735         /* check the MPI-State for termination in progress */
 736         /* wait until Inbound DoorBell Clear Register toggled */
 737         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 738         do {
 739                 udelay(1);
 740                 gst_len_mpistate =
 741                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 742                         GST_GSTLEN_MPIS_OFFSET);
 743                 if (GST_MPI_STATE_UNINIT ==
 744                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 745                         break;
 746         } while (--max_wait_count);
 747         if (!max_wait_count) {
 748                 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
 749                            gst_len_mpistate & GST_MPI_STATE_MASK);
 750                 return -1;
 751         }
 752         return 0;
 753 }
 754
 755 /**
 756  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 757  * @pm8001_ha: our hba card information
 758  */
 759 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 760 {
 761         u32 regVal, regVal1, regVal2;
 762         if (mpi_uninit_check(pm8001_ha) != 0) {
 763                 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
 764                 return -1;
 765         }
 766         /* read the scratch pad 2 register bit 2 */
 767         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 768                 & SCRATCH_PAD2_FWRDY_RST;
 769         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 770                 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
 771         } else {
 772                 unsigned long flags;
 773                 /* Trigger NMI twice via RB6 */
 774                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 775                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 776                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 777                         pm8001_dbg(pm8001_ha, FAIL,
 778                                    "Shift Bar4 to 0x%x failed\n",
 779                                    RB6_ACCESS_REG);
 780                         return -1;
 781                 }
 782                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 783                         RB6_MAGIC_NUMBER_RST);
 784                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 785                 /* wait for 100 ms */
 786                 mdelay(100);
 787                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 788                         SCRATCH_PAD2_FWRDY_RST;
 789                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 790                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 791                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 792                         pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 793                                    regVal1, regVal2);
 794                         pm8001_dbg(pm8001_ha, FAIL,
 795                                    "SCRATCH_PAD0 value = 0x%x\n",
 796                                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
 797                         pm8001_dbg(pm8001_ha, FAIL,
 798                                    "SCRATCH_PAD3 value = 0x%x\n",
 799                                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
 800                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 801                         return -1;
 802                 }
 803                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 804         }
 805         return 0;
 806 }
 807
 808 /**
 809  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 810  * the FW register status to the originated status.
 811  * @pm8001_ha: our hba card information
 812  */
 813 static int
 814 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 815 {
 816         u32     regVal, toggleVal;
 817         u32     max_wait_count;
 818         u32     regVal1, regVal2, regVal3;
 819         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 820         unsigned long flags;
 821
 822         /* step1: Check FW is ready for soft reset */
 823         if (soft_reset_ready_check(pm8001_ha) != 0) {
 824                 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
 825                 return -1;
 826         }
 827
 828         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 829         value to clear */
 830         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 831         spin_lock_irqsave(&pm8001_ha->lock, flags);
 832         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 833                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 834                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 835                            MBIC_AAP1_ADDR_BASE);
 836                 return -1;
 837         }
 838         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 839         pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
 840                    regVal);
 841         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 842         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 843         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 844                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 845                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 846                            MBIC_IOP_ADDR_BASE);
 847                 return -1;
 848         }
 849         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 850         pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
 851                    regVal);
 852         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 853
 854         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 855         pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
 856                    regVal);
 857         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 858
 859         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 860         pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt  = 0x%x\n",
 861                    regVal);
 862         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 863
 864         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 865         pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
 866                    regVal);
 867         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 868
 869         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 870         pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
 871         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 872
 873         /* read the scratch pad 1 register bit 2 */
 874         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 875                 & SCRATCH_PAD1_RST;
 876         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 877
 878         /* set signature in host scratch pad0 register to tell SPC that the
 879         host performs the soft reset */
 880         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 881
 882         /* read required registers for confirmming */
 883         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 884         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 885                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 886                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 887                            GSM_ADDR_BASE);
 888                 return -1;
 889         }
 890         pm8001_dbg(pm8001_ha, INIT,
 891                    "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
 892                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
 893
 894         /* step 3: host read GSM Configuration and Reset register */
 895         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 896         /* Put those bits to low */
 897         /* GSM XCBI offset = 0x70 0000
 898         0x00 Bit 13 COM_SLV_SW_RSTB 1
 899         0x00 Bit 12 QSSP_SW_RSTB 1
 900         0x00 Bit 11 RAAE_SW_RSTB 1
 901         0x00 Bit 9 RB_1_SW_RSTB 1
 902         0x00 Bit 8 SM_SW_RSTB 1
 903         */
 904         regVal &= ~(0x00003b00);
 905         /* host write GSM Configuration and Reset register */
 906         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 907         pm8001_dbg(pm8001_ha, INIT,
 908                    "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
 909                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
 910
 911         /* step 4: */
 912         /* disable GSM - Read Address Parity Check */
 913         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 914         pm8001_dbg(pm8001_ha, INIT,
 915                    "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
 916                    regVal1);
 917         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 918         pm8001_dbg(pm8001_ha, INIT,
 919                    "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
 920                    pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
 921
 922         /* disable GSM - Write Address Parity Check */
 923         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 924         pm8001_dbg(pm8001_ha, INIT,
 925                    "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
 926                    regVal2);
 927         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 928         pm8001_dbg(pm8001_ha, INIT,
 929                    "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
 930                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
 931
 932         /* disable GSM - Write Data Parity Check */
 933         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 934         pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
 935                    regVal3);
 936         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 937         pm8001_dbg(pm8001_ha, INIT,
 938                    "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
 939                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
 940
 941         /* step 5: delay 10 usec */
 942         udelay(10);
 943         /* step 5-b: set GPIO-0 output control to tristate anyway */
 944         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 945                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 946                 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
 947                            GPIO_ADDR_BASE);
 948                 return -1;
 949         }
 950         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 951         pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
 952                    regVal);
 953         /* set GPIO-0 output control to tri-state */
 954         regVal &= 0xFFFFFFFC;
 955         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 956
 957         /* Step 6: Reset the IOP and AAP1 */
 958         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 959         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 960                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 961                 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
 962                            SPC_TOP_LEVEL_ADDR_BASE);
 963                 return -1;
 964         }
 965         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 966         pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
 967                    regVal);
 968         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 969         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 970
 971         /* step 7: Reset the BDMA/OSSP */
 972         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 973         pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
 974                    regVal);
 975         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 976         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 977
 978         /* step 8: delay 10 usec */
 979         udelay(10);
 980
 981         /* step 9: bring the BDMA and OSSP out of reset */
 982         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 983         pm8001_dbg(pm8001_ha, INIT,
 984                    "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
 985                    regVal);
 986         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 987         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 988
 989         /* step 10: delay 10 usec */
 990         udelay(10);
 991
 992         /* step 11: reads and sets the GSM Configuration and Reset Register */
 993         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 994         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 995                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 996                 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
 997                            GSM_ADDR_BASE);
 998                 return -1;
 999         }
1000         pm8001_dbg(pm8001_ha, INIT,
1001                    "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1002                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1003         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1004         /* Put those bits to high */
1005         /* GSM XCBI offset = 0x70 0000
1006         0x00 Bit 13 COM_SLV_SW_RSTB 1
1007         0x00 Bit 12 QSSP_SW_RSTB 1
1008         0x00 Bit 11 RAAE_SW_RSTB 1
1009         0x00 Bit 9   RB_1_SW_RSTB 1
1010         0x00 Bit 8   SM_SW_RSTB 1
1011         */
1012         regVal |= (GSM_CONFIG_RESET_VALUE);
1013         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1014         pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1015                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1016
1017         /* step 12: Restore GSM - Read Address Parity Check */
1018         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1019         /* just for debugging */
1020         pm8001_dbg(pm8001_ha, INIT,
1021                    "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1022                    regVal);
1023         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1024         pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1025                    pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1026         /* Restore GSM - Write Address Parity Check */
1027         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1028         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1029         pm8001_dbg(pm8001_ha, INIT,
1030                    "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1031                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1032         /* Restore GSM - Write Data Parity Check */
1033         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1034         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1035         pm8001_dbg(pm8001_ha, INIT,
1036                    "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n",
1037                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1038
1039         /* step 13: bring the IOP and AAP1 out of reset */
1040         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1041         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1042                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1043                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1044                            SPC_TOP_LEVEL_ADDR_BASE);
1045                 return -1;
1046         }
1047         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1048         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1049         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1050
1051         /* step 14: delay 10 usec - Normal Mode */
1052         udelay(10);
1053         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1054         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1055                 /* step 15 (Normal Mode): wait until scratch pad1 register
1056                 bit 2 toggled */
1057                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1058                 do {
1059                         udelay(1);
1060                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1061                                 SCRATCH_PAD1_RST;
1062                 } while ((regVal != toggleVal) && (--max_wait_count));
1063
1064                 if (!max_wait_count) {
1065                         regVal = pm8001_cr32(pm8001_ha, 0,
1066                                 MSGU_SCRATCH_PAD_1);
1067                         pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1068                                    toggleVal, regVal);
1069                         pm8001_dbg(pm8001_ha, FAIL,
1070                                    "SCRATCH_PAD0 value = 0x%x\n",
1071                                    pm8001_cr32(pm8001_ha, 0,
1072                                                MSGU_SCRATCH_PAD_0));
1073                         pm8001_dbg(pm8001_ha, FAIL,
1074                                    "SCRATCH_PAD2 value = 0x%x\n",
1075                                    pm8001_cr32(pm8001_ha, 0,
1076                                                MSGU_SCRATCH_PAD_2));
1077                         pm8001_dbg(pm8001_ha, FAIL,
1078                                    "SCRATCH_PAD3 value = 0x%x\n",
1079                                    pm8001_cr32(pm8001_ha, 0,
1080                                                MSGU_SCRATCH_PAD_3));
1081                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1082                         return -1;
1083                 }
1084
1085                 /* step 16 (Normal) - Clear ODMR and ODCR */
1086                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1087                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1088
1089                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1090                 ready - 1 sec timeout */
1091                 /* Wait for the SPC Configuration Table to be ready */
1092                 if (check_fw_ready(pm8001_ha) == -1) {
1093                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1094                         /* return error if MPI Configuration Table not ready */
1095                         pm8001_dbg(pm8001_ha, INIT,
1096                                    "FW not ready SCRATCH_PAD1 = 0x%x\n",
1097                                    regVal);
1098                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1099                         /* return error if MPI Configuration Table not ready */
1100                         pm8001_dbg(pm8001_ha, INIT,
1101                                    "FW not ready SCRATCH_PAD2 = 0x%x\n",
1102                                    regVal);
1103                         pm8001_dbg(pm8001_ha, INIT,
1104                                    "SCRATCH_PAD0 value = 0x%x\n",
1105                                    pm8001_cr32(pm8001_ha, 0,
1106                                                MSGU_SCRATCH_PAD_0));
1107                         pm8001_dbg(pm8001_ha, INIT,
1108                                    "SCRATCH_PAD3 value = 0x%x\n",
1109                                    pm8001_cr32(pm8001_ha, 0,
1110                                                MSGU_SCRATCH_PAD_3));
1111                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1112                         return -1;
1113                 }
1114         }
1115         pm8001_bar4_shift(pm8001_ha, 0);
1116         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1117
1118         pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1119         return 0;
1120 }
1121
1122 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1123 {
1124         u32 i;
1125         u32 regVal;
1126         pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1127
1128         /* do SPC chip reset. */
1129         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1130         regVal &= ~(SPC_REG_RESET_DEVICE);
1131         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1132
1133         /* delay 10 usec */
1134         udelay(10);
1135
1136         /* bring chip reset out of reset */
1137         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1138         regVal |= SPC_REG_RESET_DEVICE;
1139         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1140
1141         /* delay 10 usec */
1142         udelay(10);
1143
1144         /* wait for 20 msec until the firmware gets reloaded */
1145         i = 20;
1146         do {
1147                 mdelay(1);
1148         } while ((--i) != 0);
1149
1150         pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1151 }
1152
1153 /**
1154  * pm8001_chip_iounmap - which mapped when initialized.
1155  * @pm8001_ha: our hba card information
1156  */
1157 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1158 {
1159         s8 bar, logical = 0;
1160         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1161                 /*
1162                 ** logical BARs for SPC:
1163                 ** bar 0 and 1 - logical BAR0
1164                 ** bar 2 and 3 - logical BAR1
1165                 ** bar4 - logical BAR2
1166                 ** bar5 - logical BAR3
1167                 ** Skip the appropriate assignments:
1168                 */
1169                 if ((bar == 1) || (bar == 3))
1170                         continue;
1171                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1172                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1173                         logical++;
1174                 }
1175         }
1176 }
1177
1178 #ifndef PM8001_USE_MSIX
1179 /**
1180  * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1181  * @pm8001_ha: our hba card information
1182  */
1183 static void
1184 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1185 {
1186         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1187         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1188 }
1189
1190 /**
1191  * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1192  * @pm8001_ha: our hba card information
1193  */
1194 static void
1195 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1196 {
1197         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1198 }
1199
1200 #else
1201
1202 /**
1203  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1204  * @pm8001_ha: our hba card information
1205  * @int_vec_idx: interrupt number to enable
1206  */
1207 static void
1208 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1209         u32 int_vec_idx)
1210 {
1211         u32 msi_index;
1212         u32 value;
1213         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1214         msi_index += MSIX_TABLE_BASE;
1215         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1216         value = (1 << int_vec_idx);
1217         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1218
1219 }
1220
1221 /**
1222  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1223  * @pm8001_ha: our hba card information
1224  * @int_vec_idx: interrupt number to disable
1225  */
1226 static void
1227 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1228         u32 int_vec_idx)
1229 {
1230         u32 msi_index;
1231         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1232         msi_index += MSIX_TABLE_BASE;
1233         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1234 }
1235 #endif
1236
1237 /**
1238  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1239  * @pm8001_ha: our hba card information
1240  * @vec: unused
1241  */
1242 static void
1243 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1244 {
1245 #ifdef PM8001_USE_MSIX
1246         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1247 #else
1248         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1249 #endif
1250 }
1251
1252 /**
1253  * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt
1254  * @pm8001_ha: our hba card information
1255  * @vec: unused
1256  */
1257 static void
1258 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1259 {
1260 #ifdef PM8001_USE_MSIX
1261         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1262 #else
1263         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1264 #endif
1265 }
1266
1267 /**
1268  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1269  * inbound queue.
1270  * @circularQ: the inbound queue  we want to transfer to HBA.
1271  * @messageSize: the message size of this transfer, normally it is 64 bytes
1272  * @messagePtr: the pointer to message.
1273  */
1274 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1275                             u16 messageSize, void **messagePtr)
1276 {
1277         u32 offset, consumer_index;
1278         struct mpi_msg_hdr *msgHeader;
1279         u8 bcCount = 1; /* only support single buffer */
1280
1281         /* Checks is the requested message size can be allocated in this queue*/
1282         if (messageSize > IOMB_SIZE_SPCV) {
1283                 *messagePtr = NULL;
1284                 return -1;
1285         }
1286
1287         /* Stores the new consumer index */
1288         consumer_index = pm8001_read_32(circularQ->ci_virt);
1289         circularQ->consumer_index = cpu_to_le32(consumer_index);
1290         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1291                 le32_to_cpu(circularQ->consumer_index)) {
1292                 *messagePtr = NULL;
1293                 return -1;
1294         }
1295         /* get memory IOMB buffer address */
1296         offset = circularQ->producer_idx * messageSize;
1297         /* increment to next bcCount element */
1298         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1299                                 % PM8001_MPI_QUEUE;
1300         /* Adds that distance to the base of the region virtual address plus
1301         the message header size*/
1302         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1303         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1304         return 0;
1305 }
1306
1307 /**
1308  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1309  * FW to tell the fw to get this message from IOMB.
1310  * @pm8001_ha: our hba card information
1311  * @circularQ: the inbound queue we want to transfer to HBA.
1312  * @opCode: the operation code represents commands which LLDD and fw recognized.
1313  * @payload: the command payload of each operation command.
1314  * @nb: size in bytes of the command payload
1315  * @responseQueue: queue to interrupt on w/ command response (if any)
1316  */
1317 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1318                          struct inbound_queue_table *circularQ,
1319                          u32 opCode, void *payload, size_t nb,
1320                          u32 responseQueue)
1321 {
1322         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1323         void *pMessage;
1324         unsigned long flags;
1325         int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
1326         int rv;
1327
1328         if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1329                 return -EINVAL;
1330
1331         spin_lock_irqsave(&circularQ->iq_lock, flags);
1332         rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1333                         &pMessage);
1334         if (rv < 0) {
1335                 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1336                 rv = -ENOMEM;
1337                 goto done;
1338         }
1339
1340         if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1341                 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1342         memcpy(pMessage, payload, nb);
1343         if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1344                 memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1345                                 (nb + sizeof(struct mpi_msg_hdr)));
1346
1347         /*Build the header*/
1348         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1349                 | ((responseQueue & 0x3F) << 16)
1350                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1351
1352         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1353         /*Update the PI to the firmware*/
1354         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1355                 circularQ->pi_offset, circularQ->producer_idx);
1356         pm8001_dbg(pm8001_ha, DEVIO,
1357                    "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1358                    responseQueue, opCode, circularQ->producer_idx,
1359                    circularQ->consumer_index);
1360 done:
1361         spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1362         return rv;
1363 }
1364
1365 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1366                             struct outbound_queue_table *circularQ, u8 bc)
1367 {
1368         u32 producer_index;
1369         struct mpi_msg_hdr *msgHeader;
1370         struct mpi_msg_hdr *pOutBoundMsgHeader;
1371
1372         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1373         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1374                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1375         if (pOutBoundMsgHeader != msgHeader) {
1376                 pm8001_dbg(pm8001_ha, FAIL,
1377                            "consumer_idx = %d msgHeader = %p\n",
1378                            circularQ->consumer_idx, msgHeader);
1379
1380                 /* Update the producer index from SPC */
1381                 producer_index = pm8001_read_32(circularQ->pi_virt);
1382                 circularQ->producer_index = cpu_to_le32(producer_index);
1383                 pm8001_dbg(pm8001_ha, FAIL,
1384                            "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1385                            circularQ->consumer_idx,
1386                            circularQ->producer_index, msgHeader);
1387                 return 0;
1388         }
1389         /* free the circular queue buffer elements associated with the message*/
1390         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1391                                 % PM8001_MPI_QUEUE;
1392         /* update the CI of outbound queue */
1393         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1394                 circularQ->consumer_idx);
1395         /* Update the producer index from SPC*/
1396         producer_index = pm8001_read_32(circularQ->pi_virt);
1397         circularQ->producer_index = cpu_to_le32(producer_index);
1398         pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1399                    circularQ->consumer_idx, circularQ->producer_index);
1400         return 0;
1401 }
1402
1403 /**
1404  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1405  * message table.
1406  * @pm8001_ha: our hba card information
1407  * @circularQ: the outbound queue  table.
1408  * @messagePtr1: the message contents of this outbound message.
1409  * @pBC: the message size.
1410  */
1411 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1412                            struct outbound_queue_table *circularQ,
1413                            void **messagePtr1, u8 *pBC)
1414 {
1415         struct mpi_msg_hdr      *msgHeader;
1416         __le32  msgHeader_tmp;
1417         u32 header_tmp;
1418         do {
1419                 /* If there are not-yet-delivered messages ... */
1420                 if (le32_to_cpu(circularQ->producer_index)
1421                         != circularQ->consumer_idx) {
1422                         /*Get the pointer to the circular queue buffer element*/
1423                         msgHeader = (struct mpi_msg_hdr *)
1424                                 (circularQ->base_virt +
1425                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1426                         /* read header */
1427                         header_tmp = pm8001_read_32(msgHeader);
1428                         msgHeader_tmp = cpu_to_le32(header_tmp);
1429                         pm8001_dbg(pm8001_ha, DEVIO,
1430                                    "outbound opcode msgheader:%x ci=%d pi=%d\n",
1431                                    msgHeader_tmp, circularQ->consumer_idx,
1432                                    circularQ->producer_index);
1433                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1434                                 if (OPC_OUB_SKIP_ENTRY !=
1435                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1436                                         *messagePtr1 =
1437                                                 ((u8 *)msgHeader) +
1438                                                 sizeof(struct mpi_msg_hdr);
1439                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1440                                                 >> 24) & 0x1f);
1441                                         pm8001_dbg(pm8001_ha, IO,
1442                                                    ": CI=%d PI=%d msgHeader=%x\n",
1443                                                    circularQ->consumer_idx,
1444                                                    circularQ->producer_index,
1445                                                    msgHeader_tmp);
1446                                         return MPI_IO_STATUS_SUCCESS;
1447                                 } else {
1448                                         circularQ->consumer_idx =
1449                                                 (circularQ->consumer_idx +
1450                                                 ((le32_to_cpu(msgHeader_tmp)
1451                                                  >> 24) & 0x1f))
1452                                                         % PM8001_MPI_QUEUE;
1453                                         msgHeader_tmp = 0;
1454                                         pm8001_write_32(msgHeader, 0, 0);
1455                                         /* update the CI of outbound queue */
1456                                         pm8001_cw32(pm8001_ha,
1457                                                 circularQ->ci_pci_bar,
1458                                                 circularQ->ci_offset,
1459                                                 circularQ->consumer_idx);
1460                                 }
1461                         } else {
1462                                 circularQ->consumer_idx =
1463                                         (circularQ->consumer_idx +
1464                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1465                                         0x1f)) % PM8001_MPI_QUEUE;
1466                                 msgHeader_tmp = 0;
1467                                 pm8001_write_32(msgHeader, 0, 0);
1468                                 /* update the CI of outbound queue */
1469                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1470                                         circularQ->ci_offset,
1471                                         circularQ->consumer_idx);
1472                                 return MPI_IO_STATUS_FAIL;
1473                         }
1474                 } else {
1475                         u32 producer_index;
1476                         void *pi_virt = circularQ->pi_virt;
1477                         /* spurious interrupt during setup if
1478                          * kexec-ing and driver doing a doorbell access
1479                          * with the pre-kexec oq interrupt setup
1480                          */
1481                         if (!pi_virt)
1482                                 break;
1483                         /* Update the producer index from SPC */
1484                         producer_index = pm8001_read_32(pi_virt);
1485                         circularQ->producer_index = cpu_to_le32(producer_index);
1486                 }
1487         } while (le32_to_cpu(circularQ->producer_index) !=
1488                 circularQ->consumer_idx);
1489         /* while we don't have any more not-yet-delivered message */
1490         /* report empty */
1491         return MPI_IO_STATUS_BUSY;
1492 }
1493
1494 void pm8001_work_fn(struct work_struct *work)
1495 {
1496         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1497         struct pm8001_device *pm8001_dev;
1498         struct domain_device *dev;
1499
1500         /*
1501          * So far, all users of this stash an associated structure here.
1502          * If we get here, and this pointer is null, then the action
1503          * was cancelled. This nullification happens when the device
1504          * goes away.
1505          */
1506         if (pw->handler != IO_FATAL_ERROR) {
1507                 pm8001_dev = pw->data; /* Most stash device structure */
1508                 if ((pm8001_dev == NULL)
1509                  || ((pw->handler != IO_XFER_ERROR_BREAK)
1510                          && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1511                         kfree(pw);
1512                         return;
1513                 }
1514         }
1515
1516         switch (pw->handler) {
1517         case IO_XFER_ERROR_BREAK:
1518         {       /* This one stashes the sas_task instead */
1519                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1520                 u32 tag;
1521                 struct pm8001_ccb_info *ccb;
1522                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1523                 unsigned long flags, flags1;
1524                 struct task_status_struct *ts;
1525                 int i;
1526
1527                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1528                         break; /* Task still on lu */
1529                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1530
1531                 spin_lock_irqsave(&t->task_state_lock, flags1);
1532                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1533                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1534                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1535                         break; /* Task got completed by another */
1536                 }
1537                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1538
1539                 /* Search for a possible ccb that matches the task */
1540                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1541                         ccb = &pm8001_ha->ccb_info[i];
1542                         tag = ccb->ccb_tag;
1543                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1544                                 break;
1545                 }
1546                 if (!ccb) {
1547                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1548                         break; /* Task got freed by another */
1549                 }
1550                 ts = &t->task_status;
1551                 ts->resp = SAS_TASK_COMPLETE;
1552                 /* Force the midlayer to retry */
1553                 ts->stat = SAS_QUEUE_FULL;
1554                 pm8001_dev = ccb->device;
1555                 if (pm8001_dev)
1556                         atomic_dec(&pm8001_dev->running_req);
1557                 spin_lock_irqsave(&t->task_state_lock, flags1);
1558                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1559                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1560                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1561                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1562                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1563                         pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1564                                    t, pw->handler, ts->resp, ts->stat);
1565                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1566                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1567                 } else {
1568                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1569                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1570                         mb();/* in order to force CPU ordering */
1571                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1572                         t->task_done(t);
1573                 }
1574         }       break;
1575         case IO_XFER_OPEN_RETRY_TIMEOUT:
1576         {       /* This one stashes the sas_task instead */
1577                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1578                 u32 tag;
1579                 struct pm8001_ccb_info *ccb;
1580                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1581                 unsigned long flags, flags1;
1582                 int i, ret = 0;
1583
1584                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1585
1586                 ret = pm8001_query_task(t);
1587
1588                 if (ret == TMF_RESP_FUNC_SUCC)
1589                         pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1590                 else if (ret == TMF_RESP_FUNC_COMPLETE)
1591                         pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1592                 else
1593                         pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1594
1595                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1596
1597                 spin_lock_irqsave(&t->task_state_lock, flags1);
1598
1599                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1600                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1601                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1602                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1603                                 (void)pm8001_abort_task(t);
1604                         break; /* Task got completed by another */
1605                 }
1606
1607                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1608
1609                 /* Search for a possible ccb that matches the task */
1610                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1611                         ccb = &pm8001_ha->ccb_info[i];
1612                         tag = ccb->ccb_tag;
1613                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1614                                 break;
1615                 }
1616                 if (!ccb) {
1617                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1618                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1619                                 (void)pm8001_abort_task(t);
1620                         break; /* Task got freed by another */
1621                 }
1622
1623                 pm8001_dev = ccb->device;
1624                 dev = pm8001_dev->sas_device;
1625
1626                 switch (ret) {
1627                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1628                         ccb->open_retry = 1; /* Snub completion */
1629                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1630                         ret = pm8001_abort_task(t);
1631                         ccb->open_retry = 0;
1632                         switch (ret) {
1633                         case TMF_RESP_FUNC_SUCC:
1634                         case TMF_RESP_FUNC_COMPLETE:
1635                                 break;
1636                         default: /* device misbehavior */
1637                                 ret = TMF_RESP_FUNC_FAILED;
1638                                 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1639                                 pm8001_I_T_nexus_reset(dev);
1640                                 break;
1641                         }
1642                         break;
1643
1644                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1645                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1646                         /* Do we need to abort the task locally? */
1647                         break;
1648
1649                 default: /* device misbehavior */
1650                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1651                         ret = TMF_RESP_FUNC_FAILED;
1652                         pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1653                         pm8001_I_T_nexus_reset(dev);
1654                 }
1655
1656                 if (ret == TMF_RESP_FUNC_FAILED)
1657                         t = NULL;
1658                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1659                 pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1660         }       break;
1661         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1662                 dev = pm8001_dev->sas_device;
1663                 pm8001_I_T_nexus_event_handler(dev);
1664                 break;
1665         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1666                 dev = pm8001_dev->sas_device;
1667                 pm8001_I_T_nexus_reset(dev);
1668                 break;
1669         case IO_DS_IN_ERROR:
1670                 dev = pm8001_dev->sas_device;
1671                 pm8001_I_T_nexus_reset(dev);
1672                 break;
1673         case IO_DS_NON_OPERATIONAL:
1674                 dev = pm8001_dev->sas_device;
1675                 pm8001_I_T_nexus_reset(dev);
1676                 break;
1677         case IO_FATAL_ERROR:
1678         {
1679                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1680                 struct pm8001_ccb_info *ccb;
1681                 struct task_status_struct *ts;
1682                 struct sas_task *task;
1683                 int i;
1684                 u32 tag, device_id;
1685
1686                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1687                         ccb = &pm8001_ha->ccb_info[i];
1688                         task = ccb->task;
1689                         ts = &task->task_status;
1690                         tag = ccb->ccb_tag;
1691                         /* check if tag is NULL */
1692                         if (!tag) {
1693                                 pm8001_dbg(pm8001_ha, FAIL,
1694                                         "tag Null\n");
1695                                 continue;
1696                         }
1697                         if (task != NULL) {
1698                                 dev = task->dev;
1699                                 if (!dev) {
1700                                         pm8001_dbg(pm8001_ha, FAIL,
1701                                                 "dev is NULL\n");
1702                                         continue;
1703                                 }
1704                                 /*complete sas task and update to top layer */
1705                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
1706                                 ts->resp = SAS_TASK_COMPLETE;
1707                                 task->task_done(task);
1708                         } else if (tag != 0xFFFFFFFF) {
1709                                 /* complete the internal commands/non-sas task */
1710                                 pm8001_dev = ccb->device;
1711                                 if (pm8001_dev->dcompletion) {
1712                                         complete(pm8001_dev->dcompletion);
1713                                         pm8001_dev->dcompletion = NULL;
1714                                 }
1715                                 complete(pm8001_ha->nvmd_completion);
1716                                 pm8001_tag_free(pm8001_ha, tag);
1717                         }
1718                 }
1719                 /* Deregister all the device ids  */
1720                 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
1721                         pm8001_dev = &pm8001_ha->devices[i];
1722                         device_id = pm8001_dev->device_id;
1723                         if (device_id) {
1724                                 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
1725                                 pm8001_free_dev(pm8001_dev);
1726                         }
1727                 }
1728         }       break;
1729         }
1730         kfree(pw);
1731 }
1732
1733 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1734                                int handler)
1735 {
1736         struct pm8001_work *pw;
1737         int ret = 0;
1738
1739         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1740         if (pw) {
1741                 pw->pm8001_ha = pm8001_ha;
1742                 pw->data = data;
1743                 pw->handler = handler;
1744                 INIT_WORK(&pw->work, pm8001_work_fn);
1745                 queue_work(pm8001_wq, &pw->work);
1746         } else
1747                 ret = -ENOMEM;
1748
1749         return ret;
1750 }
1751
1752 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1753                 struct pm8001_device *pm8001_ha_dev)
1754 {
1755         int res;
1756         u32 ccb_tag;
1757         struct pm8001_ccb_info *ccb;
1758         struct sas_task *task = NULL;
1759         struct task_abort_req task_abort;
1760         struct inbound_queue_table *circularQ;
1761         u32 opc = OPC_INB_SATA_ABORT;
1762         int ret;
1763
1764         if (!pm8001_ha_dev) {
1765                 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1766                 return;
1767         }
1768
1769         task = sas_alloc_slow_task(GFP_ATOMIC);
1770         if (!task) {
1771                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1772                 return;
1773         }
1774
1775         task->task_done = pm8001_task_done;
1776
1777         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1778         if (res) {
1779                 sas_free_task(task);
1780                 return;
1781         }
1782
1783         ccb = &pm8001_ha->ccb_info[ccb_tag];
1784         ccb->device = pm8001_ha_dev;
1785         ccb->ccb_tag = ccb_tag;
1786         ccb->task = task;
1787         ccb->n_elem = 0;
1788
1789         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1790
1791         memset(&task_abort, 0, sizeof(task_abort));
1792         task_abort.abort_all = cpu_to_le32(1);
1793         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1794         task_abort.tag = cpu_to_le32(ccb_tag);
1795
1796         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1797                         sizeof(task_abort), 0);
1798         if (ret) {
1799                 sas_free_task(task);
1800                 pm8001_tag_free(pm8001_ha, ccb_tag);
1801         }
1802
1803 }
1804
1805 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1806                 struct pm8001_device *pm8001_ha_dev)
1807 {
1808         struct sata_start_req sata_cmd;
1809         int res;
1810         u32 ccb_tag;
1811         struct pm8001_ccb_info *ccb;
1812         struct sas_task *task = NULL;
1813         struct host_to_dev_fis fis;
1814         struct domain_device *dev;
1815         struct inbound_queue_table *circularQ;
1816         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1817
1818         task = sas_alloc_slow_task(GFP_ATOMIC);
1819
1820         if (!task) {
1821                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1822                 return;
1823         }
1824         task->task_done = pm8001_task_done;
1825
1826         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1827         if (res) {
1828                 sas_free_task(task);
1829                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1830                 return;
1831         }
1832
1833         /* allocate domain device by ourselves as libsas
1834          * is not going to provide any
1835         */
1836         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1837         if (!dev) {
1838                 sas_free_task(task);
1839                 pm8001_tag_free(pm8001_ha, ccb_tag);
1840                 pm8001_dbg(pm8001_ha, FAIL,
1841                            "Domain device cannot be allocated\n");
1842                 return;
1843         }
1844         task->dev = dev;
1845         task->dev->lldd_dev = pm8001_ha_dev;
1846
1847         ccb = &pm8001_ha->ccb_info[ccb_tag];
1848         ccb->device = pm8001_ha_dev;
1849         ccb->ccb_tag = ccb_tag;
1850         ccb->task = task;
1851         ccb->n_elem = 0;
1852         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1853         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1854
1855         memset(&sata_cmd, 0, sizeof(sata_cmd));
1856         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1857
1858         /* construct read log FIS */
1859         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1860         fis.fis_type = 0x27;
1861         fis.flags = 0x80;
1862         fis.command = ATA_CMD_READ_LOG_EXT;
1863         fis.lbal = 0x10;
1864         fis.sector_count = 0x1;
1865
1866         sata_cmd.tag = cpu_to_le32(ccb_tag);
1867         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1868         sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1869         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1870
1871         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1872                         sizeof(sata_cmd), 0);
1873         if (res) {
1874                 sas_free_task(task);
1875                 pm8001_tag_free(pm8001_ha, ccb_tag);
1876                 kfree(dev);
1877         }
1878 }
1879
1880 /**
1881  * mpi_ssp_completion- process the event that FW response to the SSP request.
1882  * @pm8001_ha: our hba card information
1883  * @piomb: the message contents of this outbound message.
1884  *
1885  * When FW has completed a ssp request for example a IO request, after it has
1886  * filled the SG data with the data, it will trigger this event representing
1887  * that he has finished the job; please check the corresponding buffer.
1888  * So we will tell the caller who maybe waiting the result to tell upper layer
1889  * that the task has been finished.
1890  */
1891 static void
1892 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1893 {
1894         struct sas_task *t;
1895         struct pm8001_ccb_info *ccb;
1896         unsigned long flags;
1897         u32 status;
1898         u32 param;
1899         u32 tag;
1900         struct ssp_completion_resp *psspPayload;
1901         struct task_status_struct *ts;
1902         struct ssp_response_iu *iu;
1903         struct pm8001_device *pm8001_dev;
1904         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1905         status = le32_to_cpu(psspPayload->status);
1906         tag = le32_to_cpu(psspPayload->tag);
1907         ccb = &pm8001_ha->ccb_info[tag];
1908         if ((status == IO_ABORTED) && ccb->open_retry) {
1909                 /* Being completed by another */
1910                 ccb->open_retry = 0;
1911                 return;
1912         }
1913         pm8001_dev = ccb->device;
1914         param = le32_to_cpu(psspPayload->param);
1915
1916         t = ccb->task;
1917
1918         if (status && status != IO_UNDERFLOW)
1919                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1920         if (unlikely(!t || !t->lldd_task || !t->dev))
1921                 return;
1922         ts = &t->task_status;
1923         /* Print sas address of IO failed device */
1924         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1925                 (status != IO_UNDERFLOW))
1926                 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1927                            SAS_ADDR(t->dev->sas_addr));
1928
1929         if (status)
1930                 pm8001_dbg(pm8001_ha, IOERR,
1931                            "status:0x%x, tag:0x%x, task:0x%p\n",
1932                            status, tag, t);
1933
1934         switch (status) {
1935         case IO_SUCCESS:
1936                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1937                            param);
1938                 if (param == 0) {
1939                         ts->resp = SAS_TASK_COMPLETE;
1940                         ts->stat = SAS_SAM_STAT_GOOD;
1941                 } else {
1942                         ts->resp = SAS_TASK_COMPLETE;
1943                         ts->stat = SAS_PROTO_RESPONSE;
1944                         ts->residual = param;
1945                         iu = &psspPayload->ssp_resp_iu;
1946                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1947                 }
1948                 if (pm8001_dev)
1949                         atomic_dec(&pm8001_dev->running_req);
1950                 break;
1951         case IO_ABORTED:
1952                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1953                 ts->resp = SAS_TASK_COMPLETE;
1954                 ts->stat = SAS_ABORTED_TASK;
1955                 break;
1956         case IO_UNDERFLOW:
1957                 /* SSP Completion with error */
1958                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1959                            param);
1960                 ts->resp = SAS_TASK_COMPLETE;
1961                 ts->stat = SAS_DATA_UNDERRUN;
1962                 ts->residual = param;
1963                 if (pm8001_dev)
1964                         atomic_dec(&pm8001_dev->running_req);
1965                 break;
1966         case IO_NO_DEVICE:
1967                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1968                 ts->resp = SAS_TASK_UNDELIVERED;
1969                 ts->stat = SAS_PHY_DOWN;
1970                 break;
1971         case IO_XFER_ERROR_BREAK:
1972                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1973                 ts->resp = SAS_TASK_COMPLETE;
1974                 ts->stat = SAS_OPEN_REJECT;
1975                 /* Force the midlayer to retry */
1976                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1977                 break;
1978         case IO_XFER_ERROR_PHY_NOT_READY:
1979                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1980                 ts->resp = SAS_TASK_COMPLETE;
1981                 ts->stat = SAS_OPEN_REJECT;
1982                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1983                 break;
1984         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1985                 pm8001_dbg(pm8001_ha, IO,
1986                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1987                 ts->resp = SAS_TASK_COMPLETE;
1988                 ts->stat = SAS_OPEN_REJECT;
1989                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1990                 break;
1991         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1992                 pm8001_dbg(pm8001_ha, IO,
1993                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1994                 ts->resp = SAS_TASK_COMPLETE;
1995                 ts->stat = SAS_OPEN_REJECT;
1996                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1997                 break;
1998         case IO_OPEN_CNX_ERROR_BREAK:
1999                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2000                 ts->resp = SAS_TASK_COMPLETE;
2001                 ts->stat = SAS_OPEN_REJECT;
2002                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2003                 break;
2004         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2005                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2006                 ts->resp = SAS_TASK_COMPLETE;
2007                 ts->stat = SAS_OPEN_REJECT;
2008                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2009                 if (!t->uldd_task)
2010                         pm8001_handle_event(pm8001_ha,
2011                                 pm8001_dev,
2012                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2013                 break;
2014         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2015                 pm8001_dbg(pm8001_ha, IO,
2016                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2017                 ts->resp = SAS_TASK_COMPLETE;
2018                 ts->stat = SAS_OPEN_REJECT;
2019                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2020                 break;
2021         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2022                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2023                 ts->resp = SAS_TASK_COMPLETE;
2024                 ts->stat = SAS_OPEN_REJECT;
2025                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2026                 break;
2027         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2028                 pm8001_dbg(pm8001_ha, IO,
2029                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2030                 ts->resp = SAS_TASK_UNDELIVERED;
2031                 ts->stat = SAS_OPEN_REJECT;
2032                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2033                 break;
2034         case IO_XFER_ERROR_NAK_RECEIVED:
2035                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2036                 ts->resp = SAS_TASK_COMPLETE;
2037                 ts->stat = SAS_OPEN_REJECT;
2038                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2039                 break;
2040         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2041                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2042                 ts->resp = SAS_TASK_COMPLETE;
2043                 ts->stat = SAS_NAK_R_ERR;
2044                 break;
2045         case IO_XFER_ERROR_DMA:
2046                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2047                 ts->resp = SAS_TASK_COMPLETE;
2048                 ts->stat = SAS_OPEN_REJECT;
2049                 break;
2050         case IO_XFER_OPEN_RETRY_TIMEOUT:
2051                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2052                 ts->resp = SAS_TASK_COMPLETE;
2053                 ts->stat = SAS_OPEN_REJECT;
2054                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2055                 break;
2056         case IO_XFER_ERROR_OFFSET_MISMATCH:
2057                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2058                 ts->resp = SAS_TASK_COMPLETE;
2059                 ts->stat = SAS_OPEN_REJECT;
2060                 break;
2061         case IO_PORT_IN_RESET:
2062                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2063                 ts->resp = SAS_TASK_COMPLETE;
2064                 ts->stat = SAS_OPEN_REJECT;
2065                 break;
2066         case IO_DS_NON_OPERATIONAL:
2067                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2068                 ts->resp = SAS_TASK_COMPLETE;
2069                 ts->stat = SAS_OPEN_REJECT;
2070                 if (!t->uldd_task)
2071                         pm8001_handle_event(pm8001_ha,
2072                                 pm8001_dev,
2073                                 IO_DS_NON_OPERATIONAL);
2074                 break;
2075         case IO_DS_IN_RECOVERY:
2076                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2077                 ts->resp = SAS_TASK_COMPLETE;
2078                 ts->stat = SAS_OPEN_REJECT;
2079                 break;
2080         case IO_TM_TAG_NOT_FOUND:
2081                 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2082                 ts->resp = SAS_TASK_COMPLETE;
2083                 ts->stat = SAS_OPEN_REJECT;
2084                 break;
2085         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2086                 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2087                 ts->resp = SAS_TASK_COMPLETE;
2088                 ts->stat = SAS_OPEN_REJECT;
2089                 break;
2090         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2091                 pm8001_dbg(pm8001_ha, IO,
2092                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2093                 ts->resp = SAS_TASK_COMPLETE;
2094                 ts->stat = SAS_OPEN_REJECT;
2095                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2096                 break;
2097         default:
2098                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2099                 /* not allowed case. Therefore, return failed status */
2100                 ts->resp = SAS_TASK_COMPLETE;
2101                 ts->stat = SAS_OPEN_REJECT;
2102                 break;
2103         }
2104         pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2105                    psspPayload->ssp_resp_iu.status);
2106         spin_lock_irqsave(&t->task_state_lock, flags);
2107         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2108         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2109         t->task_state_flags |= SAS_TASK_STATE_DONE;
2110         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2111                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2112                 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2113                            t, status, ts->resp, ts->stat);
2114                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2115         } else {
2116                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2117                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2118                 mb();/* in order to force CPU ordering */
2119                 t->task_done(t);
2120         }
2121 }
2122
2123 /*See the comments for mpi_ssp_completion */
2124 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2125 {
2126         struct sas_task *t;
2127         unsigned long flags;
2128         struct task_status_struct *ts;
2129         struct pm8001_ccb_info *ccb;
2130         struct pm8001_device *pm8001_dev;
2131         struct ssp_event_resp *psspPayload =
2132                 (struct ssp_event_resp *)(piomb + 4);
2133         u32 event = le32_to_cpu(psspPayload->event);
2134         u32 tag = le32_to_cpu(psspPayload->tag);
2135         u32 port_id = le32_to_cpu(psspPayload->port_id);
2136         u32 dev_id = le32_to_cpu(psspPayload->device_id);
2137
2138         ccb = &pm8001_ha->ccb_info[tag];
2139         t = ccb->task;
2140         pm8001_dev = ccb->device;
2141         if (event)
2142                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2143         if (unlikely(!t || !t->lldd_task || !t->dev))
2144                 return;
2145         ts = &t->task_status;
2146         pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2147                    port_id, dev_id);
2148         switch (event) {
2149         case IO_OVERFLOW:
2150                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2151                 ts->resp = SAS_TASK_COMPLETE;
2152                 ts->stat = SAS_DATA_OVERRUN;
2153                 ts->residual = 0;
2154                 if (pm8001_dev)
2155                         atomic_dec(&pm8001_dev->running_req);
2156                 break;
2157         case IO_XFER_ERROR_BREAK:
2158                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2159                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2160                 return;
2161         case IO_XFER_ERROR_PHY_NOT_READY:
2162                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2163                 ts->resp = SAS_TASK_COMPLETE;
2164                 ts->stat = SAS_OPEN_REJECT;
2165                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2166                 break;
2167         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2168                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2169                 ts->resp = SAS_TASK_COMPLETE;
2170                 ts->stat = SAS_OPEN_REJECT;
2171                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2172                 break;
2173         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2174                 pm8001_dbg(pm8001_ha, IO,
2175                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2176                 ts->resp = SAS_TASK_COMPLETE;
2177                 ts->stat = SAS_OPEN_REJECT;
2178                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2179                 break;
2180         case IO_OPEN_CNX_ERROR_BREAK:
2181                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2182                 ts->resp = SAS_TASK_COMPLETE;
2183                 ts->stat = SAS_OPEN_REJECT;
2184                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2185                 break;
2186         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2187                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2188                 ts->resp = SAS_TASK_COMPLETE;
2189                 ts->stat = SAS_OPEN_REJECT;
2190                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2191                 if (!t->uldd_task)
2192                         pm8001_handle_event(pm8001_ha,
2193                                 pm8001_dev,
2194                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2195                 break;
2196         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2197                 pm8001_dbg(pm8001_ha, IO,
2198                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2199                 ts->resp = SAS_TASK_COMPLETE;
2200                 ts->stat = SAS_OPEN_REJECT;
2201                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2202                 break;
2203         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2204                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2205                 ts->resp = SAS_TASK_COMPLETE;
2206                 ts->stat = SAS_OPEN_REJECT;
2207                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2208                 break;
2209         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2210                 pm8001_dbg(pm8001_ha, IO,
2211                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2212                 ts->resp = SAS_TASK_COMPLETE;
2213                 ts->stat = SAS_OPEN_REJECT;
2214                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2215                 break;
2216         case IO_XFER_ERROR_NAK_RECEIVED:
2217                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2218                 ts->resp = SAS_TASK_COMPLETE;
2219                 ts->stat = SAS_OPEN_REJECT;
2220                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2221                 break;
2222         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2223                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2224                 ts->resp = SAS_TASK_COMPLETE;
2225                 ts->stat = SAS_NAK_R_ERR;
2226                 break;
2227         case IO_XFER_OPEN_RETRY_TIMEOUT:
2228                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2229                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2230                 return;
2231         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2232                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2233                 ts->resp = SAS_TASK_COMPLETE;
2234                 ts->stat = SAS_DATA_OVERRUN;
2235                 break;
2236         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2237                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2238                 ts->resp = SAS_TASK_COMPLETE;
2239                 ts->stat = SAS_DATA_OVERRUN;
2240                 break;
2241         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2242                 pm8001_dbg(pm8001_ha, IO,
2243                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2244                 ts->resp = SAS_TASK_COMPLETE;
2245                 ts->stat = SAS_DATA_OVERRUN;
2246                 break;
2247         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2248                 pm8001_dbg(pm8001_ha, IO,
2249                            "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2250                 ts->resp = SAS_TASK_COMPLETE;
2251                 ts->stat = SAS_DATA_OVERRUN;
2252                 break;
2253         case IO_XFER_ERROR_OFFSET_MISMATCH:
2254                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2255                 ts->resp = SAS_TASK_COMPLETE;
2256                 ts->stat = SAS_DATA_OVERRUN;
2257                 break;
2258         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2259                 pm8001_dbg(pm8001_ha, IO,
2260                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2261                 ts->resp = SAS_TASK_COMPLETE;
2262                 ts->stat = SAS_DATA_OVERRUN;
2263                 break;
2264         case IO_XFER_CMD_FRAME_ISSUED:
2265                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2266                 return;
2267         default:
2268                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2269                 /* not allowed case. Therefore, return failed status */
2270                 ts->resp = SAS_TASK_COMPLETE;
2271                 ts->stat = SAS_DATA_OVERRUN;
2272                 break;
2273         }
2274         spin_lock_irqsave(&t->task_state_lock, flags);
2275         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2276         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2277         t->task_state_flags |= SAS_TASK_STATE_DONE;
2278         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2279                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2280                 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2281                            t, event, ts->resp, ts->stat);
2282                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2283         } else {
2284                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2285                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2286                 mb();/* in order to force CPU ordering */
2287                 t->task_done(t);
2288         }
2289 }
2290
2291 /*See the comments for mpi_ssp_completion */
2292 static void
2293 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2294 {
2295         struct sas_task *t;
2296         struct pm8001_ccb_info *ccb;
2297         u32 param;
2298         u32 status;
2299         u32 tag;
2300         int i, j;
2301         u8 sata_addr_low[4];
2302         u32 temp_sata_addr_low;
2303         u8 sata_addr_hi[4];
2304         u32 temp_sata_addr_hi;
2305         struct sata_completion_resp *psataPayload;
2306         struct task_status_struct *ts;
2307         struct ata_task_resp *resp ;
2308         u32 *sata_resp;
2309         struct pm8001_device *pm8001_dev;
2310         unsigned long flags;
2311
2312         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2313         status = le32_to_cpu(psataPayload->status);
2314         tag = le32_to_cpu(psataPayload->tag);
2315
2316         if (!tag) {
2317                 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2318                 return;
2319         }
2320         ccb = &pm8001_ha->ccb_info[tag];
2321         param = le32_to_cpu(psataPayload->param);
2322         if (ccb) {
2323                 t = ccb->task;
2324                 pm8001_dev = ccb->device;
2325         } else {
2326                 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2327                 return;
2328         }
2329
2330         if (t) {
2331                 if (t->dev && (t->dev->lldd_dev))
2332                         pm8001_dev = t->dev->lldd_dev;
2333         } else {
2334                 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2335                 return;
2336         }
2337
2338         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2339                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2340                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2341                 return;
2342         }
2343
2344         ts = &t->task_status;
2345         if (!ts) {
2346                 pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2347                 return;
2348         }
2349
2350         if (status)
2351                 pm8001_dbg(pm8001_ha, IOERR,
2352                            "status:0x%x, tag:0x%x, task::0x%p\n",
2353                            status, tag, t);
2354
2355         /* Print sas address of IO failed device */
2356         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2357                 (status != IO_UNDERFLOW)) {
2358                 if (!((t->dev->parent) &&
2359                         (dev_is_expander(t->dev->parent->dev_type)))) {
2360                         for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2361                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2362                         for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
2363                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2364                         memcpy(&temp_sata_addr_low, sata_addr_low,
2365                                 sizeof(sata_addr_low));
2366                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2367                                 sizeof(sata_addr_hi));
2368                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2369                                                 |((temp_sata_addr_hi << 8) &
2370                                                 0xff0000) |
2371                                                 ((temp_sata_addr_hi >> 8)
2372                                                 & 0xff00) |
2373                                                 ((temp_sata_addr_hi << 24) &
2374                                                 0xff000000));
2375                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2376                                                 & 0xff) |
2377                                                 ((temp_sata_addr_low << 8)
2378                                                 & 0xff0000) |
2379                                                 ((temp_sata_addr_low >> 8)
2380                                                 & 0xff00) |
2381                                                 ((temp_sata_addr_low << 24)
2382                                                 & 0xff000000)) +
2383                                                 pm8001_dev->attached_phy +
2384                                                 0x10);
2385                         pm8001_dbg(pm8001_ha, FAIL,
2386                                    "SAS Address of IO Failure Drive:%08x%08x\n",
2387                                    temp_sata_addr_hi,
2388                                    temp_sata_addr_low);
2389                 } else {
2390                         pm8001_dbg(pm8001_ha, FAIL,
2391                                    "SAS Address of IO Failure Drive:%016llx\n",
2392                                    SAS_ADDR(t->dev->sas_addr));
2393                 }
2394         }
2395         switch (status) {
2396         case IO_SUCCESS:
2397                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2398                 if (param == 0) {
2399                         ts->resp = SAS_TASK_COMPLETE;
2400                         ts->stat = SAS_SAM_STAT_GOOD;
2401                         /* check if response is for SEND READ LOG */
2402                         if (pm8001_dev &&
2403                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2404                                 /* set new bit for abort_all */
2405                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2406                                 /* clear bit for read log */
2407                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2408                                 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2409                                 /* Free the tag */
2410                                 pm8001_tag_free(pm8001_ha, tag);
2411                                 sas_free_task(t);
2412                                 return;
2413                         }
2414                 } else {
2415                         u8 len;
2416                         ts->resp = SAS_TASK_COMPLETE;
2417                         ts->stat = SAS_PROTO_RESPONSE;
2418                         ts->residual = param;
2419                         pm8001_dbg(pm8001_ha, IO,
2420                                    "SAS_PROTO_RESPONSE len = %d\n",
2421                                    param);
2422                         sata_resp = &psataPayload->sata_resp[0];
2423                         resp = (struct ata_task_resp *)ts->buf;
2424                         if (t->ata_task.dma_xfer == 0 &&
2425                             t->data_dir == DMA_FROM_DEVICE) {
2426                                 len = sizeof(struct pio_setup_fis);
2427                                 pm8001_dbg(pm8001_ha, IO,
2428                                            "PIO read len = %d\n", len);
2429                         } else if (t->ata_task.use_ncq &&
2430                                    t->data_dir != DMA_NONE) {
2431                                 len = sizeof(struct set_dev_bits_fis);
2432                                 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2433                                            len);
2434                         } else {
2435                                 len = sizeof(struct dev_to_host_fis);
2436                                 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2437                                            len);
2438                         }
2439                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2440                                 resp->frame_len = len;
2441                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2442                                 ts->buf_valid_size = sizeof(*resp);
2443                         } else
2444                                 pm8001_dbg(pm8001_ha, IO,
2445                                            "response too large\n");
2446                 }
2447                 if (pm8001_dev)
2448                         atomic_dec(&pm8001_dev->running_req);
2449                 break;
2450         case IO_ABORTED:
2451                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2452                 ts->resp = SAS_TASK_COMPLETE;
2453                 ts->stat = SAS_ABORTED_TASK;
2454                 if (pm8001_dev)
2455                         atomic_dec(&pm8001_dev->running_req);
2456                 break;
2457                 /* following cases are to do cases */
2458         case IO_UNDERFLOW:
2459                 /* SATA Completion with error */
2460                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2461                 ts->resp = SAS_TASK_COMPLETE;
2462                 ts->stat = SAS_DATA_UNDERRUN;
2463                 ts->residual =  param;
2464                 if (pm8001_dev)
2465                         atomic_dec(&pm8001_dev->running_req);
2466                 break;
2467         case IO_NO_DEVICE:
2468                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2469                 ts->resp = SAS_TASK_UNDELIVERED;
2470                 ts->stat = SAS_PHY_DOWN;
2471                 if (pm8001_dev)
2472                         atomic_dec(&pm8001_dev->running_req);
2473                 break;
2474         case IO_XFER_ERROR_BREAK:
2475                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2476                 ts->resp = SAS_TASK_COMPLETE;
2477                 ts->stat = SAS_INTERRUPTED;
2478                 if (pm8001_dev)
2479                         atomic_dec(&pm8001_dev->running_req);
2480                 break;
2481         case IO_XFER_ERROR_PHY_NOT_READY:
2482                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2483                 ts->resp = SAS_TASK_COMPLETE;
2484                 ts->stat = SAS_OPEN_REJECT;
2485                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2486                 if (pm8001_dev)
2487                         atomic_dec(&pm8001_dev->running_req);
2488                 break;
2489         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2490                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2491                 ts->resp = SAS_TASK_COMPLETE;
2492                 ts->stat = SAS_OPEN_REJECT;
2493                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2494                 if (pm8001_dev)
2495                         atomic_dec(&pm8001_dev->running_req);
2496                 break;
2497         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2498                 pm8001_dbg(pm8001_ha, IO,
2499                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2500                 ts->resp = SAS_TASK_COMPLETE;
2501                 ts->stat = SAS_OPEN_REJECT;
2502                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2503                 if (pm8001_dev)
2504                         atomic_dec(&pm8001_dev->running_req);
2505                 break;
2506         case IO_OPEN_CNX_ERROR_BREAK:
2507                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2508                 ts->resp = SAS_TASK_COMPLETE;
2509                 ts->stat = SAS_OPEN_REJECT;
2510                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2511                 if (pm8001_dev)
2512                         atomic_dec(&pm8001_dev->running_req);
2513                 break;
2514         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2515                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2516                 ts->resp = SAS_TASK_COMPLETE;
2517                 ts->stat = SAS_DEV_NO_RESPONSE;
2518                 if (!t->uldd_task) {
2519                         pm8001_handle_event(pm8001_ha,
2520                                 pm8001_dev,
2521                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2522                         ts->resp = SAS_TASK_UNDELIVERED;
2523                         ts->stat = SAS_QUEUE_FULL;
2524                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2525                         return;
2526                 }
2527                 break;
2528         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2529                 pm8001_dbg(pm8001_ha, IO,
2530                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2531                 ts->resp = SAS_TASK_UNDELIVERED;
2532                 ts->stat = SAS_OPEN_REJECT;
2533                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2534                 if (!t->uldd_task) {
2535                         pm8001_handle_event(pm8001_ha,
2536                                 pm8001_dev,
2537                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2538                         ts->resp = SAS_TASK_UNDELIVERED;
2539                         ts->stat = SAS_QUEUE_FULL;
2540                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2541                         return;
2542                 }
2543                 break;
2544         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2545                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2546                 ts->resp = SAS_TASK_COMPLETE;
2547                 ts->stat = SAS_OPEN_REJECT;
2548                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2549                 if (pm8001_dev)
2550                         atomic_dec(&pm8001_dev->running_req);
2551                 break;
2552         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2553                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2554                 ts->resp = SAS_TASK_COMPLETE;
2555                 ts->stat = SAS_DEV_NO_RESPONSE;
2556                 if (!t->uldd_task) {
2557                         pm8001_handle_event(pm8001_ha,
2558                                 pm8001_dev,
2559                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2560                         ts->resp = SAS_TASK_UNDELIVERED;
2561                         ts->stat = SAS_QUEUE_FULL;
2562                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2563                         return;
2564                 }
2565                 break;
2566         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2567                 pm8001_dbg(pm8001_ha, IO,
2568                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2569                 ts->resp = SAS_TASK_COMPLETE;
2570                 ts->stat = SAS_OPEN_REJECT;
2571                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2572                 if (pm8001_dev)
2573                         atomic_dec(&pm8001_dev->running_req);
2574                 break;
2575         case IO_XFER_ERROR_NAK_RECEIVED:
2576                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2577                 ts->resp = SAS_TASK_COMPLETE;
2578                 ts->stat = SAS_NAK_R_ERR;
2579                 if (pm8001_dev)
2580                         atomic_dec(&pm8001_dev->running_req);
2581                 break;
2582         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2583                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2584                 ts->resp = SAS_TASK_COMPLETE;
2585                 ts->stat = SAS_NAK_R_ERR;
2586                 if (pm8001_dev)
2587                         atomic_dec(&pm8001_dev->running_req);
2588                 break;
2589         case IO_XFER_ERROR_DMA:
2590                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2591                 ts->resp = SAS_TASK_COMPLETE;
2592                 ts->stat = SAS_ABORTED_TASK;
2593                 if (pm8001_dev)
2594                         atomic_dec(&pm8001_dev->running_req);
2595                 break;
2596         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2597                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2598                 ts->resp = SAS_TASK_UNDELIVERED;
2599                 ts->stat = SAS_DEV_NO_RESPONSE;
2600                 if (pm8001_dev)
2601                         atomic_dec(&pm8001_dev->running_req);
2602                 break;
2603         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2604                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2605                 ts->resp = SAS_TASK_COMPLETE;
2606                 ts->stat = SAS_DATA_UNDERRUN;
2607                 if (pm8001_dev)
2608                         atomic_dec(&pm8001_dev->running_req);
2609                 break;
2610         case IO_XFER_OPEN_RETRY_TIMEOUT:
2611                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2612                 ts->resp = SAS_TASK_COMPLETE;
2613                 ts->stat = SAS_OPEN_TO;
2614                 if (pm8001_dev)
2615                         atomic_dec(&pm8001_dev->running_req);
2616                 break;
2617         case IO_PORT_IN_RESET:
2618                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2619                 ts->resp = SAS_TASK_COMPLETE;
2620                 ts->stat = SAS_DEV_NO_RESPONSE;
2621                 if (pm8001_dev)
2622                         atomic_dec(&pm8001_dev->running_req);
2623                 break;
2624         case IO_DS_NON_OPERATIONAL:
2625                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2626                 ts->resp = SAS_TASK_COMPLETE;
2627                 ts->stat = SAS_DEV_NO_RESPONSE;
2628                 if (!t->uldd_task) {
2629                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2630                                     IO_DS_NON_OPERATIONAL);
2631                         ts->resp = SAS_TASK_UNDELIVERED;
2632                         ts->stat = SAS_QUEUE_FULL;
2633                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2634                         return;
2635                 }
2636                 break;
2637         case IO_DS_IN_RECOVERY:
2638                 pm8001_dbg(pm8001_ha, IO, "  IO_DS_IN_RECOVERY\n");
2639                 ts->resp = SAS_TASK_COMPLETE;
2640                 ts->stat = SAS_DEV_NO_RESPONSE;
2641                 if (pm8001_dev)
2642                         atomic_dec(&pm8001_dev->running_req);
2643                 break;
2644         case IO_DS_IN_ERROR:
2645                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2646                 ts->resp = SAS_TASK_COMPLETE;
2647                 ts->stat = SAS_DEV_NO_RESPONSE;
2648                 if (!t->uldd_task) {
2649                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2650                                     IO_DS_IN_ERROR);
2651                         ts->resp = SAS_TASK_UNDELIVERED;
2652                         ts->stat = SAS_QUEUE_FULL;
2653                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2654                         return;
2655                 }
2656                 break;
2657         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2658                 pm8001_dbg(pm8001_ha, IO,
2659                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2660                 ts->resp = SAS_TASK_COMPLETE;
2661                 ts->stat = SAS_OPEN_REJECT;
2662                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2663                 if (pm8001_dev)
2664                         atomic_dec(&pm8001_dev->running_req);
2665                 break;
2666         default:
2667                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2668                 /* not allowed case. Therefore, return failed status */
2669                 ts->resp = SAS_TASK_COMPLETE;
2670                 ts->stat = SAS_DEV_NO_RESPONSE;
2671                 if (pm8001_dev)
2672                         atomic_dec(&pm8001_dev->running_req);
2673                 break;
2674         }
2675         spin_lock_irqsave(&t->task_state_lock, flags);
2676         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2677         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2678         t->task_state_flags |= SAS_TASK_STATE_DONE;
2679         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2680                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2681                 pm8001_dbg(pm8001_ha, FAIL,
2682                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2683                            t, status, ts->resp, ts->stat);
2684                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2685         } else {
2686                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2687                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2688         }
2689 }
2690
2691 /*See the comments for mpi_ssp_completion */
2692 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2693 {
2694         struct sas_task *t;
2695         struct task_status_struct *ts;
2696         struct pm8001_ccb_info *ccb;
2697         struct pm8001_device *pm8001_dev;
2698         struct sata_event_resp *psataPayload =
2699                 (struct sata_event_resp *)(piomb + 4);
2700         u32 event = le32_to_cpu(psataPayload->event);
2701         u32 tag = le32_to_cpu(psataPayload->tag);
2702         u32 port_id = le32_to_cpu(psataPayload->port_id);
2703         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2704
2705         ccb = &pm8001_ha->ccb_info[tag];
2706
2707         if (ccb) {
2708                 t = ccb->task;
2709                 pm8001_dev = ccb->device;
2710         } else {
2711                 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2712         }
2713         if (event)
2714                 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2715
2716         /* Check if this is NCQ error */
2717         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2718                 /* find device using device id */
2719                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2720                 /* send read log extension */
2721                 if (pm8001_dev)
2722                         pm8001_send_read_log(pm8001_ha, pm8001_dev);
2723                 return;
2724         }
2725
2726         ccb = &pm8001_ha->ccb_info[tag];
2727         t = ccb->task;
2728         pm8001_dev = ccb->device;
2729         if (event)
2730                 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2731         if (unlikely(!t || !t->lldd_task || !t->dev))
2732                 return;
2733         ts = &t->task_status;
2734         pm8001_dbg(pm8001_ha, DEVIO,
2735                    "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2736                    port_id, dev_id, tag, event);
2737         switch (event) {
2738         case IO_OVERFLOW:
2739                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2740                 ts->resp = SAS_TASK_COMPLETE;
2741                 ts->stat = SAS_DATA_OVERRUN;
2742                 ts->residual = 0;
2743                 break;
2744         case IO_XFER_ERROR_BREAK:
2745                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2746                 ts->resp = SAS_TASK_COMPLETE;
2747                 ts->stat = SAS_INTERRUPTED;
2748                 break;
2749         case IO_XFER_ERROR_PHY_NOT_READY:
2750                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2751                 ts->resp = SAS_TASK_COMPLETE;
2752                 ts->stat = SAS_OPEN_REJECT;
2753                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2754                 break;
2755         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2756                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2757                 ts->resp = SAS_TASK_COMPLETE;
2758                 ts->stat = SAS_OPEN_REJECT;
2759                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2760                 break;
2761         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2762                 pm8001_dbg(pm8001_ha, IO,
2763                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2764                 ts->resp = SAS_TASK_COMPLETE;
2765                 ts->stat = SAS_OPEN_REJECT;
2766                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2767                 break;
2768         case IO_OPEN_CNX_ERROR_BREAK:
2769                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2770                 ts->resp = SAS_TASK_COMPLETE;
2771                 ts->stat = SAS_OPEN_REJECT;
2772                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2773                 break;
2774         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2775                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2776                 ts->resp = SAS_TASK_UNDELIVERED;
2777                 ts->stat = SAS_DEV_NO_RESPONSE;
2778                 if (!t->uldd_task) {
2779                         pm8001_handle_event(pm8001_ha,
2780                                 pm8001_dev,
2781                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2782                         ts->resp = SAS_TASK_COMPLETE;
2783                         ts->stat = SAS_QUEUE_FULL;
2784                         return;
2785                 }
2786                 break;
2787         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2788                 pm8001_dbg(pm8001_ha, IO,
2789                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2790                 ts->resp = SAS_TASK_UNDELIVERED;
2791                 ts->stat = SAS_OPEN_REJECT;
2792                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2793                 break;
2794         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2795                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2796                 ts->resp = SAS_TASK_COMPLETE;
2797                 ts->stat = SAS_OPEN_REJECT;
2798                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2799                 break;
2800         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2801                 pm8001_dbg(pm8001_ha, IO,
2802                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2803                 ts->resp = SAS_TASK_COMPLETE;
2804                 ts->stat = SAS_OPEN_REJECT;
2805                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2806                 break;
2807         case IO_XFER_ERROR_NAK_RECEIVED:
2808                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2809                 ts->resp = SAS_TASK_COMPLETE;
2810                 ts->stat = SAS_NAK_R_ERR;
2811                 break;
2812         case IO_XFER_ERROR_PEER_ABORTED:
2813                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2814                 ts->resp = SAS_TASK_COMPLETE;
2815                 ts->stat = SAS_NAK_R_ERR;
2816                 break;
2817         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2818                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2819                 ts->resp = SAS_TASK_COMPLETE;
2820                 ts->stat = SAS_DATA_UNDERRUN;
2821                 break;
2822         case IO_XFER_OPEN_RETRY_TIMEOUT:
2823                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2824                 ts->resp = SAS_TASK_COMPLETE;
2825                 ts->stat = SAS_OPEN_TO;
2826                 break;
2827         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2828                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2829                 ts->resp = SAS_TASK_COMPLETE;
2830                 ts->stat = SAS_OPEN_TO;
2831                 break;
2832         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2833                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2834                 ts->resp = SAS_TASK_COMPLETE;
2835                 ts->stat = SAS_OPEN_TO;
2836                 break;
2837         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2838                 pm8001_dbg(pm8001_ha, IO,
2839                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2840                 ts->resp = SAS_TASK_COMPLETE;
2841                 ts->stat = SAS_OPEN_TO;
2842                 break;
2843         case IO_XFER_ERROR_OFFSET_MISMATCH:
2844                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2845                 ts->resp = SAS_TASK_COMPLETE;
2846                 ts->stat = SAS_OPEN_TO;
2847                 break;
2848         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2849                 pm8001_dbg(pm8001_ha, IO,
2850                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2851                 ts->resp = SAS_TASK_COMPLETE;
2852                 ts->stat = SAS_OPEN_TO;
2853                 break;
2854         case IO_XFER_CMD_FRAME_ISSUED:
2855                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2856                 break;
2857         case IO_XFER_PIO_SETUP_ERROR:
2858                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2859                 ts->resp = SAS_TASK_COMPLETE;
2860                 ts->stat = SAS_OPEN_TO;
2861                 break;
2862         default:
2863                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2864                 /* not allowed case. Therefore, return failed status */
2865                 ts->resp = SAS_TASK_COMPLETE;
2866                 ts->stat = SAS_OPEN_TO;
2867                 break;
2868         }
2869 }
2870
2871 /*See the comments for mpi_ssp_completion */
2872 static void
2873 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2874 {
2875         struct sas_task *t;
2876         struct pm8001_ccb_info *ccb;
2877         unsigned long flags;
2878         u32 status;
2879         u32 tag;
2880         struct smp_completion_resp *psmpPayload;
2881         struct task_status_struct *ts;
2882         struct pm8001_device *pm8001_dev;
2883
2884         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2885         status = le32_to_cpu(psmpPayload->status);
2886         tag = le32_to_cpu(psmpPayload->tag);
2887
2888         ccb = &pm8001_ha->ccb_info[tag];
2889         t = ccb->task;
2890         ts = &t->task_status;
2891         pm8001_dev = ccb->device;
2892         if (status) {
2893                 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2894                 pm8001_dbg(pm8001_ha, IOERR,
2895                            "status:0x%x, tag:0x%x, task:0x%p\n",
2896                            status, tag, t);
2897         }
2898         if (unlikely(!t || !t->lldd_task || !t->dev))
2899                 return;
2900
2901         switch (status) {
2902         case IO_SUCCESS:
2903                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2904                 ts->resp = SAS_TASK_COMPLETE;
2905                 ts->stat = SAS_SAM_STAT_GOOD;
2906                 if (pm8001_dev)
2907                         atomic_dec(&pm8001_dev->running_req);
2908                 break;
2909         case IO_ABORTED:
2910                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2911                 ts->resp = SAS_TASK_COMPLETE;
2912                 ts->stat = SAS_ABORTED_TASK;
2913                 if (pm8001_dev)
2914                         atomic_dec(&pm8001_dev->running_req);
2915                 break;
2916         case IO_OVERFLOW:
2917                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2918                 ts->resp = SAS_TASK_COMPLETE;
2919                 ts->stat = SAS_DATA_OVERRUN;
2920                 ts->residual = 0;
2921                 if (pm8001_dev)
2922                         atomic_dec(&pm8001_dev->running_req);
2923                 break;
2924         case IO_NO_DEVICE:
2925                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2926                 ts->resp = SAS_TASK_COMPLETE;
2927                 ts->stat = SAS_PHY_DOWN;
2928                 break;
2929         case IO_ERROR_HW_TIMEOUT:
2930                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2931                 ts->resp = SAS_TASK_COMPLETE;
2932                 ts->stat = SAS_SAM_STAT_BUSY;
2933                 break;
2934         case IO_XFER_ERROR_BREAK:
2935                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2936                 ts->resp = SAS_TASK_COMPLETE;
2937                 ts->stat = SAS_SAM_STAT_BUSY;
2938                 break;
2939         case IO_XFER_ERROR_PHY_NOT_READY:
2940                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2941                 ts->resp = SAS_TASK_COMPLETE;
2942                 ts->stat = SAS_SAM_STAT_BUSY;
2943                 break;
2944         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2945                 pm8001_dbg(pm8001_ha, IO,
2946                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2947                 ts->resp = SAS_TASK_COMPLETE;
2948                 ts->stat = SAS_OPEN_REJECT;
2949                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2950                 break;
2951         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2952                 pm8001_dbg(pm8001_ha, IO,
2953                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2954                 ts->resp = SAS_TASK_COMPLETE;
2955                 ts->stat = SAS_OPEN_REJECT;
2956                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2957                 break;
2958         case IO_OPEN_CNX_ERROR_BREAK:
2959                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2960                 ts->resp = SAS_TASK_COMPLETE;
2961                 ts->stat = SAS_OPEN_REJECT;
2962                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2963                 break;
2964         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2965                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2966                 ts->resp = SAS_TASK_COMPLETE;
2967                 ts->stat = SAS_OPEN_REJECT;
2968                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2969                 pm8001_handle_event(pm8001_ha,
2970                                 pm8001_dev,
2971                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2972                 break;
2973         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2974                 pm8001_dbg(pm8001_ha, IO,
2975                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2976                 ts->resp = SAS_TASK_COMPLETE;
2977                 ts->stat = SAS_OPEN_REJECT;
2978                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2979                 break;
2980         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2981                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2982                 ts->resp = SAS_TASK_COMPLETE;
2983                 ts->stat = SAS_OPEN_REJECT;
2984                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2985                 break;
2986         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2987                 pm8001_dbg(pm8001_ha, IO,
2988                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2989                 ts->resp = SAS_TASK_COMPLETE;
2990                 ts->stat = SAS_OPEN_REJECT;
2991                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2992                 break;
2993         case IO_XFER_ERROR_RX_FRAME:
2994                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2995                 ts->resp = SAS_TASK_COMPLETE;
2996                 ts->stat = SAS_DEV_NO_RESPONSE;
2997                 break;
2998         case IO_XFER_OPEN_RETRY_TIMEOUT:
2999                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3000                 ts->resp = SAS_TASK_COMPLETE;
3001                 ts->stat = SAS_OPEN_REJECT;
3002                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3003                 break;
3004         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3005                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3006                 ts->resp = SAS_TASK_COMPLETE;
3007                 ts->stat = SAS_QUEUE_FULL;
3008                 break;
3009         case IO_PORT_IN_RESET:
3010                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3011                 ts->resp = SAS_TASK_COMPLETE;
3012                 ts->stat = SAS_OPEN_REJECT;
3013                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3014                 break;
3015         case IO_DS_NON_OPERATIONAL:
3016                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3017                 ts->resp = SAS_TASK_COMPLETE;
3018                 ts->stat = SAS_DEV_NO_RESPONSE;
3019                 break;
3020         case IO_DS_IN_RECOVERY:
3021                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3022                 ts->resp = SAS_TASK_COMPLETE;
3023                 ts->stat = SAS_OPEN_REJECT;
3024                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3025                 break;
3026         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3027                 pm8001_dbg(pm8001_ha, IO,
3028                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3029                 ts->resp = SAS_TASK_COMPLETE;
3030                 ts->stat = SAS_OPEN_REJECT;
3031                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3032                 break;
3033         default:
3034                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3035                 ts->resp = SAS_TASK_COMPLETE;
3036                 ts->stat = SAS_DEV_NO_RESPONSE;
3037                 /* not allowed case. Therefore, return failed status */
3038                 break;
3039         }
3040         spin_lock_irqsave(&t->task_state_lock, flags);
3041         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3042         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3043         t->task_state_flags |= SAS_TASK_STATE_DONE;
3044         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3045                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3046                 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
3047                            t, status, ts->resp, ts->stat);
3048                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3049         } else {
3050                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3051                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3052                 mb();/* in order to force CPU ordering */
3053                 t->task_done(t);
3054         }
3055 }
3056
3057 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3058                 void *piomb)
3059 {
3060         struct set_dev_state_resp *pPayload =
3061                 (struct set_dev_state_resp *)(piomb + 4);
3062         u32 tag = le32_to_cpu(pPayload->tag);
3063         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3064         struct pm8001_device *pm8001_dev = ccb->device;
3065         u32 status = le32_to_cpu(pPayload->status);
3066         u32 device_id = le32_to_cpu(pPayload->device_id);
3067         u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3068         u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3069         pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3070                    device_id, pds, nds, status);
3071         complete(pm8001_dev->setds_completion);
3072         ccb->task = NULL;
3073         ccb->ccb_tag = 0xFFFFFFFF;
3074         pm8001_tag_free(pm8001_ha, tag);
3075 }
3076
3077 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3078 {
3079         struct get_nvm_data_resp *pPayload =
3080                 (struct get_nvm_data_resp *)(piomb + 4);
3081         u32 tag = le32_to_cpu(pPayload->tag);
3082         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3083         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3084         complete(pm8001_ha->nvmd_completion);
3085         pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3086         if ((dlen_status & NVMD_STAT) != 0) {
3087                 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n",
3088                                 dlen_status);
3089         }
3090         ccb->task = NULL;
3091         ccb->ccb_tag = 0xFFFFFFFF;
3092         pm8001_tag_free(pm8001_ha, tag);
3093 }
3094
3095 void
3096 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3097 {
3098         struct fw_control_ex    *fw_control_context;
3099         struct get_nvm_data_resp *pPayload =
3100                 (struct get_nvm_data_resp *)(piomb + 4);
3101         u32 tag = le32_to_cpu(pPayload->tag);
3102         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3103         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3104         u32 ir_tds_bn_dps_das_nvm =
3105                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3106         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3107         fw_control_context = ccb->fw_control_context;
3108
3109         pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3110         if ((dlen_status & NVMD_STAT) != 0) {
3111                 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n",
3112                                 dlen_status);
3113                 complete(pm8001_ha->nvmd_completion);
3114                 /* We should free tag during failure also, the tag is not being
3115                  * freed by requesting path anywhere.
3116                  */
3117                 ccb->task = NULL;
3118                 ccb->ccb_tag = 0xFFFFFFFF;
3119                 pm8001_tag_free(pm8001_ha, tag);
3120                 return;
3121         }
3122         if (ir_tds_bn_dps_das_nvm & IPMode) {
3123                 /* indirect mode - IR bit set */
3124                 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3125                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3126                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3127                                 memcpy(pm8001_ha->sas_addr,
3128                                       ((u8 *)virt_addr + 4),
3129                                        SAS_ADDR_SIZE);
3130                                 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3131                         }
3132                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3133                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3134                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3135                                 ;
3136                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3137                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3138                         ;
3139                 } else {
3140                         /* Should not be happened*/
3141                         pm8001_dbg(pm8001_ha, MSG,
3142                                    "(IR=1)Wrong Device type 0x%x\n",
3143                                    ir_tds_bn_dps_das_nvm);
3144                 }
3145         } else /* direct mode */{
3146                 pm8001_dbg(pm8001_ha, MSG,
3147                            "Get NVMD success, IR=0, dataLen=%d\n",
3148                            (dlen_status & NVMD_LEN) >> 24);
3149         }
3150         /* Though fw_control_context is freed below, usrAddr still needs
3151          * to be updated as this holds the response to the request function
3152          */
3153         memcpy(fw_control_context->usrAddr,
3154                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3155                 fw_control_context->len);
3156         kfree(ccb->fw_control_context);
3157         /* To avoid race condition, complete should be
3158          * called after the message is copied to
3159          * fw_control_context->usrAddr
3160          */
3161         complete(pm8001_ha->nvmd_completion);
3162         pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3163         ccb->task = NULL;
3164         ccb->ccb_tag = 0xFFFFFFFF;
3165         pm8001_tag_free(pm8001_ha, tag);
3166 }
3167
3168 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3169 {
3170         u32 tag;
3171         struct local_phy_ctl_resp *pPayload =
3172                 (struct local_phy_ctl_resp *)(piomb + 4);
3173         u32 status = le32_to_cpu(pPayload->status);
3174         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3175         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3176         tag = le32_to_cpu(pPayload->tag);
3177         if (status != 0) {
3178                 pm8001_dbg(pm8001_ha, MSG,
3179                            "%x phy execute %x phy op failed!\n",
3180                            phy_id, phy_op);
3181         } else {
3182                 pm8001_dbg(pm8001_ha, MSG,
3183                            "%x phy execute %x phy op success!\n",
3184                            phy_id, phy_op);
3185                 pm8001_ha->phy[phy_id].reset_success = true;
3186         }
3187         if (pm8001_ha->phy[phy_id].enable_completion) {
3188                 complete(pm8001_ha->phy[phy_id].enable_completion);
3189                 pm8001_ha->phy[phy_id].enable_completion = NULL;
3190         }
3191         pm8001_tag_free(pm8001_ha, tag);
3192         return 0;
3193 }
3194
3195 /**
3196  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3197  * @pm8001_ha: our hba card information
3198  * @i: which phy that received the event.
3199  *
3200  * when HBA driver received the identify done event or initiate FIS received
3201  * event(for SATA), it will invoke this function to notify the sas layer that
3202  * the sas toplogy has formed, please discover the the whole sas domain,
3203  * while receive a broadcast(change) primitive just tell the sas
3204  * layer to discover the changed domain rather than the whole domain.
3205  */
3206 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3207 {
3208         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3209         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3210         if (!phy->phy_attached)
3211                 return;
3212
3213         if (sas_phy->phy) {
3214                 struct sas_phy *sphy = sas_phy->phy;
3215                 sphy->negotiated_linkrate = sas_phy->linkrate;
3216                 sphy->minimum_linkrate = phy->minimum_linkrate;
3217                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3218                 sphy->maximum_linkrate = phy->maximum_linkrate;
3219                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3220         }
3221
3222         if (phy->phy_type & PORT_TYPE_SAS) {
3223                 struct sas_identify_frame *id;
3224                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3225                 id->dev_type = phy->identify.device_type;
3226                 id->initiator_bits = SAS_PROTOCOL_ALL;
3227                 id->target_bits = phy->identify.target_port_protocols;
3228         } else if (phy->phy_type & PORT_TYPE_SATA) {
3229                 /*Nothing*/
3230         }
3231         pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3232
3233         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3234         sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC);
3235 }
3236
3237 /* Get the link rate speed  */
3238 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3239 {
3240         struct sas_phy *sas_phy = phy->sas_phy.phy;
3241
3242         switch (link_rate) {
3243         case PHY_SPEED_120:
3244                 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3245                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3246                 break;
3247         case PHY_SPEED_60:
3248                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3249                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3250                 break;
3251         case PHY_SPEED_30:
3252                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3253                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3254                 break;
3255         case PHY_SPEED_15:
3256                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3257                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3258                 break;
3259         }
3260         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3261         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3262         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3263         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3264         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3265 }
3266
3267 /**
3268  * pm8001_get_attached_sas_addr - extract/generate attached SAS address
3269  * @phy: pointer to asd_phy
3270  * @sas_addr: pointer to buffer where the SAS address is to be written
3271  *
3272  * This function extracts the SAS address from an IDENTIFY frame
3273  * received.  If OOB is SATA, then a SAS address is generated from the
3274  * HA tables.
3275  *
3276  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3277  * buffer.
3278  */
3279 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3280         u8 *sas_addr)
3281 {
3282         if (phy->sas_phy.frame_rcvd[0] == 0x34
3283                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3284                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3285                 /* FIS device-to-host */
3286                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3287                 addr += phy->sas_phy.id;
3288                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3289         } else {
3290                 struct sas_identify_frame *idframe =
3291                         (void *) phy->sas_phy.frame_rcvd;
3292                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3293         }
3294 }
3295
3296 /**
3297  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3298  * @pm8001_ha: our hba card information
3299  * @Qnum: the outbound queue message number.
3300  * @SEA: source of event to ack
3301  * @port_id: port id.
3302  * @phyId: phy id.
3303  * @param0: parameter 0.
3304  * @param1: parameter 1.
3305  */
3306 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3307         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3308 {
3309         struct hw_event_ack_req  payload;
3310         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3311
3312         struct inbound_queue_table *circularQ;
3313
3314         memset((u8 *)&payload, 0, sizeof(payload));
3315         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3316         payload.tag = cpu_to_le32(1);
3317         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3318                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3319         payload.param0 = cpu_to_le32(param0);
3320         payload.param1 = cpu_to_le32(param1);
3321         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3322                         sizeof(payload), 0);
3323 }
3324
3325 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3326         u32 phyId, u32 phy_op);
3327
3328 /**
3329  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3330  * @pm8001_ha: our hba card information
3331  * @piomb: IO message buffer
3332  */
3333 static void
3334 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3335 {
3336         struct hw_event_resp *pPayload =
3337                 (struct hw_event_resp *)(piomb + 4);
3338         u32 lr_evt_status_phyid_portid =
3339                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3340         u8 link_rate =
3341                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3342         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3343         u8 phy_id =
3344                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3345         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3346         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3347         struct pm8001_port *port = &pm8001_ha->port[port_id];
3348         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3349         unsigned long flags;
3350         u8 deviceType = pPayload->sas_identify.dev_type;
3351         port->port_state =  portstate;
3352         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3353         pm8001_dbg(pm8001_ha, MSG,
3354                    "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3355                    port_id, phy_id);
3356
3357         switch (deviceType) {
3358         case SAS_PHY_UNUSED:
3359                 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3360                 break;
3361         case SAS_END_DEVICE:
3362                 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3363                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3364                         PHY_NOTIFY_ENABLE_SPINUP);
3365                 port->port_attached = 1;
3366                 pm8001_get_lrate_mode(phy, link_rate);
3367                 break;
3368         case SAS_EDGE_EXPANDER_DEVICE:
3369                 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3370                 port->port_attached = 1;
3371                 pm8001_get_lrate_mode(phy, link_rate);
3372                 break;
3373         case SAS_FANOUT_EXPANDER_DEVICE:
3374                 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3375                 port->port_attached = 1;
3376                 pm8001_get_lrate_mode(phy, link_rate);
3377                 break;
3378         default:
3379                 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3380                            deviceType);
3381                 break;
3382         }
3383         phy->phy_type |= PORT_TYPE_SAS;
3384         phy->identify.device_type = deviceType;
3385         phy->phy_attached = 1;
3386         if (phy->identify.device_type == SAS_END_DEVICE)
3387                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3388         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3389                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3390         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3391         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3392         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3393         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3394                 sizeof(struct sas_identify_frame)-4);
3395         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3396         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3397         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3398         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3399                 mdelay(200);/*delay a moment to wait disk to spinup*/
3400         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3401 }
3402
3403 /**
3404  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3405  * @pm8001_ha: our hba card information
3406  * @piomb: IO message buffer
3407  */
3408 static void
3409 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3410 {
3411         struct hw_event_resp *pPayload =
3412                 (struct hw_event_resp *)(piomb + 4);
3413         u32 lr_evt_status_phyid_portid =
3414                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3415         u8 link_rate =
3416                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3417         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3418         u8 phy_id =
3419                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3420         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3421         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3422         struct pm8001_port *port = &pm8001_ha->port[port_id];
3423         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3424         unsigned long flags;
3425         pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3426                    port_id, phy_id);
3427         port->port_state =  portstate;
3428         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3429         port->port_attached = 1;
3430         pm8001_get_lrate_mode(phy, link_rate);
3431         phy->phy_type |= PORT_TYPE_SATA;
3432         phy->phy_attached = 1;
3433         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3434         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3435         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3436         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3437                 sizeof(struct dev_to_host_fis));
3438         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3439         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3440         phy->identify.device_type = SAS_SATA_DEV;
3441         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3442         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3443         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3444 }
3445
3446 /**
3447  * hw_event_phy_down -we should notify the libsas the phy is down.
3448  * @pm8001_ha: our hba card information
3449  * @piomb: IO message buffer
3450  */
3451 static void
3452 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3453 {
3454         struct hw_event_resp *pPayload =
3455                 (struct hw_event_resp *)(piomb + 4);
3456         u32 lr_evt_status_phyid_portid =
3457                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3458         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3459         u8 phy_id =
3460                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3461         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3462         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3463         struct pm8001_port *port = &pm8001_ha->port[port_id];
3464         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3465         port->port_state =  portstate;
3466         phy->phy_type = 0;
3467         phy->identify.device_type = 0;
3468         phy->phy_attached = 0;
3469         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3470         switch (portstate) {
3471         case PORT_VALID:
3472                 break;
3473         case PORT_INVALID:
3474                 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3475                            port_id);
3476                 pm8001_dbg(pm8001_ha, MSG,
3477                            " Last phy Down and port invalid\n");
3478                 port->port_attached = 0;
3479                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3480                         port_id, phy_id, 0, 0);
3481                 break;
3482         case PORT_IN_RESET:
3483                 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3484                            port_id);
3485                 break;
3486         case PORT_NOT_ESTABLISHED:
3487                 pm8001_dbg(pm8001_ha, MSG,
3488                            " phy Down and PORT_NOT_ESTABLISHED\n");
3489                 port->port_attached = 0;
3490                 break;
3491         case PORT_LOSTCOMM:
3492                 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3493                 pm8001_dbg(pm8001_ha, MSG,
3494                            " Last phy Down and port invalid\n");
3495                 port->port_attached = 0;
3496                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3497                         port_id, phy_id, 0, 0);
3498                 break;
3499         default:
3500                 port->port_attached = 0;
3501                 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3502                            portstate);
3503                 break;
3504
3505         }
3506 }
3507
3508 /**
3509  * pm8001_mpi_reg_resp -process register device ID response.
3510  * @pm8001_ha: our hba card information
3511  * @piomb: IO message buffer
3512  *
3513  * when sas layer find a device it will notify LLDD, then the driver register
3514  * the domain device to FW, this event is the return device ID which the FW
3515  * has assigned, from now, inter-communication with FW is no longer using the
3516  * SAS address, use device ID which FW assigned.
3517  */
3518 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3519 {
3520         u32 status;
3521         u32 device_id;
3522         u32 htag;
3523         struct pm8001_ccb_info *ccb;
3524         struct pm8001_device *pm8001_dev;
3525         struct dev_reg_resp *registerRespPayload =
3526                 (struct dev_reg_resp *)(piomb + 4);
3527
3528         htag = le32_to_cpu(registerRespPayload->tag);
3529         ccb = &pm8001_ha->ccb_info[htag];
3530         pm8001_dev = ccb->device;
3531         status = le32_to_cpu(registerRespPayload->status);
3532         device_id = le32_to_cpu(registerRespPayload->device_id);
3533         pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3534                    status);
3535         switch (status) {
3536         case DEVREG_SUCCESS:
3537                 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3538                 pm8001_dev->device_id = device_id;
3539                 break;
3540         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3541                 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3542                 break;
3543         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3544                 pm8001_dbg(pm8001_ha, MSG,
3545                            "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3546                 break;
3547         case DEVREG_FAILURE_INVALID_PHY_ID:
3548                 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3549                 break;
3550         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3551                 pm8001_dbg(pm8001_ha, MSG,
3552                            "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3553                 break;
3554         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3555                 pm8001_dbg(pm8001_ha, MSG,
3556                            "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3557                 break;
3558         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3559                 pm8001_dbg(pm8001_ha, MSG,
3560                            "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3561                 break;
3562         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3563                 pm8001_dbg(pm8001_ha, MSG,
3564                            "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3565                 break;
3566         default:
3567                 pm8001_dbg(pm8001_ha, MSG,
3568                            "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3569                 break;
3570         }
3571         complete(pm8001_dev->dcompletion);
3572         ccb->task = NULL;
3573         ccb->ccb_tag = 0xFFFFFFFF;
3574         pm8001_tag_free(pm8001_ha, htag);
3575         return 0;
3576 }
3577
3578 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3579 {
3580         u32 status;
3581         u32 device_id;
3582         struct dev_reg_resp *registerRespPayload =
3583                 (struct dev_reg_resp *)(piomb + 4);
3584
3585         status = le32_to_cpu(registerRespPayload->status);
3586         device_id = le32_to_cpu(registerRespPayload->device_id);
3587         if (status != 0)
3588                 pm8001_dbg(pm8001_ha, MSG,
3589                            " deregister device failed ,status = %x, device_id = %x\n",
3590                            status, device_id);
3591         return 0;
3592 }
3593
3594 /**
3595  * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command.
3596  * @pm8001_ha: our hba card information
3597  * @piomb: IO message buffer
3598  */
3599 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3600                 void *piomb)
3601 {
3602         u32 status;
3603         struct fw_flash_Update_resp *ppayload =
3604                 (struct fw_flash_Update_resp *)(piomb + 4);
3605         u32 tag = le32_to_cpu(ppayload->tag);
3606         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3607         status = le32_to_cpu(ppayload->status);
3608         switch (status) {
3609         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3610                 pm8001_dbg(pm8001_ha, MSG,
3611                            ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3612                 break;
3613         case FLASH_UPDATE_IN_PROGRESS:
3614                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3615                 break;
3616         case FLASH_UPDATE_HDR_ERR:
3617                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3618                 break;
3619         case FLASH_UPDATE_OFFSET_ERR:
3620                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3621                 break;
3622         case FLASH_UPDATE_CRC_ERR:
3623                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3624                 break;
3625         case FLASH_UPDATE_LENGTH_ERR:
3626                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3627                 break;
3628         case FLASH_UPDATE_HW_ERR:
3629                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3630                 break;
3631         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3632                 pm8001_dbg(pm8001_ha, MSG,
3633                            ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3634                 break;
3635         case FLASH_UPDATE_DISABLED:
3636                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3637                 break;
3638         default:
3639                 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3640                            status);
3641                 break;
3642         }
3643         kfree(ccb->fw_control_context);
3644         ccb->task = NULL;
3645         ccb->ccb_tag = 0xFFFFFFFF;
3646         pm8001_tag_free(pm8001_ha, tag);
3647         complete(pm8001_ha->nvmd_completion);
3648         return 0;
3649 }
3650
3651 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3652 {
3653         u32 status;
3654         int i;
3655         struct general_event_resp *pPayload =
3656                 (struct general_event_resp *)(piomb + 4);
3657         status = le32_to_cpu(pPayload->status);
3658         pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3659         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3660                 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3661                            i,
3662                            pPayload->inb_IOMB_payload[i]);
3663         return 0;
3664 }
3665
3666 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3667 {
3668         struct sas_task *t;
3669         struct pm8001_ccb_info *ccb;
3670         unsigned long flags;
3671         u32 status ;
3672         u32 tag, scp;
3673         struct task_status_struct *ts;
3674         struct pm8001_device *pm8001_dev;
3675
3676         struct task_abort_resp *pPayload =
3677                 (struct task_abort_resp *)(piomb + 4);
3678
3679         status = le32_to_cpu(pPayload->status);
3680         tag = le32_to_cpu(pPayload->tag);
3681         if (!tag) {
3682                 pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n");
3683                 return -1;
3684         }
3685
3686         scp = le32_to_cpu(pPayload->scp);
3687         ccb = &pm8001_ha->ccb_info[tag];
3688         t = ccb->task;
3689         pm8001_dev = ccb->device; /* retrieve device */
3690
3691         if (!t) {
3692                 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3693                 return -1;
3694         }
3695         ts = &t->task_status;
3696         if (status != 0)
3697                 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3698                            status, tag, scp);
3699         switch (status) {
3700         case IO_SUCCESS:
3701                 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3702                 ts->resp = SAS_TASK_COMPLETE;
3703                 ts->stat = SAS_SAM_STAT_GOOD;
3704                 break;
3705         case IO_NOT_VALID:
3706                 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3707                 ts->resp = TMF_RESP_FUNC_FAILED;
3708                 break;
3709         }
3710         spin_lock_irqsave(&t->task_state_lock, flags);
3711         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3712         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3713         t->task_state_flags |= SAS_TASK_STATE_DONE;
3714         spin_unlock_irqrestore(&t->task_state_lock, flags);
3715         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3716         mb();
3717
3718         if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3719                 sas_free_task(t);
3720                 pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3721         } else {
3722                 t->task_done(t);
3723         }
3724
3725         return 0;
3726 }
3727
3728 /**
3729  * mpi_hw_event -The hw event has come.
3730  * @pm8001_ha: our hba card information
3731  * @piomb: IO message buffer
3732  */
3733 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3734 {
3735         unsigned long flags;
3736         struct hw_event_resp *pPayload =
3737                 (struct hw_event_resp *)(piomb + 4);
3738         u32 lr_evt_status_phyid_portid =
3739                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3740         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3741         u8 phy_id =
3742                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3743         u16 eventType =
3744                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3745         u8 status =
3746                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3747         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3748         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3749         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3750         pm8001_dbg(pm8001_ha, DEVIO,
3751                    "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3752                    port_id, phy_id, eventType, status);
3753         switch (eventType) {
3754         case HW_EVENT_PHY_START_STATUS:
3755                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3756                            status);
3757                 if (status == 0)
3758                         phy->phy_state = 1;
3759
3760                 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3761                                 phy->enable_completion != NULL) {
3762                         complete(phy->enable_completion);
3763                         phy->enable_completion = NULL;
3764                 }
3765                 break;
3766         case HW_EVENT_SAS_PHY_UP:
3767                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3768                 hw_event_sas_phy_up(pm8001_ha, piomb);
3769                 break;
3770         case HW_EVENT_SATA_PHY_UP:
3771                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3772                 hw_event_sata_phy_up(pm8001_ha, piomb);
3773                 break;
3774         case HW_EVENT_PHY_STOP_STATUS:
3775                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3776                            status);
3777                 if (status == 0)
3778                         phy->phy_state = 0;
3779                 break;
3780         case HW_EVENT_SATA_SPINUP_HOLD:
3781                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3782                 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3783                         GFP_ATOMIC);
3784                 break;
3785         case HW_EVENT_PHY_DOWN:
3786                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3787                 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3788                         GFP_ATOMIC);
3789                 phy->phy_attached = 0;
3790                 phy->phy_state = 0;
3791                 hw_event_phy_down(pm8001_ha, piomb);
3792                 break;
3793         case HW_EVENT_PORT_INVALID:
3794                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3795                 sas_phy_disconnected(sas_phy);
3796                 phy->phy_attached = 0;
3797                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3798                         GFP_ATOMIC);
3799                 break;
3800         /* the broadcast change primitive received, tell the LIBSAS this event
3801         to revalidate the sas domain*/
3802         case HW_EVENT_BROADCAST_CHANGE:
3803                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3804                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3805                         port_id, phy_id, 1, 0);
3806                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3807                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3808                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3809                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3810                         GFP_ATOMIC);
3811                 break;
3812         case HW_EVENT_PHY_ERROR:
3813                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3814                 sas_phy_disconnected(&phy->sas_phy);
3815                 phy->phy_attached = 0;
3816                 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3817                 break;
3818         case HW_EVENT_BROADCAST_EXP:
3819                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3820                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3821                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3822                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3823                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3824                         GFP_ATOMIC);
3825                 break;
3826         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3827                 pm8001_dbg(pm8001_ha, MSG,
3828                            "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3829                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3830                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3831                 sas_phy_disconnected(sas_phy);
3832                 phy->phy_attached = 0;
3833                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3834                         GFP_ATOMIC);
3835                 break;
3836         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3837                 pm8001_dbg(pm8001_ha, MSG,
3838                            "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3839                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3840                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3841                         port_id, phy_id, 0, 0);
3842                 sas_phy_disconnected(sas_phy);
3843                 phy->phy_attached = 0;
3844                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3845                         GFP_ATOMIC);
3846                 break;
3847         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3848                 pm8001_dbg(pm8001_ha, MSG,
3849                            "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3850                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3851                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3852                         port_id, phy_id, 0, 0);
3853                 sas_phy_disconnected(sas_phy);
3854                 phy->phy_attached = 0;
3855                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3856                         GFP_ATOMIC);
3857                 break;
3858         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3859                 pm8001_dbg(pm8001_ha, MSG,
3860                            "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3861                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3862                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3863                         port_id, phy_id, 0, 0);
3864                 sas_phy_disconnected(sas_phy);
3865                 phy->phy_attached = 0;
3866                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3867                         GFP_ATOMIC);
3868                 break;
3869         case HW_EVENT_MALFUNCTION:
3870                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3871                 break;
3872         case HW_EVENT_BROADCAST_SES:
3873                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3874                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3875                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3876                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3877                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3878                         GFP_ATOMIC);
3879                 break;
3880         case HW_EVENT_INBOUND_CRC_ERROR:
3881                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3882                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3883                         HW_EVENT_INBOUND_CRC_ERROR,
3884                         port_id, phy_id, 0, 0);
3885                 break;
3886         case HW_EVENT_HARD_RESET_RECEIVED:
3887                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3888                 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3889                 break;
3890         case HW_EVENT_ID_FRAME_TIMEOUT:
3891                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3892                 sas_phy_disconnected(sas_phy);
3893                 phy->phy_attached = 0;
3894                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3895                         GFP_ATOMIC);
3896                 break;
3897         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3898                 pm8001_dbg(pm8001_ha, MSG,
3899                            "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3900                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3901                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3902                         port_id, phy_id, 0, 0);
3903                 sas_phy_disconnected(sas_phy);
3904                 phy->phy_attached = 0;
3905                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3906                         GFP_ATOMIC);
3907                 break;
3908         case HW_EVENT_PORT_RESET_TIMER_TMO:
3909                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3910                 sas_phy_disconnected(sas_phy);
3911                 phy->phy_attached = 0;
3912                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3913                         GFP_ATOMIC);
3914                 break;
3915         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3916                 pm8001_dbg(pm8001_ha, MSG,
3917                            "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3918                 sas_phy_disconnected(sas_phy);
3919                 phy->phy_attached = 0;
3920                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3921                         GFP_ATOMIC);
3922                 break;
3923         case HW_EVENT_PORT_RECOVER:
3924                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3925                 break;
3926         case HW_EVENT_PORT_RESET_COMPLETE:
3927                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3928                 break;
3929         case EVENT_BROADCAST_ASYNCH_EVENT:
3930                 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3931                 break;
3932         default:
3933                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3934                            eventType);
3935                 break;
3936         }
3937         return 0;
3938 }
3939
3940 /**
3941  * process_one_iomb - process one outbound Queue memory block
3942  * @pm8001_ha: our hba card information
3943  * @piomb: IO message buffer
3944  */
3945 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3946 {
3947         __le32 pHeader = *(__le32 *)piomb;
3948         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3949
3950         pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3951
3952         switch (opc) {
3953         case OPC_OUB_ECHO:
3954                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3955                 break;
3956         case OPC_OUB_HW_EVENT:
3957                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3958                 mpi_hw_event(pm8001_ha, piomb);
3959                 break;
3960         case OPC_OUB_SSP_COMP:
3961                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3962                 mpi_ssp_completion(pm8001_ha, piomb);
3963                 break;
3964         case OPC_OUB_SMP_COMP:
3965                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3966                 mpi_smp_completion(pm8001_ha, piomb);
3967                 break;
3968         case OPC_OUB_LOCAL_PHY_CNTRL:
3969                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3970                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3971                 break;
3972         case OPC_OUB_DEV_REGIST:
3973                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3974                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3975                 break;
3976         case OPC_OUB_DEREG_DEV:
3977                 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3978                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3979                 break;
3980         case OPC_OUB_GET_DEV_HANDLE:
3981                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3982                 break;
3983         case OPC_OUB_SATA_COMP:
3984                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3985                 mpi_sata_completion(pm8001_ha, piomb);
3986                 break;
3987         case OPC_OUB_SATA_EVENT:
3988                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3989                 mpi_sata_event(pm8001_ha, piomb);
3990                 break;
3991         case OPC_OUB_SSP_EVENT:
3992                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3993                 mpi_ssp_event(pm8001_ha, piomb);
3994                 break;
3995         case OPC_OUB_DEV_HANDLE_ARRIV:
3996                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3997                 /*This is for target*/
3998                 break;
3999         case OPC_OUB_SSP_RECV_EVENT:
4000                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
4001                 /*This is for target*/
4002                 break;
4003         case OPC_OUB_DEV_INFO:
4004                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
4005                 break;
4006         case OPC_OUB_FW_FLASH_UPDATE:
4007                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
4008                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4009                 break;
4010         case OPC_OUB_GPIO_RESPONSE:
4011                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
4012                 break;
4013         case OPC_OUB_GPIO_EVENT:
4014                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
4015                 break;
4016         case OPC_OUB_GENERAL_EVENT:
4017                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
4018                 pm8001_mpi_general_event(pm8001_ha, piomb);
4019                 break;
4020         case OPC_OUB_SSP_ABORT_RSP:
4021                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
4022                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4023                 break;
4024         case OPC_OUB_SATA_ABORT_RSP:
4025                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
4026                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4027                 break;
4028         case OPC_OUB_SAS_DIAG_MODE_START_END:
4029                 pm8001_dbg(pm8001_ha, MSG,
4030                            "OPC_OUB_SAS_DIAG_MODE_START_END\n");
4031                 break;
4032         case OPC_OUB_SAS_DIAG_EXECUTE:
4033                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
4034                 break;
4035         case OPC_OUB_GET_TIME_STAMP:
4036                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
4037                 break;
4038         case OPC_OUB_SAS_HW_EVENT_ACK:
4039                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
4040                 break;
4041         case OPC_OUB_PORT_CONTROL:
4042                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
4043                 break;
4044         case OPC_OUB_SMP_ABORT_RSP:
4045                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
4046                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4047                 break;
4048         case OPC_OUB_GET_NVMD_DATA:
4049                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
4050                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4051                 break;
4052         case OPC_OUB_SET_NVMD_DATA:
4053                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
4054                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4055                 break;
4056         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4057                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
4058                 break;
4059         case OPC_OUB_SET_DEVICE_STATE:
4060                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
4061                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4062                 break;
4063         case OPC_OUB_GET_DEVICE_STATE:
4064                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4065                 break;
4066         case OPC_OUB_SET_DEV_INFO:
4067                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4068                 break;
4069         case OPC_OUB_SAS_RE_INITIALIZE:
4070                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
4071                 break;
4072         default:
4073                 pm8001_dbg(pm8001_ha, DEVIO,
4074                            "Unknown outbound Queue IOMB OPC = %x\n",
4075                            opc);
4076                 break;
4077         }
4078 }
4079
4080 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4081 {
4082         struct outbound_queue_table *circularQ;
4083         void *pMsg1 = NULL;
4084         u8 bc;
4085         u32 ret = MPI_IO_STATUS_FAIL;
4086         unsigned long flags;
4087
4088         spin_lock_irqsave(&pm8001_ha->lock, flags);
4089         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4090         do {
4091                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4092                 if (MPI_IO_STATUS_SUCCESS == ret) {
4093                         /* process the outbound message */
4094                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4095                         /* free the message from the outbound circular buffer */
4096                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4097                                                         circularQ, bc);
4098                 }
4099                 if (MPI_IO_STATUS_BUSY == ret) {
4100                         /* Update the producer index from SPC */
4101                         circularQ->producer_index =
4102                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4103                         if (le32_to_cpu(circularQ->producer_index) ==
4104                                 circularQ->consumer_idx)
4105                                 /* OQ is empty */
4106                                 break;
4107                 }
4108         } while (1);
4109         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4110         return ret;
4111 }
4112
4113 /* DMA_... to our direction translation. */
4114 static const u8 data_dir_flags[] = {
4115         [DMA_BIDIRECTIONAL]     = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4116         [DMA_TO_DEVICE]         = DATA_DIR_OUT,         /* OUTBOUND */
4117         [DMA_FROM_DEVICE]       = DATA_DIR_IN,          /* INBOUND */
4118         [DMA_NONE]              = DATA_DIR_NONE,        /* NO TRANSFER */
4119 };
4120 void
4121 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4122 {
4123         int i;
4124         struct scatterlist *sg;
4125         struct pm8001_prd *buf_prd = prd;
4126
4127         for_each_sg(scatter, sg, nr, i) {
4128                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4129                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4130                 buf_prd->im_len.e = 0;
4131                 buf_prd++;
4132         }
4133 }
4134
4135 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4136 {
4137         psmp_cmd->tag = hTag;
4138         psmp_cmd->device_id = cpu_to_le32(deviceID);
4139         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4140 }
4141
4142 /**
4143  * pm8001_chip_smp_req - send a SMP task to FW
4144  * @pm8001_ha: our hba card information.
4145  * @ccb: the ccb information this request used.
4146  */
4147 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4148         struct pm8001_ccb_info *ccb)
4149 {
4150         int elem, rc;
4151         struct sas_task *task = ccb->task;
4152         struct domain_device *dev = task->dev;
4153         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4154         struct scatterlist *sg_req, *sg_resp;
4155         u32 req_len, resp_len;
4156         struct smp_req smp_cmd;
4157         u32 opc;
4158         struct inbound_queue_table *circularQ;
4159
4160         memset(&smp_cmd, 0, sizeof(smp_cmd));
4161         /*
4162          * DMA-map SMP request, response buffers
4163          */
4164         sg_req = &task->smp_task.smp_req;
4165         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4166         if (!elem)
4167                 return -ENOMEM;
4168         req_len = sg_dma_len(sg_req);
4169
4170         sg_resp = &task->smp_task.smp_resp;
4171         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4172         if (!elem) {
4173                 rc = -ENOMEM;
4174                 goto err_out;
4175         }
4176         resp_len = sg_dma_len(sg_resp);
4177         /* must be in dwords */
4178         if ((req_len & 0x3) || (resp_len & 0x3)) {
4179                 rc = -EINVAL;
4180                 goto err_out_2;
4181         }
4182
4183         opc = OPC_INB_SMP_REQUEST;
4184         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4185         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4186         smp_cmd.long_smp_req.long_req_addr =
4187                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4188         smp_cmd.long_smp_req.long_req_size =
4189                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4190         smp_cmd.long_smp_req.long_resp_addr =
4191                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4192         smp_cmd.long_smp_req.long_resp_size =
4193                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4194         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4195         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4196                         &smp_cmd, sizeof(smp_cmd), 0);
4197         if (rc)
4198                 goto err_out_2;
4199
4200         return 0;
4201
4202 err_out_2:
4203         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4204                         DMA_FROM_DEVICE);
4205 err_out:
4206         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4207                         DMA_TO_DEVICE);
4208         return rc;
4209 }
4210
4211 /**
4212  * pm8001_chip_ssp_io_req - send a SSP task to FW
4213  * @pm8001_ha: our hba card information.
4214  * @ccb: the ccb information this request used.
4215  */
4216 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4217         struct pm8001_ccb_info *ccb)
4218 {
4219         struct sas_task *task = ccb->task;
4220         struct domain_device *dev = task->dev;
4221         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4222         struct ssp_ini_io_start_req ssp_cmd;
4223         u32 tag = ccb->ccb_tag;
4224         int ret;
4225         u64 phys_addr;
4226         struct inbound_queue_table *circularQ;
4227         u32 opc = OPC_INB_SSPINIIOSTART;
4228         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4229         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4230         ssp_cmd.dir_m_tlr =
4231                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4232         SAS 1.1 compatible TLR*/
4233         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4234         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4235         ssp_cmd.tag = cpu_to_le32(tag);
4236         if (task->ssp_task.enable_first_burst)
4237                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4238         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4239         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4240         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4241                task->ssp_task.cmd->cmd_len);
4242         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4243
4244         /* fill in PRD (scatter/gather) table, if any */
4245         if (task->num_scatter > 1) {
4246                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4247                 phys_addr = ccb->ccb_dma_handle;
4248                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4249                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4250                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4251         } else if (task->num_scatter == 1) {
4252                 u64 dma_addr = sg_dma_address(task->scatter);
4253                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4254                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4255                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4256                 ssp_cmd.esgl = 0;
4257         } else if (task->num_scatter == 0) {
4258                 ssp_cmd.addr_low = 0;
4259                 ssp_cmd.addr_high = 0;
4260                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4261                 ssp_cmd.esgl = 0;
4262         }
4263         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd,
4264                         sizeof(ssp_cmd), 0);
4265         return ret;
4266 }
4267
4268 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4269         struct pm8001_ccb_info *ccb)
4270 {
4271         struct sas_task *task = ccb->task;
4272         struct domain_device *dev = task->dev;
4273         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4274         u32 tag = ccb->ccb_tag;
4275         int ret;
4276         struct sata_start_req sata_cmd;
4277         u32 hdr_tag, ncg_tag = 0;
4278         u64 phys_addr;
4279         u32 ATAP = 0x0;
4280         u32 dir;
4281         struct inbound_queue_table *circularQ;
4282         unsigned long flags;
4283         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4284         memset(&sata_cmd, 0, sizeof(sata_cmd));
4285         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4286
4287         if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4288                 ATAP = 0x04;  /* no data*/
4289                 pm8001_dbg(pm8001_ha, IO, "no data\n");
4290         } else if (likely(!task->ata_task.device_control_reg_update)) {
4291                 if (task->ata_task.use_ncq &&
4292                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4293                         ATAP = 0x07; /* FPDMA */
4294                         pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4295                 } else if (task->ata_task.dma_xfer) {
4296                         ATAP = 0x06; /* DMA */
4297                         pm8001_dbg(pm8001_ha, IO, "DMA\n");
4298                 } else {
4299                         ATAP = 0x05; /* PIO*/
4300                         pm8001_dbg(pm8001_ha, IO, "PIO\n");
4301                 }
4302         }
4303         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4304                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4305                 ncg_tag = hdr_tag;
4306         }
4307         dir = data_dir_flags[task->data_dir] << 8;
4308         sata_cmd.tag = cpu_to_le32(tag);
4309         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4310         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4311         sata_cmd.ncqtag_atap_dir_m =
4312                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4313         sata_cmd.sata_fis = task->ata_task.fis;
4314         if (likely(!task->ata_task.device_control_reg_update))
4315                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4316         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4317         /* fill in PRD (scatter/gather) table, if any */
4318         if (task->num_scatter > 1) {
4319                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4320                 phys_addr = ccb->ccb_dma_handle;
4321                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4322                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4323                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4324         } else if (task->num_scatter == 1) {
4325                 u64 dma_addr = sg_dma_address(task->scatter);
4326                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4327                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4328                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4329                 sata_cmd.esgl = 0;
4330         } else if (task->num_scatter == 0) {
4331                 sata_cmd.addr_low = 0;
4332                 sata_cmd.addr_high = 0;
4333                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4334                 sata_cmd.esgl = 0;
4335         }
4336
4337         /* Check for read log for failed drive and return */
4338         if (sata_cmd.sata_fis.command == 0x2f) {
4339                 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4340                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4341                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4342                         struct task_status_struct *ts;
4343
4344                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4345                         ts = &task->task_status;
4346
4347                         spin_lock_irqsave(&task->task_state_lock, flags);
4348                         ts->resp = SAS_TASK_COMPLETE;
4349                         ts->stat = SAS_SAM_STAT_GOOD;
4350                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4351                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4352                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4353                         if (unlikely((task->task_state_flags &
4354                                         SAS_TASK_STATE_ABORTED))) {
4355                                 spin_unlock_irqrestore(&task->task_state_lock,
4356                                                         flags);
4357                                 pm8001_dbg(pm8001_ha, FAIL,
4358                                            "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4359                                            task, ts->resp,
4360                                            ts->stat);
4361                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4362                         } else {
4363                                 spin_unlock_irqrestore(&task->task_state_lock,
4364                                                         flags);
4365                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4366                                                                 ccb, tag);
4367                                 return 0;
4368                         }
4369                 }
4370         }
4371
4372         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
4373                         sizeof(sata_cmd), 0);
4374         return ret;
4375 }
4376
4377 /**
4378  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4379  * @pm8001_ha: our hba card information.
4380  * @phy_id: the phy id which we wanted to start up.
4381  */
4382 static int
4383 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4384 {
4385         struct phy_start_req payload;
4386         struct inbound_queue_table *circularQ;
4387         int ret;
4388         u32 tag = 0x01;
4389         u32 opcode = OPC_INB_PHYSTART;
4390         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4391         memset(&payload, 0, sizeof(payload));
4392         payload.tag = cpu_to_le32(tag);
4393         /*
4394          ** [0:7]   PHY Identifier
4395          ** [8:11]  link rate 1.5G, 3G, 6G
4396          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4397          ** [14]    0b disable spin up hold; 1b enable spin up hold
4398          */
4399         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4400                 LINKMODE_AUTO | LINKRATE_15 |
4401                 LINKRATE_30 | LINKRATE_60 | phy_id);
4402         payload.sas_identify.dev_type = SAS_END_DEVICE;
4403         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4404         memcpy(payload.sas_identify.sas_addr,
4405                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4406         payload.sas_identify.phy_id = phy_id;
4407         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4408                         sizeof(payload), 0);
4409         return ret;
4410 }
4411
4412 /**
4413  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4414  * @pm8001_ha: our hba card information.
4415  * @phy_id: the phy id which we wanted to start up.
4416  */
4417 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4418                                     u8 phy_id)
4419 {
4420         struct phy_stop_req payload;
4421         struct inbound_queue_table *circularQ;
4422         int ret;
4423         u32 tag = 0x01;
4424         u32 opcode = OPC_INB_PHYSTOP;
4425         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4426         memset(&payload, 0, sizeof(payload));
4427         payload.tag = cpu_to_le32(tag);
4428         payload.phy_id = cpu_to_le32(phy_id);
4429         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4430                         sizeof(payload), 0);
4431         return ret;
4432 }
4433
4434 /*
4435  * see comments on pm8001_mpi_reg_resp.
4436  */
4437 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4438         struct pm8001_device *pm8001_dev, u32 flag)
4439 {
4440         struct reg_dev_req payload;
4441         u32     opc;
4442         u32 stp_sspsmp_sata = 0x4;
4443         struct inbound_queue_table *circularQ;
4444         u32 linkrate, phy_id;
4445         int rc, tag = 0xdeadbeef;
4446         struct pm8001_ccb_info *ccb;
4447         u8 retryFlag = 0x1;
4448         u16 firstBurstSize = 0;
4449         u16 ITNT = 2000;
4450         struct domain_device *dev = pm8001_dev->sas_device;
4451         struct domain_device *parent_dev = dev->parent;
4452         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4453
4454         memset(&payload, 0, sizeof(payload));
4455         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4456         if (rc)
4457                 return rc;
4458         ccb = &pm8001_ha->ccb_info[tag];
4459         ccb->device = pm8001_dev;
4460         ccb->ccb_tag = tag;
4461         payload.tag = cpu_to_le32(tag);
4462         if (flag == 1)
4463                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4464         else {
4465                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4466                         stp_sspsmp_sata = 0x00; /* stp*/
4467                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4468                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4469                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4470                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4471         }
4472         if (parent_dev && dev_is_expander(parent_dev->dev_type))
4473                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4474         else
4475                 phy_id = pm8001_dev->attached_phy;
4476         opc = OPC_INB_REG_DEV;
4477         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4478                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4479         payload.phyid_portid =
4480                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4481                 ((phy_id & 0x0F) << 4));
4482         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4483                 ((linkrate & 0x0F) * 0x1000000) |
4484                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4485         payload.firstburstsize_ITNexustimeout =
4486                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4487         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4488                 SAS_ADDR_SIZE);
4489         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4490                         sizeof(payload), 0);
4491         if (rc)
4492                 pm8001_tag_free(pm8001_ha, tag);
4493
4494         return rc;
4495 }
4496
4497 /*
4498  * see comments on pm8001_mpi_reg_resp.
4499  */
4500 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4501         u32 device_id)
4502 {
4503         struct dereg_dev_req payload;
4504         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4505         int ret;
4506         struct inbound_queue_table *circularQ;
4507
4508         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4509         memset(&payload, 0, sizeof(payload));
4510         payload.tag = cpu_to_le32(1);
4511         payload.device_id = cpu_to_le32(device_id);
4512         pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4513                    device_id);
4514         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4515                         sizeof(payload), 0);
4516         return ret;
4517 }
4518
4519 /**
4520  * pm8001_chip_phy_ctl_req - support the local phy operation
4521  * @pm8001_ha: our hba card information.
4522  * @phyId: the phy id which we wanted to operate
4523  * @phy_op: the phy operation to request
4524  */
4525 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4526         u32 phyId, u32 phy_op)
4527 {
4528         struct local_phy_ctl_req payload;
4529         struct inbound_queue_table *circularQ;
4530         int ret;
4531         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4532         memset(&payload, 0, sizeof(payload));
4533         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4534         payload.tag = cpu_to_le32(1);
4535         payload.phyop_phyid =
4536                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4537         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4538                         sizeof(payload), 0);
4539         return ret;
4540 }
4541
4542 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4543 {
4544 #ifdef PM8001_USE_MSIX
4545         return 1;
4546 #else
4547         u32 value;
4548
4549         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4550         if (value)
4551                 return 1;
4552         return 0;
4553 #endif
4554 }
4555
4556 /**
4557  * pm8001_chip_isr - PM8001 isr handler.
4558  * @pm8001_ha: our hba card information.
4559  * @vec: IRQ number
4560  */
4561 static irqreturn_t
4562 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4563 {
4564         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4565         pm8001_dbg(pm8001_ha, DEVIO,
4566                    "irq vec %d, ODMR:0x%x\n",
4567                    vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4568         process_oq(pm8001_ha, vec);
4569         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4570         return IRQ_HANDLED;
4571 }
4572
4573 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4574         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4575 {
4576         struct task_abort_req task_abort;
4577         struct inbound_queue_table *circularQ;
4578         int ret;
4579         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4580         memset(&task_abort, 0, sizeof(task_abort));
4581         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4582                 task_abort.abort_all = 0;
4583                 task_abort.device_id = cpu_to_le32(dev_id);
4584                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4585                 task_abort.tag = cpu_to_le32(cmd_tag);
4586         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4587                 task_abort.abort_all = cpu_to_le32(1);
4588                 task_abort.device_id = cpu_to_le32(dev_id);
4589                 task_abort.tag = cpu_to_le32(cmd_tag);
4590         }
4591         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
4592                         sizeof(task_abort), 0);
4593         return ret;
4594 }
4595
4596 /*
4597  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4598  */
4599 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4600         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4601 {
4602         u32 opc, device_id;
4603         int rc = TMF_RESP_FUNC_FAILED;
4604         pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4605                    cmd_tag, task_tag);
4606         if (pm8001_dev->dev_type == SAS_END_DEVICE)
4607                 opc = OPC_INB_SSP_ABORT;
4608         else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4609                 opc = OPC_INB_SATA_ABORT;
4610         else
4611                 opc = OPC_INB_SMP_ABORT;/* SMP */
4612         device_id = pm8001_dev->device_id;
4613         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4614                 task_tag, cmd_tag);
4615         if (rc != TMF_RESP_FUNC_COMPLETE)
4616                 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4617         return rc;
4618 }
4619
4620 /**
4621  * pm8001_chip_ssp_tm_req - built the task management command.
4622  * @pm8001_ha: our hba card information.
4623  * @ccb: the ccb information.
4624  * @tmf: task management function.
4625  */
4626 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4627         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4628 {
4629         struct sas_task *task = ccb->task;
4630         struct domain_device *dev = task->dev;
4631         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4632         u32 opc = OPC_INB_SSPINITMSTART;
4633         struct inbound_queue_table *circularQ;
4634         struct ssp_ini_tm_start_req sspTMCmd;
4635         int ret;
4636
4637         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4638         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4639         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4640         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4641         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4642         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4643         if (pm8001_ha->chip_id != chip_8001)
4644                 sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4645         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4646         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd,
4647                         sizeof(sspTMCmd), 0);
4648         return ret;
4649 }
4650
4651 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4652         void *payload)
4653 {
4654         u32 opc = OPC_INB_GET_NVMD_DATA;
4655         u32 nvmd_type;
4656         int rc;
4657         u32 tag;
4658         struct pm8001_ccb_info *ccb;
4659         struct inbound_queue_table *circularQ;
4660         struct get_nvm_data_req nvmd_req;
4661         struct fw_control_ex *fw_control_context;
4662         struct pm8001_ioctl_payload *ioctl_payload = payload;
4663
4664         nvmd_type = ioctl_payload->minor_function;
4665         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4666         if (!fw_control_context)
4667                 return -ENOMEM;
4668         fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4669         fw_control_context->len = ioctl_payload->rd_length;
4670         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4671         memset(&nvmd_req, 0, sizeof(nvmd_req));
4672         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4673         if (rc) {
4674                 kfree(fw_control_context);
4675                 return rc;
4676         }
4677         ccb = &pm8001_ha->ccb_info[tag];
4678         ccb->ccb_tag = tag;
4679         ccb->fw_control_context = fw_control_context;
4680         nvmd_req.tag = cpu_to_le32(tag);
4681
4682         switch (nvmd_type) {
4683         case TWI_DEVICE: {
4684                 u32 twi_addr, twi_page_size;
4685                 twi_addr = 0xa8;
4686                 twi_page_size = 2;
4687
4688                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4689                         twi_page_size << 8 | TWI_DEVICE);
4690                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4691                 nvmd_req.resp_addr_hi =
4692                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4693                 nvmd_req.resp_addr_lo =
4694                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4695                 break;
4696         }
4697         case C_SEEPROM: {
4698                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4699                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4700                 nvmd_req.resp_addr_hi =
4701                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4702                 nvmd_req.resp_addr_lo =
4703                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4704                 break;
4705         }
4706         case VPD_FLASH: {
4707                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4708                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4709                 nvmd_req.resp_addr_hi =
4710                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4711                 nvmd_req.resp_addr_lo =
4712                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4713                 break;
4714         }
4715         case EXPAN_ROM: {
4716                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4717                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4718                 nvmd_req.resp_addr_hi =
4719                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4720                 nvmd_req.resp_addr_lo =
4721                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4722                 break;
4723         }
4724         case IOP_RDUMP: {
4725                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4726                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4727                 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4728                 nvmd_req.resp_addr_hi =
4729                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4730                 nvmd_req.resp_addr_lo =
4731                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4732                 break;
4733         }
4734         default:
4735                 break;
4736         }
4737         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4738                         sizeof(nvmd_req), 0);
4739         if (rc) {
4740                 kfree(fw_control_context);
4741                 pm8001_tag_free(pm8001_ha, tag);
4742         }
4743         return rc;
4744 }
4745
4746 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4747         void *payload)
4748 {
4749         u32 opc = OPC_INB_SET_NVMD_DATA;
4750         u32 nvmd_type;
4751         int rc;
4752         u32 tag;
4753         struct pm8001_ccb_info *ccb;
4754         struct inbound_queue_table *circularQ;
4755         struct set_nvm_data_req nvmd_req;
4756         struct fw_control_ex *fw_control_context;
4757         struct pm8001_ioctl_payload *ioctl_payload = payload;
4758
4759         nvmd_type = ioctl_payload->minor_function;
4760         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4761         if (!fw_control_context)
4762                 return -ENOMEM;
4763         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4764         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4765                 &ioctl_payload->func_specific,
4766                 ioctl_payload->wr_length);
4767         memset(&nvmd_req, 0, sizeof(nvmd_req));
4768         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4769         if (rc) {
4770                 kfree(fw_control_context);
4771                 return -EBUSY;
4772         }
4773         ccb = &pm8001_ha->ccb_info[tag];
4774         ccb->fw_control_context = fw_control_context;
4775         ccb->ccb_tag = tag;
4776         nvmd_req.tag = cpu_to_le32(tag);
4777         switch (nvmd_type) {
4778         case TWI_DEVICE: {
4779                 u32 twi_addr, twi_page_size;
4780                 twi_addr = 0xa8;
4781                 twi_page_size = 2;
4782                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4783                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4784                         twi_page_size << 8 | TWI_DEVICE);
4785                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4786                 nvmd_req.resp_addr_hi =
4787                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4788                 nvmd_req.resp_addr_lo =
4789                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4790                 break;
4791         }
4792         case C_SEEPROM:
4793                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4794                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4795                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4796                 nvmd_req.resp_addr_hi =
4797                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4798                 nvmd_req.resp_addr_lo =
4799                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4800                 break;
4801         case VPD_FLASH:
4802                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4803                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4804                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4805                 nvmd_req.resp_addr_hi =
4806                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4807                 nvmd_req.resp_addr_lo =
4808                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4809                 break;
4810         case EXPAN_ROM:
4811                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4812                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4813                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4814                 nvmd_req.resp_addr_hi =
4815                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4816                 nvmd_req.resp_addr_lo =
4817                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4818                 break;
4819         default:
4820                 break;
4821         }
4822         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4823                         sizeof(nvmd_req), 0);
4824         if (rc) {
4825                 kfree(fw_control_context);
4826                 pm8001_tag_free(pm8001_ha, tag);
4827         }
4828         return rc;
4829 }
4830
4831 /**
4832  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4833  * @pm8001_ha: our hba card information.
4834  * @fw_flash_updata_info: firmware flash update param
4835  * @tag: Tag to apply to the payload
4836  */
4837 int
4838 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4839         void *fw_flash_updata_info, u32 tag)
4840 {
4841         struct fw_flash_Update_req payload;
4842         struct fw_flash_updata_info *info;
4843         struct inbound_queue_table *circularQ;
4844         int ret;
4845         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4846
4847         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4848         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4849         info = fw_flash_updata_info;
4850         payload.tag = cpu_to_le32(tag);
4851         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4852         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4853         payload.total_image_len = cpu_to_le32(info->total_image_len);
4854         payload.len = info->sgl.im_len.len ;
4855         payload.sgl_addr_lo =
4856                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4857         payload.sgl_addr_hi =
4858                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4859         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4860                         sizeof(payload), 0);
4861         return ret;
4862 }
4863
4864 int
4865 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4866         void *payload)
4867 {
4868         struct fw_flash_updata_info flash_update_info;
4869         struct fw_control_info *fw_control;
4870         struct fw_control_ex *fw_control_context;
4871         int rc;
4872         u32 tag;
4873         struct pm8001_ccb_info *ccb;
4874         void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4875         dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4876         struct pm8001_ioctl_payload *ioctl_payload = payload;
4877
4878         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4879         if (!fw_control_context)
4880                 return -ENOMEM;
4881         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4882         pm8001_dbg(pm8001_ha, DEVIO,
4883                    "dma fw_control context input length :%x\n",
4884                    fw_control->len);
4885         memcpy(buffer, fw_control->buffer, fw_control->len);
4886         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4887         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4888         flash_update_info.sgl.im_len.e = 0;
4889         flash_update_info.cur_image_offset = fw_control->offset;
4890         flash_update_info.cur_image_len = fw_control->len;
4891         flash_update_info.total_image_len = fw_control->size;
4892         fw_control_context->fw_control = fw_control;
4893         fw_control_context->virtAddr = buffer;
4894         fw_control_context->phys_addr = phys_addr;
4895         fw_control_context->len = fw_control->len;
4896         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4897         if (rc) {
4898                 kfree(fw_control_context);
4899                 return -EBUSY;
4900         }
4901         ccb = &pm8001_ha->ccb_info[tag];
4902         ccb->fw_control_context = fw_control_context;
4903         ccb->ccb_tag = tag;
4904         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4905                 tag);
4906         if (rc) {
4907                 kfree(fw_control_context);
4908                 pm8001_tag_free(pm8001_ha, tag);
4909         }
4910
4911         return rc;
4912 }
4913
4914 ssize_t
4915 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4916 {
4917         u32 value, rem, offset = 0, bar = 0;
4918         u32 index, work_offset, dw_length;
4919         u32 shift_value, gsm_base, gsm_dump_offset;
4920         char *direct_data;
4921         struct Scsi_Host *shost = class_to_shost(cdev);
4922         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4923         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4924
4925         direct_data = buf;
4926         gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4927
4928         /* check max is 1 Mbytes */
4929         if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4930                 ((gsm_dump_offset + length) > 0x1000000))
4931                         return -EINVAL;
4932
4933         if (pm8001_ha->chip_id == chip_8001)
4934                 bar = 2;
4935         else
4936                 bar = 1;
4937
4938         work_offset = gsm_dump_offset & 0xFFFF0000;
4939         offset = gsm_dump_offset & 0x0000FFFF;
4940         gsm_dump_offset = work_offset;
4941         /* adjust length to dword boundary */
4942         rem = length & 3;
4943         dw_length = length >> 2;
4944
4945         for (index = 0; index < dw_length; index++) {
4946                 if ((work_offset + offset) & 0xFFFF0000) {
4947                         if (pm8001_ha->chip_id == chip_8001)
4948                                 shift_value = ((gsm_dump_offset + offset) &
4949                                                 SHIFT_REG_64K_MASK);
4950                         else
4951                                 shift_value = (((gsm_dump_offset + offset) &
4952                                                 SHIFT_REG_64K_MASK) >>
4953                                                 SHIFT_REG_BIT_SHIFT);
4954
4955                         if (pm8001_ha->chip_id == chip_8001) {
4956                                 gsm_base = GSM_BASE;
4957                                 if (-1 == pm8001_bar4_shift(pm8001_ha,
4958                                                 (gsm_base + shift_value)))
4959                                         return -EIO;
4960                         } else {
4961                                 gsm_base = 0;
4962                                 if (-1 == pm80xx_bar4_shift(pm8001_ha,
4963                                                 (gsm_base + shift_value)))
4964                                         return -EIO;
4965                         }
4966                         gsm_dump_offset = (gsm_dump_offset + offset) &
4967                                                 0xFFFF0000;
4968                         work_offset = 0;
4969                         offset = offset & 0x0000FFFF;
4970                 }
4971                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4972                                                 0x0000FFFF);
4973                 direct_data += sprintf(direct_data, "%08x ", value);
4974                 offset += 4;
4975         }
4976         if (rem != 0) {
4977                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4978                                                 0x0000FFFF);
4979                 /* xfr for non_dw */
4980                 direct_data += sprintf(direct_data, "%08x ", value);
4981         }
4982         /* Shift back to BAR4 original address */
4983         if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4984                         return -EIO;
4985         pm8001_ha->fatal_forensic_shift_offset += 1024;
4986
4987         if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4988                 pm8001_ha->fatal_forensic_shift_offset = 0;
4989         return direct_data - buf;
4990 }
4991
4992 int
4993 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4994         struct pm8001_device *pm8001_dev, u32 state)
4995 {
4996         struct set_dev_state_req payload;
4997         struct inbound_queue_table *circularQ;
4998         struct pm8001_ccb_info *ccb;
4999         int rc;
5000         u32 tag;
5001         u32 opc = OPC_INB_SET_DEVICE_STATE;
5002         memset(&payload, 0, sizeof(payload));
5003         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5004         if (rc)
5005                 return -1;
5006         ccb = &pm8001_ha->ccb_info[tag];
5007         ccb->ccb_tag = tag;
5008         ccb->device = pm8001_dev;
5009         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5010         payload.tag = cpu_to_le32(tag);
5011         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
5012         payload.nds = cpu_to_le32(state);
5013         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5014                         sizeof(payload), 0);
5015         if (rc)
5016                 pm8001_tag_free(pm8001_ha, tag);
5017
5018         return rc;
5019
5020 }
5021
5022 static int
5023 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5024 {
5025         struct sas_re_initialization_req payload;
5026         struct inbound_queue_table *circularQ;
5027         struct pm8001_ccb_info *ccb;
5028         int rc;
5029         u32 tag;
5030         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5031         memset(&payload, 0, sizeof(payload));
5032         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5033         if (rc)
5034                 return -ENOMEM;
5035         ccb = &pm8001_ha->ccb_info[tag];
5036         ccb->ccb_tag = tag;
5037         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5038         payload.tag = cpu_to_le32(tag);
5039         payload.SSAHOLT = cpu_to_le32(0xd << 25);
5040         payload.sata_hol_tmo = cpu_to_le32(80);
5041         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5042         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5043                         sizeof(payload), 0);
5044         if (rc)
5045                 pm8001_tag_free(pm8001_ha, tag);
5046         return rc;
5047
5048 }
5049
5050 const struct pm8001_dispatch pm8001_8001_dispatch = {
5051         .name                   = "pmc8001",
5052         .chip_init              = pm8001_chip_init,
5053         .chip_soft_rst          = pm8001_chip_soft_rst,
5054         .chip_rst               = pm8001_hw_chip_rst,
5055         .chip_iounmap           = pm8001_chip_iounmap,
5056         .isr                    = pm8001_chip_isr,
5057         .is_our_interrupt       = pm8001_chip_is_our_interrupt,
5058         .isr_process_oq         = process_oq,
5059         .interrupt_enable       = pm8001_chip_interrupt_enable,
5060         .interrupt_disable      = pm8001_chip_interrupt_disable,
5061         .make_prd               = pm8001_chip_make_sg,
5062         .smp_req                = pm8001_chip_smp_req,
5063         .ssp_io_req             = pm8001_chip_ssp_io_req,
5064         .sata_req               = pm8001_chip_sata_req,
5065         .phy_start_req          = pm8001_chip_phy_start_req,
5066         .phy_stop_req           = pm8001_chip_phy_stop_req,
5067         .reg_dev_req            = pm8001_chip_reg_dev_req,
5068         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5069         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
5070         .task_abort             = pm8001_chip_abort_task,
5071         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5072         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5073         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5074         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5075         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5076         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
5077         .fatal_errors           = pm80xx_fatal_errors,
5078 };