drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192         u32 ib_offset = pm8001_ha->ib_offset;
 193         u32 ob_offset = pm8001_ha->ob_offset;
 194         u32 ci_offset = pm8001_ha->ci_offset;
 195         u32 pi_offset = pm8001_ha->pi_offset;
 196
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 199         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 201         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 203                                                                          0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 205                                                                          0;
 206         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 208         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 210
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 212                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 214                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 215         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 216                 PM8001_EVENT_LOG_SIZE;
 217         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 219                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 221                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 222         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 223                 PM8001_EVENT_LOG_SIZE;
 224         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 225         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 226         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 227                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 228                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 229                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 230                         pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
 231                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 232                 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
 233                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 234                   (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
 235                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 236                         pm8001_ha->memoryMap.region[ib_offset + i].total_len;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 238                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
 239                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 240                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
 241                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 242                         pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
 243                 offsetib = i * 0x20;
 244                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 245                         get_pci_bar_index(pm8001_mr32(addressib,
 246                                 (offsetib + 0x14)));
 247                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 248                         pm8001_mr32(addressib, (offsetib + 0x18));
 249                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 250                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 251         }
 252         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 253                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 254                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 255                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 256                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
 257                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 258                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
 259                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 260                   (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
 261                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 262                         pm8001_ha->memoryMap.region[ob_offset + i].total_len;
 263                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 264                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
 265                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 266                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
 267                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 268                         0 | (10 << 16) | (i << 24);
 269                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 270                         pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
 271                 offsetob = i * 0x24;
 272                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 273                         get_pci_bar_index(pm8001_mr32(addressob,
 274                         offsetob + 0x14));
 275                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 276                         pm8001_mr32(addressob, (offsetob + 0x18));
 277                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 278                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 279         }
 280 }
 281
 282 /**
 283  * update_main_config_table - update the main default table to the HBA.
 284  * @pm8001_ha: our hba card information
 285  */
 286 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 287 {
 288         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 289         pm8001_mw32(address, 0x24,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 291         pm8001_mw32(address, 0x28,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 293         pm8001_mw32(address, 0x2C,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 295         pm8001_mw32(address, 0x30,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 297         pm8001_mw32(address, 0x34,
 298                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 299         pm8001_mw32(address, 0x38,
 300                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 301                                         outbound_tgt_ITNexus_event_pid0_3);
 302         pm8001_mw32(address, 0x3C,
 303                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 304                                         outbound_tgt_ITNexus_event_pid4_7);
 305         pm8001_mw32(address, 0x40,
 306                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 307                                         outbound_tgt_ssp_event_pid0_3);
 308         pm8001_mw32(address, 0x44,
 309                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 310                                         outbound_tgt_ssp_event_pid4_7);
 311         pm8001_mw32(address, 0x48,
 312                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 313                                         outbound_tgt_smp_event_pid0_3);
 314         pm8001_mw32(address, 0x4C,
 315                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 316                                         outbound_tgt_smp_event_pid4_7);
 317         pm8001_mw32(address, 0x50,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 319         pm8001_mw32(address, 0x54,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 321         pm8001_mw32(address, 0x58,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 323         pm8001_mw32(address, 0x5C,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 325         pm8001_mw32(address, 0x60,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 327         pm8001_mw32(address, 0x64,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 329         pm8001_mw32(address, 0x68,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 331         pm8001_mw32(address, 0x6C,
 332                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 333         pm8001_mw32(address, 0x70,
 334                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 335 }
 336
 337 /**
 338  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 339  * @pm8001_ha: our hba card information
 340  * @number: entry in the queue
 341  */
 342 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 343                                      int number)
 344 {
 345         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 346         u16 offset = number * 0x20;
 347         pm8001_mw32(address, offset + 0x00,
 348                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 349         pm8001_mw32(address, offset + 0x04,
 350                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 351         pm8001_mw32(address, offset + 0x08,
 352                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 353         pm8001_mw32(address, offset + 0x0C,
 354                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 355         pm8001_mw32(address, offset + 0x10,
 356                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 357 }
 358
 359 /**
 360  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 361  * @pm8001_ha: our hba card information
 362  * @number: entry in the queue
 363  */
 364 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 365                                       int number)
 366 {
 367         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 368         u16 offset = number * 0x24;
 369         pm8001_mw32(address, offset + 0x00,
 370                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 371         pm8001_mw32(address, offset + 0x04,
 372                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 373         pm8001_mw32(address, offset + 0x08,
 374                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 375         pm8001_mw32(address, offset + 0x0C,
 376                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 377         pm8001_mw32(address, offset + 0x10,
 378                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 379         pm8001_mw32(address, offset + 0x1C,
 380                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 381 }
 382
 383 /**
 384  * pm8001_bar4_shift - function is called to shift BAR base address
 385  * @pm8001_ha : our hba card infomation
 386  * @shiftValue : shifting value in memory bar.
 387  */
 388 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 389 {
 390         u32 regVal;
 391         unsigned long start;
 392
 393         /* program the inbound AXI translation Lower Address */
 394         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 395
 396         /* confirm the setting is written */
 397         start = jiffies + HZ; /* 1 sec */
 398         do {
 399                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 400         } while ((regVal != shiftValue) && time_before(jiffies, start));
 401
 402         if (regVal != shiftValue) {
 403                 pm8001_dbg(pm8001_ha, INIT,
 404                            "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
 405                            regVal);
 406                 return -1;
 407         }
 408         return 0;
 409 }
 410
 411 /**
 412  * mpi_set_phys_g3_with_ssc
 413  * @pm8001_ha: our hba card information
 414  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 415  */
 416 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 417                                      u32 SSCbit)
 418 {
 419         u32 value, offset, i;
 420         unsigned long flags;
 421
 422 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 423 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 424 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 425 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 426 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 427 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 428 #define SNW3_PHY_CAPABILITIES_PARITY 31
 429
 430    /*
 431     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 432     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 433     */
 434         spin_lock_irqsave(&pm8001_ha->lock, flags);
 435         if (-1 == pm8001_bar4_shift(pm8001_ha,
 436                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 437                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 438                 return;
 439         }
 440
 441         for (i = 0; i < 4; i++) {
 442                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 443                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 444         }
 445         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 446         if (-1 == pm8001_bar4_shift(pm8001_ha,
 447                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 448                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 449                 return;
 450         }
 451         for (i = 4; i < 8; i++) {
 452                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 453                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 454         }
 455         /*************************************************************
 456         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 457         Device MABC SMOD0 Controls
 458         Address: (via MEMBASE-III):
 459         Using shifted destination address 0x0_0000: with Offset 0xD8
 460
 461         31:28 R/W Reserved Do not change
 462         27:24 R/W SAS_SMOD_SPRDUP 0000
 463         23:20 R/W SAS_SMOD_SPRDDN 0000
 464         19:0  R/W  Reserved Do not change
 465         Upon power-up this register will read as 0x8990c016,
 466         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 467         so that the written value will be 0x8090c016.
 468         This will ensure only down-spreading SSC is enabled on the SPC.
 469         *************************************************************/
 470         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 471         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 472
 473         /*set the shifted destination address to 0x0 to avoid error operation */
 474         pm8001_bar4_shift(pm8001_ha, 0x0);
 475         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 476         return;
 477 }
 478
 479 /**
 480  * mpi_set_open_retry_interval_reg
 481  * @pm8001_ha: our hba card information
 482  * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 483  */
 484 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 485                                             u32 interval)
 486 {
 487         u32 offset;
 488         u32 value;
 489         u32 i;
 490         unsigned long flags;
 491
 492 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 493 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 494 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 495 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 496 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 497
 498         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 499         spin_lock_irqsave(&pm8001_ha->lock, flags);
 500         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 501         if (-1 == pm8001_bar4_shift(pm8001_ha,
 502                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 503                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 504                 return;
 505         }
 506         for (i = 0; i < 4; i++) {
 507                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 508                 pm8001_cw32(pm8001_ha, 2, offset, value);
 509         }
 510
 511         if (-1 == pm8001_bar4_shift(pm8001_ha,
 512                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 513                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 514                 return;
 515         }
 516         for (i = 4; i < 8; i++) {
 517                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 518                 pm8001_cw32(pm8001_ha, 2, offset, value);
 519         }
 520         /*set the shifted destination address to 0x0 to avoid error operation */
 521         pm8001_bar4_shift(pm8001_ha, 0x0);
 522         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 523         return;
 524 }
 525
 526 /**
 527  * mpi_init_check - check firmware initialization status.
 528  * @pm8001_ha: our hba card information
 529  */
 530 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 531 {
 532         u32 max_wait_count;
 533         u32 value;
 534         u32 gst_len_mpistate;
 535         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 536         table is updated */
 537         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 538         /* wait until Inbound DoorBell Clear Register toggled */
 539         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 540         do {
 541                 udelay(1);
 542                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 543                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 544         } while ((value != 0) && (--max_wait_count));
 545
 546         if (!max_wait_count)
 547                 return -1;
 548         /* check the MPI-State for initialization */
 549         gst_len_mpistate =
 550                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 551                 GST_GSTLEN_MPIS_OFFSET);
 552         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 553                 return -1;
 554         /* check MPI Initialization error */
 555         gst_len_mpistate = gst_len_mpistate >> 16;
 556         if (0x0000 != gst_len_mpistate)
 557                 return -1;
 558         return 0;
 559 }
 560
 561 /**
 562  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 563  * @pm8001_ha: our hba card information
 564  */
 565 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 566 {
 567         u32 value, value1;
 568         u32 max_wait_count;
 569         /* check error state */
 570         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 571         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 572         /* check AAP error */
 573         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 574                 /* error state */
 575                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 576                 return -1;
 577         }
 578
 579         /* check IOP error */
 580         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 581                 /* error state */
 582                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 583                 return -1;
 584         }
 585
 586         /* bit 4-31 of scratch pad1 should be zeros if it is not
 587         in error state*/
 588         if (value & SCRATCH_PAD1_STATE_MASK) {
 589                 /* error case */
 590                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 591                 return -1;
 592         }
 593
 594         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 595         in error state */
 596         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 597                 /* error case */
 598                 return -1;
 599         }
 600
 601         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 602
 603         /* wait until scratch pad 1 and 2 registers in ready state  */
 604         do {
 605                 udelay(1);
 606                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 607                         & SCRATCH_PAD1_RDY;
 608                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 609                         & SCRATCH_PAD2_RDY;
 610                 if ((--max_wait_count) == 0)
 611                         return -1;
 612         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 613         return 0;
 614 }
 615
 616 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 617 {
 618         void __iomem *base_addr;
 619         u32     value;
 620         u32     offset;
 621         u32     pcibar;
 622         u32     pcilogic;
 623
 624         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 625         offset = value & 0x03FFFFFF;
 626         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
 627         pcilogic = (value & 0xFC000000) >> 26;
 628         pcibar = get_pci_bar_index(pcilogic);
 629         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
 630         pm8001_ha->main_cfg_tbl_addr = base_addr =
 631                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 632         pm8001_ha->general_stat_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 634         pm8001_ha->inbnd_q_tbl_addr =
 635                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 636         pm8001_ha->outbnd_q_tbl_addr =
 637                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 638 }
 639
 640 /**
 641  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 642  * @pm8001_ha: our hba card information
 643  */
 644 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 645 {
 646         u32 i = 0;
 647         u16 deviceid;
 648         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 649         /* 8081 controllers need BAR shift to access MPI space
 650         * as this is shared with BIOS data */
 651         if (deviceid == 0x8081 || deviceid == 0x0042) {
 652                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 653                         pm8001_dbg(pm8001_ha, FAIL,
 654                                    "Shift Bar4 to 0x%x failed\n",
 655                                    GSM_SM_BASE);
 656                         return -1;
 657                 }
 658         }
 659         /* check the firmware status */
 660         if (-1 == check_fw_ready(pm8001_ha)) {
 661                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
 662                 return -EBUSY;
 663         }
 664
 665         /* Initialize pci space address eg: mpi offset */
 666         init_pci_device_addresses(pm8001_ha);
 667         init_default_table_values(pm8001_ha);
 668         read_main_config_table(pm8001_ha);
 669         read_general_status_table(pm8001_ha);
 670         read_inbnd_queue_table(pm8001_ha);
 671         read_outbnd_queue_table(pm8001_ha);
 672         /* update main config table ,inbound table and outbound table */
 673         update_main_config_table(pm8001_ha);
 674         for (i = 0; i < pm8001_ha->max_q_num; i++)
 675                 update_inbnd_queue_table(pm8001_ha, i);
 676         for (i = 0; i < pm8001_ha->max_q_num; i++)
 677                 update_outbnd_queue_table(pm8001_ha, i);
 678         /* 8081 controller donot require these operations */
 679         if (deviceid != 0x8081 && deviceid != 0x0042) {
 680                 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 681                 /* 7->130ms, 34->500ms, 119->1.5s */
 682                 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 683         }
 684         /* notify firmware update finished and check initialization status */
 685         if (0 == mpi_init_check(pm8001_ha)) {
 686                 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
 687         } else
 688                 return -EBUSY;
 689         /*This register is a 16-bit timer with a resolution of 1us. This is the
 690         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 691         Zero is not a valid value. A value of 1 in the register will cause the
 692         interrupts to be normal. A value greater than 1 will cause coalescing
 693         delays.*/
 694         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 695         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 696         return 0;
 697 }
 698
 699 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 700 {
 701         u32 max_wait_count;
 702         u32 value;
 703         u32 gst_len_mpistate;
 704         u16 deviceid;
 705         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 706         if (deviceid == 0x8081 || deviceid == 0x0042) {
 707                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 708                         pm8001_dbg(pm8001_ha, FAIL,
 709                                    "Shift Bar4 to 0x%x failed\n",
 710                                    GSM_SM_BASE);
 711                         return -1;
 712                 }
 713         }
 714         init_pci_device_addresses(pm8001_ha);
 715         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 716         table is stop */
 717         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 718
 719         /* wait until Inbound DoorBell Clear Register toggled */
 720         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 721         do {
 722                 udelay(1);
 723                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 724                 value &= SPC_MSGU_CFG_TABLE_RESET;
 725         } while ((value != 0) && (--max_wait_count));
 726
 727         if (!max_wait_count) {
 728                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
 729                            value);
 730                 return -1;
 731         }
 732
 733         /* check the MPI-State for termination in progress */
 734         /* wait until Inbound DoorBell Clear Register toggled */
 735         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 736         do {
 737                 udelay(1);
 738                 gst_len_mpistate =
 739                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 740                         GST_GSTLEN_MPIS_OFFSET);
 741                 if (GST_MPI_STATE_UNINIT ==
 742                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 743                         break;
 744         } while (--max_wait_count);
 745         if (!max_wait_count) {
 746                 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
 747                            gst_len_mpistate & GST_MPI_STATE_MASK);
 748                 return -1;
 749         }
 750         return 0;
 751 }
 752
 753 /**
 754  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 755  * @pm8001_ha: our hba card information
 756  */
 757 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 758 {
 759         u32 regVal, regVal1, regVal2;
 760         if (mpi_uninit_check(pm8001_ha) != 0) {
 761                 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
 762                 return -1;
 763         }
 764         /* read the scratch pad 2 register bit 2 */
 765         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 766                 & SCRATCH_PAD2_FWRDY_RST;
 767         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 768                 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
 769         } else {
 770                 unsigned long flags;
 771                 /* Trigger NMI twice via RB6 */
 772                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 773                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 774                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 775                         pm8001_dbg(pm8001_ha, FAIL,
 776                                    "Shift Bar4 to 0x%x failed\n",
 777                                    RB6_ACCESS_REG);
 778                         return -1;
 779                 }
 780                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 781                         RB6_MAGIC_NUMBER_RST);
 782                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 783                 /* wait for 100 ms */
 784                 mdelay(100);
 785                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 786                         SCRATCH_PAD2_FWRDY_RST;
 787                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 788                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 789                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 790                         pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 791                                    regVal1, regVal2);
 792                         pm8001_dbg(pm8001_ha, FAIL,
 793                                    "SCRATCH_PAD0 value = 0x%x\n",
 794                                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
 795                         pm8001_dbg(pm8001_ha, FAIL,
 796                                    "SCRATCH_PAD3 value = 0x%x\n",
 797                                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
 798                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 799                         return -1;
 800                 }
 801                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 802         }
 803         return 0;
 804 }
 805
 806 /**
 807  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 808  * the FW register status to the originated status.
 809  * @pm8001_ha: our hba card information
 810  */
 811 static int
 812 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 813 {
 814         u32     regVal, toggleVal;
 815         u32     max_wait_count;
 816         u32     regVal1, regVal2, regVal3;
 817         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 818         unsigned long flags;
 819
 820         /* step1: Check FW is ready for soft reset */
 821         if (soft_reset_ready_check(pm8001_ha) != 0) {
 822                 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
 823                 return -1;
 824         }
 825
 826         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 827         value to clear */
 828         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 829         spin_lock_irqsave(&pm8001_ha->lock, flags);
 830         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 831                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 832                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 833                            MBIC_AAP1_ADDR_BASE);
 834                 return -1;
 835         }
 836         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 837         pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
 838                    regVal);
 839         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 840         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 841         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 842                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 843                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 844                            MBIC_IOP_ADDR_BASE);
 845                 return -1;
 846         }
 847         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 848         pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
 849                    regVal);
 850         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 851
 852         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 853         pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
 854                    regVal);
 855         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 856
 857         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 858         pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt  = 0x%x\n",
 859                    regVal);
 860         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 861
 862         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 863         pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
 864                    regVal);
 865         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 866
 867         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 868         pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
 869         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 870
 871         /* read the scratch pad 1 register bit 2 */
 872         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 873                 & SCRATCH_PAD1_RST;
 874         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 875
 876         /* set signature in host scratch pad0 register to tell SPC that the
 877         host performs the soft reset */
 878         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 879
 880         /* read required registers for confirmming */
 881         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 882         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 883                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 884                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 885                            GSM_ADDR_BASE);
 886                 return -1;
 887         }
 888         pm8001_dbg(pm8001_ha, INIT,
 889                    "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
 890                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
 891
 892         /* step 3: host read GSM Configuration and Reset register */
 893         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 894         /* Put those bits to low */
 895         /* GSM XCBI offset = 0x70 0000
 896         0x00 Bit 13 COM_SLV_SW_RSTB 1
 897         0x00 Bit 12 QSSP_SW_RSTB 1
 898         0x00 Bit 11 RAAE_SW_RSTB 1
 899         0x00 Bit 9 RB_1_SW_RSTB 1
 900         0x00 Bit 8 SM_SW_RSTB 1
 901         */
 902         regVal &= ~(0x00003b00);
 903         /* host write GSM Configuration and Reset register */
 904         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 905         pm8001_dbg(pm8001_ha, INIT,
 906                    "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
 907                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
 908
 909         /* step 4: */
 910         /* disable GSM - Read Address Parity Check */
 911         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 912         pm8001_dbg(pm8001_ha, INIT,
 913                    "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
 914                    regVal1);
 915         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 916         pm8001_dbg(pm8001_ha, INIT,
 917                    "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
 918                    pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
 919
 920         /* disable GSM - Write Address Parity Check */
 921         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 922         pm8001_dbg(pm8001_ha, INIT,
 923                    "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
 924                    regVal2);
 925         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 926         pm8001_dbg(pm8001_ha, INIT,
 927                    "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
 928                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
 929
 930         /* disable GSM - Write Data Parity Check */
 931         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 932         pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
 933                    regVal3);
 934         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 935         pm8001_dbg(pm8001_ha, INIT,
 936                    "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
 937                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
 938
 939         /* step 5: delay 10 usec */
 940         udelay(10);
 941         /* step 5-b: set GPIO-0 output control to tristate anyway */
 942         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 943                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 944                 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
 945                            GPIO_ADDR_BASE);
 946                 return -1;
 947         }
 948         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 949         pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
 950                    regVal);
 951         /* set GPIO-0 output control to tri-state */
 952         regVal &= 0xFFFFFFFC;
 953         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 954
 955         /* Step 6: Reset the IOP and AAP1 */
 956         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 957         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 958                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 959                 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
 960                            SPC_TOP_LEVEL_ADDR_BASE);
 961                 return -1;
 962         }
 963         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 964         pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
 965                    regVal);
 966         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 967         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 968
 969         /* step 7: Reset the BDMA/OSSP */
 970         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 971         pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
 972                    regVal);
 973         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 974         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 975
 976         /* step 8: delay 10 usec */
 977         udelay(10);
 978
 979         /* step 9: bring the BDMA and OSSP out of reset */
 980         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 981         pm8001_dbg(pm8001_ha, INIT,
 982                    "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
 983                    regVal);
 984         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 985         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 986
 987         /* step 10: delay 10 usec */
 988         udelay(10);
 989
 990         /* step 11: reads and sets the GSM Configuration and Reset Register */
 991         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 992         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 993                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 994                 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
 995                            GSM_ADDR_BASE);
 996                 return -1;
 997         }
 998         pm8001_dbg(pm8001_ha, INIT,
 999                    "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1000                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1001         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1002         /* Put those bits to high */
1003         /* GSM XCBI offset = 0x70 0000
1004         0x00 Bit 13 COM_SLV_SW_RSTB 1
1005         0x00 Bit 12 QSSP_SW_RSTB 1
1006         0x00 Bit 11 RAAE_SW_RSTB 1
1007         0x00 Bit 9   RB_1_SW_RSTB 1
1008         0x00 Bit 8   SM_SW_RSTB 1
1009         */
1010         regVal |= (GSM_CONFIG_RESET_VALUE);
1011         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1012         pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1013                    pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1014
1015         /* step 12: Restore GSM - Read Address Parity Check */
1016         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1017         /* just for debugging */
1018         pm8001_dbg(pm8001_ha, INIT,
1019                    "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1020                    regVal);
1021         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1022         pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1023                    pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1024         /* Restore GSM - Write Address Parity Check */
1025         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1026         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1027         pm8001_dbg(pm8001_ha, INIT,
1028                    "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1029                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1030         /* Restore GSM - Write Data Parity Check */
1031         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1032         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1033         pm8001_dbg(pm8001_ha, INIT,
1034                    "GSM 0x700048 - Write Data Parity Check Enableis set to = 0x%x\n",
1035                    pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1036
1037         /* step 13: bring the IOP and AAP1 out of reset */
1038         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1039         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1040                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1041                 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1042                            SPC_TOP_LEVEL_ADDR_BASE);
1043                 return -1;
1044         }
1045         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1046         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1047         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1048
1049         /* step 14: delay 10 usec - Normal Mode */
1050         udelay(10);
1051         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1052         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1053                 /* step 15 (Normal Mode): wait until scratch pad1 register
1054                 bit 2 toggled */
1055                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1056                 do {
1057                         udelay(1);
1058                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1059                                 SCRATCH_PAD1_RST;
1060                 } while ((regVal != toggleVal) && (--max_wait_count));
1061
1062                 if (!max_wait_count) {
1063                         regVal = pm8001_cr32(pm8001_ha, 0,
1064                                 MSGU_SCRATCH_PAD_1);
1065                         pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1066                                    toggleVal, regVal);
1067                         pm8001_dbg(pm8001_ha, FAIL,
1068                                    "SCRATCH_PAD0 value = 0x%x\n",
1069                                    pm8001_cr32(pm8001_ha, 0,
1070                                                MSGU_SCRATCH_PAD_0));
1071                         pm8001_dbg(pm8001_ha, FAIL,
1072                                    "SCRATCH_PAD2 value = 0x%x\n",
1073                                    pm8001_cr32(pm8001_ha, 0,
1074                                                MSGU_SCRATCH_PAD_2));
1075                         pm8001_dbg(pm8001_ha, FAIL,
1076                                    "SCRATCH_PAD3 value = 0x%x\n",
1077                                    pm8001_cr32(pm8001_ha, 0,
1078                                                MSGU_SCRATCH_PAD_3));
1079                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1080                         return -1;
1081                 }
1082
1083                 /* step 16 (Normal) - Clear ODMR and ODCR */
1084                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1085                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1086
1087                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1088                 ready - 1 sec timeout */
1089                 /* Wait for the SPC Configuration Table to be ready */
1090                 if (check_fw_ready(pm8001_ha) == -1) {
1091                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1092                         /* return error if MPI Configuration Table not ready */
1093                         pm8001_dbg(pm8001_ha, INIT,
1094                                    "FW not ready SCRATCH_PAD1 = 0x%x\n",
1095                                    regVal);
1096                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1097                         /* return error if MPI Configuration Table not ready */
1098                         pm8001_dbg(pm8001_ha, INIT,
1099                                    "FW not ready SCRATCH_PAD2 = 0x%x\n",
1100                                    regVal);
1101                         pm8001_dbg(pm8001_ha, INIT,
1102                                    "SCRATCH_PAD0 value = 0x%x\n",
1103                                    pm8001_cr32(pm8001_ha, 0,
1104                                                MSGU_SCRATCH_PAD_0));
1105                         pm8001_dbg(pm8001_ha, INIT,
1106                                    "SCRATCH_PAD3 value = 0x%x\n",
1107                                    pm8001_cr32(pm8001_ha, 0,
1108                                                MSGU_SCRATCH_PAD_3));
1109                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1110                         return -1;
1111                 }
1112         }
1113         pm8001_bar4_shift(pm8001_ha, 0);
1114         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1115
1116         pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1117         return 0;
1118 }
1119
1120 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1121 {
1122         u32 i;
1123         u32 regVal;
1124         pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1125
1126         /* do SPC chip reset. */
1127         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1128         regVal &= ~(SPC_REG_RESET_DEVICE);
1129         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1130
1131         /* delay 10 usec */
1132         udelay(10);
1133
1134         /* bring chip reset out of reset */
1135         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1136         regVal |= SPC_REG_RESET_DEVICE;
1137         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1138
1139         /* delay 10 usec */
1140         udelay(10);
1141
1142         /* wait for 20 msec until the firmware gets reloaded */
1143         i = 20;
1144         do {
1145                 mdelay(1);
1146         } while ((--i) != 0);
1147
1148         pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1149 }
1150
1151 /**
1152  * pm8001_chip_iounmap - which maped when initialized.
1153  * @pm8001_ha: our hba card information
1154  */
1155 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1156 {
1157         s8 bar, logical = 0;
1158         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1159                 /*
1160                 ** logical BARs for SPC:
1161                 ** bar 0 and 1 - logical BAR0
1162                 ** bar 2 and 3 - logical BAR1
1163                 ** bar4 - logical BAR2
1164                 ** bar5 - logical BAR3
1165                 ** Skip the appropriate assignments:
1166                 */
1167                 if ((bar == 1) || (bar == 3))
1168                         continue;
1169                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1170                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1171                         logical++;
1172                 }
1173         }
1174 }
1175
1176 #ifndef PM8001_USE_MSIX
1177 /**
1178  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1179  * @pm8001_ha: our hba card information
1180  */
1181 static void
1182 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1183 {
1184         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1185         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1186 }
1187
1188  /**
1189   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1190   * @pm8001_ha: our hba card information
1191   */
1192 static void
1193 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1194 {
1195         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1196 }
1197
1198 #else
1199
1200 /**
1201  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1202  * @pm8001_ha: our hba card information
1203  * @int_vec_idx: interrupt number to enable
1204  */
1205 static void
1206 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1207         u32 int_vec_idx)
1208 {
1209         u32 msi_index;
1210         u32 value;
1211         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1212         msi_index += MSIX_TABLE_BASE;
1213         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1214         value = (1 << int_vec_idx);
1215         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1216
1217 }
1218
1219 /**
1220  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1221  * @pm8001_ha: our hba card information
1222  * @int_vec_idx: interrupt number to disable
1223  */
1224 static void
1225 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1226         u32 int_vec_idx)
1227 {
1228         u32 msi_index;
1229         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1230         msi_index += MSIX_TABLE_BASE;
1231         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1232 }
1233 #endif
1234
1235 /**
1236  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1237  * @pm8001_ha: our hba card information
1238  * @vec: unused
1239  */
1240 static void
1241 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1242 {
1243 #ifdef PM8001_USE_MSIX
1244         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1245 #else
1246         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1247 #endif
1248 }
1249
1250 /**
1251  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1252  * @pm8001_ha: our hba card information
1253  * @vec: unused
1254  */
1255 static void
1256 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1257 {
1258 #ifdef PM8001_USE_MSIX
1259         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1260 #else
1261         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1262 #endif
1263 }
1264
1265 /**
1266  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1267  * inbound queue.
1268  * @circularQ: the inbound queue  we want to transfer to HBA.
1269  * @messageSize: the message size of this transfer, normally it is 64 bytes
1270  * @messagePtr: the pointer to message.
1271  */
1272 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1273                             u16 messageSize, void **messagePtr)
1274 {
1275         u32 offset, consumer_index;
1276         struct mpi_msg_hdr *msgHeader;
1277         u8 bcCount = 1; /* only support single buffer */
1278
1279         /* Checks is the requested message size can be allocated in this queue*/
1280         if (messageSize > IOMB_SIZE_SPCV) {
1281                 *messagePtr = NULL;
1282                 return -1;
1283         }
1284
1285         /* Stores the new consumer index */
1286         consumer_index = pm8001_read_32(circularQ->ci_virt);
1287         circularQ->consumer_index = cpu_to_le32(consumer_index);
1288         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1289                 le32_to_cpu(circularQ->consumer_index)) {
1290                 *messagePtr = NULL;
1291                 return -1;
1292         }
1293         /* get memory IOMB buffer address */
1294         offset = circularQ->producer_idx * messageSize;
1295         /* increment to next bcCount element */
1296         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1297                                 % PM8001_MPI_QUEUE;
1298         /* Adds that distance to the base of the region virtual address plus
1299         the message header size*/
1300         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1301         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1302         return 0;
1303 }
1304
1305 /**
1306  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1307  * FW to tell the fw to get this message from IOMB.
1308  * @pm8001_ha: our hba card information
1309  * @circularQ: the inbound queue we want to transfer to HBA.
1310  * @opCode: the operation code represents commands which LLDD and fw recognized.
1311  * @payload: the command payload of each operation command.
1312  * @nb: size in bytes of the command payload
1313  * @responseQueue: queue to interrupt on w/ command response (if any)
1314  */
1315 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1316                          struct inbound_queue_table *circularQ,
1317                          u32 opCode, void *payload, size_t nb,
1318                          u32 responseQueue)
1319 {
1320         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1321         void *pMessage;
1322         unsigned long flags;
1323         int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
1324         int rv = -1;
1325
1326         if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1327                 return -EINVAL;
1328
1329         spin_lock_irqsave(&circularQ->iq_lock, flags);
1330         rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1331                         &pMessage);
1332         if (rv < 0) {
1333                 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1334                 rv = -ENOMEM;
1335                 goto done;
1336         }
1337
1338         if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1339                 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1340         memcpy(pMessage, payload, nb);
1341         if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1342                 memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1343                                 (nb + sizeof(struct mpi_msg_hdr)));
1344
1345         /*Build the header*/
1346         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1347                 | ((responseQueue & 0x3F) << 16)
1348                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1349
1350         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1351         /*Update the PI to the firmware*/
1352         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1353                 circularQ->pi_offset, circularQ->producer_idx);
1354         pm8001_dbg(pm8001_ha, DEVIO,
1355                    "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1356                    responseQueue, opCode, circularQ->producer_idx,
1357                    circularQ->consumer_index);
1358 done:
1359         spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1360         return rv;
1361 }
1362
1363 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1364                             struct outbound_queue_table *circularQ, u8 bc)
1365 {
1366         u32 producer_index;
1367         struct mpi_msg_hdr *msgHeader;
1368         struct mpi_msg_hdr *pOutBoundMsgHeader;
1369
1370         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1371         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1372                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1373         if (pOutBoundMsgHeader != msgHeader) {
1374                 pm8001_dbg(pm8001_ha, FAIL,
1375                            "consumer_idx = %d msgHeader = %p\n",
1376                            circularQ->consumer_idx, msgHeader);
1377
1378                 /* Update the producer index from SPC */
1379                 producer_index = pm8001_read_32(circularQ->pi_virt);
1380                 circularQ->producer_index = cpu_to_le32(producer_index);
1381                 pm8001_dbg(pm8001_ha, FAIL,
1382                            "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1383                            circularQ->consumer_idx,
1384                            circularQ->producer_index, msgHeader);
1385                 return 0;
1386         }
1387         /* free the circular queue buffer elements associated with the message*/
1388         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1389                                 % PM8001_MPI_QUEUE;
1390         /* update the CI of outbound queue */
1391         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1392                 circularQ->consumer_idx);
1393         /* Update the producer index from SPC*/
1394         producer_index = pm8001_read_32(circularQ->pi_virt);
1395         circularQ->producer_index = cpu_to_le32(producer_index);
1396         pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1397                    circularQ->consumer_idx, circularQ->producer_index);
1398         return 0;
1399 }
1400
1401 /**
1402  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1403  * message table.
1404  * @pm8001_ha: our hba card information
1405  * @circularQ: the outbound queue  table.
1406  * @messagePtr1: the message contents of this outbound message.
1407  * @pBC: the message size.
1408  */
1409 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1410                            struct outbound_queue_table *circularQ,
1411                            void **messagePtr1, u8 *pBC)
1412 {
1413         struct mpi_msg_hdr      *msgHeader;
1414         __le32  msgHeader_tmp;
1415         u32 header_tmp;
1416         do {
1417                 /* If there are not-yet-delivered messages ... */
1418                 if (le32_to_cpu(circularQ->producer_index)
1419                         != circularQ->consumer_idx) {
1420                         /*Get the pointer to the circular queue buffer element*/
1421                         msgHeader = (struct mpi_msg_hdr *)
1422                                 (circularQ->base_virt +
1423                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1424                         /* read header */
1425                         header_tmp = pm8001_read_32(msgHeader);
1426                         msgHeader_tmp = cpu_to_le32(header_tmp);
1427                         pm8001_dbg(pm8001_ha, DEVIO,
1428                                    "outbound opcode msgheader:%x ci=%d pi=%d\n",
1429                                    msgHeader_tmp, circularQ->consumer_idx,
1430                                    circularQ->producer_index);
1431                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1432                                 if (OPC_OUB_SKIP_ENTRY !=
1433                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1434                                         *messagePtr1 =
1435                                                 ((u8 *)msgHeader) +
1436                                                 sizeof(struct mpi_msg_hdr);
1437                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1438                                                 >> 24) & 0x1f);
1439                                         pm8001_dbg(pm8001_ha, IO,
1440                                                    ": CI=%d PI=%d msgHeader=%x\n",
1441                                                    circularQ->consumer_idx,
1442                                                    circularQ->producer_index,
1443                                                    msgHeader_tmp);
1444                                         return MPI_IO_STATUS_SUCCESS;
1445                                 } else {
1446                                         circularQ->consumer_idx =
1447                                                 (circularQ->consumer_idx +
1448                                                 ((le32_to_cpu(msgHeader_tmp)
1449                                                  >> 24) & 0x1f))
1450                                                         % PM8001_MPI_QUEUE;
1451                                         msgHeader_tmp = 0;
1452                                         pm8001_write_32(msgHeader, 0, 0);
1453                                         /* update the CI of outbound queue */
1454                                         pm8001_cw32(pm8001_ha,
1455                                                 circularQ->ci_pci_bar,
1456                                                 circularQ->ci_offset,
1457                                                 circularQ->consumer_idx);
1458                                 }
1459                         } else {
1460                                 circularQ->consumer_idx =
1461                                         (circularQ->consumer_idx +
1462                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1463                                         0x1f)) % PM8001_MPI_QUEUE;
1464                                 msgHeader_tmp = 0;
1465                                 pm8001_write_32(msgHeader, 0, 0);
1466                                 /* update the CI of outbound queue */
1467                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1468                                         circularQ->ci_offset,
1469                                         circularQ->consumer_idx);
1470                                 return MPI_IO_STATUS_FAIL;
1471                         }
1472                 } else {
1473                         u32 producer_index;
1474                         void *pi_virt = circularQ->pi_virt;
1475                         /* spurious interrupt during setup if
1476                          * kexec-ing and driver doing a doorbell access
1477                          * with the pre-kexec oq interrupt setup
1478                          */
1479                         if (!pi_virt)
1480                                 break;
1481                         /* Update the producer index from SPC */
1482                         producer_index = pm8001_read_32(pi_virt);
1483                         circularQ->producer_index = cpu_to_le32(producer_index);
1484                 }
1485         } while (le32_to_cpu(circularQ->producer_index) !=
1486                 circularQ->consumer_idx);
1487         /* while we don't have any more not-yet-delivered message */
1488         /* report empty */
1489         return MPI_IO_STATUS_BUSY;
1490 }
1491
1492 void pm8001_work_fn(struct work_struct *work)
1493 {
1494         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1495         struct pm8001_device *pm8001_dev;
1496         struct domain_device *dev;
1497
1498         /*
1499          * So far, all users of this stash an associated structure here.
1500          * If we get here, and this pointer is null, then the action
1501          * was cancelled. This nullification happens when the device
1502          * goes away.
1503          */
1504         pm8001_dev = pw->data; /* Most stash device structure */
1505         if ((pm8001_dev == NULL)
1506          || ((pw->handler != IO_XFER_ERROR_BREAK)
1507           && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1508                 kfree(pw);
1509                 return;
1510         }
1511
1512         switch (pw->handler) {
1513         case IO_XFER_ERROR_BREAK:
1514         {       /* This one stashes the sas_task instead */
1515                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1516                 u32 tag;
1517                 struct pm8001_ccb_info *ccb;
1518                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1519                 unsigned long flags, flags1;
1520                 struct task_status_struct *ts;
1521                 int i;
1522
1523                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1524                         break; /* Task still on lu */
1525                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1526
1527                 spin_lock_irqsave(&t->task_state_lock, flags1);
1528                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1529                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1530                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1531                         break; /* Task got completed by another */
1532                 }
1533                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1534
1535                 /* Search for a possible ccb that matches the task */
1536                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1537                         ccb = &pm8001_ha->ccb_info[i];
1538                         tag = ccb->ccb_tag;
1539                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1540                                 break;
1541                 }
1542                 if (!ccb) {
1543                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1544                         break; /* Task got freed by another */
1545                 }
1546                 ts = &t->task_status;
1547                 ts->resp = SAS_TASK_COMPLETE;
1548                 /* Force the midlayer to retry */
1549                 ts->stat = SAS_QUEUE_FULL;
1550                 pm8001_dev = ccb->device;
1551                 if (pm8001_dev)
1552                         atomic_dec(&pm8001_dev->running_req);
1553                 spin_lock_irqsave(&t->task_state_lock, flags1);
1554                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1555                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1556                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1557                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1558                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1559                         pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1560                                    t, pw->handler, ts->resp, ts->stat);
1561                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1562                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1563                 } else {
1564                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1565                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1566                         mb();/* in order to force CPU ordering */
1567                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1568                         t->task_done(t);
1569                 }
1570         }       break;
1571         case IO_XFER_OPEN_RETRY_TIMEOUT:
1572         {       /* This one stashes the sas_task instead */
1573                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1574                 u32 tag;
1575                 struct pm8001_ccb_info *ccb;
1576                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1577                 unsigned long flags, flags1;
1578                 int i, ret = 0;
1579
1580                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1581
1582                 ret = pm8001_query_task(t);
1583
1584                 if (ret == TMF_RESP_FUNC_SUCC)
1585                         pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1586                 else if (ret == TMF_RESP_FUNC_COMPLETE)
1587                         pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1588                 else
1589                         pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1590
1591                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1592
1593                 spin_lock_irqsave(&t->task_state_lock, flags1);
1594
1595                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1596                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1597                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1598                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1599                                 (void)pm8001_abort_task(t);
1600                         break; /* Task got completed by another */
1601                 }
1602
1603                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1604
1605                 /* Search for a possible ccb that matches the task */
1606                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1607                         ccb = &pm8001_ha->ccb_info[i];
1608                         tag = ccb->ccb_tag;
1609                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1610                                 break;
1611                 }
1612                 if (!ccb) {
1613                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1614                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1615                                 (void)pm8001_abort_task(t);
1616                         break; /* Task got freed by another */
1617                 }
1618
1619                 pm8001_dev = ccb->device;
1620                 dev = pm8001_dev->sas_device;
1621
1622                 switch (ret) {
1623                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1624                         ccb->open_retry = 1; /* Snub completion */
1625                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1626                         ret = pm8001_abort_task(t);
1627                         ccb->open_retry = 0;
1628                         switch (ret) {
1629                         case TMF_RESP_FUNC_SUCC:
1630                         case TMF_RESP_FUNC_COMPLETE:
1631                                 break;
1632                         default: /* device misbehavior */
1633                                 ret = TMF_RESP_FUNC_FAILED;
1634                                 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1635                                 pm8001_I_T_nexus_reset(dev);
1636                                 break;
1637                         }
1638                         break;
1639
1640                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1641                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1642                         /* Do we need to abort the task locally? */
1643                         break;
1644
1645                 default: /* device misbehavior */
1646                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1647                         ret = TMF_RESP_FUNC_FAILED;
1648                         pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1649                         pm8001_I_T_nexus_reset(dev);
1650                 }
1651
1652                 if (ret == TMF_RESP_FUNC_FAILED)
1653                         t = NULL;
1654                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1655                 pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1656         }       break;
1657         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1658                 dev = pm8001_dev->sas_device;
1659                 pm8001_I_T_nexus_event_handler(dev);
1660                 break;
1661         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1662                 dev = pm8001_dev->sas_device;
1663                 pm8001_I_T_nexus_reset(dev);
1664                 break;
1665         case IO_DS_IN_ERROR:
1666                 dev = pm8001_dev->sas_device;
1667                 pm8001_I_T_nexus_reset(dev);
1668                 break;
1669         case IO_DS_NON_OPERATIONAL:
1670                 dev = pm8001_dev->sas_device;
1671                 pm8001_I_T_nexus_reset(dev);
1672                 break;
1673         }
1674         kfree(pw);
1675 }
1676
1677 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1678                                int handler)
1679 {
1680         struct pm8001_work *pw;
1681         int ret = 0;
1682
1683         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1684         if (pw) {
1685                 pw->pm8001_ha = pm8001_ha;
1686                 pw->data = data;
1687                 pw->handler = handler;
1688                 INIT_WORK(&pw->work, pm8001_work_fn);
1689                 queue_work(pm8001_wq, &pw->work);
1690         } else
1691                 ret = -ENOMEM;
1692
1693         return ret;
1694 }
1695
1696 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1697                 struct pm8001_device *pm8001_ha_dev)
1698 {
1699         int res;
1700         u32 ccb_tag;
1701         struct pm8001_ccb_info *ccb;
1702         struct sas_task *task = NULL;
1703         struct task_abort_req task_abort;
1704         struct inbound_queue_table *circularQ;
1705         u32 opc = OPC_INB_SATA_ABORT;
1706         int ret;
1707
1708         if (!pm8001_ha_dev) {
1709                 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1710                 return;
1711         }
1712
1713         task = sas_alloc_slow_task(GFP_ATOMIC);
1714         if (!task) {
1715                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1716                 return;
1717         }
1718
1719         task->task_done = pm8001_task_done;
1720
1721         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1722         if (res) {
1723                 sas_free_task(task);
1724                 return;
1725         }
1726
1727         ccb = &pm8001_ha->ccb_info[ccb_tag];
1728         ccb->device = pm8001_ha_dev;
1729         ccb->ccb_tag = ccb_tag;
1730         ccb->task = task;
1731         ccb->n_elem = 0;
1732
1733         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1734
1735         memset(&task_abort, 0, sizeof(task_abort));
1736         task_abort.abort_all = cpu_to_le32(1);
1737         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1738         task_abort.tag = cpu_to_le32(ccb_tag);
1739
1740         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1741                         sizeof(task_abort), 0);
1742         if (ret) {
1743                 sas_free_task(task);
1744                 pm8001_tag_free(pm8001_ha, ccb_tag);
1745         }
1746
1747 }
1748
1749 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1750                 struct pm8001_device *pm8001_ha_dev)
1751 {
1752         struct sata_start_req sata_cmd;
1753         int res;
1754         u32 ccb_tag;
1755         struct pm8001_ccb_info *ccb;
1756         struct sas_task *task = NULL;
1757         struct host_to_dev_fis fis;
1758         struct domain_device *dev;
1759         struct inbound_queue_table *circularQ;
1760         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1761
1762         task = sas_alloc_slow_task(GFP_ATOMIC);
1763
1764         if (!task) {
1765                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1766                 return;
1767         }
1768         task->task_done = pm8001_task_done;
1769
1770         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1771         if (res) {
1772                 sas_free_task(task);
1773                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1774                 return;
1775         }
1776
1777         /* allocate domain device by ourselves as libsas
1778          * is not going to provide any
1779         */
1780         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1781         if (!dev) {
1782                 sas_free_task(task);
1783                 pm8001_tag_free(pm8001_ha, ccb_tag);
1784                 pm8001_dbg(pm8001_ha, FAIL,
1785                            "Domain device cannot be allocated\n");
1786                 return;
1787         }
1788         task->dev = dev;
1789         task->dev->lldd_dev = pm8001_ha_dev;
1790
1791         ccb = &pm8001_ha->ccb_info[ccb_tag];
1792         ccb->device = pm8001_ha_dev;
1793         ccb->ccb_tag = ccb_tag;
1794         ccb->task = task;
1795         ccb->n_elem = 0;
1796         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1797         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1798
1799         memset(&sata_cmd, 0, sizeof(sata_cmd));
1800         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1801
1802         /* construct read log FIS */
1803         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1804         fis.fis_type = 0x27;
1805         fis.flags = 0x80;
1806         fis.command = ATA_CMD_READ_LOG_EXT;
1807         fis.lbal = 0x10;
1808         fis.sector_count = 0x1;
1809
1810         sata_cmd.tag = cpu_to_le32(ccb_tag);
1811         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1812         sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1813         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1814
1815         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1816                         sizeof(sata_cmd), 0);
1817         if (res) {
1818                 sas_free_task(task);
1819                 pm8001_tag_free(pm8001_ha, ccb_tag);
1820                 kfree(dev);
1821         }
1822 }
1823
1824 /**
1825  * mpi_ssp_completion- process the event that FW response to the SSP request.
1826  * @pm8001_ha: our hba card information
1827  * @piomb: the message contents of this outbound message.
1828  *
1829  * When FW has completed a ssp request for example a IO request, after it has
1830  * filled the SG data with the data, it will trigger this event represent
1831  * that he has finished the job,please check the coresponding buffer.
1832  * So we will tell the caller who maybe waiting the result to tell upper layer
1833  * that the task has been finished.
1834  */
1835 static void
1836 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1837 {
1838         struct sas_task *t;
1839         struct pm8001_ccb_info *ccb;
1840         unsigned long flags;
1841         u32 status;
1842         u32 param;
1843         u32 tag;
1844         struct ssp_completion_resp *psspPayload;
1845         struct task_status_struct *ts;
1846         struct ssp_response_iu *iu;
1847         struct pm8001_device *pm8001_dev;
1848         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1849         status = le32_to_cpu(psspPayload->status);
1850         tag = le32_to_cpu(psspPayload->tag);
1851         ccb = &pm8001_ha->ccb_info[tag];
1852         if ((status == IO_ABORTED) && ccb->open_retry) {
1853                 /* Being completed by another */
1854                 ccb->open_retry = 0;
1855                 return;
1856         }
1857         pm8001_dev = ccb->device;
1858         param = le32_to_cpu(psspPayload->param);
1859
1860         t = ccb->task;
1861
1862         if (status && status != IO_UNDERFLOW)
1863                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1864         if (unlikely(!t || !t->lldd_task || !t->dev))
1865                 return;
1866         ts = &t->task_status;
1867         /* Print sas address of IO failed device */
1868         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1869                 (status != IO_UNDERFLOW))
1870                 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1871                            SAS_ADDR(t->dev->sas_addr));
1872
1873         if (status)
1874                 pm8001_dbg(pm8001_ha, IOERR,
1875                            "status:0x%x, tag:0x%x, task:0x%p\n",
1876                            status, tag, t);
1877
1878         switch (status) {
1879         case IO_SUCCESS:
1880                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1881                            param);
1882                 if (param == 0) {
1883                         ts->resp = SAS_TASK_COMPLETE;
1884                         ts->stat = SAS_SAM_STAT_GOOD;
1885                 } else {
1886                         ts->resp = SAS_TASK_COMPLETE;
1887                         ts->stat = SAS_PROTO_RESPONSE;
1888                         ts->residual = param;
1889                         iu = &psspPayload->ssp_resp_iu;
1890                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1891                 }
1892                 if (pm8001_dev)
1893                         atomic_dec(&pm8001_dev->running_req);
1894                 break;
1895         case IO_ABORTED:
1896                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1897                 ts->resp = SAS_TASK_COMPLETE;
1898                 ts->stat = SAS_ABORTED_TASK;
1899                 break;
1900         case IO_UNDERFLOW:
1901                 /* SSP Completion with error */
1902                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1903                            param);
1904                 ts->resp = SAS_TASK_COMPLETE;
1905                 ts->stat = SAS_DATA_UNDERRUN;
1906                 ts->residual = param;
1907                 if (pm8001_dev)
1908                         atomic_dec(&pm8001_dev->running_req);
1909                 break;
1910         case IO_NO_DEVICE:
1911                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1912                 ts->resp = SAS_TASK_UNDELIVERED;
1913                 ts->stat = SAS_PHY_DOWN;
1914                 break;
1915         case IO_XFER_ERROR_BREAK:
1916                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1917                 ts->resp = SAS_TASK_COMPLETE;
1918                 ts->stat = SAS_OPEN_REJECT;
1919                 /* Force the midlayer to retry */
1920                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1921                 break;
1922         case IO_XFER_ERROR_PHY_NOT_READY:
1923                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1924                 ts->resp = SAS_TASK_COMPLETE;
1925                 ts->stat = SAS_OPEN_REJECT;
1926                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1927                 break;
1928         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1929                 pm8001_dbg(pm8001_ha, IO,
1930                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1931                 ts->resp = SAS_TASK_COMPLETE;
1932                 ts->stat = SAS_OPEN_REJECT;
1933                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1934                 break;
1935         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1936                 pm8001_dbg(pm8001_ha, IO,
1937                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1938                 ts->resp = SAS_TASK_COMPLETE;
1939                 ts->stat = SAS_OPEN_REJECT;
1940                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1941                 break;
1942         case IO_OPEN_CNX_ERROR_BREAK:
1943                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1944                 ts->resp = SAS_TASK_COMPLETE;
1945                 ts->stat = SAS_OPEN_REJECT;
1946                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1947                 break;
1948         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1949                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1950                 ts->resp = SAS_TASK_COMPLETE;
1951                 ts->stat = SAS_OPEN_REJECT;
1952                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1953                 if (!t->uldd_task)
1954                         pm8001_handle_event(pm8001_ha,
1955                                 pm8001_dev,
1956                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1957                 break;
1958         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1959                 pm8001_dbg(pm8001_ha, IO,
1960                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1961                 ts->resp = SAS_TASK_COMPLETE;
1962                 ts->stat = SAS_OPEN_REJECT;
1963                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1964                 break;
1965         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1966                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1967                 ts->resp = SAS_TASK_COMPLETE;
1968                 ts->stat = SAS_OPEN_REJECT;
1969                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1970                 break;
1971         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1972                 pm8001_dbg(pm8001_ha, IO,
1973                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
1974                 ts->resp = SAS_TASK_UNDELIVERED;
1975                 ts->stat = SAS_OPEN_REJECT;
1976                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1977                 break;
1978         case IO_XFER_ERROR_NAK_RECEIVED:
1979                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
1980                 ts->resp = SAS_TASK_COMPLETE;
1981                 ts->stat = SAS_OPEN_REJECT;
1982                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1983                 break;
1984         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1985                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
1986                 ts->resp = SAS_TASK_COMPLETE;
1987                 ts->stat = SAS_NAK_R_ERR;
1988                 break;
1989         case IO_XFER_ERROR_DMA:
1990                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
1991                 ts->resp = SAS_TASK_COMPLETE;
1992                 ts->stat = SAS_OPEN_REJECT;
1993                 break;
1994         case IO_XFER_OPEN_RETRY_TIMEOUT:
1995                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1996                 ts->resp = SAS_TASK_COMPLETE;
1997                 ts->stat = SAS_OPEN_REJECT;
1998                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1999                 break;
2000         case IO_XFER_ERROR_OFFSET_MISMATCH:
2001                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2002                 ts->resp = SAS_TASK_COMPLETE;
2003                 ts->stat = SAS_OPEN_REJECT;
2004                 break;
2005         case IO_PORT_IN_RESET:
2006                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2007                 ts->resp = SAS_TASK_COMPLETE;
2008                 ts->stat = SAS_OPEN_REJECT;
2009                 break;
2010         case IO_DS_NON_OPERATIONAL:
2011                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2012                 ts->resp = SAS_TASK_COMPLETE;
2013                 ts->stat = SAS_OPEN_REJECT;
2014                 if (!t->uldd_task)
2015                         pm8001_handle_event(pm8001_ha,
2016                                 pm8001_dev,
2017                                 IO_DS_NON_OPERATIONAL);
2018                 break;
2019         case IO_DS_IN_RECOVERY:
2020                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2021                 ts->resp = SAS_TASK_COMPLETE;
2022                 ts->stat = SAS_OPEN_REJECT;
2023                 break;
2024         case IO_TM_TAG_NOT_FOUND:
2025                 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2026                 ts->resp = SAS_TASK_COMPLETE;
2027                 ts->stat = SAS_OPEN_REJECT;
2028                 break;
2029         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2030                 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2031                 ts->resp = SAS_TASK_COMPLETE;
2032                 ts->stat = SAS_OPEN_REJECT;
2033                 break;
2034         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2035                 pm8001_dbg(pm8001_ha, IO,
2036                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2037                 ts->resp = SAS_TASK_COMPLETE;
2038                 ts->stat = SAS_OPEN_REJECT;
2039                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2040                 break;
2041         default:
2042                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2043                 /* not allowed case. Therefore, return failed status */
2044                 ts->resp = SAS_TASK_COMPLETE;
2045                 ts->stat = SAS_OPEN_REJECT;
2046                 break;
2047         }
2048         pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2049                    psspPayload->ssp_resp_iu.status);
2050         spin_lock_irqsave(&t->task_state_lock, flags);
2051         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2052         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2053         t->task_state_flags |= SAS_TASK_STATE_DONE;
2054         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2055                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2056                 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2057                            t, status, ts->resp, ts->stat);
2058                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2059         } else {
2060                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2061                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2062                 mb();/* in order to force CPU ordering */
2063                 t->task_done(t);
2064         }
2065 }
2066
2067 /*See the comments for mpi_ssp_completion */
2068 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2069 {
2070         struct sas_task *t;
2071         unsigned long flags;
2072         struct task_status_struct *ts;
2073         struct pm8001_ccb_info *ccb;
2074         struct pm8001_device *pm8001_dev;
2075         struct ssp_event_resp *psspPayload =
2076                 (struct ssp_event_resp *)(piomb + 4);
2077         u32 event = le32_to_cpu(psspPayload->event);
2078         u32 tag = le32_to_cpu(psspPayload->tag);
2079         u32 port_id = le32_to_cpu(psspPayload->port_id);
2080         u32 dev_id = le32_to_cpu(psspPayload->device_id);
2081
2082         ccb = &pm8001_ha->ccb_info[tag];
2083         t = ccb->task;
2084         pm8001_dev = ccb->device;
2085         if (event)
2086                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2087         if (unlikely(!t || !t->lldd_task || !t->dev))
2088                 return;
2089         ts = &t->task_status;
2090         pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2091                    port_id, dev_id);
2092         switch (event) {
2093         case IO_OVERFLOW:
2094                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2095                 ts->resp = SAS_TASK_COMPLETE;
2096                 ts->stat = SAS_DATA_OVERRUN;
2097                 ts->residual = 0;
2098                 if (pm8001_dev)
2099                         atomic_dec(&pm8001_dev->running_req);
2100                 break;
2101         case IO_XFER_ERROR_BREAK:
2102                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2103                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2104                 return;
2105         case IO_XFER_ERROR_PHY_NOT_READY:
2106                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2107                 ts->resp = SAS_TASK_COMPLETE;
2108                 ts->stat = SAS_OPEN_REJECT;
2109                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2110                 break;
2111         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2112                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2113                 ts->resp = SAS_TASK_COMPLETE;
2114                 ts->stat = SAS_OPEN_REJECT;
2115                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2116                 break;
2117         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2118                 pm8001_dbg(pm8001_ha, IO,
2119                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2120                 ts->resp = SAS_TASK_COMPLETE;
2121                 ts->stat = SAS_OPEN_REJECT;
2122                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2123                 break;
2124         case IO_OPEN_CNX_ERROR_BREAK:
2125                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2126                 ts->resp = SAS_TASK_COMPLETE;
2127                 ts->stat = SAS_OPEN_REJECT;
2128                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2129                 break;
2130         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2131                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2132                 ts->resp = SAS_TASK_COMPLETE;
2133                 ts->stat = SAS_OPEN_REJECT;
2134                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2135                 if (!t->uldd_task)
2136                         pm8001_handle_event(pm8001_ha,
2137                                 pm8001_dev,
2138                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2139                 break;
2140         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2141                 pm8001_dbg(pm8001_ha, IO,
2142                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2143                 ts->resp = SAS_TASK_COMPLETE;
2144                 ts->stat = SAS_OPEN_REJECT;
2145                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2146                 break;
2147         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2148                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2149                 ts->resp = SAS_TASK_COMPLETE;
2150                 ts->stat = SAS_OPEN_REJECT;
2151                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2152                 break;
2153         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2154                 pm8001_dbg(pm8001_ha, IO,
2155                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2156                 ts->resp = SAS_TASK_COMPLETE;
2157                 ts->stat = SAS_OPEN_REJECT;
2158                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2159                 break;
2160         case IO_XFER_ERROR_NAK_RECEIVED:
2161                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2162                 ts->resp = SAS_TASK_COMPLETE;
2163                 ts->stat = SAS_OPEN_REJECT;
2164                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2165                 break;
2166         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2167                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2168                 ts->resp = SAS_TASK_COMPLETE;
2169                 ts->stat = SAS_NAK_R_ERR;
2170                 break;
2171         case IO_XFER_OPEN_RETRY_TIMEOUT:
2172                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2173                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2174                 return;
2175         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2176                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2177                 ts->resp = SAS_TASK_COMPLETE;
2178                 ts->stat = SAS_DATA_OVERRUN;
2179                 break;
2180         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2181                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2182                 ts->resp = SAS_TASK_COMPLETE;
2183                 ts->stat = SAS_DATA_OVERRUN;
2184                 break;
2185         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2186                 pm8001_dbg(pm8001_ha, IO,
2187                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2188                 ts->resp = SAS_TASK_COMPLETE;
2189                 ts->stat = SAS_DATA_OVERRUN;
2190                 break;
2191         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2192                 pm8001_dbg(pm8001_ha, IO,
2193                            "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2194                 ts->resp = SAS_TASK_COMPLETE;
2195                 ts->stat = SAS_DATA_OVERRUN;
2196                 break;
2197         case IO_XFER_ERROR_OFFSET_MISMATCH:
2198                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2199                 ts->resp = SAS_TASK_COMPLETE;
2200                 ts->stat = SAS_DATA_OVERRUN;
2201                 break;
2202         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2203                 pm8001_dbg(pm8001_ha, IO,
2204                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2205                 ts->resp = SAS_TASK_COMPLETE;
2206                 ts->stat = SAS_DATA_OVERRUN;
2207                 break;
2208         case IO_XFER_CMD_FRAME_ISSUED:
2209                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2210                 return;
2211         default:
2212                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2213                 /* not allowed case. Therefore, return failed status */
2214                 ts->resp = SAS_TASK_COMPLETE;
2215                 ts->stat = SAS_DATA_OVERRUN;
2216                 break;
2217         }
2218         spin_lock_irqsave(&t->task_state_lock, flags);
2219         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2220         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2221         t->task_state_flags |= SAS_TASK_STATE_DONE;
2222         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2223                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2224                 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2225                            t, event, ts->resp, ts->stat);
2226                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2227         } else {
2228                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2229                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2230                 mb();/* in order to force CPU ordering */
2231                 t->task_done(t);
2232         }
2233 }
2234
2235 /*See the comments for mpi_ssp_completion */
2236 static void
2237 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2238 {
2239         struct sas_task *t;
2240         struct pm8001_ccb_info *ccb;
2241         u32 param;
2242         u32 status;
2243         u32 tag;
2244         int i, j;
2245         u8 sata_addr_low[4];
2246         u32 temp_sata_addr_low;
2247         u8 sata_addr_hi[4];
2248         u32 temp_sata_addr_hi;
2249         struct sata_completion_resp *psataPayload;
2250         struct task_status_struct *ts;
2251         struct ata_task_resp *resp ;
2252         u32 *sata_resp;
2253         struct pm8001_device *pm8001_dev;
2254         unsigned long flags;
2255
2256         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2257         status = le32_to_cpu(psataPayload->status);
2258         tag = le32_to_cpu(psataPayload->tag);
2259
2260         if (!tag) {
2261                 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2262                 return;
2263         }
2264         ccb = &pm8001_ha->ccb_info[tag];
2265         param = le32_to_cpu(psataPayload->param);
2266         if (ccb) {
2267                 t = ccb->task;
2268                 pm8001_dev = ccb->device;
2269         } else {
2270                 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2271                 return;
2272         }
2273
2274         if (t) {
2275                 if (t->dev && (t->dev->lldd_dev))
2276                         pm8001_dev = t->dev->lldd_dev;
2277         } else {
2278                 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2279                 return;
2280         }
2281
2282         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2283                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2284                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2285                 return;
2286         }
2287
2288         ts = &t->task_status;
2289         if (!ts) {
2290                 pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2291                 return;
2292         }
2293
2294         if (status)
2295                 pm8001_dbg(pm8001_ha, IOERR,
2296                            "status:0x%x, tag:0x%x, task::0x%p\n",
2297                            status, tag, t);
2298
2299         /* Print sas address of IO failed device */
2300         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2301                 (status != IO_UNDERFLOW)) {
2302                 if (!((t->dev->parent) &&
2303                         (dev_is_expander(t->dev->parent->dev_type)))) {
2304                         for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2305                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2306                         for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2307                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2308                         memcpy(&temp_sata_addr_low, sata_addr_low,
2309                                 sizeof(sata_addr_low));
2310                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2311                                 sizeof(sata_addr_hi));
2312                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2313                                                 |((temp_sata_addr_hi << 8) &
2314                                                 0xff0000) |
2315                                                 ((temp_sata_addr_hi >> 8)
2316                                                 & 0xff00) |
2317                                                 ((temp_sata_addr_hi << 24) &
2318                                                 0xff000000));
2319                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2320                                                 & 0xff) |
2321                                                 ((temp_sata_addr_low << 8)
2322                                                 & 0xff0000) |
2323                                                 ((temp_sata_addr_low >> 8)
2324                                                 & 0xff00) |
2325                                                 ((temp_sata_addr_low << 24)
2326                                                 & 0xff000000)) +
2327                                                 pm8001_dev->attached_phy +
2328                                                 0x10);
2329                         pm8001_dbg(pm8001_ha, FAIL,
2330                                    "SAS Address of IO Failure Drive:%08x%08x\n",
2331                                    temp_sata_addr_hi,
2332                                    temp_sata_addr_low);
2333                 } else {
2334                         pm8001_dbg(pm8001_ha, FAIL,
2335                                    "SAS Address of IO Failure Drive:%016llx\n",
2336                                    SAS_ADDR(t->dev->sas_addr));
2337                 }
2338         }
2339         switch (status) {
2340         case IO_SUCCESS:
2341                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2342                 if (param == 0) {
2343                         ts->resp = SAS_TASK_COMPLETE;
2344                         ts->stat = SAS_SAM_STAT_GOOD;
2345                         /* check if response is for SEND READ LOG */
2346                         if (pm8001_dev &&
2347                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2348                                 /* set new bit for abort_all */
2349                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2350                                 /* clear bit for read log */
2351                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2352                                 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2353                                 /* Free the tag */
2354                                 pm8001_tag_free(pm8001_ha, tag);
2355                                 sas_free_task(t);
2356                                 return;
2357                         }
2358                 } else {
2359                         u8 len;
2360                         ts->resp = SAS_TASK_COMPLETE;
2361                         ts->stat = SAS_PROTO_RESPONSE;
2362                         ts->residual = param;
2363                         pm8001_dbg(pm8001_ha, IO,
2364                                    "SAS_PROTO_RESPONSE len = %d\n",
2365                                    param);
2366                         sata_resp = &psataPayload->sata_resp[0];
2367                         resp = (struct ata_task_resp *)ts->buf;
2368                         if (t->ata_task.dma_xfer == 0 &&
2369                             t->data_dir == DMA_FROM_DEVICE) {
2370                                 len = sizeof(struct pio_setup_fis);
2371                                 pm8001_dbg(pm8001_ha, IO,
2372                                            "PIO read len = %d\n", len);
2373                         } else if (t->ata_task.use_ncq &&
2374                                    t->data_dir != DMA_NONE) {
2375                                 len = sizeof(struct set_dev_bits_fis);
2376                                 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2377                                            len);
2378                         } else {
2379                                 len = sizeof(struct dev_to_host_fis);
2380                                 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2381                                            len);
2382                         }
2383                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2384                                 resp->frame_len = len;
2385                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2386                                 ts->buf_valid_size = sizeof(*resp);
2387                         } else
2388                                 pm8001_dbg(pm8001_ha, IO,
2389                                            "response too large\n");
2390                 }
2391                 if (pm8001_dev)
2392                         atomic_dec(&pm8001_dev->running_req);
2393                 break;
2394         case IO_ABORTED:
2395                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2396                 ts->resp = SAS_TASK_COMPLETE;
2397                 ts->stat = SAS_ABORTED_TASK;
2398                 if (pm8001_dev)
2399                         atomic_dec(&pm8001_dev->running_req);
2400                 break;
2401                 /* following cases are to do cases */
2402         case IO_UNDERFLOW:
2403                 /* SATA Completion with error */
2404                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2405                 ts->resp = SAS_TASK_COMPLETE;
2406                 ts->stat = SAS_DATA_UNDERRUN;
2407                 ts->residual =  param;
2408                 if (pm8001_dev)
2409                         atomic_dec(&pm8001_dev->running_req);
2410                 break;
2411         case IO_NO_DEVICE:
2412                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2413                 ts->resp = SAS_TASK_UNDELIVERED;
2414                 ts->stat = SAS_PHY_DOWN;
2415                 if (pm8001_dev)
2416                         atomic_dec(&pm8001_dev->running_req);
2417                 break;
2418         case IO_XFER_ERROR_BREAK:
2419                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2420                 ts->resp = SAS_TASK_COMPLETE;
2421                 ts->stat = SAS_INTERRUPTED;
2422                 if (pm8001_dev)
2423                         atomic_dec(&pm8001_dev->running_req);
2424                 break;
2425         case IO_XFER_ERROR_PHY_NOT_READY:
2426                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2427                 ts->resp = SAS_TASK_COMPLETE;
2428                 ts->stat = SAS_OPEN_REJECT;
2429                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2430                 if (pm8001_dev)
2431                         atomic_dec(&pm8001_dev->running_req);
2432                 break;
2433         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2434                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2435                 ts->resp = SAS_TASK_COMPLETE;
2436                 ts->stat = SAS_OPEN_REJECT;
2437                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2438                 if (pm8001_dev)
2439                         atomic_dec(&pm8001_dev->running_req);
2440                 break;
2441         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2442                 pm8001_dbg(pm8001_ha, IO,
2443                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2444                 ts->resp = SAS_TASK_COMPLETE;
2445                 ts->stat = SAS_OPEN_REJECT;
2446                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2447                 if (pm8001_dev)
2448                         atomic_dec(&pm8001_dev->running_req);
2449                 break;
2450         case IO_OPEN_CNX_ERROR_BREAK:
2451                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2452                 ts->resp = SAS_TASK_COMPLETE;
2453                 ts->stat = SAS_OPEN_REJECT;
2454                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2455                 if (pm8001_dev)
2456                         atomic_dec(&pm8001_dev->running_req);
2457                 break;
2458         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2459                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2460                 ts->resp = SAS_TASK_COMPLETE;
2461                 ts->stat = SAS_DEV_NO_RESPONSE;
2462                 if (!t->uldd_task) {
2463                         pm8001_handle_event(pm8001_ha,
2464                                 pm8001_dev,
2465                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2466                         ts->resp = SAS_TASK_UNDELIVERED;
2467                         ts->stat = SAS_QUEUE_FULL;
2468                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2469                         return;
2470                 }
2471                 break;
2472         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2473                 pm8001_dbg(pm8001_ha, IO,
2474                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2475                 ts->resp = SAS_TASK_UNDELIVERED;
2476                 ts->stat = SAS_OPEN_REJECT;
2477                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2478                 if (!t->uldd_task) {
2479                         pm8001_handle_event(pm8001_ha,
2480                                 pm8001_dev,
2481                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2482                         ts->resp = SAS_TASK_UNDELIVERED;
2483                         ts->stat = SAS_QUEUE_FULL;
2484                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2485                         return;
2486                 }
2487                 break;
2488         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2489                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2490                 ts->resp = SAS_TASK_COMPLETE;
2491                 ts->stat = SAS_OPEN_REJECT;
2492                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2493                 if (pm8001_dev)
2494                         atomic_dec(&pm8001_dev->running_req);
2495                 break;
2496         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2497                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2498                 ts->resp = SAS_TASK_COMPLETE;
2499                 ts->stat = SAS_DEV_NO_RESPONSE;
2500                 if (!t->uldd_task) {
2501                         pm8001_handle_event(pm8001_ha,
2502                                 pm8001_dev,
2503                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2504                         ts->resp = SAS_TASK_UNDELIVERED;
2505                         ts->stat = SAS_QUEUE_FULL;
2506                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2507                         return;
2508                 }
2509                 break;
2510         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2511                 pm8001_dbg(pm8001_ha, IO,
2512                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2513                 ts->resp = SAS_TASK_COMPLETE;
2514                 ts->stat = SAS_OPEN_REJECT;
2515                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2516                 if (pm8001_dev)
2517                         atomic_dec(&pm8001_dev->running_req);
2518                 break;
2519         case IO_XFER_ERROR_NAK_RECEIVED:
2520                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2521                 ts->resp = SAS_TASK_COMPLETE;
2522                 ts->stat = SAS_NAK_R_ERR;
2523                 if (pm8001_dev)
2524                         atomic_dec(&pm8001_dev->running_req);
2525                 break;
2526         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2527                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2528                 ts->resp = SAS_TASK_COMPLETE;
2529                 ts->stat = SAS_NAK_R_ERR;
2530                 if (pm8001_dev)
2531                         atomic_dec(&pm8001_dev->running_req);
2532                 break;
2533         case IO_XFER_ERROR_DMA:
2534                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2535                 ts->resp = SAS_TASK_COMPLETE;
2536                 ts->stat = SAS_ABORTED_TASK;
2537                 if (pm8001_dev)
2538                         atomic_dec(&pm8001_dev->running_req);
2539                 break;
2540         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2541                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2542                 ts->resp = SAS_TASK_UNDELIVERED;
2543                 ts->stat = SAS_DEV_NO_RESPONSE;
2544                 if (pm8001_dev)
2545                         atomic_dec(&pm8001_dev->running_req);
2546                 break;
2547         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2548                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2549                 ts->resp = SAS_TASK_COMPLETE;
2550                 ts->stat = SAS_DATA_UNDERRUN;
2551                 if (pm8001_dev)
2552                         atomic_dec(&pm8001_dev->running_req);
2553                 break;
2554         case IO_XFER_OPEN_RETRY_TIMEOUT:
2555                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2556                 ts->resp = SAS_TASK_COMPLETE;
2557                 ts->stat = SAS_OPEN_TO;
2558                 if (pm8001_dev)
2559                         atomic_dec(&pm8001_dev->running_req);
2560                 break;
2561         case IO_PORT_IN_RESET:
2562                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2563                 ts->resp = SAS_TASK_COMPLETE;
2564                 ts->stat = SAS_DEV_NO_RESPONSE;
2565                 if (pm8001_dev)
2566                         atomic_dec(&pm8001_dev->running_req);
2567                 break;
2568         case IO_DS_NON_OPERATIONAL:
2569                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2570                 ts->resp = SAS_TASK_COMPLETE;
2571                 ts->stat = SAS_DEV_NO_RESPONSE;
2572                 if (!t->uldd_task) {
2573                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2574                                     IO_DS_NON_OPERATIONAL);
2575                         ts->resp = SAS_TASK_UNDELIVERED;
2576                         ts->stat = SAS_QUEUE_FULL;
2577                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2578                         return;
2579                 }
2580                 break;
2581         case IO_DS_IN_RECOVERY:
2582                 pm8001_dbg(pm8001_ha, IO, "  IO_DS_IN_RECOVERY\n");
2583                 ts->resp = SAS_TASK_COMPLETE;
2584                 ts->stat = SAS_DEV_NO_RESPONSE;
2585                 if (pm8001_dev)
2586                         atomic_dec(&pm8001_dev->running_req);
2587                 break;
2588         case IO_DS_IN_ERROR:
2589                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2590                 ts->resp = SAS_TASK_COMPLETE;
2591                 ts->stat = SAS_DEV_NO_RESPONSE;
2592                 if (!t->uldd_task) {
2593                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2594                                     IO_DS_IN_ERROR);
2595                         ts->resp = SAS_TASK_UNDELIVERED;
2596                         ts->stat = SAS_QUEUE_FULL;
2597                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2598                         return;
2599                 }
2600                 break;
2601         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2602                 pm8001_dbg(pm8001_ha, IO,
2603                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2604                 ts->resp = SAS_TASK_COMPLETE;
2605                 ts->stat = SAS_OPEN_REJECT;
2606                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2607                 if (pm8001_dev)
2608                         atomic_dec(&pm8001_dev->running_req);
2609                 break;
2610         default:
2611                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2612                 /* not allowed case. Therefore, return failed status */
2613                 ts->resp = SAS_TASK_COMPLETE;
2614                 ts->stat = SAS_DEV_NO_RESPONSE;
2615                 if (pm8001_dev)
2616                         atomic_dec(&pm8001_dev->running_req);
2617                 break;
2618         }
2619         spin_lock_irqsave(&t->task_state_lock, flags);
2620         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2621         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2622         t->task_state_flags |= SAS_TASK_STATE_DONE;
2623         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2624                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2625                 pm8001_dbg(pm8001_ha, FAIL,
2626                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2627                            t, status, ts->resp, ts->stat);
2628                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2629         } else {
2630                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2631                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2632         }
2633 }
2634
2635 /*See the comments for mpi_ssp_completion */
2636 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2637 {
2638         struct sas_task *t;
2639         struct task_status_struct *ts;
2640         struct pm8001_ccb_info *ccb;
2641         struct pm8001_device *pm8001_dev;
2642         struct sata_event_resp *psataPayload =
2643                 (struct sata_event_resp *)(piomb + 4);
2644         u32 event = le32_to_cpu(psataPayload->event);
2645         u32 tag = le32_to_cpu(psataPayload->tag);
2646         u32 port_id = le32_to_cpu(psataPayload->port_id);
2647         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2648         unsigned long flags;
2649
2650         ccb = &pm8001_ha->ccb_info[tag];
2651
2652         if (ccb) {
2653                 t = ccb->task;
2654                 pm8001_dev = ccb->device;
2655         } else {
2656                 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2657         }
2658         if (event)
2659                 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2660
2661         /* Check if this is NCQ error */
2662         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2663                 /* find device using device id */
2664                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2665                 /* send read log extension */
2666                 if (pm8001_dev)
2667                         pm8001_send_read_log(pm8001_ha, pm8001_dev);
2668                 return;
2669         }
2670
2671         ccb = &pm8001_ha->ccb_info[tag];
2672         t = ccb->task;
2673         pm8001_dev = ccb->device;
2674         if (event)
2675                 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2676         if (unlikely(!t || !t->lldd_task || !t->dev))
2677                 return;
2678         ts = &t->task_status;
2679         pm8001_dbg(pm8001_ha, DEVIO,
2680                    "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2681                    port_id, dev_id, tag, event);
2682         switch (event) {
2683         case IO_OVERFLOW:
2684                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2685                 ts->resp = SAS_TASK_COMPLETE;
2686                 ts->stat = SAS_DATA_OVERRUN;
2687                 ts->residual = 0;
2688                 if (pm8001_dev)
2689                         atomic_dec(&pm8001_dev->running_req);
2690                 break;
2691         case IO_XFER_ERROR_BREAK:
2692                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2693                 ts->resp = SAS_TASK_COMPLETE;
2694                 ts->stat = SAS_INTERRUPTED;
2695                 break;
2696         case IO_XFER_ERROR_PHY_NOT_READY:
2697                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2698                 ts->resp = SAS_TASK_COMPLETE;
2699                 ts->stat = SAS_OPEN_REJECT;
2700                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2701                 break;
2702         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2703                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2704                 ts->resp = SAS_TASK_COMPLETE;
2705                 ts->stat = SAS_OPEN_REJECT;
2706                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2707                 break;
2708         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2709                 pm8001_dbg(pm8001_ha, IO,
2710                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2711                 ts->resp = SAS_TASK_COMPLETE;
2712                 ts->stat = SAS_OPEN_REJECT;
2713                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2714                 break;
2715         case IO_OPEN_CNX_ERROR_BREAK:
2716                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2717                 ts->resp = SAS_TASK_COMPLETE;
2718                 ts->stat = SAS_OPEN_REJECT;
2719                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2720                 break;
2721         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2722                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2723                 ts->resp = SAS_TASK_UNDELIVERED;
2724                 ts->stat = SAS_DEV_NO_RESPONSE;
2725                 if (!t->uldd_task) {
2726                         pm8001_handle_event(pm8001_ha,
2727                                 pm8001_dev,
2728                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2729                         ts->resp = SAS_TASK_COMPLETE;
2730                         ts->stat = SAS_QUEUE_FULL;
2731                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2732                         return;
2733                 }
2734                 break;
2735         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2736                 pm8001_dbg(pm8001_ha, IO,
2737                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2738                 ts->resp = SAS_TASK_UNDELIVERED;
2739                 ts->stat = SAS_OPEN_REJECT;
2740                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2741                 break;
2742         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2743                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2744                 ts->resp = SAS_TASK_COMPLETE;
2745                 ts->stat = SAS_OPEN_REJECT;
2746                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2747                 break;
2748         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2749                 pm8001_dbg(pm8001_ha, IO,
2750                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2751                 ts->resp = SAS_TASK_COMPLETE;
2752                 ts->stat = SAS_OPEN_REJECT;
2753                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2754                 break;
2755         case IO_XFER_ERROR_NAK_RECEIVED:
2756                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2757                 ts->resp = SAS_TASK_COMPLETE;
2758                 ts->stat = SAS_NAK_R_ERR;
2759                 break;
2760         case IO_XFER_ERROR_PEER_ABORTED:
2761                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2762                 ts->resp = SAS_TASK_COMPLETE;
2763                 ts->stat = SAS_NAK_R_ERR;
2764                 break;
2765         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2766                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2767                 ts->resp = SAS_TASK_COMPLETE;
2768                 ts->stat = SAS_DATA_UNDERRUN;
2769                 break;
2770         case IO_XFER_OPEN_RETRY_TIMEOUT:
2771                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2772                 ts->resp = SAS_TASK_COMPLETE;
2773                 ts->stat = SAS_OPEN_TO;
2774                 break;
2775         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2776                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2777                 ts->resp = SAS_TASK_COMPLETE;
2778                 ts->stat = SAS_OPEN_TO;
2779                 break;
2780         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2781                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2782                 ts->resp = SAS_TASK_COMPLETE;
2783                 ts->stat = SAS_OPEN_TO;
2784                 break;
2785         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2786                 pm8001_dbg(pm8001_ha, IO,
2787                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2788                 ts->resp = SAS_TASK_COMPLETE;
2789                 ts->stat = SAS_OPEN_TO;
2790                 break;
2791         case IO_XFER_ERROR_OFFSET_MISMATCH:
2792                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2793                 ts->resp = SAS_TASK_COMPLETE;
2794                 ts->stat = SAS_OPEN_TO;
2795                 break;
2796         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2797                 pm8001_dbg(pm8001_ha, IO,
2798                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2799                 ts->resp = SAS_TASK_COMPLETE;
2800                 ts->stat = SAS_OPEN_TO;
2801                 break;
2802         case IO_XFER_CMD_FRAME_ISSUED:
2803                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2804                 break;
2805         case IO_XFER_PIO_SETUP_ERROR:
2806                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2807                 ts->resp = SAS_TASK_COMPLETE;
2808                 ts->stat = SAS_OPEN_TO;
2809                 break;
2810         default:
2811                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2812                 /* not allowed case. Therefore, return failed status */
2813                 ts->resp = SAS_TASK_COMPLETE;
2814                 ts->stat = SAS_OPEN_TO;
2815                 break;
2816         }
2817         spin_lock_irqsave(&t->task_state_lock, flags);
2818         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2819         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2820         t->task_state_flags |= SAS_TASK_STATE_DONE;
2821         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2822                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2823                 pm8001_dbg(pm8001_ha, FAIL,
2824                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2825                            t, event, ts->resp, ts->stat);
2826                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2827         } else {
2828                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2829                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2830         }
2831 }
2832
2833 /*See the comments for mpi_ssp_completion */
2834 static void
2835 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2836 {
2837         struct sas_task *t;
2838         struct pm8001_ccb_info *ccb;
2839         unsigned long flags;
2840         u32 status;
2841         u32 tag;
2842         struct smp_completion_resp *psmpPayload;
2843         struct task_status_struct *ts;
2844         struct pm8001_device *pm8001_dev;
2845
2846         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2847         status = le32_to_cpu(psmpPayload->status);
2848         tag = le32_to_cpu(psmpPayload->tag);
2849
2850         ccb = &pm8001_ha->ccb_info[tag];
2851         t = ccb->task;
2852         ts = &t->task_status;
2853         pm8001_dev = ccb->device;
2854         if (status) {
2855                 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2856                 pm8001_dbg(pm8001_ha, IOERR,
2857                            "status:0x%x, tag:0x%x, task:0x%p\n",
2858                            status, tag, t);
2859         }
2860         if (unlikely(!t || !t->lldd_task || !t->dev))
2861                 return;
2862
2863         switch (status) {
2864         case IO_SUCCESS:
2865                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2866                 ts->resp = SAS_TASK_COMPLETE;
2867                 ts->stat = SAS_SAM_STAT_GOOD;
2868                 if (pm8001_dev)
2869                         atomic_dec(&pm8001_dev->running_req);
2870                 break;
2871         case IO_ABORTED:
2872                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2873                 ts->resp = SAS_TASK_COMPLETE;
2874                 ts->stat = SAS_ABORTED_TASK;
2875                 if (pm8001_dev)
2876                         atomic_dec(&pm8001_dev->running_req);
2877                 break;
2878         case IO_OVERFLOW:
2879                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2880                 ts->resp = SAS_TASK_COMPLETE;
2881                 ts->stat = SAS_DATA_OVERRUN;
2882                 ts->residual = 0;
2883                 if (pm8001_dev)
2884                         atomic_dec(&pm8001_dev->running_req);
2885                 break;
2886         case IO_NO_DEVICE:
2887                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2888                 ts->resp = SAS_TASK_COMPLETE;
2889                 ts->stat = SAS_PHY_DOWN;
2890                 break;
2891         case IO_ERROR_HW_TIMEOUT:
2892                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2893                 ts->resp = SAS_TASK_COMPLETE;
2894                 ts->stat = SAS_SAM_STAT_BUSY;
2895                 break;
2896         case IO_XFER_ERROR_BREAK:
2897                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2898                 ts->resp = SAS_TASK_COMPLETE;
2899                 ts->stat = SAS_SAM_STAT_BUSY;
2900                 break;
2901         case IO_XFER_ERROR_PHY_NOT_READY:
2902                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2903                 ts->resp = SAS_TASK_COMPLETE;
2904                 ts->stat = SAS_SAM_STAT_BUSY;
2905                 break;
2906         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2907                 pm8001_dbg(pm8001_ha, IO,
2908                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2909                 ts->resp = SAS_TASK_COMPLETE;
2910                 ts->stat = SAS_OPEN_REJECT;
2911                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2912                 break;
2913         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2914                 pm8001_dbg(pm8001_ha, IO,
2915                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2916                 ts->resp = SAS_TASK_COMPLETE;
2917                 ts->stat = SAS_OPEN_REJECT;
2918                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2919                 break;
2920         case IO_OPEN_CNX_ERROR_BREAK:
2921                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2922                 ts->resp = SAS_TASK_COMPLETE;
2923                 ts->stat = SAS_OPEN_REJECT;
2924                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2925                 break;
2926         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2927                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2928                 ts->resp = SAS_TASK_COMPLETE;
2929                 ts->stat = SAS_OPEN_REJECT;
2930                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2931                 pm8001_handle_event(pm8001_ha,
2932                                 pm8001_dev,
2933                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2934                 break;
2935         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2936                 pm8001_dbg(pm8001_ha, IO,
2937                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2938                 ts->resp = SAS_TASK_COMPLETE;
2939                 ts->stat = SAS_OPEN_REJECT;
2940                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2941                 break;
2942         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2943                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2944                 ts->resp = SAS_TASK_COMPLETE;
2945                 ts->stat = SAS_OPEN_REJECT;
2946                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2947                 break;
2948         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2949                 pm8001_dbg(pm8001_ha, IO,
2950                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2951                 ts->resp = SAS_TASK_COMPLETE;
2952                 ts->stat = SAS_OPEN_REJECT;
2953                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2954                 break;
2955         case IO_XFER_ERROR_RX_FRAME:
2956                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2957                 ts->resp = SAS_TASK_COMPLETE;
2958                 ts->stat = SAS_DEV_NO_RESPONSE;
2959                 break;
2960         case IO_XFER_OPEN_RETRY_TIMEOUT:
2961                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2962                 ts->resp = SAS_TASK_COMPLETE;
2963                 ts->stat = SAS_OPEN_REJECT;
2964                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2965                 break;
2966         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2967                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
2968                 ts->resp = SAS_TASK_COMPLETE;
2969                 ts->stat = SAS_QUEUE_FULL;
2970                 break;
2971         case IO_PORT_IN_RESET:
2972                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2973                 ts->resp = SAS_TASK_COMPLETE;
2974                 ts->stat = SAS_OPEN_REJECT;
2975                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2976                 break;
2977         case IO_DS_NON_OPERATIONAL:
2978                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2979                 ts->resp = SAS_TASK_COMPLETE;
2980                 ts->stat = SAS_DEV_NO_RESPONSE;
2981                 break;
2982         case IO_DS_IN_RECOVERY:
2983                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2984                 ts->resp = SAS_TASK_COMPLETE;
2985                 ts->stat = SAS_OPEN_REJECT;
2986                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2987                 break;
2988         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2989                 pm8001_dbg(pm8001_ha, IO,
2990                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2991                 ts->resp = SAS_TASK_COMPLETE;
2992                 ts->stat = SAS_OPEN_REJECT;
2993                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2994                 break;
2995         default:
2996                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2997                 ts->resp = SAS_TASK_COMPLETE;
2998                 ts->stat = SAS_DEV_NO_RESPONSE;
2999                 /* not allowed case. Therefore, return failed status */
3000                 break;
3001         }
3002         spin_lock_irqsave(&t->task_state_lock, flags);
3003         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3004         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3005         t->task_state_flags |= SAS_TASK_STATE_DONE;
3006         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3007                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3008                 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
3009                            t, status, ts->resp, ts->stat);
3010                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3011         } else {
3012                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3013                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3014                 mb();/* in order to force CPU ordering */
3015                 t->task_done(t);
3016         }
3017 }
3018
3019 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3020                 void *piomb)
3021 {
3022         struct set_dev_state_resp *pPayload =
3023                 (struct set_dev_state_resp *)(piomb + 4);
3024         u32 tag = le32_to_cpu(pPayload->tag);
3025         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3026         struct pm8001_device *pm8001_dev = ccb->device;
3027         u32 status = le32_to_cpu(pPayload->status);
3028         u32 device_id = le32_to_cpu(pPayload->device_id);
3029         u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3030         u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3031         pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3032                    device_id, pds, nds, status);
3033         complete(pm8001_dev->setds_completion);
3034         ccb->task = NULL;
3035         ccb->ccb_tag = 0xFFFFFFFF;
3036         pm8001_tag_free(pm8001_ha, tag);
3037 }
3038
3039 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3040 {
3041         struct get_nvm_data_resp *pPayload =
3042                 (struct get_nvm_data_resp *)(piomb + 4);
3043         u32 tag = le32_to_cpu(pPayload->tag);
3044         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3045         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3046         complete(pm8001_ha->nvmd_completion);
3047         pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3048         if ((dlen_status & NVMD_STAT) != 0) {
3049                 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error!\n");
3050                 return;
3051         }
3052         ccb->task = NULL;
3053         ccb->ccb_tag = 0xFFFFFFFF;
3054         pm8001_tag_free(pm8001_ha, tag);
3055 }
3056
3057 void
3058 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3059 {
3060         struct fw_control_ex    *fw_control_context;
3061         struct get_nvm_data_resp *pPayload =
3062                 (struct get_nvm_data_resp *)(piomb + 4);
3063         u32 tag = le32_to_cpu(pPayload->tag);
3064         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3065         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3066         u32 ir_tds_bn_dps_das_nvm =
3067                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3068         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3069         fw_control_context = ccb->fw_control_context;
3070
3071         pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3072         if ((dlen_status & NVMD_STAT) != 0) {
3073                 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error!\n");
3074                 complete(pm8001_ha->nvmd_completion);
3075                 return;
3076         }
3077
3078         if (ir_tds_bn_dps_das_nvm & IPMode) {
3079                 /* indirect mode - IR bit set */
3080                 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3081                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3082                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3083                                 memcpy(pm8001_ha->sas_addr,
3084                                       ((u8 *)virt_addr + 4),
3085                                        SAS_ADDR_SIZE);
3086                                 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3087                         }
3088                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3089                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3090                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3091                                 ;
3092                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3093                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3094                         ;
3095                 } else {
3096                         /* Should not be happened*/
3097                         pm8001_dbg(pm8001_ha, MSG,
3098                                    "(IR=1)Wrong Device type 0x%x\n",
3099                                    ir_tds_bn_dps_das_nvm);
3100                 }
3101         } else /* direct mode */{
3102                 pm8001_dbg(pm8001_ha, MSG,
3103                            "Get NVMD success, IR=0, dataLen=%d\n",
3104                            (dlen_status & NVMD_LEN) >> 24);
3105         }
3106         /* Though fw_control_context is freed below, usrAddr still needs
3107          * to be updated as this holds the response to the request function
3108          */
3109         memcpy(fw_control_context->usrAddr,
3110                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3111                 fw_control_context->len);
3112         kfree(ccb->fw_control_context);
3113         /* To avoid race condition, complete should be
3114          * called after the message is copied to
3115          * fw_control_context->usrAddr
3116          */
3117         complete(pm8001_ha->nvmd_completion);
3118         pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3119         ccb->task = NULL;
3120         ccb->ccb_tag = 0xFFFFFFFF;
3121         pm8001_tag_free(pm8001_ha, tag);
3122 }
3123
3124 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3125 {
3126         u32 tag;
3127         struct local_phy_ctl_resp *pPayload =
3128                 (struct local_phy_ctl_resp *)(piomb + 4);
3129         u32 status = le32_to_cpu(pPayload->status);
3130         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3131         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3132         tag = le32_to_cpu(pPayload->tag);
3133         if (status != 0) {
3134                 pm8001_dbg(pm8001_ha, MSG,
3135                            "%x phy execute %x phy op failed!\n",
3136                            phy_id, phy_op);
3137         } else {
3138                 pm8001_dbg(pm8001_ha, MSG,
3139                            "%x phy execute %x phy op success!\n",
3140                            phy_id, phy_op);
3141                 pm8001_ha->phy[phy_id].reset_success = true;
3142         }
3143         if (pm8001_ha->phy[phy_id].enable_completion) {
3144                 complete(pm8001_ha->phy[phy_id].enable_completion);
3145                 pm8001_ha->phy[phy_id].enable_completion = NULL;
3146         }
3147         pm8001_tag_free(pm8001_ha, tag);
3148         return 0;
3149 }
3150
3151 /**
3152  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3153  * @pm8001_ha: our hba card information
3154  * @i: which phy that received the event.
3155  *
3156  * when HBA driver received the identify done event or initiate FIS received
3157  * event(for SATA), it will invoke this function to notify the sas layer that
3158  * the sas toplogy has formed, please discover the the whole sas domain,
3159  * while receive a broadcast(change) primitive just tell the sas
3160  * layer to discover the changed domain rather than the whole domain.
3161  */
3162 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3163 {
3164         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3165         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3166         if (!phy->phy_attached)
3167                 return;
3168
3169         if (sas_phy->phy) {
3170                 struct sas_phy *sphy = sas_phy->phy;
3171                 sphy->negotiated_linkrate = sas_phy->linkrate;
3172                 sphy->minimum_linkrate = phy->minimum_linkrate;
3173                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3174                 sphy->maximum_linkrate = phy->maximum_linkrate;
3175                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3176         }
3177
3178         if (phy->phy_type & PORT_TYPE_SAS) {
3179                 struct sas_identify_frame *id;
3180                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3181                 id->dev_type = phy->identify.device_type;
3182                 id->initiator_bits = SAS_PROTOCOL_ALL;
3183                 id->target_bits = phy->identify.target_port_protocols;
3184         } else if (phy->phy_type & PORT_TYPE_SATA) {
3185                 /*Nothing*/
3186         }
3187         pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3188
3189         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3190         sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3191 }
3192
3193 /* Get the link rate speed  */
3194 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3195 {
3196         struct sas_phy *sas_phy = phy->sas_phy.phy;
3197
3198         switch (link_rate) {
3199         case PHY_SPEED_120:
3200                 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3201                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3202                 break;
3203         case PHY_SPEED_60:
3204                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3205                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3206                 break;
3207         case PHY_SPEED_30:
3208                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3209                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3210                 break;
3211         case PHY_SPEED_15:
3212                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3213                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3214                 break;
3215         }
3216         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3217         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3218         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3219         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3220         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3221 }
3222
3223 /**
3224  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3225  * @phy: pointer to asd_phy
3226  * @sas_addr: pointer to buffer where the SAS address is to be written
3227  *
3228  * This function extracts the SAS address from an IDENTIFY frame
3229  * received.  If OOB is SATA, then a SAS address is generated from the
3230  * HA tables.
3231  *
3232  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3233  * buffer.
3234  */
3235 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3236         u8 *sas_addr)
3237 {
3238         if (phy->sas_phy.frame_rcvd[0] == 0x34
3239                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3240                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3241                 /* FIS device-to-host */
3242                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3243                 addr += phy->sas_phy.id;
3244                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3245         } else {
3246                 struct sas_identify_frame *idframe =
3247                         (void *) phy->sas_phy.frame_rcvd;
3248                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3249         }
3250 }
3251
3252 /**
3253  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3254  * @pm8001_ha: our hba card information
3255  * @Qnum: the outbound queue message number.
3256  * @SEA: source of event to ack
3257  * @port_id: port id.
3258  * @phyId: phy id.
3259  * @param0: parameter 0.
3260  * @param1: parameter 1.
3261  */
3262 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3263         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3264 {
3265         struct hw_event_ack_req  payload;
3266         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3267
3268         struct inbound_queue_table *circularQ;
3269
3270         memset((u8 *)&payload, 0, sizeof(payload));
3271         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3272         payload.tag = cpu_to_le32(1);
3273         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3274                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3275         payload.param0 = cpu_to_le32(param0);
3276         payload.param1 = cpu_to_le32(param1);
3277         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3278                         sizeof(payload), 0);
3279 }
3280
3281 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3282         u32 phyId, u32 phy_op);
3283
3284 /**
3285  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3286  * @pm8001_ha: our hba card information
3287  * @piomb: IO message buffer
3288  */
3289 static void
3290 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3291 {
3292         struct hw_event_resp *pPayload =
3293                 (struct hw_event_resp *)(piomb + 4);
3294         u32 lr_evt_status_phyid_portid =
3295                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3296         u8 link_rate =
3297                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3298         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3299         u8 phy_id =
3300                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3301         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3302         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3303         struct pm8001_port *port = &pm8001_ha->port[port_id];
3304         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3305         unsigned long flags;
3306         u8 deviceType = pPayload->sas_identify.dev_type;
3307         port->port_state =  portstate;
3308         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3309         pm8001_dbg(pm8001_ha, MSG,
3310                    "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3311                    port_id, phy_id);
3312
3313         switch (deviceType) {
3314         case SAS_PHY_UNUSED:
3315                 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3316                 break;
3317         case SAS_END_DEVICE:
3318                 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3319                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3320                         PHY_NOTIFY_ENABLE_SPINUP);
3321                 port->port_attached = 1;
3322                 pm8001_get_lrate_mode(phy, link_rate);
3323                 break;
3324         case SAS_EDGE_EXPANDER_DEVICE:
3325                 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3326                 port->port_attached = 1;
3327                 pm8001_get_lrate_mode(phy, link_rate);
3328                 break;
3329         case SAS_FANOUT_EXPANDER_DEVICE:
3330                 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3331                 port->port_attached = 1;
3332                 pm8001_get_lrate_mode(phy, link_rate);
3333                 break;
3334         default:
3335                 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3336                            deviceType);
3337                 break;
3338         }
3339         phy->phy_type |= PORT_TYPE_SAS;
3340         phy->identify.device_type = deviceType;
3341         phy->phy_attached = 1;
3342         if (phy->identify.device_type == SAS_END_DEVICE)
3343                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3344         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3345                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3346         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3347         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3348         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3349         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3350                 sizeof(struct sas_identify_frame)-4);
3351         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3352         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3353         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3354         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3355                 mdelay(200);/*delay a moment to wait disk to spinup*/
3356         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3357 }
3358
3359 /**
3360  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3361  * @pm8001_ha: our hba card information
3362  * @piomb: IO message buffer
3363  */
3364 static void
3365 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3366 {
3367         struct hw_event_resp *pPayload =
3368                 (struct hw_event_resp *)(piomb + 4);
3369         u32 lr_evt_status_phyid_portid =
3370                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3371         u8 link_rate =
3372                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3373         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3374         u8 phy_id =
3375                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3376         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3377         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3378         struct pm8001_port *port = &pm8001_ha->port[port_id];
3379         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3380         unsigned long flags;
3381         pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3382                    port_id, phy_id);
3383         port->port_state =  portstate;
3384         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3385         port->port_attached = 1;
3386         pm8001_get_lrate_mode(phy, link_rate);
3387         phy->phy_type |= PORT_TYPE_SATA;
3388         phy->phy_attached = 1;
3389         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3390         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3391         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3392         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3393                 sizeof(struct dev_to_host_fis));
3394         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3395         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3396         phy->identify.device_type = SAS_SATA_DEV;
3397         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3398         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3399         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3400 }
3401
3402 /**
3403  * hw_event_phy_down -we should notify the libsas the phy is down.
3404  * @pm8001_ha: our hba card information
3405  * @piomb: IO message buffer
3406  */
3407 static void
3408 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3409 {
3410         struct hw_event_resp *pPayload =
3411                 (struct hw_event_resp *)(piomb + 4);
3412         u32 lr_evt_status_phyid_portid =
3413                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3414         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3415         u8 phy_id =
3416                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3417         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3418         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3419         struct pm8001_port *port = &pm8001_ha->port[port_id];
3420         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3421         port->port_state =  portstate;
3422         phy->phy_type = 0;
3423         phy->identify.device_type = 0;
3424         phy->phy_attached = 0;
3425         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3426         switch (portstate) {
3427         case PORT_VALID:
3428                 break;
3429         case PORT_INVALID:
3430                 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3431                            port_id);
3432                 pm8001_dbg(pm8001_ha, MSG,
3433                            " Last phy Down and port invalid\n");
3434                 port->port_attached = 0;
3435                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3436                         port_id, phy_id, 0, 0);
3437                 break;
3438         case PORT_IN_RESET:
3439                 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3440                            port_id);
3441                 break;
3442         case PORT_NOT_ESTABLISHED:
3443                 pm8001_dbg(pm8001_ha, MSG,
3444                            " phy Down and PORT_NOT_ESTABLISHED\n");
3445                 port->port_attached = 0;
3446                 break;
3447         case PORT_LOSTCOMM:
3448                 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3449                 pm8001_dbg(pm8001_ha, MSG,
3450                            " Last phy Down and port invalid\n");
3451                 port->port_attached = 0;
3452                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3453                         port_id, phy_id, 0, 0);
3454                 break;
3455         default:
3456                 port->port_attached = 0;
3457                 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3458                            portstate);
3459                 break;
3460
3461         }
3462 }
3463
3464 /**
3465  * pm8001_mpi_reg_resp -process register device ID response.
3466  * @pm8001_ha: our hba card information
3467  * @piomb: IO message buffer
3468  *
3469  * when sas layer find a device it will notify LLDD, then the driver register
3470  * the domain device to FW, this event is the return device ID which the FW
3471  * has assigned, from now,inter-communication with FW is no longer using the
3472  * SAS address, use device ID which FW assigned.
3473  */
3474 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3475 {
3476         u32 status;
3477         u32 device_id;
3478         u32 htag;
3479         struct pm8001_ccb_info *ccb;
3480         struct pm8001_device *pm8001_dev;
3481         struct dev_reg_resp *registerRespPayload =
3482                 (struct dev_reg_resp *)(piomb + 4);
3483
3484         htag = le32_to_cpu(registerRespPayload->tag);
3485         ccb = &pm8001_ha->ccb_info[htag];
3486         pm8001_dev = ccb->device;
3487         status = le32_to_cpu(registerRespPayload->status);
3488         device_id = le32_to_cpu(registerRespPayload->device_id);
3489         pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3490                    status);
3491         switch (status) {
3492         case DEVREG_SUCCESS:
3493                 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3494                 pm8001_dev->device_id = device_id;
3495                 break;
3496         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3497                 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3498                 break;
3499         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3500                 pm8001_dbg(pm8001_ha, MSG,
3501                            "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3502                 break;
3503         case DEVREG_FAILURE_INVALID_PHY_ID:
3504                 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3505                 break;
3506         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3507                 pm8001_dbg(pm8001_ha, MSG,
3508                            "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3509                 break;
3510         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3511                 pm8001_dbg(pm8001_ha, MSG,
3512                            "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3513                 break;
3514         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3515                 pm8001_dbg(pm8001_ha, MSG,
3516                            "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3517                 break;
3518         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3519                 pm8001_dbg(pm8001_ha, MSG,
3520                            "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3521                 break;
3522         default:
3523                 pm8001_dbg(pm8001_ha, MSG,
3524                            "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3525                 break;
3526         }
3527         complete(pm8001_dev->dcompletion);
3528         ccb->task = NULL;
3529         ccb->ccb_tag = 0xFFFFFFFF;
3530         pm8001_tag_free(pm8001_ha, htag);
3531         return 0;
3532 }
3533
3534 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3535 {
3536         u32 status;
3537         u32 device_id;
3538         struct dev_reg_resp *registerRespPayload =
3539                 (struct dev_reg_resp *)(piomb + 4);
3540
3541         status = le32_to_cpu(registerRespPayload->status);
3542         device_id = le32_to_cpu(registerRespPayload->device_id);
3543         if (status != 0)
3544                 pm8001_dbg(pm8001_ha, MSG,
3545                            " deregister device failed ,status = %x, device_id = %x\n",
3546                            status, device_id);
3547         return 0;
3548 }
3549
3550 /**
3551  * fw_flash_update_resp - Response from FW for flash update command.
3552  * @pm8001_ha: our hba card information
3553  * @piomb: IO message buffer
3554  */
3555 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3556                 void *piomb)
3557 {
3558         u32 status;
3559         struct fw_flash_Update_resp *ppayload =
3560                 (struct fw_flash_Update_resp *)(piomb + 4);
3561         u32 tag = le32_to_cpu(ppayload->tag);
3562         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3563         status = le32_to_cpu(ppayload->status);
3564         switch (status) {
3565         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3566                 pm8001_dbg(pm8001_ha, MSG,
3567                            ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3568                 break;
3569         case FLASH_UPDATE_IN_PROGRESS:
3570                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3571                 break;
3572         case FLASH_UPDATE_HDR_ERR:
3573                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3574                 break;
3575         case FLASH_UPDATE_OFFSET_ERR:
3576                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3577                 break;
3578         case FLASH_UPDATE_CRC_ERR:
3579                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3580                 break;
3581         case FLASH_UPDATE_LENGTH_ERR:
3582                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3583                 break;
3584         case FLASH_UPDATE_HW_ERR:
3585                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3586                 break;
3587         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3588                 pm8001_dbg(pm8001_ha, MSG,
3589                            ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3590                 break;
3591         case FLASH_UPDATE_DISABLED:
3592                 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3593                 break;
3594         default:
3595                 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3596                            status);
3597                 break;
3598         }
3599         kfree(ccb->fw_control_context);
3600         ccb->task = NULL;
3601         ccb->ccb_tag = 0xFFFFFFFF;
3602         pm8001_tag_free(pm8001_ha, tag);
3603         complete(pm8001_ha->nvmd_completion);
3604         return 0;
3605 }
3606
3607 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3608 {
3609         u32 status;
3610         int i;
3611         struct general_event_resp *pPayload =
3612                 (struct general_event_resp *)(piomb + 4);
3613         status = le32_to_cpu(pPayload->status);
3614         pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3615         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3616                 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3617                            i,
3618                            pPayload->inb_IOMB_payload[i]);
3619         return 0;
3620 }
3621
3622 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3623 {
3624         struct sas_task *t;
3625         struct pm8001_ccb_info *ccb;
3626         unsigned long flags;
3627         u32 status ;
3628         u32 tag, scp;
3629         struct task_status_struct *ts;
3630         struct pm8001_device *pm8001_dev;
3631
3632         struct task_abort_resp *pPayload =
3633                 (struct task_abort_resp *)(piomb + 4);
3634
3635         status = le32_to_cpu(pPayload->status);
3636         tag = le32_to_cpu(pPayload->tag);
3637         if (!tag) {
3638                 pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n");
3639                 return -1;
3640         }
3641
3642         scp = le32_to_cpu(pPayload->scp);
3643         ccb = &pm8001_ha->ccb_info[tag];
3644         t = ccb->task;
3645         pm8001_dev = ccb->device; /* retrieve device */
3646
3647         if (!t) {
3648                 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3649                 return -1;
3650         }
3651         ts = &t->task_status;
3652         if (status != 0)
3653                 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3654                            status, tag, scp);
3655         switch (status) {
3656         case IO_SUCCESS:
3657                 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3658                 ts->resp = SAS_TASK_COMPLETE;
3659                 ts->stat = SAS_SAM_STAT_GOOD;
3660                 break;
3661         case IO_NOT_VALID:
3662                 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3663                 ts->resp = TMF_RESP_FUNC_FAILED;
3664                 break;
3665         }
3666         spin_lock_irqsave(&t->task_state_lock, flags);
3667         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3668         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3669         t->task_state_flags |= SAS_TASK_STATE_DONE;
3670         spin_unlock_irqrestore(&t->task_state_lock, flags);
3671         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3672         mb();
3673
3674         if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3675                 sas_free_task(t);
3676                 pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3677         } else {
3678                 t->task_done(t);
3679         }
3680
3681         return 0;
3682 }
3683
3684 /**
3685  * mpi_hw_event -The hw event has come.
3686  * @pm8001_ha: our hba card information
3687  * @piomb: IO message buffer
3688  */
3689 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3690 {
3691         unsigned long flags;
3692         struct hw_event_resp *pPayload =
3693                 (struct hw_event_resp *)(piomb + 4);
3694         u32 lr_evt_status_phyid_portid =
3695                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3696         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3697         u8 phy_id =
3698                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3699         u16 eventType =
3700                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3701         u8 status =
3702                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3703         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3704         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3705         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3706         pm8001_dbg(pm8001_ha, DEVIO,
3707                    "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3708                    port_id, phy_id, eventType, status);
3709         switch (eventType) {
3710         case HW_EVENT_PHY_START_STATUS:
3711                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3712                            status);
3713                 if (status == 0)
3714                         phy->phy_state = 1;
3715
3716                 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3717                                 phy->enable_completion != NULL) {
3718                         complete(phy->enable_completion);
3719                         phy->enable_completion = NULL;
3720                 }
3721                 break;
3722         case HW_EVENT_SAS_PHY_UP:
3723                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3724                 hw_event_sas_phy_up(pm8001_ha, piomb);
3725                 break;
3726         case HW_EVENT_SATA_PHY_UP:
3727                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3728                 hw_event_sata_phy_up(pm8001_ha, piomb);
3729                 break;
3730         case HW_EVENT_PHY_STOP_STATUS:
3731                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3732                            status);
3733                 if (status == 0)
3734                         phy->phy_state = 0;
3735                 break;
3736         case HW_EVENT_SATA_SPINUP_HOLD:
3737                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3738                 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3739                 break;
3740         case HW_EVENT_PHY_DOWN:
3741                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3742                 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3743                 phy->phy_attached = 0;
3744                 phy->phy_state = 0;
3745                 hw_event_phy_down(pm8001_ha, piomb);
3746                 break;
3747         case HW_EVENT_PORT_INVALID:
3748                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3749                 sas_phy_disconnected(sas_phy);
3750                 phy->phy_attached = 0;
3751                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3752                 break;
3753         /* the broadcast change primitive received, tell the LIBSAS this event
3754         to revalidate the sas domain*/
3755         case HW_EVENT_BROADCAST_CHANGE:
3756                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3757                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3758                         port_id, phy_id, 1, 0);
3759                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3760                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3761                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3762                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3763                 break;
3764         case HW_EVENT_PHY_ERROR:
3765                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3766                 sas_phy_disconnected(&phy->sas_phy);
3767                 phy->phy_attached = 0;
3768                 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3769                 break;
3770         case HW_EVENT_BROADCAST_EXP:
3771                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3772                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3773                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3774                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3775                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3776                 break;
3777         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3778                 pm8001_dbg(pm8001_ha, MSG,
3779                            "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3780                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3781                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3782                 sas_phy_disconnected(sas_phy);
3783                 phy->phy_attached = 0;
3784                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3785                 break;
3786         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3787                 pm8001_dbg(pm8001_ha, MSG,
3788                            "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3789                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3790                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3791                         port_id, phy_id, 0, 0);
3792                 sas_phy_disconnected(sas_phy);
3793                 phy->phy_attached = 0;
3794                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3795                 break;
3796         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3797                 pm8001_dbg(pm8001_ha, MSG,
3798                            "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3799                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3800                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3801                         port_id, phy_id, 0, 0);
3802                 sas_phy_disconnected(sas_phy);
3803                 phy->phy_attached = 0;
3804                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3805                 break;
3806         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3807                 pm8001_dbg(pm8001_ha, MSG,
3808                            "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3809                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3810                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3811                         port_id, phy_id, 0, 0);
3812                 sas_phy_disconnected(sas_phy);
3813                 phy->phy_attached = 0;
3814                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3815                 break;
3816         case HW_EVENT_MALFUNCTION:
3817                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3818                 break;
3819         case HW_EVENT_BROADCAST_SES:
3820                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3821                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3822                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3823                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3824                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3825                 break;
3826         case HW_EVENT_INBOUND_CRC_ERROR:
3827                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3828                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3829                         HW_EVENT_INBOUND_CRC_ERROR,
3830                         port_id, phy_id, 0, 0);
3831                 break;
3832         case HW_EVENT_HARD_RESET_RECEIVED:
3833                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3834                 sas_notify_port_event(sas_phy, PORTE_HARD_RESET);
3835                 break;
3836         case HW_EVENT_ID_FRAME_TIMEOUT:
3837                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3838                 sas_phy_disconnected(sas_phy);
3839                 phy->phy_attached = 0;
3840                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3841                 break;
3842         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3843                 pm8001_dbg(pm8001_ha, MSG,
3844                            "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3845                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3846                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3847                         port_id, phy_id, 0, 0);
3848                 sas_phy_disconnected(sas_phy);
3849                 phy->phy_attached = 0;
3850                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3851                 break;
3852         case HW_EVENT_PORT_RESET_TIMER_TMO:
3853                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3854                 sas_phy_disconnected(sas_phy);
3855                 phy->phy_attached = 0;
3856                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3857                 break;
3858         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3859                 pm8001_dbg(pm8001_ha, MSG,
3860                            "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3861                 sas_phy_disconnected(sas_phy);
3862                 phy->phy_attached = 0;
3863                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3864                 break;
3865         case HW_EVENT_PORT_RECOVER:
3866                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3867                 break;
3868         case HW_EVENT_PORT_RESET_COMPLETE:
3869                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3870                 break;
3871         case EVENT_BROADCAST_ASYNCH_EVENT:
3872                 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3873                 break;
3874         default:
3875                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3876                            eventType);
3877                 break;
3878         }
3879         return 0;
3880 }
3881
3882 /**
3883  * process_one_iomb - process one outbound Queue memory block
3884  * @pm8001_ha: our hba card information
3885  * @piomb: IO message buffer
3886  */
3887 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3888 {
3889         __le32 pHeader = *(__le32 *)piomb;
3890         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3891
3892         pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3893
3894         switch (opc) {
3895         case OPC_OUB_ECHO:
3896                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3897                 break;
3898         case OPC_OUB_HW_EVENT:
3899                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3900                 mpi_hw_event(pm8001_ha, piomb);
3901                 break;
3902         case OPC_OUB_SSP_COMP:
3903                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3904                 mpi_ssp_completion(pm8001_ha, piomb);
3905                 break;
3906         case OPC_OUB_SMP_COMP:
3907                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3908                 mpi_smp_completion(pm8001_ha, piomb);
3909                 break;
3910         case OPC_OUB_LOCAL_PHY_CNTRL:
3911                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3912                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3913                 break;
3914         case OPC_OUB_DEV_REGIST:
3915                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3916                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3917                 break;
3918         case OPC_OUB_DEREG_DEV:
3919                 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3920                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3921                 break;
3922         case OPC_OUB_GET_DEV_HANDLE:
3923                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3924                 break;
3925         case OPC_OUB_SATA_COMP:
3926                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3927                 mpi_sata_completion(pm8001_ha, piomb);
3928                 break;
3929         case OPC_OUB_SATA_EVENT:
3930                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3931                 mpi_sata_event(pm8001_ha, piomb);
3932                 break;
3933         case OPC_OUB_SSP_EVENT:
3934                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3935                 mpi_ssp_event(pm8001_ha, piomb);
3936                 break;
3937         case OPC_OUB_DEV_HANDLE_ARRIV:
3938                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3939                 /*This is for target*/
3940                 break;
3941         case OPC_OUB_SSP_RECV_EVENT:
3942                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3943                 /*This is for target*/
3944                 break;
3945         case OPC_OUB_DEV_INFO:
3946                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
3947                 break;
3948         case OPC_OUB_FW_FLASH_UPDATE:
3949                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3950                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3951                 break;
3952         case OPC_OUB_GPIO_RESPONSE:
3953                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3954                 break;
3955         case OPC_OUB_GPIO_EVENT:
3956                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3957                 break;
3958         case OPC_OUB_GENERAL_EVENT:
3959                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3960                 pm8001_mpi_general_event(pm8001_ha, piomb);
3961                 break;
3962         case OPC_OUB_SSP_ABORT_RSP:
3963                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3964                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3965                 break;
3966         case OPC_OUB_SATA_ABORT_RSP:
3967                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3968                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3969                 break;
3970         case OPC_OUB_SAS_DIAG_MODE_START_END:
3971                 pm8001_dbg(pm8001_ha, MSG,
3972                            "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3973                 break;
3974         case OPC_OUB_SAS_DIAG_EXECUTE:
3975                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3976                 break;
3977         case OPC_OUB_GET_TIME_STAMP:
3978                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3979                 break;
3980         case OPC_OUB_SAS_HW_EVENT_ACK:
3981                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3982                 break;
3983         case OPC_OUB_PORT_CONTROL:
3984                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3985                 break;
3986         case OPC_OUB_SMP_ABORT_RSP:
3987                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3988                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3989                 break;
3990         case OPC_OUB_GET_NVMD_DATA:
3991                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3992                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3993                 break;
3994         case OPC_OUB_SET_NVMD_DATA:
3995                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3996                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3997                 break;
3998         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3999                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
4000                 break;
4001         case OPC_OUB_SET_DEVICE_STATE:
4002                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
4003                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4004                 break;
4005         case OPC_OUB_GET_DEVICE_STATE:
4006                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4007                 break;
4008         case OPC_OUB_SET_DEV_INFO:
4009                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4010                 break;
4011         case OPC_OUB_SAS_RE_INITIALIZE:
4012                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
4013                 break;
4014         default:
4015                 pm8001_dbg(pm8001_ha, DEVIO,
4016                            "Unknown outbound Queue IOMB OPC = %x\n",
4017                            opc);
4018                 break;
4019         }
4020 }
4021
4022 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4023 {
4024         struct outbound_queue_table *circularQ;
4025         void *pMsg1 = NULL;
4026         u8 bc;
4027         u32 ret = MPI_IO_STATUS_FAIL;
4028         unsigned long flags;
4029
4030         spin_lock_irqsave(&pm8001_ha->lock, flags);
4031         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4032         do {
4033                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4034                 if (MPI_IO_STATUS_SUCCESS == ret) {
4035                         /* process the outbound message */
4036                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4037                         /* free the message from the outbound circular buffer */
4038                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4039                                                         circularQ, bc);
4040                 }
4041                 if (MPI_IO_STATUS_BUSY == ret) {
4042                         /* Update the producer index from SPC */
4043                         circularQ->producer_index =
4044                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4045                         if (le32_to_cpu(circularQ->producer_index) ==
4046                                 circularQ->consumer_idx)
4047                                 /* OQ is empty */
4048                                 break;
4049                 }
4050         } while (1);
4051         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4052         return ret;
4053 }
4054
4055 /* DMA_... to our direction translation. */
4056 static const u8 data_dir_flags[] = {
4057         [DMA_BIDIRECTIONAL]     = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4058         [DMA_TO_DEVICE]         = DATA_DIR_OUT,         /* OUTBOUND */
4059         [DMA_FROM_DEVICE]       = DATA_DIR_IN,          /* INBOUND */
4060         [DMA_NONE]              = DATA_DIR_NONE,        /* NO TRANSFER */
4061 };
4062 void
4063 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4064 {
4065         int i;
4066         struct scatterlist *sg;
4067         struct pm8001_prd *buf_prd = prd;
4068
4069         for_each_sg(scatter, sg, nr, i) {
4070                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4071                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4072                 buf_prd->im_len.e = 0;
4073                 buf_prd++;
4074         }
4075 }
4076
4077 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4078 {
4079         psmp_cmd->tag = hTag;
4080         psmp_cmd->device_id = cpu_to_le32(deviceID);
4081         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4082 }
4083
4084 /**
4085  * pm8001_chip_smp_req - send a SMP task to FW
4086  * @pm8001_ha: our hba card information.
4087  * @ccb: the ccb information this request used.
4088  */
4089 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4090         struct pm8001_ccb_info *ccb)
4091 {
4092         int elem, rc;
4093         struct sas_task *task = ccb->task;
4094         struct domain_device *dev = task->dev;
4095         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4096         struct scatterlist *sg_req, *sg_resp;
4097         u32 req_len, resp_len;
4098         struct smp_req smp_cmd;
4099         u32 opc;
4100         struct inbound_queue_table *circularQ;
4101
4102         memset(&smp_cmd, 0, sizeof(smp_cmd));
4103         /*
4104          * DMA-map SMP request, response buffers
4105          */
4106         sg_req = &task->smp_task.smp_req;
4107         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4108         if (!elem)
4109                 return -ENOMEM;
4110         req_len = sg_dma_len(sg_req);
4111
4112         sg_resp = &task->smp_task.smp_resp;
4113         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4114         if (!elem) {
4115                 rc = -ENOMEM;
4116                 goto err_out;
4117         }
4118         resp_len = sg_dma_len(sg_resp);
4119         /* must be in dwords */
4120         if ((req_len & 0x3) || (resp_len & 0x3)) {
4121                 rc = -EINVAL;
4122                 goto err_out_2;
4123         }
4124
4125         opc = OPC_INB_SMP_REQUEST;
4126         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4127         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4128         smp_cmd.long_smp_req.long_req_addr =
4129                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4130         smp_cmd.long_smp_req.long_req_size =
4131                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4132         smp_cmd.long_smp_req.long_resp_addr =
4133                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4134         smp_cmd.long_smp_req.long_resp_size =
4135                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4136         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4137         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4138                         &smp_cmd, sizeof(smp_cmd), 0);
4139         if (rc)
4140                 goto err_out_2;
4141
4142         return 0;
4143
4144 err_out_2:
4145         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4146                         DMA_FROM_DEVICE);
4147 err_out:
4148         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4149                         DMA_TO_DEVICE);
4150         return rc;
4151 }
4152
4153 /**
4154  * pm8001_chip_ssp_io_req - send a SSP task to FW
4155  * @pm8001_ha: our hba card information.
4156  * @ccb: the ccb information this request used.
4157  */
4158 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4159         struct pm8001_ccb_info *ccb)
4160 {
4161         struct sas_task *task = ccb->task;
4162         struct domain_device *dev = task->dev;
4163         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4164         struct ssp_ini_io_start_req ssp_cmd;
4165         u32 tag = ccb->ccb_tag;
4166         int ret;
4167         u64 phys_addr;
4168         struct inbound_queue_table *circularQ;
4169         u32 opc = OPC_INB_SSPINIIOSTART;
4170         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4171         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4172         ssp_cmd.dir_m_tlr =
4173                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4174         SAS 1.1 compatible TLR*/
4175         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4176         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4177         ssp_cmd.tag = cpu_to_le32(tag);
4178         if (task->ssp_task.enable_first_burst)
4179                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4180         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4181         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4182         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4183                task->ssp_task.cmd->cmd_len);
4184         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4185
4186         /* fill in PRD (scatter/gather) table, if any */
4187         if (task->num_scatter > 1) {
4188                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4189                 phys_addr = ccb->ccb_dma_handle;
4190                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4191                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4192                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4193         } else if (task->num_scatter == 1) {
4194                 u64 dma_addr = sg_dma_address(task->scatter);
4195                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4196                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4197                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4198                 ssp_cmd.esgl = 0;
4199         } else if (task->num_scatter == 0) {
4200                 ssp_cmd.addr_low = 0;
4201                 ssp_cmd.addr_high = 0;
4202                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4203                 ssp_cmd.esgl = 0;
4204         }
4205         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd,
4206                         sizeof(ssp_cmd), 0);
4207         return ret;
4208 }
4209
4210 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4211         struct pm8001_ccb_info *ccb)
4212 {
4213         struct sas_task *task = ccb->task;
4214         struct domain_device *dev = task->dev;
4215         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4216         u32 tag = ccb->ccb_tag;
4217         int ret;
4218         struct sata_start_req sata_cmd;
4219         u32 hdr_tag, ncg_tag = 0;
4220         u64 phys_addr;
4221         u32 ATAP = 0x0;
4222         u32 dir;
4223         struct inbound_queue_table *circularQ;
4224         unsigned long flags;
4225         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4226         memset(&sata_cmd, 0, sizeof(sata_cmd));
4227         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4228
4229         if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4230                 ATAP = 0x04;  /* no data*/
4231                 pm8001_dbg(pm8001_ha, IO, "no data\n");
4232         } else if (likely(!task->ata_task.device_control_reg_update)) {
4233                 if (task->ata_task.use_ncq &&
4234                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4235                         ATAP = 0x07; /* FPDMA */
4236                         pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4237                 } else if (task->ata_task.dma_xfer) {
4238                         ATAP = 0x06; /* DMA */
4239                         pm8001_dbg(pm8001_ha, IO, "DMA\n");
4240                 } else {
4241                         ATAP = 0x05; /* PIO*/
4242                         pm8001_dbg(pm8001_ha, IO, "PIO\n");
4243                 }
4244         }
4245         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4246                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4247                 ncg_tag = hdr_tag;
4248         }
4249         dir = data_dir_flags[task->data_dir] << 8;
4250         sata_cmd.tag = cpu_to_le32(tag);
4251         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4252         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4253         sata_cmd.ncqtag_atap_dir_m =
4254                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4255         sata_cmd.sata_fis = task->ata_task.fis;
4256         if (likely(!task->ata_task.device_control_reg_update))
4257                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4258         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4259         /* fill in PRD (scatter/gather) table, if any */
4260         if (task->num_scatter > 1) {
4261                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4262                 phys_addr = ccb->ccb_dma_handle;
4263                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4264                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4265                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4266         } else if (task->num_scatter == 1) {
4267                 u64 dma_addr = sg_dma_address(task->scatter);
4268                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4269                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4270                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4271                 sata_cmd.esgl = 0;
4272         } else if (task->num_scatter == 0) {
4273                 sata_cmd.addr_low = 0;
4274                 sata_cmd.addr_high = 0;
4275                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4276                 sata_cmd.esgl = 0;
4277         }
4278
4279         /* Check for read log for failed drive and return */
4280         if (sata_cmd.sata_fis.command == 0x2f) {
4281                 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4282                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4283                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4284                         struct task_status_struct *ts;
4285
4286                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4287                         ts = &task->task_status;
4288
4289                         spin_lock_irqsave(&task->task_state_lock, flags);
4290                         ts->resp = SAS_TASK_COMPLETE;
4291                         ts->stat = SAS_SAM_STAT_GOOD;
4292                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4293                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4294                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4295                         if (unlikely((task->task_state_flags &
4296                                         SAS_TASK_STATE_ABORTED))) {
4297                                 spin_unlock_irqrestore(&task->task_state_lock,
4298                                                         flags);
4299                                 pm8001_dbg(pm8001_ha, FAIL,
4300                                            "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4301                                            task, ts->resp,
4302                                            ts->stat);
4303                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4304                         } else {
4305                                 spin_unlock_irqrestore(&task->task_state_lock,
4306                                                         flags);
4307                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4308                                                                 ccb, tag);
4309                                 return 0;
4310                         }
4311                 }
4312         }
4313
4314         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
4315                         sizeof(sata_cmd), 0);
4316         return ret;
4317 }
4318
4319 /**
4320  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4321  * @pm8001_ha: our hba card information.
4322  * @phy_id: the phy id which we wanted to start up.
4323  */
4324 static int
4325 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4326 {
4327         struct phy_start_req payload;
4328         struct inbound_queue_table *circularQ;
4329         int ret;
4330         u32 tag = 0x01;
4331         u32 opcode = OPC_INB_PHYSTART;
4332         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4333         memset(&payload, 0, sizeof(payload));
4334         payload.tag = cpu_to_le32(tag);
4335         /*
4336          ** [0:7]   PHY Identifier
4337          ** [8:11]  link rate 1.5G, 3G, 6G
4338          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4339          ** [14]    0b disable spin up hold; 1b enable spin up hold
4340          */
4341         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4342                 LINKMODE_AUTO | LINKRATE_15 |
4343                 LINKRATE_30 | LINKRATE_60 | phy_id);
4344         payload.sas_identify.dev_type = SAS_END_DEVICE;
4345         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4346         memcpy(payload.sas_identify.sas_addr,
4347                 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4348         payload.sas_identify.phy_id = phy_id;
4349         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4350                         sizeof(payload), 0);
4351         return ret;
4352 }
4353
4354 /**
4355  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4356  * @pm8001_ha: our hba card information.
4357  * @phy_id: the phy id which we wanted to start up.
4358  */
4359 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4360                                     u8 phy_id)
4361 {
4362         struct phy_stop_req payload;
4363         struct inbound_queue_table *circularQ;
4364         int ret;
4365         u32 tag = 0x01;
4366         u32 opcode = OPC_INB_PHYSTOP;
4367         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4368         memset(&payload, 0, sizeof(payload));
4369         payload.tag = cpu_to_le32(tag);
4370         payload.phy_id = cpu_to_le32(phy_id);
4371         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4372                         sizeof(payload), 0);
4373         return ret;
4374 }
4375
4376 /*
4377  * see comments on pm8001_mpi_reg_resp.
4378  */
4379 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4380         struct pm8001_device *pm8001_dev, u32 flag)
4381 {
4382         struct reg_dev_req payload;
4383         u32     opc;
4384         u32 stp_sspsmp_sata = 0x4;
4385         struct inbound_queue_table *circularQ;
4386         u32 linkrate, phy_id;
4387         int rc, tag = 0xdeadbeef;
4388         struct pm8001_ccb_info *ccb;
4389         u8 retryFlag = 0x1;
4390         u16 firstBurstSize = 0;
4391         u16 ITNT = 2000;
4392         struct domain_device *dev = pm8001_dev->sas_device;
4393         struct domain_device *parent_dev = dev->parent;
4394         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4395
4396         memset(&payload, 0, sizeof(payload));
4397         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4398         if (rc)
4399                 return rc;
4400         ccb = &pm8001_ha->ccb_info[tag];
4401         ccb->device = pm8001_dev;
4402         ccb->ccb_tag = tag;
4403         payload.tag = cpu_to_le32(tag);
4404         if (flag == 1)
4405                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4406         else {
4407                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4408                         stp_sspsmp_sata = 0x00; /* stp*/
4409                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4410                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4411                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4412                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4413         }
4414         if (parent_dev && dev_is_expander(parent_dev->dev_type))
4415                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4416         else
4417                 phy_id = pm8001_dev->attached_phy;
4418         opc = OPC_INB_REG_DEV;
4419         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4420                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4421         payload.phyid_portid =
4422                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4423                 ((phy_id & 0x0F) << 4));
4424         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4425                 ((linkrate & 0x0F) * 0x1000000) |
4426                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4427         payload.firstburstsize_ITNexustimeout =
4428                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4429         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4430                 SAS_ADDR_SIZE);
4431         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4432                         sizeof(payload), 0);
4433         if (rc)
4434                 pm8001_tag_free(pm8001_ha, tag);
4435
4436         return rc;
4437 }
4438
4439 /*
4440  * see comments on pm8001_mpi_reg_resp.
4441  */
4442 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4443         u32 device_id)
4444 {
4445         struct dereg_dev_req payload;
4446         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4447         int ret;
4448         struct inbound_queue_table *circularQ;
4449
4450         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4451         memset(&payload, 0, sizeof(payload));
4452         payload.tag = cpu_to_le32(1);
4453         payload.device_id = cpu_to_le32(device_id);
4454         pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4455                    device_id);
4456         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4457                         sizeof(payload), 0);
4458         return ret;
4459 }
4460
4461 /**
4462  * pm8001_chip_phy_ctl_req - support the local phy operation
4463  * @pm8001_ha: our hba card information.
4464  * @phyId: the phy id which we wanted to operate
4465  * @phy_op: the phy operation to request
4466  */
4467 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4468         u32 phyId, u32 phy_op)
4469 {
4470         struct local_phy_ctl_req payload;
4471         struct inbound_queue_table *circularQ;
4472         int ret;
4473         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4474         memset(&payload, 0, sizeof(payload));
4475         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4476         payload.tag = cpu_to_le32(1);
4477         payload.phyop_phyid =
4478                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4479         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4480                         sizeof(payload), 0);
4481         return ret;
4482 }
4483
4484 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4485 {
4486 #ifdef PM8001_USE_MSIX
4487         return 1;
4488 #else
4489         u32 value;
4490
4491         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4492         if (value)
4493                 return 1;
4494         return 0;
4495 #endif
4496 }
4497
4498 /**
4499  * pm8001_chip_isr - PM8001 isr handler.
4500  * @pm8001_ha: our hba card information.
4501  * @vec: IRQ number
4502  */
4503 static irqreturn_t
4504 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4505 {
4506         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4507         pm8001_dbg(pm8001_ha, DEVIO,
4508                    "irq vec %d, ODMR:0x%x\n",
4509                    vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4510         process_oq(pm8001_ha, vec);
4511         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4512         return IRQ_HANDLED;
4513 }
4514
4515 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4516         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4517 {
4518         struct task_abort_req task_abort;
4519         struct inbound_queue_table *circularQ;
4520         int ret;
4521         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4522         memset(&task_abort, 0, sizeof(task_abort));
4523         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4524                 task_abort.abort_all = 0;
4525                 task_abort.device_id = cpu_to_le32(dev_id);
4526                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4527                 task_abort.tag = cpu_to_le32(cmd_tag);
4528         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4529                 task_abort.abort_all = cpu_to_le32(1);
4530                 task_abort.device_id = cpu_to_le32(dev_id);
4531                 task_abort.tag = cpu_to_le32(cmd_tag);
4532         }
4533         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
4534                         sizeof(task_abort), 0);
4535         return ret;
4536 }
4537
4538 /*
4539  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4540  */
4541 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4542         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4543 {
4544         u32 opc, device_id;
4545         int rc = TMF_RESP_FUNC_FAILED;
4546         pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4547                    cmd_tag, task_tag);
4548         if (pm8001_dev->dev_type == SAS_END_DEVICE)
4549                 opc = OPC_INB_SSP_ABORT;
4550         else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4551                 opc = OPC_INB_SATA_ABORT;
4552         else
4553                 opc = OPC_INB_SMP_ABORT;/* SMP */
4554         device_id = pm8001_dev->device_id;
4555         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4556                 task_tag, cmd_tag);
4557         if (rc != TMF_RESP_FUNC_COMPLETE)
4558                 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4559         return rc;
4560 }
4561
4562 /**
4563  * pm8001_chip_ssp_tm_req - built the task management command.
4564  * @pm8001_ha: our hba card information.
4565  * @ccb: the ccb information.
4566  * @tmf: task management function.
4567  */
4568 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4569         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4570 {
4571         struct sas_task *task = ccb->task;
4572         struct domain_device *dev = task->dev;
4573         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4574         u32 opc = OPC_INB_SSPINITMSTART;
4575         struct inbound_queue_table *circularQ;
4576         struct ssp_ini_tm_start_req sspTMCmd;
4577         int ret;
4578
4579         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4580         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4581         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4582         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4583         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4584         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4585         if (pm8001_ha->chip_id != chip_8001)
4586                 sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4587         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4588         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd,
4589                         sizeof(sspTMCmd), 0);
4590         return ret;
4591 }
4592
4593 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4594         void *payload)
4595 {
4596         u32 opc = OPC_INB_GET_NVMD_DATA;
4597         u32 nvmd_type;
4598         int rc;
4599         u32 tag;
4600         struct pm8001_ccb_info *ccb;
4601         struct inbound_queue_table *circularQ;
4602         struct get_nvm_data_req nvmd_req;
4603         struct fw_control_ex *fw_control_context;
4604         struct pm8001_ioctl_payload *ioctl_payload = payload;
4605
4606         nvmd_type = ioctl_payload->minor_function;
4607         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4608         if (!fw_control_context)
4609                 return -ENOMEM;
4610         fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4611         fw_control_context->len = ioctl_payload->rd_length;
4612         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4613         memset(&nvmd_req, 0, sizeof(nvmd_req));
4614         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4615         if (rc) {
4616                 kfree(fw_control_context);
4617                 return rc;
4618         }
4619         ccb = &pm8001_ha->ccb_info[tag];
4620         ccb->ccb_tag = tag;
4621         ccb->fw_control_context = fw_control_context;
4622         nvmd_req.tag = cpu_to_le32(tag);
4623
4624         switch (nvmd_type) {
4625         case TWI_DEVICE: {
4626                 u32 twi_addr, twi_page_size;
4627                 twi_addr = 0xa8;
4628                 twi_page_size = 2;
4629
4630                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4631                         twi_page_size << 8 | TWI_DEVICE);
4632                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4633                 nvmd_req.resp_addr_hi =
4634                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4635                 nvmd_req.resp_addr_lo =
4636                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4637                 break;
4638         }
4639         case C_SEEPROM: {
4640                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4641                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4642                 nvmd_req.resp_addr_hi =
4643                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4644                 nvmd_req.resp_addr_lo =
4645                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4646                 break;
4647         }
4648         case VPD_FLASH: {
4649                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4650                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4651                 nvmd_req.resp_addr_hi =
4652                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4653                 nvmd_req.resp_addr_lo =
4654                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4655                 break;
4656         }
4657         case EXPAN_ROM: {
4658                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4659                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4660                 nvmd_req.resp_addr_hi =
4661                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4662                 nvmd_req.resp_addr_lo =
4663                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4664                 break;
4665         }
4666         case IOP_RDUMP: {
4667                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4668                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4669                 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4670                 nvmd_req.resp_addr_hi =
4671                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4672                 nvmd_req.resp_addr_lo =
4673                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4674                 break;
4675         }
4676         default:
4677                 break;
4678         }
4679         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4680                         sizeof(nvmd_req), 0);
4681         if (rc) {
4682                 kfree(fw_control_context);
4683                 pm8001_tag_free(pm8001_ha, tag);
4684         }
4685         return rc;
4686 }
4687
4688 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4689         void *payload)
4690 {
4691         u32 opc = OPC_INB_SET_NVMD_DATA;
4692         u32 nvmd_type;
4693         int rc;
4694         u32 tag;
4695         struct pm8001_ccb_info *ccb;
4696         struct inbound_queue_table *circularQ;
4697         struct set_nvm_data_req nvmd_req;
4698         struct fw_control_ex *fw_control_context;
4699         struct pm8001_ioctl_payload *ioctl_payload = payload;
4700
4701         nvmd_type = ioctl_payload->minor_function;
4702         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4703         if (!fw_control_context)
4704                 return -ENOMEM;
4705         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4706         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4707                 &ioctl_payload->func_specific,
4708                 ioctl_payload->wr_length);
4709         memset(&nvmd_req, 0, sizeof(nvmd_req));
4710         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4711         if (rc) {
4712                 kfree(fw_control_context);
4713                 return -EBUSY;
4714         }
4715         ccb = &pm8001_ha->ccb_info[tag];
4716         ccb->fw_control_context = fw_control_context;
4717         ccb->ccb_tag = tag;
4718         nvmd_req.tag = cpu_to_le32(tag);
4719         switch (nvmd_type) {
4720         case TWI_DEVICE: {
4721                 u32 twi_addr, twi_page_size;
4722                 twi_addr = 0xa8;
4723                 twi_page_size = 2;
4724                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4725                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4726                         twi_page_size << 8 | TWI_DEVICE);
4727                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4728                 nvmd_req.resp_addr_hi =
4729                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4730                 nvmd_req.resp_addr_lo =
4731                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4732                 break;
4733         }
4734         case C_SEEPROM:
4735                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4736                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4737                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4738                 nvmd_req.resp_addr_hi =
4739                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4740                 nvmd_req.resp_addr_lo =
4741                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4742                 break;
4743         case VPD_FLASH:
4744                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4745                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4746                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4747                 nvmd_req.resp_addr_hi =
4748                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4749                 nvmd_req.resp_addr_lo =
4750                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4751                 break;
4752         case EXPAN_ROM:
4753                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4754                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4755                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4756                 nvmd_req.resp_addr_hi =
4757                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4758                 nvmd_req.resp_addr_lo =
4759                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4760                 break;
4761         default:
4762                 break;
4763         }
4764         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4765                         sizeof(nvmd_req), 0);
4766         if (rc) {
4767                 kfree(fw_control_context);
4768                 pm8001_tag_free(pm8001_ha, tag);
4769         }
4770         return rc;
4771 }
4772
4773 /**
4774  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4775  * @pm8001_ha: our hba card information.
4776  * @fw_flash_updata_info: firmware flash update param
4777  * @tag: Tag to apply to the payload
4778  */
4779 int
4780 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4781         void *fw_flash_updata_info, u32 tag)
4782 {
4783         struct fw_flash_Update_req payload;
4784         struct fw_flash_updata_info *info;
4785         struct inbound_queue_table *circularQ;
4786         int ret;
4787         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4788
4789         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4790         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4791         info = fw_flash_updata_info;
4792         payload.tag = cpu_to_le32(tag);
4793         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4794         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4795         payload.total_image_len = cpu_to_le32(info->total_image_len);
4796         payload.len = info->sgl.im_len.len ;
4797         payload.sgl_addr_lo =
4798                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4799         payload.sgl_addr_hi =
4800                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4801         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4802                         sizeof(payload), 0);
4803         return ret;
4804 }
4805
4806 int
4807 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4808         void *payload)
4809 {
4810         struct fw_flash_updata_info flash_update_info;
4811         struct fw_control_info *fw_control;
4812         struct fw_control_ex *fw_control_context;
4813         int rc;
4814         u32 tag;
4815         struct pm8001_ccb_info *ccb;
4816         void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4817         dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4818         struct pm8001_ioctl_payload *ioctl_payload = payload;
4819
4820         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4821         if (!fw_control_context)
4822                 return -ENOMEM;
4823         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4824         pm8001_dbg(pm8001_ha, DEVIO,
4825                    "dma fw_control context input length :%x\n",
4826                    fw_control->len);
4827         memcpy(buffer, fw_control->buffer, fw_control->len);
4828         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4829         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4830         flash_update_info.sgl.im_len.e = 0;
4831         flash_update_info.cur_image_offset = fw_control->offset;
4832         flash_update_info.cur_image_len = fw_control->len;
4833         flash_update_info.total_image_len = fw_control->size;
4834         fw_control_context->fw_control = fw_control;
4835         fw_control_context->virtAddr = buffer;
4836         fw_control_context->phys_addr = phys_addr;
4837         fw_control_context->len = fw_control->len;
4838         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4839         if (rc) {
4840                 kfree(fw_control_context);
4841                 return -EBUSY;
4842         }
4843         ccb = &pm8001_ha->ccb_info[tag];
4844         ccb->fw_control_context = fw_control_context;
4845         ccb->ccb_tag = tag;
4846         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4847                 tag);
4848         if (rc) {
4849                 kfree(fw_control_context);
4850                 pm8001_tag_free(pm8001_ha, tag);
4851         }
4852
4853         return rc;
4854 }
4855
4856 ssize_t
4857 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4858 {
4859         u32 value, rem, offset = 0, bar = 0;
4860         u32 index, work_offset, dw_length;
4861         u32 shift_value, gsm_base, gsm_dump_offset;
4862         char *direct_data;
4863         struct Scsi_Host *shost = class_to_shost(cdev);
4864         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4865         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4866
4867         direct_data = buf;
4868         gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4869
4870         /* check max is 1 Mbytes */
4871         if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4872                 ((gsm_dump_offset + length) > 0x1000000))
4873                         return -EINVAL;
4874
4875         if (pm8001_ha->chip_id == chip_8001)
4876                 bar = 2;
4877         else
4878                 bar = 1;
4879
4880         work_offset = gsm_dump_offset & 0xFFFF0000;
4881         offset = gsm_dump_offset & 0x0000FFFF;
4882         gsm_dump_offset = work_offset;
4883         /* adjust length to dword boundary */
4884         rem = length & 3;
4885         dw_length = length >> 2;
4886
4887         for (index = 0; index < dw_length; index++) {
4888                 if ((work_offset + offset) & 0xFFFF0000) {
4889                         if (pm8001_ha->chip_id == chip_8001)
4890                                 shift_value = ((gsm_dump_offset + offset) &
4891                                                 SHIFT_REG_64K_MASK);
4892                         else
4893                                 shift_value = (((gsm_dump_offset + offset) &
4894                                                 SHIFT_REG_64K_MASK) >>
4895                                                 SHIFT_REG_BIT_SHIFT);
4896
4897                         if (pm8001_ha->chip_id == chip_8001) {
4898                                 gsm_base = GSM_BASE;
4899                                 if (-1 == pm8001_bar4_shift(pm8001_ha,
4900                                                 (gsm_base + shift_value)))
4901                                         return -EIO;
4902                         } else {
4903                                 gsm_base = 0;
4904                                 if (-1 == pm80xx_bar4_shift(pm8001_ha,
4905                                                 (gsm_base + shift_value)))
4906                                         return -EIO;
4907                         }
4908                         gsm_dump_offset = (gsm_dump_offset + offset) &
4909                                                 0xFFFF0000;
4910                         work_offset = 0;
4911                         offset = offset & 0x0000FFFF;
4912                 }
4913                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4914                                                 0x0000FFFF);
4915                 direct_data += sprintf(direct_data, "%08x ", value);
4916                 offset += 4;
4917         }
4918         if (rem != 0) {
4919                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4920                                                 0x0000FFFF);
4921                 /* xfr for non_dw */
4922                 direct_data += sprintf(direct_data, "%08x ", value);
4923         }
4924         /* Shift back to BAR4 original address */
4925         if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4926                         return -EIO;
4927         pm8001_ha->fatal_forensic_shift_offset += 1024;
4928
4929         if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4930                 pm8001_ha->fatal_forensic_shift_offset = 0;
4931         return direct_data - buf;
4932 }
4933
4934 int
4935 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4936         struct pm8001_device *pm8001_dev, u32 state)
4937 {
4938         struct set_dev_state_req payload;
4939         struct inbound_queue_table *circularQ;
4940         struct pm8001_ccb_info *ccb;
4941         int rc;
4942         u32 tag;
4943         u32 opc = OPC_INB_SET_DEVICE_STATE;
4944         memset(&payload, 0, sizeof(payload));
4945         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4946         if (rc)
4947                 return -1;
4948         ccb = &pm8001_ha->ccb_info[tag];
4949         ccb->ccb_tag = tag;
4950         ccb->device = pm8001_dev;
4951         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4952         payload.tag = cpu_to_le32(tag);
4953         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4954         payload.nds = cpu_to_le32(state);
4955         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4956                         sizeof(payload), 0);
4957         if (rc)
4958                 pm8001_tag_free(pm8001_ha, tag);
4959
4960         return rc;
4961
4962 }
4963
4964 static int
4965 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4966 {
4967         struct sas_re_initialization_req payload;
4968         struct inbound_queue_table *circularQ;
4969         struct pm8001_ccb_info *ccb;
4970         int rc;
4971         u32 tag;
4972         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4973         memset(&payload, 0, sizeof(payload));
4974         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4975         if (rc)
4976                 return -ENOMEM;
4977         ccb = &pm8001_ha->ccb_info[tag];
4978         ccb->ccb_tag = tag;
4979         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4980         payload.tag = cpu_to_le32(tag);
4981         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4982         payload.sata_hol_tmo = cpu_to_le32(80);
4983         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4984         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4985                         sizeof(payload), 0);
4986         if (rc)
4987                 pm8001_tag_free(pm8001_ha, tag);
4988         return rc;
4989
4990 }
4991
4992 const struct pm8001_dispatch pm8001_8001_dispatch = {
4993         .name                   = "pmc8001",
4994         .chip_init              = pm8001_chip_init,
4995         .chip_soft_rst          = pm8001_chip_soft_rst,
4996         .chip_rst               = pm8001_hw_chip_rst,
4997         .chip_iounmap           = pm8001_chip_iounmap,
4998         .isr                    = pm8001_chip_isr,
4999         .is_our_interrupt       = pm8001_chip_is_our_interrupt,
5000         .isr_process_oq         = process_oq,
5001         .interrupt_enable       = pm8001_chip_interrupt_enable,
5002         .interrupt_disable      = pm8001_chip_interrupt_disable,
5003         .make_prd               = pm8001_chip_make_sg,
5004         .smp_req                = pm8001_chip_smp_req,
5005         .ssp_io_req             = pm8001_chip_ssp_io_req,
5006         .sata_req               = pm8001_chip_sata_req,
5007         .phy_start_req          = pm8001_chip_phy_start_req,
5008         .phy_stop_req           = pm8001_chip_phy_stop_req,
5009         .reg_dev_req            = pm8001_chip_reg_dev_req,
5010         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5011         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
5012         .task_abort             = pm8001_chip_abort_task,
5013         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5014         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5015         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5016         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5017         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5018         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
5019 };