GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / scsi / myrb.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
4  *
5  * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
6  *
7  * Based on the original DAC960 driver,
8  * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
9  * Portions Copyright 2002 by Mylex (An IBM Business Unit)
10  *
11  */
12
13 #ifndef MYRB_H
14 #define MYRB_H
15
16 #define MYRB_MAX_LDEVS                  32
17 #define MYRB_MAX_CHANNELS               3
18 #define MYRB_MAX_TARGETS                16
19 #define MYRB_MAX_PHYSICAL_DEVICES       45
20 #define MYRB_SCATTER_GATHER_LIMIT       32
21 #define MYRB_CMD_MBOX_COUNT             256
22 #define MYRB_STAT_MBOX_COUNT            1024
23
24 #define MYRB_BLKSIZE_BITS               9
25 #define MYRB_MAILBOX_TIMEOUT            1000000
26
27 #define MYRB_DCMD_TAG                   1
28 #define MYRB_MCMD_TAG                   2
29
30 #define MYRB_PRIMARY_MONITOR_INTERVAL (10 * HZ)
31 #define MYRB_SECONDARY_MONITOR_INTERVAL (60 * HZ)
32
33 /*
34  * DAC960 V1 Firmware Command Opcodes.
35  */
36 enum myrb_cmd_opcode {
37         /* I/O Commands */
38         MYRB_CMD_READ_EXTENDED =        0x33,
39         MYRB_CMD_WRITE_EXTENDED =       0x34,
40         MYRB_CMD_READAHEAD_EXTENDED =   0x35,
41         MYRB_CMD_READ_EXTENDED_SG =     0xB3,
42         MYRB_CMD_WRITE_EXTENDED_SG =    0xB4,
43         MYRB_CMD_READ =                 0x36,
44         MYRB_CMD_READ_SG =              0xB6,
45         MYRB_CMD_WRITE =                0x37,
46         MYRB_CMD_WRITE_SG =             0xB7,
47         MYRB_CMD_DCDB =                 0x04,
48         MYRB_CMD_DCDB_SG =              0x84,
49         MYRB_CMD_FLUSH =                0x0A,
50         /* Controller Status Related Commands */
51         MYRB_CMD_ENQUIRY =              0x53,
52         MYRB_CMD_ENQUIRY2 =             0x1C,
53         MYRB_CMD_GET_LDRV_ELEMENT =     0x55,
54         MYRB_CMD_GET_LDEV_INFO =        0x19,
55         MYRB_CMD_IOPORTREAD =           0x39,
56         MYRB_CMD_IOPORTWRITE =          0x3A,
57         MYRB_CMD_GET_SD_STATS =         0x3E,
58         MYRB_CMD_GET_PD_STATS =         0x3F,
59         MYRB_CMD_EVENT_LOG_OPERATION =  0x72,
60         /* Device Related Commands */
61         MYRB_CMD_START_DEVICE =         0x10,
62         MYRB_CMD_GET_DEVICE_STATE =     0x50,
63         MYRB_CMD_STOP_CHANNEL =         0x13,
64         MYRB_CMD_START_CHANNEL =        0x12,
65         MYRB_CMD_RESET_CHANNEL =        0x1A,
66         /* Commands Associated with Data Consistency and Errors */
67         MYRB_CMD_REBUILD =              0x09,
68         MYRB_CMD_REBUILD_ASYNC =        0x16,
69         MYRB_CMD_CHECK_CONSISTENCY =    0x0F,
70         MYRB_CMD_CHECK_CONSISTENCY_ASYNC = 0x1E,
71         MYRB_CMD_REBUILD_STAT =         0x0C,
72         MYRB_CMD_GET_REBUILD_PROGRESS = 0x27,
73         MYRB_CMD_REBUILD_CONTROL =      0x1F,
74         MYRB_CMD_READ_BADBLOCK_TABLE =  0x0B,
75         MYRB_CMD_READ_BADDATA_TABLE =   0x25,
76         MYRB_CMD_CLEAR_BADDATA_TABLE =  0x26,
77         MYRB_CMD_GET_ERROR_TABLE =      0x17,
78         MYRB_CMD_ADD_CAPACITY_ASYNC =   0x2A,
79         MYRB_CMD_BGI_CONTROL =          0x2B,
80         /* Configuration Related Commands */
81         MYRB_CMD_READ_CONFIG2 =         0x3D,
82         MYRB_CMD_WRITE_CONFIG2 =        0x3C,
83         MYRB_CMD_READ_CONFIG_ONDISK =   0x4A,
84         MYRB_CMD_WRITE_CONFIG_ONDISK =  0x4B,
85         MYRB_CMD_READ_CONFIG =          0x4E,
86         MYRB_CMD_READ_BACKUP_CONFIG =   0x4D,
87         MYRB_CMD_WRITE_CONFIG =         0x4F,
88         MYRB_CMD_ADD_CONFIG =           0x4C,
89         MYRB_CMD_READ_CONFIG_LABEL =    0x48,
90         MYRB_CMD_WRITE_CONFIG_LABEL =   0x49,
91         /* Firmware Upgrade Related Commands */
92         MYRB_CMD_LOAD_IMAGE =           0x20,
93         MYRB_CMD_STORE_IMAGE =          0x21,
94         MYRB_CMD_PROGRAM_IMAGE =        0x22,
95         /* Diagnostic Commands */
96         MYRB_CMD_SET_DIAGNOSTIC_MODE =  0x31,
97         MYRB_CMD_RUN_DIAGNOSTIC =       0x32,
98         /* Subsystem Service Commands */
99         MYRB_CMD_GET_SUBSYS_DATA =      0x70,
100         MYRB_CMD_SET_SUBSYS_PARAM =     0x71,
101         /* Version 2.xx Firmware Commands */
102         MYRB_CMD_ENQUIRY_OLD =          0x05,
103         MYRB_CMD_GET_DEVICE_STATE_OLD = 0x14,
104         MYRB_CMD_READ_OLD =             0x02,
105         MYRB_CMD_WRITE_OLD =            0x03,
106         MYRB_CMD_READ_SG_OLD =          0x82,
107         MYRB_CMD_WRITE_SG_OLD =         0x83
108 } __packed;
109
110 /*
111  * DAC960 V1 Firmware Command Status Codes.
112  */
113 #define MYRB_STATUS_SUCCESS                     0x0000  /* Common */
114 #define MYRB_STATUS_CHECK_CONDITION             0x0002  /* Common */
115 #define MYRB_STATUS_NO_DEVICE                   0x0102  /* Common */
116 #define MYRB_STATUS_INVALID_ADDRESS             0x0105  /* Common */
117 #define MYRB_STATUS_INVALID_PARAM               0x0105  /* Common */
118 #define MYRB_STATUS_IRRECOVERABLE_DATA_ERROR    0x0001  /* I/O */
119 #define MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE 0x0002  /* I/O */
120 #define MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV   0x0105  /* I/O */
121 #define MYRB_STATUS_BAD_DATA                    0x010C  /* I/O */
122 #define MYRB_STATUS_DEVICE_BUSY                 0x0008  /* DCDB */
123 #define MYRB_STATUS_DEVICE_NONRESPONSIVE        0x000E  /* DCDB */
124 #define MYRB_STATUS_COMMAND_TERMINATED          0x000F  /* DCDB */
125 #define MYRB_STATUS_START_DEVICE_FAILED         0x0002  /* Device */
126 #define MYRB_STATUS_INVALID_CHANNEL_OR_TARGET   0x0105  /* Device */
127 #define MYRB_STATUS_CHANNEL_BUSY                0x0106  /* Device */
128 #define MYRB_STATUS_OUT_OF_MEMORY               0x0107  /* Device */
129 #define MYRB_STATUS_CHANNEL_NOT_STOPPED         0x0002  /* Device */
130 #define MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE 0x0002 /* Consistency */
131 #define MYRB_STATUS_RBLD_BADBLOCKS              0x0003  /* Consistency */
132 #define MYRB_STATUS_RBLD_NEW_DISK_FAILED        0x0004  /* Consistency */
133 #define MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS    0x0106  /* Consistency */
134 #define MYRB_STATUS_DEPENDENT_DISK_DEAD         0x0002  /* Consistency */
135 #define MYRB_STATUS_INCONSISTENT_BLOCKS         0x0003  /* Consistency */
136 #define MYRB_STATUS_INVALID_OR_NONREDUNDANT_LDRV 0x0105 /* Consistency */
137 #define MYRB_STATUS_NO_RBLD_OR_CHECK_INPROGRESS 0x0105  /* Consistency */
138 #define MYRB_STATUS_RBLD_IN_PROGRESS_DATA_VALID 0x0000  /* Consistency */
139 #define MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE    0x0002  /* Consistency */
140 #define MYRB_STATUS_RBLD_FAILED_BADBLOCKS       0x0003  /* Consistency */
141 #define MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED 0x0004 /* Consistency */
142 #define MYRB_STATUS_RBLD_SUCCESS                0x0100  /* Consistency */
143 #define MYRB_STATUS_RBLD_SUCCESS_TERMINATED     0x0107  /* Consistency */
144 #define MYRB_STATUS_RBLD_NOT_CHECKED            0x0108  /* Consistency */
145 #define MYRB_STATUS_BGI_SUCCESS                 0x0100  /* Consistency */
146 #define MYRB_STATUS_BGI_ABORTED                 0x0005  /* Consistency */
147 #define MYRB_STATUS_NO_BGI_INPROGRESS           0x0105  /* Consistency */
148 #define MYRB_STATUS_ADD_CAPACITY_INPROGRESS     0x0004  /* Consistency */
149 #define MYRB_STATUS_ADD_CAPACITY_FAILED_OR_SUSPENDED 0x00F4 /* Consistency */
150 #define MYRB_STATUS_CONFIG2_CSUM_ERROR          0x0002  /* Configuration */
151 #define MYRB_STATUS_CONFIGURATION_SUSPENDED     0x0106  /* Configuration */
152 #define MYRB_STATUS_FAILED_TO_CONFIGURE_NVRAM   0x0105  /* Configuration */
153 #define MYRB_STATUS_CONFIGURATION_NOT_SAVED     0x0106  /* Configuration */
154 #define MYRB_STATUS_SUBSYS_NOTINSTALLED         0x0001  /* Subsystem */
155 #define MYRB_STATUS_SUBSYS_FAILED               0x0002  /* Subsystem */
156 #define MYRB_STATUS_SUBSYS_BUSY                 0x0106  /* Subsystem */
157 #define MYRB_STATUS_SUBSYS_TIMEOUT              0x0108  /* Subsystem */
158
159 /*
160  * DAC960 V1 Firmware Enquiry Command reply structure.
161  */
162 struct myrb_enquiry {
163         unsigned char ldev_count;                       /* Byte 0 */
164         unsigned int rsvd1:24;                          /* Bytes 1-3 */
165         unsigned int ldev_sizes[32];                    /* Bytes 4-131 */
166         unsigned short flash_age;                       /* Bytes 132-133 */
167         struct {
168                 unsigned char deferred:1;               /* Byte 134 Bit 0 */
169                 unsigned char low_bat:1;                /* Byte 134 Bit 1 */
170                 unsigned char rsvd2:6;                  /* Byte 134 Bits 2-7 */
171         } status;
172         unsigned char rsvd3:8;                          /* Byte 135 */
173         unsigned char fw_minor_version;                 /* Byte 136 */
174         unsigned char fw_major_version;                 /* Byte 137 */
175         enum {
176                 MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS =       0x00,
177                 MYRB_STDBY_RBLD_IN_PROGRESS =                   0x01,
178                 MYRB_BG_RBLD_IN_PROGRESS =                      0x02,
179                 MYRB_BG_CHECK_IN_PROGRESS =                     0x03,
180                 MYRB_STDBY_RBLD_COMPLETED_WITH_ERROR =          0xFF,
181                 MYRB_BG_RBLD_OR_CHECK_FAILED_DRIVE_FAILED =     0xF0,
182                 MYRB_BG_RBLD_OR_CHECK_FAILED_LDEV_FAILED =      0xF1,
183                 MYRB_BG_RBLD_OR_CHECK_FAILED_OTHER =            0xF2,
184                 MYRB_BG_RBLD_OR_CHECK_SUCCESS_TERMINATED =      0xF3
185         } __packed rbld;                /* Byte 138 */
186         unsigned char max_tcq;                          /* Byte 139 */
187         unsigned char ldev_offline;                     /* Byte 140 */
188         unsigned char rsvd4:8;                          /* Byte 141 */
189         unsigned short ev_seq;                          /* Bytes 142-143 */
190         unsigned char ldev_critical;                    /* Byte 144 */
191         unsigned int rsvd5:24;                          /* Bytes 145-147 */
192         unsigned char pdev_dead;                        /* Byte 148 */
193         unsigned char rsvd6:8;                          /* Byte 149 */
194         unsigned char rbld_count;                       /* Byte 150 */
195         struct {
196                 unsigned char rsvd7:3;                  /* Byte 151 Bits 0-2 */
197                 unsigned char bbu_present:1;            /* Byte 151 Bit 3 */
198                 unsigned char rsvd8:4;                  /* Byte 151 Bits 4-7 */
199         } misc;
200         struct {
201                 unsigned char target;
202                 unsigned char channel;
203         } dead_drives[21];                              /* Bytes 152-194 */
204         unsigned char rsvd9[62];                        /* Bytes 195-255 */
205 } __packed;
206
207 /*
208  * DAC960 V1 Firmware Enquiry2 Command reply structure.
209  */
210 struct myrb_enquiry2 {
211         struct {
212                 enum {
213                         DAC960_V1_P_PD_PU =                     0x01,
214                         DAC960_V1_PL =                          0x02,
215                         DAC960_V1_PG =                          0x10,
216                         DAC960_V1_PJ =                          0x11,
217                         DAC960_V1_PR =                          0x12,
218                         DAC960_V1_PT =                          0x13,
219                         DAC960_V1_PTL0 =                        0x14,
220                         DAC960_V1_PRL =                         0x15,
221                         DAC960_V1_PTL1 =                        0x16,
222                         DAC960_V1_1164P =                       0x20
223                 } __packed sub_model;           /* Byte 0 */
224                 unsigned char actual_channels;                  /* Byte 1 */
225                 enum {
226                         MYRB_5_CHANNEL_BOARD =          0x01,
227                         MYRB_3_CHANNEL_BOARD =          0x02,
228                         MYRB_2_CHANNEL_BOARD =          0x03,
229                         MYRB_3_CHANNEL_ASIC_DAC =       0x04
230                 } __packed model;               /* Byte 2 */
231                 enum {
232                         MYRB_EISA_CONTROLLER =          0x01,
233                         MYRB_MCA_CONTROLLER =           0x02,
234                         MYRB_PCI_CONTROLLER =           0x03,
235                         MYRB_SCSI_TO_SCSI =             0x08
236                 } __packed controller;  /* Byte 3 */
237         } hw;                                           /* Bytes 0-3 */
238         /* MajorVersion.MinorVersion-FirmwareType-TurnID */
239         struct {
240                 unsigned char major_version;            /* Byte 4 */
241                 unsigned char minor_version;            /* Byte 5 */
242                 unsigned char turn_id;                  /* Byte 6 */
243                 char firmware_type;                     /* Byte 7 */
244         } fw;                                           /* Bytes 4-7 */
245         unsigned int rsvd1;                             /* Byte 8-11 */
246         unsigned char cfg_chan;                         /* Byte 12 */
247         unsigned char cur_chan;                         /* Byte 13 */
248         unsigned char max_targets;                      /* Byte 14 */
249         unsigned char max_tcq;                          /* Byte 15 */
250         unsigned char max_ldev;                         /* Byte 16 */
251         unsigned char max_arms;                         /* Byte 17 */
252         unsigned char max_spans;                        /* Byte 18 */
253         unsigned char rsvd2;                            /* Byte 19 */
254         unsigned int rsvd3;                             /* Bytes 20-23 */
255         unsigned int mem_size;                          /* Bytes 24-27 */
256         unsigned int cache_size;                        /* Bytes 28-31 */
257         unsigned int flash_size;                        /* Bytes 32-35 */
258         unsigned int nvram_size;                        /* Bytes 36-39 */
259         struct {
260                 enum {
261                         MYRB_RAM_TYPE_DRAM =            0x0,
262                         MYRB_RAM_TYPE_EDO =                     0x1,
263                         MYRB_RAM_TYPE_SDRAM =           0x2,
264                         MYRB_RAM_TYPE_Last =            0x7
265                 } __packed ram:3;       /* Byte 40 Bits 0-2 */
266                 enum {
267                         MYRB_ERR_CORR_None =    0x0,
268                         MYRB_ERR_CORR_Parity =  0x1,
269                         MYRB_ERR_CORR_ECC =             0x2,
270                         MYRB_ERR_CORR_Last =    0x7
271                 } __packed ec:3;        /* Byte 40 Bits 3-5 */
272                 unsigned char fast_page:1;              /* Byte 40 Bit 6 */
273                 unsigned char low_power:1;              /* Byte 40 Bit 7 */
274                 unsigned char rsvd4;                    /* Bytes 41 */
275         } mem_type;
276         unsigned short clock_speed;                     /* Bytes 42-43 */
277         unsigned short mem_speed;                       /* Bytes 44-45 */
278         unsigned short hw_speed;                        /* Bytes 46-47 */
279         unsigned char rsvd5[12];                        /* Bytes 48-59 */
280         unsigned short max_cmds;                        /* Bytes 60-61 */
281         unsigned short max_sge;                         /* Bytes 62-63 */
282         unsigned short max_drv_cmds;                    /* Bytes 64-65 */
283         unsigned short max_io_desc;                     /* Bytes 66-67 */
284         unsigned short max_sectors;                     /* Bytes 68-69 */
285         unsigned char latency;                          /* Byte 70 */
286         unsigned char rsvd6;                            /* Byte 71 */
287         unsigned char scsi_tmo;                         /* Byte 72 */
288         unsigned char rsvd7;                            /* Byte 73 */
289         unsigned short min_freelines;                   /* Bytes 74-75 */
290         unsigned char rsvd8[8];                         /* Bytes 76-83 */
291         unsigned char rbld_rate_const;                  /* Byte 84 */
292         unsigned char rsvd9[11];                        /* Byte 85-95 */
293         unsigned short pdrv_block_size;                 /* Bytes 96-97 */
294         unsigned short ldev_block_size;                 /* Bytes 98-99 */
295         unsigned short max_blocks_per_cmd;              /* Bytes 100-101 */
296         unsigned short block_factor;                    /* Bytes 102-103 */
297         unsigned short cacheline_size;                  /* Bytes 104-105 */
298         struct {
299                 enum {
300                         MYRB_WIDTH_NARROW_8BIT =                0x0,
301                         MYRB_WIDTH_WIDE_16BIT =                 0x1,
302                         MYRB_WIDTH_WIDE_32BIT =                 0x2
303                 } __packed bus_width:2; /* Byte 106 Bits 0-1 */
304                 enum {
305                         MYRB_SCSI_SPEED_FAST =                  0x0,
306                         MYRB_SCSI_SPEED_ULTRA =                 0x1,
307                         MYRB_SCSI_SPEED_ULTRA2 =                0x2
308                 } __packed bus_speed:2; /* Byte 106 Bits 2-3 */
309                 unsigned char differential:1;           /* Byte 106 Bit 4 */
310                 unsigned char rsvd10:3;                 /* Byte 106 Bits 5-7 */
311         } scsi_cap;
312         unsigned char rsvd11[5];                        /* Byte 107-111 */
313         unsigned short fw_build;                        /* Bytes 112-113 */
314         enum {
315                 MYRB_FAULT_AEMI =                               0x01,
316                 MYRB_FAULT_OEM1 =                               0x02,
317                 MYRB_FAULT_OEM2 =                               0x04,
318                 MYRB_FAULT_OEM3 =                               0x08,
319                 MYRB_FAULT_CONNER =                             0x10,
320                 MYRB_FAULT_SAFTE =                              0x20
321         } __packed fault_mgmt;          /* Byte 114 */
322         unsigned char rsvd12;                           /* Byte 115 */
323         struct {
324                 unsigned int clustering:1;              /* Byte 116 Bit 0 */
325                 unsigned int online_RAID_expansion:1;   /* Byte 116 Bit 1 */
326                 unsigned int readahead:1;               /* Byte 116 Bit 2 */
327                 unsigned int bgi:1;                     /* Byte 116 Bit 3 */
328                 unsigned int rsvd13:28;                 /* Bytes 116-119 */
329         } fw_features;
330         unsigned char rsvd14[8];                        /* Bytes 120-127 */
331 } __packed;
332
333 /*
334  * DAC960 V1 Firmware Logical Drive State type.
335  */
336 enum myrb_devstate {
337         MYRB_DEVICE_DEAD =              0x00,
338         MYRB_DEVICE_WO =                0x02,
339         MYRB_DEVICE_ONLINE =            0x03,
340         MYRB_DEVICE_CRITICAL =          0x04,
341         MYRB_DEVICE_STANDBY =           0x10,
342         MYRB_DEVICE_OFFLINE =           0xFF
343 } __packed;
344
345 /*
346  * DAC960 V1 RAID Levels
347  */
348 enum myrb_raidlevel {
349         MYRB_RAID_LEVEL0 =              0x0,     /* RAID 0 */
350         MYRB_RAID_LEVEL1 =              0x1,     /* RAID 1 */
351         MYRB_RAID_LEVEL3 =              0x3,     /* RAID 3 */
352         MYRB_RAID_LEVEL5 =              0x5,     /* RAID 5 */
353         MYRB_RAID_LEVEL6 =              0x6,     /* RAID 6 */
354         MYRB_RAID_JBOD =                0x7,     /* RAID 7 (JBOD) */
355 } __packed;
356
357 /*
358  * DAC960 V1 Firmware Logical Drive Information structure.
359  */
360 struct myrb_ldev_info {
361         unsigned int size;                              /* Bytes 0-3 */
362         enum myrb_devstate state;                       /* Byte 4 */
363         unsigned int raid_level:7;                      /* Byte 5 Bits 0-6 */
364         unsigned int wb_enabled:1;                      /* Byte 5 Bit 7 */
365         unsigned int rsvd:16;                           /* Bytes 6-7 */
366 };
367
368 /*
369  * DAC960 V1 Firmware Perform Event Log Operation Types.
370  */
371 #define DAC960_V1_GetEventLogEntry              0x00
372
373 /*
374  * DAC960 V1 Firmware Get Event Log Entry Command reply structure.
375  */
376 struct myrb_log_entry {
377         unsigned char msg_type;                 /* Byte 0 */
378         unsigned char msg_len;                  /* Byte 1 */
379         unsigned char target:5;                 /* Byte 2 Bits 0-4 */
380         unsigned char channel:3;                /* Byte 2 Bits 5-7 */
381         unsigned char lun:6;                    /* Byte 3 Bits 0-5 */
382         unsigned char rsvd1:2;                  /* Byte 3 Bits 6-7 */
383         unsigned short seq_num;                 /* Bytes 4-5 */
384         unsigned char sense[26];                /* Bytes 6-31 */
385 };
386
387 /*
388  * DAC960 V1 Firmware Get Device State Command reply structure.
389  * The structure is padded by 2 bytes for compatibility with Version 2.xx
390  * Firmware.
391  */
392 struct myrb_pdev_state {
393         unsigned int present:1;                 /* Byte 0 Bit 0 */
394         unsigned int :7;                                /* Byte 0 Bits 1-7 */
395         enum {
396                 MYRB_TYPE_OTHER =                       0x0,
397                 MYRB_TYPE_DISK =                        0x1,
398                 MYRB_TYPE_TAPE =                        0x2,
399                 MYRB_TYPE_CDROM_OR_WORM =               0x3
400         } __packed devtype:2;           /* Byte 1 Bits 0-1 */
401         unsigned int rsvd1:1;                           /* Byte 1 Bit 2 */
402         unsigned int fast20:1;                          /* Byte 1 Bit 3 */
403         unsigned int sync:1;                            /* Byte 1 Bit 4 */
404         unsigned int fast:1;                            /* Byte 1 Bit 5 */
405         unsigned int wide:1;                            /* Byte 1 Bit 6 */
406         unsigned int tcq_supported:1;                   /* Byte 1 Bit 7 */
407         enum myrb_devstate state;                       /* Byte 2 */
408         unsigned int rsvd2:8;                           /* Byte 3 */
409         unsigned int sync_multiplier;                   /* Byte 4 */
410         unsigned int sync_offset:5;                     /* Byte 5 Bits 0-4 */
411         unsigned int rsvd3:3;                           /* Byte 5 Bits 5-7 */
412         unsigned int size;                              /* Bytes 6-9 */
413         unsigned int rsvd4:16;                  /* Bytes 10-11 */
414 } __packed;
415
416 /*
417  * DAC960 V1 Firmware Get Rebuild Progress Command reply structure.
418  */
419 struct myrb_rbld_progress {
420         unsigned int ldev_num;                          /* Bytes 0-3 */
421         unsigned int ldev_size;                         /* Bytes 4-7 */
422         unsigned int blocks_left;                       /* Bytes 8-11 */
423 };
424
425 /*
426  * DAC960 V1 Firmware Background Initialization Status Command reply structure.
427  */
428 struct myrb_bgi_status {
429         unsigned int ldev_size;                         /* Bytes 0-3 */
430         unsigned int blocks_done;                       /* Bytes 4-7 */
431         unsigned char rsvd1[12];                        /* Bytes 8-19 */
432         unsigned int ldev_num;                          /* Bytes 20-23 */
433         unsigned char raid_level;                       /* Byte 24 */
434         enum {
435                 MYRB_BGI_INVALID =      0x00,
436                 MYRB_BGI_STARTED =      0x02,
437                 MYRB_BGI_INPROGRESS =   0x04,
438                 MYRB_BGI_SUSPENDED =    0x05,
439                 MYRB_BGI_CANCELLED =    0x06
440         } __packed status;              /* Byte 25 */
441         unsigned char rsvd2[6];                         /* Bytes 26-31 */
442 };
443
444 /*
445  * DAC960 V1 Firmware Error Table Entry structure.
446  */
447 struct myrb_error_entry {
448         unsigned char parity_err;                       /* Byte 0 */
449         unsigned char soft_err;                         /* Byte 1 */
450         unsigned char hard_err;                         /* Byte 2 */
451         unsigned char misc_err;                         /* Byte 3 */
452 };
453
454 /*
455  * DAC960 V1 Firmware Read Config2 Command reply structure.
456  */
457 struct myrb_config2 {
458         unsigned rsvd1:1;                               /* Byte 0 Bit 0 */
459         unsigned active_negation:1;                     /* Byte 0 Bit 1 */
460         unsigned rsvd2:5;                               /* Byte 0 Bits 2-6 */
461         unsigned no_rescan_on_reset_during_scan:1;      /* Byte 0 Bit 7 */
462         unsigned StorageWorks_support:1;                /* Byte 1 Bit 0 */
463         unsigned HewlettPackard_support:1;              /* Byte 1 Bit 1 */
464         unsigned no_disconnect_on_first_command:1;      /* Byte 1 Bit 2 */
465         unsigned rsvd3:2;                               /* Byte 1 Bits 3-4 */
466         unsigned AEMI_ARM:1;                            /* Byte 1 Bit 5 */
467         unsigned AEMI_OFM:1;                            /* Byte 1 Bit 6 */
468         unsigned rsvd4:1;                               /* Byte 1 Bit 7 */
469         enum {
470                 MYRB_OEMID_MYLEX =              0x00,
471                 MYRB_OEMID_IBM =                0x08,
472                 MYRB_OEMID_HP =                 0x0A,
473                 MYRB_OEMID_DEC =                0x0C,
474                 MYRB_OEMID_SIEMENS =            0x10,
475                 MYRB_OEMID_INTEL =              0x12
476         } __packed OEMID;               /* Byte 2 */
477         unsigned char oem_model_number;                 /* Byte 3 */
478         unsigned char physical_sector;                  /* Byte 4 */
479         unsigned char logical_sector;                   /* Byte 5 */
480         unsigned char block_factor;                     /* Byte 6 */
481         unsigned readahead_enabled:1;                   /* Byte 7 Bit 0 */
482         unsigned low_BIOS_delay:1;                      /* Byte 7 Bit 1 */
483         unsigned rsvd5:2;                               /* Byte 7 Bits 2-3 */
484         unsigned restrict_reassign_to_one_sector:1;     /* Byte 7 Bit 4 */
485         unsigned rsvd6:1;                               /* Byte 7 Bit 5 */
486         unsigned FUA_during_write_recovery:1;           /* Byte 7 Bit 6 */
487         unsigned enable_LeftSymmetricRAID5Algorithm:1;  /* Byte 7 Bit 7 */
488         unsigned char default_rebuild_rate;             /* Byte 8 */
489         unsigned char rsvd7;                            /* Byte 9 */
490         unsigned char blocks_per_cacheline;             /* Byte 10 */
491         unsigned char blocks_per_stripe;                /* Byte 11 */
492         struct {
493                 enum {
494                         MYRB_SPEED_ASYNC =              0x0,
495                         MYRB_SPEED_SYNC_8MHz =          0x1,
496                         MYRB_SPEED_SYNC_5MHz =          0x2,
497                         MYRB_SPEED_SYNC_10_OR_20MHz =   0x3
498                 } __packed speed:2;     /* Byte 11 Bits 0-1 */
499                 unsigned force_8bit:1;                  /* Byte 11 Bit 2 */
500                 unsigned disable_fast20:1;              /* Byte 11 Bit 3 */
501                 unsigned rsvd8:3;                       /* Byte 11 Bits 4-6 */
502                 unsigned enable_tcq:1;                  /* Byte 11 Bit 7 */
503         } __packed channelparam[6];     /* Bytes 12-17 */
504         unsigned char SCSIInitiatorID;                  /* Byte 18 */
505         unsigned char rsvd9;                            /* Byte 19 */
506         enum {
507                 MYRB_STARTUP_CONTROLLER_SPINUP =        0x00,
508                 MYRB_STARTUP_POWERON_SPINUP =           0x01
509         } __packed startup;             /* Byte 20 */
510         unsigned char simultaneous_device_spinup_count; /* Byte 21 */
511         unsigned char seconds_delay_between_spinups;    /* Byte 22 */
512         unsigned char rsvd10[29];                       /* Bytes 23-51 */
513         unsigned BIOS_disabled:1;                       /* Byte 52 Bit 0 */
514         unsigned CDROM_boot_enabled:1;                  /* Byte 52 Bit 1 */
515         unsigned rsvd11:3;                              /* Byte 52 Bits 2-4 */
516         enum {
517                 MYRB_GEOM_128_32 =              0x0,
518                 MYRB_GEOM_255_63 =              0x1,
519                 MYRB_GEOM_RESERVED1 =           0x2,
520                 MYRB_GEOM_RESERVED2 =           0x3
521         } __packed drive_geometry:2;    /* Byte 52 Bits 5-6 */
522         unsigned rsvd12:1;                              /* Byte 52 Bit 7 */
523         unsigned char rsvd13[9];                        /* Bytes 53-61 */
524         unsigned short csum;                            /* Bytes 62-63 */
525 };
526
527 /*
528  * DAC960 V1 Firmware DCDB request structure.
529  */
530 struct myrb_dcdb {
531         unsigned target:4;                               /* Byte 0 Bits 0-3 */
532         unsigned channel:4;                              /* Byte 0 Bits 4-7 */
533         enum {
534                 MYRB_DCDB_XFER_NONE =           0,
535                 MYRB_DCDB_XFER_DEVICE_TO_SYSTEM = 1,
536                 MYRB_DCDB_XFER_SYSTEM_TO_DEVICE = 2,
537                 MYRB_DCDB_XFER_ILLEGAL =        3
538         } __packed data_xfer:2;                         /* Byte 1 Bits 0-1 */
539         unsigned early_status:1;                        /* Byte 1 Bit 2 */
540         unsigned rsvd1:1;                               /* Byte 1 Bit 3 */
541         enum {
542                 MYRB_DCDB_TMO_24_HRS =  0,
543                 MYRB_DCDB_TMO_10_SECS = 1,
544                 MYRB_DCDB_TMO_60_SECS = 2,
545                 MYRB_DCDB_TMO_10_MINS = 3
546         } __packed timeout:2;                           /* Byte 1 Bits 4-5 */
547         unsigned no_autosense:1;                        /* Byte 1 Bit 6 */
548         unsigned allow_disconnect:1;                    /* Byte 1 Bit 7 */
549         unsigned short xfer_len_lo;                     /* Bytes 2-3 */
550         u32 dma_addr;                                   /* Bytes 4-7 */
551         unsigned char cdb_len:4;                        /* Byte 8 Bits 0-3 */
552         unsigned char xfer_len_hi4:4;                   /* Byte 8 Bits 4-7 */
553         unsigned char sense_len;                        /* Byte 9 */
554         unsigned char cdb[12];                          /* Bytes 10-21 */
555         unsigned char sense[64];                        /* Bytes 22-85 */
556         unsigned char status;                           /* Byte 86 */
557         unsigned char rsvd2;                            /* Byte 87 */
558 };
559
560 /*
561  * DAC960 V1 Firmware Scatter/Gather List Type 1 32 Bit Address
562  *32 Bit Byte Count structure.
563  */
564 struct myrb_sge {
565         u32 sge_addr;           /* Bytes 0-3 */
566         u32 sge_count;          /* Bytes 4-7 */
567 };
568
569 /*
570  * 13 Byte DAC960 V1 Firmware Command Mailbox structure.
571  * Bytes 13-15 are not used.  The structure is padded to 16 bytes for
572  * efficient access.
573  */
574 union myrb_cmd_mbox {
575         unsigned int words[4];                          /* Words 0-3 */
576         unsigned char bytes[16];                        /* Bytes 0-15 */
577         struct {
578                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
579                 unsigned char id;                       /* Byte 1 */
580                 unsigned char rsvd[14];                 /* Bytes 2-15 */
581         } __packed common;
582         struct {
583                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
584                 unsigned char id;                       /* Byte 1 */
585                 unsigned char rsvd1[6];                 /* Bytes 2-7 */
586                 u32 addr;                               /* Bytes 8-11 */
587                 unsigned char rsvd2[4];                 /* Bytes 12-15 */
588         } __packed type3;
589         struct {
590                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
591                 unsigned char id;                       /* Byte 1 */
592                 unsigned char optype;                   /* Byte 2 */
593                 unsigned char rsvd1[5];                 /* Bytes 3-7 */
594                 u32 addr;                               /* Bytes 8-11 */
595                 unsigned char rsvd2[4];                 /* Bytes 12-15 */
596         } __packed type3B;
597         struct {
598                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
599                 unsigned char id;                       /* Byte 1 */
600                 unsigned char rsvd1[5];                 /* Bytes 2-6 */
601                 unsigned char ldev_num:6;               /* Byte 7 Bits 0-6 */
602                 unsigned char auto_restore:1;           /* Byte 7 Bit 7 */
603                 unsigned char rsvd2[8];                 /* Bytes 8-15 */
604         } __packed type3C;
605         struct {
606                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
607                 unsigned char id;                       /* Byte 1 */
608                 unsigned char channel;                  /* Byte 2 */
609                 unsigned char target;                   /* Byte 3 */
610                 enum myrb_devstate state;               /* Byte 4 */
611                 unsigned char rsvd1[3];                 /* Bytes 5-7 */
612                 u32 addr;                               /* Bytes 8-11 */
613                 unsigned char rsvd2[4];                 /* Bytes 12-15 */
614         } __packed type3D;
615         struct {
616                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
617                 unsigned char id;                       /* Byte 1 */
618                 unsigned char optype;                   /* Byte 2 */
619                 unsigned char opqual;                   /* Byte 3 */
620                 unsigned short ev_seq;                  /* Bytes 4-5 */
621                 unsigned char rsvd1[2];                 /* Bytes 6-7 */
622                 u32 addr;                               /* Bytes 8-11 */
623                 unsigned char rsvd2[4];                 /* Bytes 12-15 */
624         } __packed type3E;
625         struct {
626                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
627                 unsigned char id;                       /* Byte 1 */
628                 unsigned char rsvd1[2];                 /* Bytes 2-3 */
629                 unsigned char rbld_rate;                /* Byte 4 */
630                 unsigned char rsvd2[3];                 /* Bytes 5-7 */
631                 u32 addr;                               /* Bytes 8-11 */
632                 unsigned char rsvd3[4];                 /* Bytes 12-15 */
633         } __packed type3R;
634         struct {
635                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
636                 unsigned char id;                       /* Byte 1 */
637                 unsigned short xfer_len;                /* Bytes 2-3 */
638                 unsigned int lba;                       /* Bytes 4-7 */
639                 u32 addr;                               /* Bytes 8-11 */
640                 unsigned char ldev_num;                 /* Byte 12 */
641                 unsigned char rsvd[3];                  /* Bytes 13-15 */
642         } __packed type4;
643         struct {
644                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
645                 unsigned char id;                       /* Byte 1 */
646                 struct {
647                         unsigned short xfer_len:11;     /* Bytes 2-3 */
648                         unsigned char ldev_num:5;       /* Byte 3 Bits 3-7 */
649                 } __packed ld;
650                 unsigned int lba;                       /* Bytes 4-7 */
651                 u32 addr;                               /* Bytes 8-11 */
652                 unsigned char sg_count:6;               /* Byte 12 Bits 0-5 */
653                 enum {
654                         MYRB_SGL_ADDR32_COUNT32 = 0x0,
655                         MYRB_SGL_ADDR32_COUNT16 = 0x1,
656                         MYRB_SGL_COUNT32_ADDR32 = 0x2,
657                         MYRB_SGL_COUNT16_ADDR32 = 0x3
658                 } __packed sg_type:2;   /* Byte 12 Bits 6-7 */
659                 unsigned char rsvd[3];                  /* Bytes 13-15 */
660         } __packed type5;
661         struct {
662                 enum myrb_cmd_opcode opcode;            /* Byte 0 */
663                 unsigned char id;                       /* Byte 1 */
664                 unsigned char opcode2;                  /* Byte 2 */
665                 unsigned char rsvd1:8;                  /* Byte 3 */
666                 u32 cmd_mbox_addr;                      /* Bytes 4-7 */
667                 u32 stat_mbox_addr;                     /* Bytes 8-11 */
668                 unsigned char rsvd2[4];                 /* Bytes 12-15 */
669         } __packed typeX;
670 };
671
672 /*
673  * DAC960 V1 Firmware Controller Status Mailbox structure.
674  */
675 struct myrb_stat_mbox {
676         unsigned char id;               /* Byte 0 */
677         unsigned char rsvd:7;           /* Byte 1 Bits 0-6 */
678         unsigned char valid:1;                  /* Byte 1 Bit 7 */
679         unsigned short status;          /* Bytes 2-3 */
680 };
681
682 struct myrb_cmdblk {
683         union myrb_cmd_mbox mbox;
684         unsigned short status;
685         struct completion *completion;
686         struct myrb_dcdb *dcdb;
687         dma_addr_t dcdb_addr;
688         struct myrb_sge *sgl;
689         dma_addr_t sgl_addr;
690 };
691
692 struct myrb_hba {
693         unsigned int ldev_block_size;
694         unsigned char ldev_geom_heads;
695         unsigned char ldev_geom_sectors;
696         unsigned char bus_width;
697         unsigned short stripe_size;
698         unsigned short segment_size;
699         unsigned short new_ev_seq;
700         unsigned short old_ev_seq;
701         bool dual_mode_interface;
702         bool bgi_status_supported;
703         bool safte_enabled;
704         bool need_ldev_info;
705         bool need_err_info;
706         bool need_rbld;
707         bool need_cc_status;
708         bool need_bgi_status;
709         bool rbld_first;
710
711         struct pci_dev *pdev;
712         struct Scsi_Host *host;
713
714         struct workqueue_struct *work_q;
715         char work_q_name[20];
716         struct delayed_work monitor_work;
717         unsigned long primary_monitor_time;
718         unsigned long secondary_monitor_time;
719
720         struct dma_pool *sg_pool;
721         struct dma_pool *dcdb_pool;
722
723         spinlock_t queue_lock;
724
725         void (*qcmd)(struct myrb_hba *cs, struct myrb_cmdblk *cmd_blk);
726         void (*write_cmd_mbox)(union myrb_cmd_mbox *next_mbox,
727                                union myrb_cmd_mbox *cmd_mbox);
728         void (*get_cmd_mbox)(void __iomem *base);
729         void (*disable_intr)(void __iomem *base);
730         void (*reset)(void __iomem *base);
731
732         unsigned int ctlr_num;
733         unsigned char model_name[20];
734         unsigned char fw_version[12];
735
736         unsigned int irq;
737         phys_addr_t io_addr;
738         phys_addr_t pci_addr;
739         void __iomem *io_base;
740         void __iomem *mmio_base;
741
742         size_t cmd_mbox_size;
743         dma_addr_t cmd_mbox_addr;
744         union myrb_cmd_mbox *first_cmd_mbox;
745         union myrb_cmd_mbox *last_cmd_mbox;
746         union myrb_cmd_mbox *next_cmd_mbox;
747         union myrb_cmd_mbox *prev_cmd_mbox1;
748         union myrb_cmd_mbox *prev_cmd_mbox2;
749
750         size_t stat_mbox_size;
751         dma_addr_t stat_mbox_addr;
752         struct myrb_stat_mbox *first_stat_mbox;
753         struct myrb_stat_mbox *last_stat_mbox;
754         struct myrb_stat_mbox *next_stat_mbox;
755
756         struct myrb_cmdblk dcmd_blk;
757         struct myrb_cmdblk mcmd_blk;
758         struct mutex dcmd_mutex;
759
760         struct myrb_enquiry *enquiry;
761         dma_addr_t enquiry_addr;
762
763         struct myrb_error_entry *err_table;
764         dma_addr_t err_table_addr;
765
766         unsigned short last_rbld_status;
767
768         struct myrb_ldev_info *ldev_info_buf;
769         dma_addr_t ldev_info_addr;
770
771         struct myrb_bgi_status bgi_status;
772
773         struct mutex dma_mutex;
774 };
775
776 /*
777  * DAC960 LA Series Controller Interface Register Offsets.
778  */
779 #define DAC960_LA_mmio_size             0x80
780
781 enum DAC960_LA_reg_offset {
782         DAC960_LA_IRQMASK_OFFSET        = 0x34,
783         DAC960_LA_CMDOP_OFFSET          = 0x50,
784         DAC960_LA_CMDID_OFFSET          = 0x51,
785         DAC960_LA_MBOX2_OFFSET          = 0x52,
786         DAC960_LA_MBOX3_OFFSET          = 0x53,
787         DAC960_LA_MBOX4_OFFSET          = 0x54,
788         DAC960_LA_MBOX5_OFFSET          = 0x55,
789         DAC960_LA_MBOX6_OFFSET          = 0x56,
790         DAC960_LA_MBOX7_OFFSET          = 0x57,
791         DAC960_LA_MBOX8_OFFSET          = 0x58,
792         DAC960_LA_MBOX9_OFFSET          = 0x59,
793         DAC960_LA_MBOX10_OFFSET         = 0x5A,
794         DAC960_LA_MBOX11_OFFSET         = 0x5B,
795         DAC960_LA_MBOX12_OFFSET         = 0x5C,
796         DAC960_LA_STSID_OFFSET          = 0x5D,
797         DAC960_LA_STS_OFFSET            = 0x5E,
798         DAC960_LA_IDB_OFFSET            = 0x60,
799         DAC960_LA_ODB_OFFSET            = 0x61,
800         DAC960_LA_ERRSTS_OFFSET         = 0x63,
801 };
802
803 /*
804  * DAC960 LA Series Inbound Door Bell Register.
805  */
806 #define DAC960_LA_IDB_HWMBOX_NEW_CMD 0x01
807 #define DAC960_LA_IDB_HWMBOX_ACK_STS 0x02
808 #define DAC960_LA_IDB_GEN_IRQ 0x04
809 #define DAC960_LA_IDB_CTRL_RESET 0x08
810 #define DAC960_LA_IDB_MMBOX_NEW_CMD 0x10
811
812 #define DAC960_LA_IDB_HWMBOX_EMPTY 0x01
813 #define DAC960_LA_IDB_INIT_DONE 0x02
814
815 /*
816  * DAC960 LA Series Outbound Door Bell Register.
817  */
818 #define DAC960_LA_ODB_HWMBOX_ACK_IRQ 0x01
819 #define DAC960_LA_ODB_MMBOX_ACK_IRQ 0x02
820 #define DAC960_LA_ODB_HWMBOX_STS_AVAIL 0x01
821 #define DAC960_LA_ODB_MMBOX_STS_AVAIL 0x02
822
823 /*
824  * DAC960 LA Series Interrupt Mask Register.
825  */
826 #define DAC960_LA_IRQMASK_DISABLE_IRQ 0x04
827
828 /*
829  * DAC960 LA Series Error Status Register.
830  */
831 #define DAC960_LA_ERRSTS_PENDING 0x02
832
833 /*
834  * DAC960 PG Series Controller Interface Register Offsets.
835  */
836 #define DAC960_PG_mmio_size             0x2000
837
838 enum DAC960_PG_reg_offset {
839         DAC960_PG_IDB_OFFSET            = 0x0020,
840         DAC960_PG_ODB_OFFSET            = 0x002C,
841         DAC960_PG_IRQMASK_OFFSET        = 0x0034,
842         DAC960_PG_CMDOP_OFFSET          = 0x1000,
843         DAC960_PG_CMDID_OFFSET          = 0x1001,
844         DAC960_PG_MBOX2_OFFSET          = 0x1002,
845         DAC960_PG_MBOX3_OFFSET          = 0x1003,
846         DAC960_PG_MBOX4_OFFSET          = 0x1004,
847         DAC960_PG_MBOX5_OFFSET          = 0x1005,
848         DAC960_PG_MBOX6_OFFSET          = 0x1006,
849         DAC960_PG_MBOX7_OFFSET          = 0x1007,
850         DAC960_PG_MBOX8_OFFSET          = 0x1008,
851         DAC960_PG_MBOX9_OFFSET          = 0x1009,
852         DAC960_PG_MBOX10_OFFSET         = 0x100A,
853         DAC960_PG_MBOX11_OFFSET         = 0x100B,
854         DAC960_PG_MBOX12_OFFSET         = 0x100C,
855         DAC960_PG_STSID_OFFSET          = 0x1018,
856         DAC960_PG_STS_OFFSET            = 0x101A,
857         DAC960_PG_ERRSTS_OFFSET         = 0x103F,
858 };
859
860 /*
861  * DAC960 PG Series Inbound Door Bell Register.
862  */
863 #define DAC960_PG_IDB_HWMBOX_NEW_CMD 0x01
864 #define DAC960_PG_IDB_HWMBOX_ACK_STS 0x02
865 #define DAC960_PG_IDB_GEN_IRQ 0x04
866 #define DAC960_PG_IDB_CTRL_RESET 0x08
867 #define DAC960_PG_IDB_MMBOX_NEW_CMD 0x10
868
869 #define DAC960_PG_IDB_HWMBOX_FULL 0x01
870 #define DAC960_PG_IDB_INIT_IN_PROGRESS 0x02
871
872 /*
873  * DAC960 PG Series Outbound Door Bell Register.
874  */
875 #define DAC960_PG_ODB_HWMBOX_ACK_IRQ 0x01
876 #define DAC960_PG_ODB_MMBOX_ACK_IRQ 0x02
877 #define DAC960_PG_ODB_HWMBOX_STS_AVAIL 0x01
878 #define DAC960_PG_ODB_MMBOX_STS_AVAIL 0x02
879
880 /*
881  * DAC960 PG Series Interrupt Mask Register.
882  */
883 #define DAC960_PG_IRQMASK_MSI_MASK1 0x03
884 #define DAC960_PG_IRQMASK_DISABLE_IRQ 0x04
885 #define DAC960_PG_IRQMASK_MSI_MASK2 0xF8
886
887 /*
888  * DAC960 PG Series Error Status Register.
889  */
890 #define DAC960_PG_ERRSTS_PENDING 0x04
891
892 /*
893  * DAC960 PD Series Controller Interface Register Offsets.
894  */
895 #define DAC960_PD_mmio_size             0x80
896
897 enum DAC960_PD_reg_offset {
898         DAC960_PD_CMDOP_OFFSET          = 0x00,
899         DAC960_PD_CMDID_OFFSET          = 0x01,
900         DAC960_PD_MBOX2_OFFSET          = 0x02,
901         DAC960_PD_MBOX3_OFFSET          = 0x03,
902         DAC960_PD_MBOX4_OFFSET          = 0x04,
903         DAC960_PD_MBOX5_OFFSET          = 0x05,
904         DAC960_PD_MBOX6_OFFSET          = 0x06,
905         DAC960_PD_MBOX7_OFFSET          = 0x07,
906         DAC960_PD_MBOX8_OFFSET          = 0x08,
907         DAC960_PD_MBOX9_OFFSET          = 0x09,
908         DAC960_PD_MBOX10_OFFSET         = 0x0A,
909         DAC960_PD_MBOX11_OFFSET         = 0x0B,
910         DAC960_PD_MBOX12_OFFSET         = 0x0C,
911         DAC960_PD_STSID_OFFSET          = 0x0D,
912         DAC960_PD_STS_OFFSET            = 0x0E,
913         DAC960_PD_ERRSTS_OFFSET         = 0x3F,
914         DAC960_PD_IDB_OFFSET            = 0x40,
915         DAC960_PD_ODB_OFFSET            = 0x41,
916         DAC960_PD_IRQEN_OFFSET          = 0x43,
917 };
918
919 /*
920  * DAC960 PD Series Inbound Door Bell Register.
921  */
922 #define DAC960_PD_IDB_HWMBOX_NEW_CMD 0x01
923 #define DAC960_PD_IDB_HWMBOX_ACK_STS 0x02
924 #define DAC960_PD_IDB_GEN_IRQ 0x04
925 #define DAC960_PD_IDB_CTRL_RESET 0x08
926
927 #define DAC960_PD_IDB_HWMBOX_FULL 0x01
928 #define DAC960_PD_IDB_INIT_IN_PROGRESS 0x02
929
930 /*
931  * DAC960 PD Series Outbound Door Bell Register.
932  */
933 #define DAC960_PD_ODB_HWMBOX_ACK_IRQ 0x01
934 #define DAC960_PD_ODB_HWMBOX_STS_AVAIL 0x01
935
936 /*
937  * DAC960 PD Series Interrupt Enable Register.
938  */
939 #define DAC960_PD_IRQMASK_ENABLE_IRQ 0x01
940
941 /*
942  * DAC960 PD Series Error Status Register.
943  */
944 #define DAC960_PD_ERRSTS_PENDING 0x04
945
946 typedef int (*myrb_hw_init_t)(struct pci_dev *pdev,
947                               struct myrb_hba *cb, void __iomem *base);
948 typedef unsigned short (*mbox_mmio_init_t)(struct pci_dev *pdev,
949                                            void __iomem *base,
950                                            union myrb_cmd_mbox *mbox);
951
952 struct myrb_privdata {
953         myrb_hw_init_t          hw_init;
954         irq_handler_t           irq_handler;
955         unsigned int            mmio_size;
956 };
957
958 #endif /* MYRB_H */