1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Marvell 88SE64xx/88SE94xx register IO interface
5 * Copyright 2007 Red Hat, Inc.
6 * Copyright 2008 Marvell. <kewei@marvell.com>
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
14 #define mr32(reg) readl(regs + reg)
15 #define mw32(reg, val) writel((val), regs + reg)
16 #define mw32_f(reg, val) do { \
21 #define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
22 #define ior32(reg) inl((unsigned long)(regs + reg))
23 #define iow16(reg, val) outw((unsigned long)(val, regs + reg))
24 #define ior16(reg) inw((unsigned long)(regs + reg))
25 #define iow8(reg, val) outb((unsigned long)(val, regs + reg))
26 #define ior8(reg) inb((unsigned long)(regs + reg))
28 static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
30 void __iomem *regs = mvi->regs;
31 mw32(MVS_CMD_ADDR, addr);
32 return mr32(MVS_CMD_DATA);
35 static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
37 void __iomem *regs = mvi->regs;
38 mw32(MVS_CMD_ADDR, addr);
39 mw32(MVS_CMD_DATA, val);
42 static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
44 void __iomem *regs = mvi->regs;
45 return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
46 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
49 static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
51 void __iomem *regs = mvi->regs;
53 mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
55 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
58 static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
61 void __iomem *regs = mvi->regs + off;
62 void __iomem *regs2 = mvi->regs + off2;
63 return (port < 4) ? readl(regs + port * 8) :
64 readl(regs2 + (port - 4) * 8);
67 static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
70 void __iomem *regs = mvi->regs + off;
71 void __iomem *regs2 = mvi->regs + off2;
73 writel(val, regs + port * 8);
75 writel(val, regs2 + (port - 4) * 8);
78 static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
80 return mvs_read_port(mvi, MVS_P0_CFG_DATA,
81 MVS_P4_CFG_DATA, port);
84 static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
87 mvs_write_port(mvi, MVS_P0_CFG_DATA,
88 MVS_P4_CFG_DATA, port, val);
91 static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
94 mvs_write_port(mvi, MVS_P0_CFG_ADDR,
95 MVS_P4_CFG_ADDR, port, addr);
99 static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
101 return mvs_read_port(mvi, MVS_P0_VSR_DATA,
102 MVS_P4_VSR_DATA, port);
105 static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
108 mvs_write_port(mvi, MVS_P0_VSR_DATA,
109 MVS_P4_VSR_DATA, port, val);
112 static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
115 mvs_write_port(mvi, MVS_P0_VSR_ADDR,
116 MVS_P4_VSR_ADDR, port, addr);
120 static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
122 return mvs_read_port(mvi, MVS_P0_INT_STAT,
123 MVS_P4_INT_STAT, port);
126 static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
129 mvs_write_port(mvi, MVS_P0_INT_STAT,
130 MVS_P4_INT_STAT, port, val);
133 static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
135 return mvs_read_port(mvi, MVS_P0_INT_MASK,
136 MVS_P4_INT_MASK, port);
140 static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
143 mvs_write_port(mvi, MVS_P0_INT_MASK,
144 MVS_P4_INT_MASK, port, val);
147 static inline void mvs_phy_hacks(struct mvs_info *mvi)
151 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
154 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
156 /* enable retry 127 times */
157 mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
159 /* extend open frame timeout to max */
160 tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
163 mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
165 mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
167 /* not to halt for different port op during wideport link change */
168 mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
171 static inline void mvs_int_sata(struct mvs_info *mvi)
174 void __iomem *regs = mvi->regs;
175 tmp = mr32(MVS_INT_STAT_SRS_0);
177 mw32(MVS_INT_STAT_SRS_0, tmp);
178 MVS_CHIP_DISP->clear_active_cmds(mvi);
181 static inline void mvs_int_full(struct mvs_info *mvi)
183 void __iomem *regs = mvi->regs;
187 stat = mr32(MVS_INT_STAT);
188 mvs_int_rx(mvi, false);
190 for (i = 0; i < mvi->chip->n_phy; i++) {
191 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
193 mvs_int_port(mvi, i, tmp);
196 if (stat & CINT_NON_SPEC_NCQ_ERROR)
197 MVS_CHIP_DISP->non_spec_ncq_error(mvi);
202 mw32(MVS_INT_STAT, stat);
205 static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
207 void __iomem *regs = mvi->regs;
208 mw32(MVS_TX_PROD_IDX, tx);
211 static inline u32 mvs_rx_update(struct mvs_info *mvi)
213 void __iomem *regs = mvi->regs;
214 return mr32(MVS_RX_CONS_IDX);
217 static inline u32 mvs_get_prd_size(void)
219 return sizeof(struct mvs_prd);
222 static inline u32 mvs_get_prd_count(void)
227 static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
229 u16 link_stat, link_spd;
230 const char *spd[] = {
235 if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
238 pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
239 link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
242 dev_printk(KERN_INFO, mvi->dev,
243 "mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
244 (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
248 static inline u32 mvs_hw_max_link_rate(void)
250 return MAX_LINK_RATE;
253 #endif /* _MV_CHIPS_H_ */