drivers/scsi/mpt3sas/mpt3sas_base.c

   1 /*
   2  * This is the Fusion MPT base driver providing common API layer interface
   3  * for access to MPT (Message Passing Technology) firmware.
   4  *
   5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
   6  * Copyright (C) 2012-2014  LSI Corporation
   7  * Copyright (C) 2013-2014 Avago Technologies
   8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * NO WARRANTY
  21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25  * solely responsible for determining the appropriateness of using and
  26  * distributing the Program and assumes all risks associated with its
  27  * exercise of rights under this Agreement, including but not limited to
  28  * the risks and costs of program errors, damage to or loss of data,
  29  * programs or equipment, and unavailability or interruption of operations.
  30
  31  * DISCLAIMER OF LIABILITY
  32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39
  40  * You should have received a copy of the GNU General Public License
  41  * along with this program; if not, write to the Free Software
  42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
  43  * USA.
  44  */
  45
  46 #include <linux/kernel.h>
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/init.h>
  50 #include <linux/slab.h>
  51 #include <linux/types.h>
  52 #include <linux/pci.h>
  53 #include <linux/kdev_t.h>
  54 #include <linux/blkdev.h>
  55 #include <linux/delay.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/dma-mapping.h>
  58 #include <linux/io.h>
  59 #include <linux/time.h>
  60 #include <linux/ktime.h>
  61 #include <linux/kthread.h>
  62 #include <asm/page.h>        /* To get host page size per arch */
  63 #include <linux/aer.h>
  64
  65
  66 #include "mpt3sas_base.h"
  67
  68 static MPT_CALLBACK     mpt_callbacks[MPT_MAX_CALLBACKS];
  69
  70
  71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  72
  73  /* maximum controller queue depth */
  74 #define MAX_HBA_QUEUE_DEPTH     30000
  75 #define MAX_CHAIN_DEPTH         100000
  76 static int max_queue_depth = -1;
  77 module_param(max_queue_depth, int, 0444);
  78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  79
  80 static int max_sgl_entries = -1;
  81 module_param(max_sgl_entries, int, 0444);
  82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  83
  84 static int msix_disable = -1;
  85 module_param(msix_disable, int, 0444);
  86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  87
  88 static int smp_affinity_enable = 1;
  89 module_param(smp_affinity_enable, int, 0444);
  90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
  91
  92 static int max_msix_vectors = -1;
  93 module_param(max_msix_vectors, int, 0444);
  94 MODULE_PARM_DESC(max_msix_vectors,
  95         " max msix vectors");
  96
  97 static int irqpoll_weight = -1;
  98 module_param(irqpoll_weight, int, 0444);
  99 MODULE_PARM_DESC(irqpoll_weight,
 100         "irq poll weight (default= one fourth of HBA queue depth)");
 101
 102 static int mpt3sas_fwfault_debug;
 103 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
 104         " enable detection of firmware fault and halt firmware - (default=0)");
 105
 106 static int perf_mode = -1;
 107 module_param(perf_mode, int, 0444);
 108 MODULE_PARM_DESC(perf_mode,
 109         "Performance mode (only for Aero/Sea Generation), options:\n\t\t"
 110         "0 - balanced: high iops mode is enabled &\n\t\t"
 111         "interrupt coalescing is enabled only on high iops queues,\n\t\t"
 112         "1 - iops: high iops mode is disabled &\n\t\t"
 113         "interrupt coalescing is enabled on all queues,\n\t\t"
 114         "2 - latency: high iops mode is disabled &\n\t\t"
 115         "interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
 116         "\t\tdefault - default perf_mode is 'balanced'"
 117         );
 118
 119 static int poll_queues;
 120 module_param(poll_queues, int, 0444);
 121 MODULE_PARM_DESC(poll_queues, "Number of queues to be use for io_uring poll mode.\n\t\t"
 122         "This parameter is effective only if host_tagset_enable=1. &\n\t\t"
 123         "when poll_queues are enabled then &\n\t\t"
 124         "perf_mode is set to latency mode. &\n\t\t"
 125         );
 126
 127 enum mpt3sas_perf_mode {
 128         MPT_PERF_MODE_DEFAULT   = -1,
 129         MPT_PERF_MODE_BALANCED  = 0,
 130         MPT_PERF_MODE_IOPS      = 1,
 131         MPT_PERF_MODE_LATENCY   = 2,
 132 };
 133
 134 static int
 135 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
 136                 u32 ioc_state, int timeout);
 137 static int
 138 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
 139 static void
 140 _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
 141
 142 /**
 143  * mpt3sas_base_check_cmd_timeout - Function
 144  *              to check timeout and command termination due
 145  *              to Host reset.
 146  *
 147  * @ioc:        per adapter object.
 148  * @status:     Status of issued command.
 149  * @mpi_request:mf request pointer.
 150  * @sz:         size of buffer.
 151  *
 152  * Return: 1/0 Reset to be done or Not
 153  */
 154 u8
 155 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
 156                 u8 status, void *mpi_request, int sz)
 157 {
 158         u8 issue_reset = 0;
 159
 160         if (!(status & MPT3_CMD_RESET))
 161                 issue_reset = 1;
 162
 163         ioc_err(ioc, "Command %s\n",
 164                 issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
 165         _debug_dump_mf(mpi_request, sz);
 166
 167         return issue_reset;
 168 }
 169
 170 /**
 171  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
 172  * @val: ?
 173  * @kp: ?
 174  *
 175  * Return: ?
 176  */
 177 static int
 178 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
 179 {
 180         int ret = param_set_int(val, kp);
 181         struct MPT3SAS_ADAPTER *ioc;
 182
 183         if (ret)
 184                 return ret;
 185
 186         /* global ioc spinlock to protect controller list on list operations */
 187         pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
 188         spin_lock(&gioc_lock);
 189         list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
 190                 ioc->fwfault_debug = mpt3sas_fwfault_debug;
 191         spin_unlock(&gioc_lock);
 192         return 0;
 193 }
 194 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
 195         param_get_int, &mpt3sas_fwfault_debug, 0644);
 196
 197 /**
 198  * _base_readl_aero - retry readl for max three times.
 199  * @addr: MPT Fusion system interface register address
 200  *
 201  * Retry the readl() for max three times if it gets zero value
 202  * while reading the system interface register.
 203  */
 204 static inline u32
 205 _base_readl_aero(const volatile void __iomem *addr)
 206 {
 207         u32 i = 0, ret_val;
 208
 209         do {
 210                 ret_val = readl(addr);
 211                 i++;
 212         } while (ret_val == 0 && i < 3);
 213
 214         return ret_val;
 215 }
 216
 217 static inline u32
 218 _base_readl(const volatile void __iomem *addr)
 219 {
 220         return readl(addr);
 221 }
 222
 223 /**
 224  * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
 225  *                                in BAR0 space.
 226  *
 227  * @ioc: per adapter object
 228  * @reply: reply message frame(lower 32bit addr)
 229  * @index: System request message index.
 230  */
 231 static void
 232 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
 233                 u32 index)
 234 {
 235         /*
 236          * 256 is offset within sys register.
 237          * 256 offset MPI frame starts. Max MPI frame supported is 32.
 238          * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
 239          */
 240         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 241         void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
 242                         MPI_FRAME_START_OFFSET +
 243                         (cmd_credit * ioc->request_sz) + (index * sizeof(u32));
 244
 245         writel(reply, reply_free_iomem);
 246 }
 247
 248 /**
 249  * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
 250  *                              to system/BAR0 region.
 251  *
 252  * @dst_iomem: Pointer to the destination location in BAR0 space.
 253  * @src: Pointer to the Source data.
 254  * @size: Size of data to be copied.
 255  */
 256 static void
 257 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
 258 {
 259         int i;
 260         u32 *src_virt_mem = (u32 *)src;
 261
 262         for (i = 0; i < size/4; i++)
 263                 writel((u32)src_virt_mem[i],
 264                                 (void __iomem *)dst_iomem + (i * 4));
 265 }
 266
 267 /**
 268  * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
 269  *
 270  * @dst_iomem: Pointer to the destination location in BAR0 space.
 271  * @src: Pointer to the Source data.
 272  * @size: Size of data to be copied.
 273  */
 274 static void
 275 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
 276 {
 277         int i;
 278         u32 *src_virt_mem = (u32 *)(src);
 279
 280         for (i = 0; i < size/4; i++)
 281                 writel((u32)src_virt_mem[i],
 282                         (void __iomem *)dst_iomem + (i * 4));
 283 }
 284
 285 /**
 286  * _base_get_chain - Calculates and Returns virtual chain address
 287  *                       for the provided smid in BAR0 space.
 288  *
 289  * @ioc: per adapter object
 290  * @smid: system request message index
 291  * @sge_chain_count: Scatter gather chain count.
 292  *
 293  * Return: the chain address.
 294  */
 295 static inline void __iomem*
 296 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
 297                 u8 sge_chain_count)
 298 {
 299         void __iomem *base_chain, *chain_virt;
 300         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 301
 302         base_chain  = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
 303                 (cmd_credit * ioc->request_sz) +
 304                 REPLY_FREE_POOL_SIZE;
 305         chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
 306                         ioc->request_sz) + (sge_chain_count * ioc->request_sz);
 307         return chain_virt;
 308 }
 309
 310 /**
 311  * _base_get_chain_phys - Calculates and Returns physical address
 312  *                      in BAR0 for scatter gather chains, for
 313  *                      the provided smid.
 314  *
 315  * @ioc: per adapter object
 316  * @smid: system request message index
 317  * @sge_chain_count: Scatter gather chain count.
 318  *
 319  * Return: Physical chain address.
 320  */
 321 static inline phys_addr_t
 322 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
 323                 u8 sge_chain_count)
 324 {
 325         phys_addr_t base_chain_phys, chain_phys;
 326         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 327
 328         base_chain_phys  = ioc->chip_phys + MPI_FRAME_START_OFFSET +
 329                 (cmd_credit * ioc->request_sz) +
 330                 REPLY_FREE_POOL_SIZE;
 331         chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
 332                         ioc->request_sz) + (sge_chain_count * ioc->request_sz);
 333         return chain_phys;
 334 }
 335
 336 /**
 337  * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
 338  *                      buffer address for the provided smid.
 339  *                      (Each smid can have 64K starts from 17024)
 340  *
 341  * @ioc: per adapter object
 342  * @smid: system request message index
 343  *
 344  * Return: Pointer to buffer location in BAR0.
 345  */
 346
 347 static void __iomem *
 348 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 349 {
 350         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 351         // Added extra 1 to reach end of chain.
 352         void __iomem *chain_end = _base_get_chain(ioc,
 353                         cmd_credit + 1,
 354                         ioc->facts.MaxChainDepth);
 355         return chain_end + (smid * 64 * 1024);
 356 }
 357
 358 /**
 359  * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
 360  *              Host buffer Physical address for the provided smid.
 361  *              (Each smid can have 64K starts from 17024)
 362  *
 363  * @ioc: per adapter object
 364  * @smid: system request message index
 365  *
 366  * Return: Pointer to buffer location in BAR0.
 367  */
 368 static phys_addr_t
 369 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 370 {
 371         u16 cmd_credit = ioc->facts.RequestCredit + 1;
 372         phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
 373                         cmd_credit + 1,
 374                         ioc->facts.MaxChainDepth);
 375         return chain_end_phys + (smid * 64 * 1024);
 376 }
 377
 378 /**
 379  * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
 380  *                      lookup list and Provides chain_buffer
 381  *                      address for the matching dma address.
 382  *                      (Each smid can have 64K starts from 17024)
 383  *
 384  * @ioc: per adapter object
 385  * @chain_buffer_dma: Chain buffer dma address.
 386  *
 387  * Return: Pointer to chain buffer. Or Null on Failure.
 388  */
 389 static void *
 390 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
 391                 dma_addr_t chain_buffer_dma)
 392 {
 393         u16 index, j;
 394         struct chain_tracker *ct;
 395
 396         for (index = 0; index < ioc->scsiio_depth; index++) {
 397                 for (j = 0; j < ioc->chains_needed_per_io; j++) {
 398                         ct = &ioc->chain_lookup[index].chains_per_smid[j];
 399                         if (ct && ct->chain_buffer_dma == chain_buffer_dma)
 400                                 return ct->chain_buffer;
 401                 }
 402         }
 403         ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
 404         return NULL;
 405 }
 406
 407 /**
 408  * _clone_sg_entries -  MPI EP's scsiio and config requests
 409  *                      are handled here. Base function for
 410  *                      double buffering, before submitting
 411  *                      the requests.
 412  *
 413  * @ioc: per adapter object.
 414  * @mpi_request: mf request pointer.
 415  * @smid: system request message index.
 416  */
 417 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
 418                 void *mpi_request, u16 smid)
 419 {
 420         Mpi2SGESimple32_t *sgel, *sgel_next;
 421         u32  sgl_flags, sge_chain_count = 0;
 422         bool is_write = false;
 423         u16 i = 0;
 424         void __iomem *buffer_iomem;
 425         phys_addr_t buffer_iomem_phys;
 426         void __iomem *buff_ptr;
 427         phys_addr_t buff_ptr_phys;
 428         void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
 429         void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
 430         phys_addr_t dst_addr_phys;
 431         MPI2RequestHeader_t *request_hdr;
 432         struct scsi_cmnd *scmd;
 433         struct scatterlist *sg_scmd = NULL;
 434         int is_scsiio_req = 0;
 435
 436         request_hdr = (MPI2RequestHeader_t *) mpi_request;
 437
 438         if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
 439                 Mpi25SCSIIORequest_t *scsiio_request =
 440                         (Mpi25SCSIIORequest_t *)mpi_request;
 441                 sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
 442                 is_scsiio_req = 1;
 443         } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
 444                 Mpi2ConfigRequest_t  *config_req =
 445                         (Mpi2ConfigRequest_t *)mpi_request;
 446                 sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
 447         } else
 448                 return;
 449
 450         /* From smid we can get scsi_cmd, once we have sg_scmd,
 451          * we just need to get sg_virt and sg_next to get virtual
 452          * address associated with sgel->Address.
 453          */
 454
 455         if (is_scsiio_req) {
 456                 /* Get scsi_cmd using smid */
 457                 scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
 458                 if (scmd == NULL) {
 459                         ioc_err(ioc, "scmd is NULL\n");
 460                         return;
 461                 }
 462
 463                 /* Get sg_scmd from scmd provided */
 464                 sg_scmd = scsi_sglist(scmd);
 465         }
 466
 467         /*
 468          * 0 - 255      System register
 469          * 256 - 4352   MPI Frame. (This is based on maxCredit 32)
 470          * 4352 - 4864  Reply_free pool (512 byte is reserved
 471          *              considering maxCredit 32. Reply need extra
 472          *              room, for mCPU case kept four times of
 473          *              maxCredit).
 474          * 4864 - 17152 SGE chain element. (32cmd * 3 chain of
 475          *              128 byte size = 12288)
 476          * 17152 - x    Host buffer mapped with smid.
 477          *              (Each smid can have 64K Max IO.)
 478          * BAR0+Last 1K MSIX Addr and Data
 479          * Total size in use 2113664 bytes of 4MB BAR0
 480          */
 481
 482         buffer_iomem = _base_get_buffer_bar0(ioc, smid);
 483         buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
 484
 485         buff_ptr = buffer_iomem;
 486         buff_ptr_phys = buffer_iomem_phys;
 487         WARN_ON(buff_ptr_phys > U32_MAX);
 488
 489         if (le32_to_cpu(sgel->FlagsLength) &
 490                         (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
 491                 is_write = true;
 492
 493         for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
 494
 495                 sgl_flags =
 496                     (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
 497
 498                 switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
 499                 case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
 500                         /*
 501                          * Helper function which on passing
 502                          * chain_buffer_dma returns chain_buffer. Get
 503                          * the virtual address for sgel->Address
 504                          */
 505                         sgel_next =
 506                                 _base_get_chain_buffer_dma_to_chain_buffer(ioc,
 507                                                 le32_to_cpu(sgel->Address));
 508                         if (sgel_next == NULL)
 509                                 return;
 510                         /*
 511                          * This is coping 128 byte chain
 512                          * frame (not a host buffer)
 513                          */
 514                         dst_chain_addr[sge_chain_count] =
 515                                 _base_get_chain(ioc,
 516                                         smid, sge_chain_count);
 517                         src_chain_addr[sge_chain_count] =
 518                                                 (void *) sgel_next;
 519                         dst_addr_phys = _base_get_chain_phys(ioc,
 520                                                 smid, sge_chain_count);
 521                         WARN_ON(dst_addr_phys > U32_MAX);
 522                         sgel->Address =
 523                                 cpu_to_le32(lower_32_bits(dst_addr_phys));
 524                         sgel = sgel_next;
 525                         sge_chain_count++;
 526                         break;
 527                 case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
 528                         if (is_write) {
 529                                 if (is_scsiio_req) {
 530                                         _base_clone_to_sys_mem(buff_ptr,
 531                                             sg_virt(sg_scmd),
 532                                             (le32_to_cpu(sgel->FlagsLength) &
 533                                             0x00ffffff));
 534                                         /*
 535                                          * FIXME: this relies on a a zero
 536                                          * PCI mem_offset.
 537                                          */
 538                                         sgel->Address =
 539                                             cpu_to_le32((u32)buff_ptr_phys);
 540                                 } else {
 541                                         _base_clone_to_sys_mem(buff_ptr,
 542                                             ioc->config_vaddr,
 543                                             (le32_to_cpu(sgel->FlagsLength) &
 544                                             0x00ffffff));
 545                                         sgel->Address =
 546                                             cpu_to_le32((u32)buff_ptr_phys);
 547                                 }
 548                         }
 549                         buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
 550                             0x00ffffff);
 551                         buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
 552                             0x00ffffff);
 553                         if ((le32_to_cpu(sgel->FlagsLength) &
 554                             (MPI2_SGE_FLAGS_END_OF_BUFFER
 555                                         << MPI2_SGE_FLAGS_SHIFT)))
 556                                 goto eob_clone_chain;
 557                         else {
 558                                 /*
 559                                  * Every single element in MPT will have
 560                                  * associated sg_next. Better to sanity that
 561                                  * sg_next is not NULL, but it will be a bug
 562                                  * if it is null.
 563                                  */
 564                                 if (is_scsiio_req) {
 565                                         sg_scmd = sg_next(sg_scmd);
 566                                         if (sg_scmd)
 567                                                 sgel++;
 568                                         else
 569                                                 goto eob_clone_chain;
 570                                 }
 571                         }
 572                         break;
 573                 }
 574         }
 575
 576 eob_clone_chain:
 577         for (i = 0; i < sge_chain_count; i++) {
 578                 if (is_scsiio_req)
 579                         _base_clone_to_sys_mem(dst_chain_addr[i],
 580                                 src_chain_addr[i], ioc->request_sz);
 581         }
 582 }
 583
 584 /**
 585  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
 586  * @arg: input argument, used to derive ioc
 587  *
 588  * Return:
 589  * 0 if controller is removed from pci subsystem.
 590  * -1 for other case.
 591  */
 592 static int mpt3sas_remove_dead_ioc_func(void *arg)
 593 {
 594         struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
 595         struct pci_dev *pdev;
 596
 597         if (!ioc)
 598                 return -1;
 599
 600         pdev = ioc->pdev;
 601         if (!pdev)
 602                 return -1;
 603         pci_stop_and_remove_bus_device_locked(pdev);
 604         return 0;
 605 }
 606
 607 /**
 608  * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp.
 609  * @ioc: Per Adapter Object
 610  *
 611  * Return: nothing.
 612  */
 613 static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc)
 614 {
 615         Mpi26IoUnitControlRequest_t *mpi_request;
 616         Mpi26IoUnitControlReply_t *mpi_reply;
 617         u16 smid;
 618         ktime_t current_time;
 619         u64 TimeStamp = 0;
 620         u8 issue_reset = 0;
 621
 622         mutex_lock(&ioc->scsih_cmds.mutex);
 623         if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) {
 624                 ioc_err(ioc, "scsih_cmd in use %s\n", __func__);
 625                 goto out;
 626         }
 627         ioc->scsih_cmds.status = MPT3_CMD_PENDING;
 628         smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx);
 629         if (!smid) {
 630                 ioc_err(ioc, "Failed obtaining a smid %s\n", __func__);
 631                 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
 632                 goto out;
 633         }
 634         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
 635         ioc->scsih_cmds.smid = smid;
 636         memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t));
 637         mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL;
 638         mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER;
 639         mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP;
 640         current_time = ktime_get_real();
 641         TimeStamp = ktime_to_ms(current_time);
 642         mpi_request->Reserved7 = cpu_to_le32(TimeStamp >> 32);
 643         mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp & 0xFFFFFFFF);
 644         init_completion(&ioc->scsih_cmds.done);
 645         ioc->put_smid_default(ioc, smid);
 646         dinitprintk(ioc, ioc_info(ioc,
 647             "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n",
 648             TimeStamp));
 649         wait_for_completion_timeout(&ioc->scsih_cmds.done,
 650                 MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ);
 651         if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) {
 652                 mpt3sas_check_cmd_timeout(ioc,
 653                     ioc->scsih_cmds.status, mpi_request,
 654                     sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset);
 655                 goto issue_host_reset;
 656         }
 657         if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) {
 658                 mpi_reply = ioc->scsih_cmds.reply;
 659                 dinitprintk(ioc, ioc_info(ioc,
 660                     "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n",
 661                     le16_to_cpu(mpi_reply->IOCStatus),
 662                     le32_to_cpu(mpi_reply->IOCLogInfo)));
 663         }
 664 issue_host_reset:
 665         if (issue_reset)
 666                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 667         ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
 668 out:
 669         mutex_unlock(&ioc->scsih_cmds.mutex);
 670 }
 671
 672 /**
 673  * _base_fault_reset_work - workq handling ioc fault conditions
 674  * @work: input argument, used to derive ioc
 675  *
 676  * Context: sleep.
 677  */
 678 static void
 679 _base_fault_reset_work(struct work_struct *work)
 680 {
 681         struct MPT3SAS_ADAPTER *ioc =
 682             container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
 683         unsigned long    flags;
 684         u32 doorbell;
 685         int rc;
 686         struct task_struct *p;
 687
 688
 689         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 690         if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) ||
 691                         ioc->pci_error_recovery)
 692                 goto rearm_timer;
 693         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 694
 695         doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 696         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
 697                 ioc_err(ioc, "SAS host is non-operational !!!!\n");
 698
 699                 /* It may be possible that EEH recovery can resolve some of
 700                  * pci bus failure issues rather removing the dead ioc function
 701                  * by considering controller is in a non-operational state. So
 702                  * here priority is given to the EEH recovery. If it doesn't
 703                  * not resolve this issue, mpt3sas driver will consider this
 704                  * controller to non-operational state and remove the dead ioc
 705                  * function.
 706                  */
 707                 if (ioc->non_operational_loop++ < 5) {
 708                         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
 709                                                          flags);
 710                         goto rearm_timer;
 711                 }
 712
 713                 /*
 714                  * Call _scsih_flush_pending_cmds callback so that we flush all
 715                  * pending commands back to OS. This call is required to avoid
 716                  * deadlock at block layer. Dead IOC will fail to do diag reset,
 717                  * and this call is safe since dead ioc will never return any
 718                  * command back from HW.
 719                  */
 720                 mpt3sas_base_pause_mq_polling(ioc);
 721                 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
 722                 /*
 723                  * Set remove_host flag early since kernel thread will
 724                  * take some time to execute.
 725                  */
 726                 ioc->remove_host = 1;
 727                 /*Remove the Dead Host */
 728                 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
 729                     "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
 730                 if (IS_ERR(p))
 731                         ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
 732                                 __func__);
 733                 else
 734                         ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
 735                                 __func__);
 736                 return; /* don't rearm timer */
 737         }
 738
 739         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
 740                 u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
 741                     ioc->manu_pg11.CoreDumpTOSec :
 742                     MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
 743
 744                 timeout /= (FAULT_POLLING_INTERVAL/1000);
 745
 746                 if (ioc->ioc_coredump_loop == 0) {
 747                         mpt3sas_print_coredump_info(ioc,
 748                             doorbell & MPI2_DOORBELL_DATA_MASK);
 749                         /* do not accept any IOs and disable the interrupts */
 750                         spin_lock_irqsave(
 751                             &ioc->ioc_reset_in_progress_lock, flags);
 752                         ioc->shost_recovery = 1;
 753                         spin_unlock_irqrestore(
 754                             &ioc->ioc_reset_in_progress_lock, flags);
 755                         mpt3sas_base_mask_interrupts(ioc);
 756                         mpt3sas_base_pause_mq_polling(ioc);
 757                         _base_clear_outstanding_commands(ioc);
 758                 }
 759
 760                 ioc_info(ioc, "%s: CoreDump loop %d.",
 761                     __func__, ioc->ioc_coredump_loop);
 762
 763                 /* Wait until CoreDump completes or times out */
 764                 if (ioc->ioc_coredump_loop++ < timeout) {
 765                         spin_lock_irqsave(
 766                             &ioc->ioc_reset_in_progress_lock, flags);
 767                         goto rearm_timer;
 768                 }
 769         }
 770
 771         if (ioc->ioc_coredump_loop) {
 772                 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
 773                         ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
 774                             __func__, ioc->ioc_coredump_loop);
 775                 else
 776                         ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
 777                             __func__, ioc->ioc_coredump_loop);
 778                 ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
 779         }
 780         ioc->non_operational_loop = 0;
 781         if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
 782                 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 783                 ioc_warn(ioc, "%s: hard reset: %s\n",
 784                          __func__, rc == 0 ? "success" : "failed");
 785                 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 786                 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
 787                         mpt3sas_print_fault_code(ioc, doorbell &
 788                             MPI2_DOORBELL_DATA_MASK);
 789                 } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
 790                     MPI2_IOC_STATE_COREDUMP)
 791                         mpt3sas_print_coredump_info(ioc, doorbell &
 792                             MPI2_DOORBELL_DATA_MASK);
 793                 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
 794                     MPI2_IOC_STATE_OPERATIONAL)
 795                         return; /* don't rearm timer */
 796         }
 797         ioc->ioc_coredump_loop = 0;
 798         if (ioc->time_sync_interval &&
 799             ++ioc->timestamp_update_count >= ioc->time_sync_interval) {
 800                 ioc->timestamp_update_count = 0;
 801                 _base_sync_drv_fw_timestamp(ioc);
 802         }
 803         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 804  rearm_timer:
 805         if (ioc->fault_reset_work_q)
 806                 queue_delayed_work(ioc->fault_reset_work_q,
 807                     &ioc->fault_reset_work,
 808                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 809         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 810 }
 811
 812 /**
 813  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
 814  * @ioc: per adapter object
 815  *
 816  * Context: sleep.
 817  */
 818 void
 819 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
 820 {
 821         unsigned long    flags;
 822
 823         if (ioc->fault_reset_work_q)
 824                 return;
 825
 826         ioc->timestamp_update_count = 0;
 827         /* initialize fault polling */
 828
 829         INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
 830         snprintf(ioc->fault_reset_work_q_name,
 831             sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
 832             ioc->driver_name, ioc->id);
 833         ioc->fault_reset_work_q =
 834                 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
 835         if (!ioc->fault_reset_work_q) {
 836                 ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
 837                 return;
 838         }
 839         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 840         if (ioc->fault_reset_work_q)
 841                 queue_delayed_work(ioc->fault_reset_work_q,
 842                     &ioc->fault_reset_work,
 843                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 844         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 845 }
 846
 847 /**
 848  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
 849  * @ioc: per adapter object
 850  *
 851  * Context: sleep.
 852  */
 853 void
 854 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
 855 {
 856         unsigned long flags;
 857         struct workqueue_struct *wq;
 858
 859         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 860         wq = ioc->fault_reset_work_q;
 861         ioc->fault_reset_work_q = NULL;
 862         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 863         if (wq) {
 864                 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
 865                         flush_workqueue(wq);
 866                 destroy_workqueue(wq);
 867         }
 868 }
 869
 870 /**
 871  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
 872  * @ioc: per adapter object
 873  * @fault_code: fault code
 874  */
 875 void
 876 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
 877 {
 878         ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
 879 }
 880
 881 /**
 882  * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
 883  * @ioc: per adapter object
 884  * @fault_code: fault code
 885  *
 886  * Return: nothing.
 887  */
 888 void
 889 mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
 890 {
 891         ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
 892 }
 893
 894 /**
 895  * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
 896  * completes or times out
 897  * @ioc: per adapter object
 898  * @caller: caller function name
 899  *
 900  * Return: 0 for success, non-zero for failure.
 901  */
 902 int
 903 mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
 904                 const char *caller)
 905 {
 906         u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
 907                         ioc->manu_pg11.CoreDumpTOSec :
 908                         MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
 909
 910         int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
 911                                         timeout);
 912
 913         if (ioc_state)
 914                 ioc_err(ioc,
 915                     "%s: CoreDump timed out. (ioc_state=0x%x)\n",
 916                     caller, ioc_state);
 917         else
 918                 ioc_info(ioc,
 919                     "%s: CoreDump completed. (ioc_state=0x%x)\n",
 920                     caller, ioc_state);
 921
 922         return ioc_state;
 923 }
 924
 925 /**
 926  * mpt3sas_halt_firmware - halt's mpt controller firmware
 927  * @ioc: per adapter object
 928  *
 929  * For debugging timeout related issues.  Writing 0xCOFFEE00
 930  * to the doorbell register will halt controller firmware. With
 931  * the purpose to stop both driver and firmware, the enduser can
 932  * obtain a ring buffer from controller UART.
 933  */
 934 void
 935 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
 936 {
 937         u32 doorbell;
 938
 939         if (!ioc->fwfault_debug)
 940                 return;
 941
 942         dump_stack();
 943
 944         doorbell = ioc->base_readl(&ioc->chip->Doorbell);
 945         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
 946                 mpt3sas_print_fault_code(ioc, doorbell &
 947                     MPI2_DOORBELL_DATA_MASK);
 948         } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
 949             MPI2_IOC_STATE_COREDUMP) {
 950                 mpt3sas_print_coredump_info(ioc, doorbell &
 951                     MPI2_DOORBELL_DATA_MASK);
 952         } else {
 953                 writel(0xC0FFEE00, &ioc->chip->Doorbell);
 954                 ioc_err(ioc, "Firmware is halted due to command timeout\n");
 955         }
 956
 957         if (ioc->fwfault_debug == 2)
 958                 for (;;)
 959                         ;
 960         else
 961                 panic("panic in %s\n", __func__);
 962 }
 963
 964 /**
 965  * _base_sas_ioc_info - verbose translation of the ioc status
 966  * @ioc: per adapter object
 967  * @mpi_reply: reply mf payload returned from firmware
 968  * @request_hdr: request mf
 969  */
 970 static void
 971 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
 972         MPI2RequestHeader_t *request_hdr)
 973 {
 974         u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
 975             MPI2_IOCSTATUS_MASK;
 976         char *desc = NULL;
 977         u16 frame_sz;
 978         char *func_str = NULL;
 979
 980         /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
 981         if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
 982             request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
 983             request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
 984                 return;
 985
 986         if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
 987                 return;
 988         /*
 989          * Older Firmware version doesn't support driver trigger pages.
 990          * So, skip displaying 'config invalid type' type
 991          * of error message.
 992          */
 993         if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
 994                 Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr;
 995
 996                 if ((rqst->ExtPageType ==
 997                     MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) &&
 998                     !(ioc->logging_level & MPT_DEBUG_CONFIG)) {
 999                         return;
1000                 }
1001         }
1002
1003         switch (ioc_status) {
1004
1005 /****************************************************************************
1006 *  Common IOCStatus values for all replies
1007 ****************************************************************************/
1008
1009         case MPI2_IOCSTATUS_INVALID_FUNCTION:
1010                 desc = "invalid function";
1011                 break;
1012         case MPI2_IOCSTATUS_BUSY:
1013                 desc = "busy";
1014                 break;
1015         case MPI2_IOCSTATUS_INVALID_SGL:
1016                 desc = "invalid sgl";
1017                 break;
1018         case MPI2_IOCSTATUS_INTERNAL_ERROR:
1019                 desc = "internal error";
1020                 break;
1021         case MPI2_IOCSTATUS_INVALID_VPID:
1022                 desc = "invalid vpid";
1023                 break;
1024         case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
1025                 desc = "insufficient resources";
1026                 break;
1027         case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
1028                 desc = "insufficient power";
1029                 break;
1030         case MPI2_IOCSTATUS_INVALID_FIELD:
1031                 desc = "invalid field";
1032                 break;
1033         case MPI2_IOCSTATUS_INVALID_STATE:
1034                 desc = "invalid state";
1035                 break;
1036         case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
1037                 desc = "op state not supported";
1038                 break;
1039
1040 /****************************************************************************
1041 *  Config IOCStatus values
1042 ****************************************************************************/
1043
1044         case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
1045                 desc = "config invalid action";
1046                 break;
1047         case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
1048                 desc = "config invalid type";
1049                 break;
1050         case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
1051                 desc = "config invalid page";
1052                 break;
1053         case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
1054                 desc = "config invalid data";
1055                 break;
1056         case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
1057                 desc = "config no defaults";
1058                 break;
1059         case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
1060                 desc = "config cant commit";
1061                 break;
1062
1063 /****************************************************************************
1064 *  SCSI IO Reply
1065 ****************************************************************************/
1066
1067         case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
1068         case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
1069         case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
1070         case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
1071         case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
1072         case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
1073         case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
1074         case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
1075         case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
1076         case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
1077         case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
1078         case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
1079                 break;
1080
1081 /****************************************************************************
1082 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
1083 ****************************************************************************/
1084
1085         case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
1086                 desc = "eedp guard error";
1087                 break;
1088         case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
1089                 desc = "eedp ref tag error";
1090                 break;
1091         case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
1092                 desc = "eedp app tag error";
1093                 break;
1094
1095 /****************************************************************************
1096 *  SCSI Target values
1097 ****************************************************************************/
1098
1099         case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
1100                 desc = "target invalid io index";
1101                 break;
1102         case MPI2_IOCSTATUS_TARGET_ABORTED:
1103                 desc = "target aborted";
1104                 break;
1105         case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
1106                 desc = "target no conn retryable";
1107                 break;
1108         case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
1109                 desc = "target no connection";
1110                 break;
1111         case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
1112                 desc = "target xfer count mismatch";
1113                 break;
1114         case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
1115                 desc = "target data offset error";
1116                 break;
1117         case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
1118                 desc = "target too much write data";
1119                 break;
1120         case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
1121                 desc = "target iu too short";
1122                 break;
1123         case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
1124                 desc = "target ack nak timeout";
1125                 break;
1126         case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
1127                 desc = "target nak received";
1128                 break;
1129
1130 /****************************************************************************
1131 *  Serial Attached SCSI values
1132 ****************************************************************************/
1133
1134         case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
1135                 desc = "smp request failed";
1136                 break;
1137         case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
1138                 desc = "smp data overrun";
1139                 break;
1140
1141 /****************************************************************************
1142 *  Diagnostic Buffer Post / Diagnostic Release values
1143 ****************************************************************************/
1144
1145         case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
1146                 desc = "diagnostic released";
1147                 break;
1148         default:
1149                 break;
1150         }
1151
1152         if (!desc)
1153                 return;
1154
1155         switch (request_hdr->Function) {
1156         case MPI2_FUNCTION_CONFIG:
1157                 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
1158                 func_str = "config_page";
1159                 break;
1160         case MPI2_FUNCTION_SCSI_TASK_MGMT:
1161                 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
1162                 func_str = "task_mgmt";
1163                 break;
1164         case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
1165                 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
1166                 func_str = "sas_iounit_ctl";
1167                 break;
1168         case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
1169                 frame_sz = sizeof(Mpi2SepRequest_t);
1170                 func_str = "enclosure";
1171                 break;
1172         case MPI2_FUNCTION_IOC_INIT:
1173                 frame_sz = sizeof(Mpi2IOCInitRequest_t);
1174                 func_str = "ioc_init";
1175                 break;
1176         case MPI2_FUNCTION_PORT_ENABLE:
1177                 frame_sz = sizeof(Mpi2PortEnableRequest_t);
1178                 func_str = "port_enable";
1179                 break;
1180         case MPI2_FUNCTION_SMP_PASSTHROUGH:
1181                 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
1182                 func_str = "smp_passthru";
1183                 break;
1184         case MPI2_FUNCTION_NVME_ENCAPSULATED:
1185                 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
1186                     ioc->sge_size;
1187                 func_str = "nvme_encapsulated";
1188                 break;
1189         default:
1190                 frame_sz = 32;
1191                 func_str = "unknown";
1192                 break;
1193         }
1194
1195         ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
1196                  desc, ioc_status, request_hdr, func_str);
1197
1198         _debug_dump_mf(request_hdr, frame_sz/4);
1199 }
1200
1201 /**
1202  * _base_display_event_data - verbose translation of firmware asyn events
1203  * @ioc: per adapter object
1204  * @mpi_reply: reply mf payload returned from firmware
1205  */
1206 static void
1207 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
1208         Mpi2EventNotificationReply_t *mpi_reply)
1209 {
1210         char *desc = NULL;
1211         u16 event;
1212
1213         if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
1214                 return;
1215
1216         event = le16_to_cpu(mpi_reply->Event);
1217
1218         switch (event) {
1219         case MPI2_EVENT_LOG_DATA:
1220                 desc = "Log Data";
1221                 break;
1222         case MPI2_EVENT_STATE_CHANGE:
1223                 desc = "Status Change";
1224                 break;
1225         case MPI2_EVENT_HARD_RESET_RECEIVED:
1226                 desc = "Hard Reset Received";
1227                 break;
1228         case MPI2_EVENT_EVENT_CHANGE:
1229                 desc = "Event Change";
1230                 break;
1231         case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
1232                 desc = "Device Status Change";
1233                 break;
1234         case MPI2_EVENT_IR_OPERATION_STATUS:
1235                 if (!ioc->hide_ir_msg)
1236                         desc = "IR Operation Status";
1237                 break;
1238         case MPI2_EVENT_SAS_DISCOVERY:
1239         {
1240                 Mpi2EventDataSasDiscovery_t *event_data =
1241                     (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1242                 ioc_info(ioc, "Discovery: (%s)",
1243                          event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
1244                          "start" : "stop");
1245                 if (event_data->DiscoveryStatus)
1246                         pr_cont(" discovery_status(0x%08x)",
1247                             le32_to_cpu(event_data->DiscoveryStatus));
1248                 pr_cont("\n");
1249                 return;
1250         }
1251         case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
1252                 desc = "SAS Broadcast Primitive";
1253                 break;
1254         case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
1255                 desc = "SAS Init Device Status Change";
1256                 break;
1257         case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
1258                 desc = "SAS Init Table Overflow";
1259                 break;
1260         case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1261                 desc = "SAS Topology Change List";
1262                 break;
1263         case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
1264                 desc = "SAS Enclosure Device Status Change";
1265                 break;
1266         case MPI2_EVENT_IR_VOLUME:
1267                 if (!ioc->hide_ir_msg)
1268                         desc = "IR Volume";
1269                 break;
1270         case MPI2_EVENT_IR_PHYSICAL_DISK:
1271                 if (!ioc->hide_ir_msg)
1272                         desc = "IR Physical Disk";
1273                 break;
1274         case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
1275                 if (!ioc->hide_ir_msg)
1276                         desc = "IR Configuration Change List";
1277                 break;
1278         case MPI2_EVENT_LOG_ENTRY_ADDED:
1279                 if (!ioc->hide_ir_msg)
1280                         desc = "Log Entry Added";
1281                 break;
1282         case MPI2_EVENT_TEMP_THRESHOLD:
1283                 desc = "Temperature Threshold";
1284                 break;
1285         case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
1286                 desc = "Cable Event";
1287                 break;
1288         case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1289                 desc = "SAS Device Discovery Error";
1290                 break;
1291         case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
1292                 desc = "PCIE Device Status Change";
1293                 break;
1294         case MPI2_EVENT_PCIE_ENUMERATION:
1295         {
1296                 Mpi26EventDataPCIeEnumeration_t *event_data =
1297                         (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1298                 ioc_info(ioc, "PCIE Enumeration: (%s)",
1299                          event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
1300                          "start" : "stop");
1301                 if (event_data->EnumerationStatus)
1302                         pr_cont("enumeration_status(0x%08x)",
1303                                 le32_to_cpu(event_data->EnumerationStatus));
1304                 pr_cont("\n");
1305                 return;
1306         }
1307         case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1308                 desc = "PCIE Topology Change List";
1309                 break;
1310         }
1311
1312         if (!desc)
1313                 return;
1314
1315         ioc_info(ioc, "%s\n", desc);
1316 }
1317
1318 /**
1319  * _base_sas_log_info - verbose translation of firmware log info
1320  * @ioc: per adapter object
1321  * @log_info: log info
1322  */
1323 static void
1324 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
1325 {
1326         union loginfo_type {
1327                 u32     loginfo;
1328                 struct {
1329                         u32     subcode:16;
1330                         u32     code:8;
1331                         u32     originator:4;
1332                         u32     bus_type:4;
1333                 } dw;
1334         };
1335         union loginfo_type sas_loginfo;
1336         char *originator_str = NULL;
1337
1338         sas_loginfo.loginfo = log_info;
1339         if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1340                 return;
1341
1342         /* each nexus loss loginfo */
1343         if (log_info == 0x31170000)
1344                 return;
1345
1346         /* eat the loginfos associated with task aborts */
1347         if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
1348             0x31140000 || log_info == 0x31130000))
1349                 return;
1350
1351         switch (sas_loginfo.dw.originator) {
1352         case 0:
1353                 originator_str = "IOP";
1354                 break;
1355         case 1:
1356                 originator_str = "PL";
1357                 break;
1358         case 2:
1359                 if (!ioc->hide_ir_msg)
1360                         originator_str = "IR";
1361                 else
1362                         originator_str = "WarpDrive";
1363                 break;
1364         }
1365
1366         ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1367                  log_info,
1368                  originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1369 }
1370
1371 /**
1372  * _base_display_reply_info - handle reply descriptors depending on IOC Status
1373  * @ioc: per adapter object
1374  * @smid: system request message index
1375  * @msix_index: MSIX table index supplied by the OS
1376  * @reply: reply message frame (lower 32bit addr)
1377  */
1378 static void
1379 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1380         u32 reply)
1381 {
1382         MPI2DefaultReply_t *mpi_reply;
1383         u16 ioc_status;
1384         u32 loginfo = 0;
1385
1386         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1387         if (unlikely(!mpi_reply)) {
1388                 ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
1389                         __FILE__, __LINE__, __func__);
1390                 return;
1391         }
1392         ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
1393
1394         if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
1395             (ioc->logging_level & MPT_DEBUG_REPLY)) {
1396                 _base_sas_ioc_info(ioc , mpi_reply,
1397                    mpt3sas_base_get_msg_frame(ioc, smid));
1398         }
1399
1400         if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1401                 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1402                 _base_sas_log_info(ioc, loginfo);
1403         }
1404
1405         if (ioc_status || loginfo) {
1406                 ioc_status &= MPI2_IOCSTATUS_MASK;
1407                 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
1408         }
1409 }
1410
1411 /**
1412  * mpt3sas_base_done - base internal command completion routine
1413  * @ioc: per adapter object
1414  * @smid: system request message index
1415  * @msix_index: MSIX table index supplied by the OS
1416  * @reply: reply message frame(lower 32bit addr)
1417  *
1418  * Return:
1419  * 1 meaning mf should be freed from _base_interrupt
1420  * 0 means the mf is freed from this function.
1421  */
1422 u8
1423 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1424         u32 reply)
1425 {
1426         MPI2DefaultReply_t *mpi_reply;
1427
1428         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1429         if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
1430                 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
1431
1432         if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
1433                 return 1;
1434
1435         ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
1436         if (mpi_reply) {
1437                 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
1438                 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1439         }
1440         ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
1441
1442         complete(&ioc->base_cmds.done);
1443         return 1;
1444 }
1445
1446 /**
1447  * _base_async_event - main callback handler for firmware asyn events
1448  * @ioc: per adapter object
1449  * @msix_index: MSIX table index supplied by the OS
1450  * @reply: reply message frame(lower 32bit addr)
1451  *
1452  * Return:
1453  * 1 meaning mf should be freed from _base_interrupt
1454  * 0 means the mf is freed from this function.
1455  */
1456 static u8
1457 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1458 {
1459         Mpi2EventNotificationReply_t *mpi_reply;
1460         Mpi2EventAckRequest_t *ack_request;
1461         u16 smid;
1462         struct _event_ack_list *delayed_event_ack;
1463
1464         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1465         if (!mpi_reply)
1466                 return 1;
1467         if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
1468                 return 1;
1469
1470         _base_display_event_data(ioc, mpi_reply);
1471
1472         if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
1473                 goto out;
1474         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
1475         if (!smid) {
1476                 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
1477                                         GFP_ATOMIC);
1478                 if (!delayed_event_ack)
1479                         goto out;
1480                 INIT_LIST_HEAD(&delayed_event_ack->list);
1481                 delayed_event_ack->Event = mpi_reply->Event;
1482                 delayed_event_ack->EventContext = mpi_reply->EventContext;
1483                 list_add_tail(&delayed_event_ack->list,
1484                                 &ioc->delayed_event_ack_list);
1485                 dewtprintk(ioc,
1486                            ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
1487                                     le16_to_cpu(mpi_reply->Event)));
1488                 goto out;
1489         }
1490
1491         ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
1492         memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
1493         ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
1494         ack_request->Event = mpi_reply->Event;
1495         ack_request->EventContext = mpi_reply->EventContext;
1496         ack_request->VF_ID = 0;  /* TODO */
1497         ack_request->VP_ID = 0;
1498         ioc->put_smid_default(ioc, smid);
1499
1500  out:
1501
1502         /* scsih callback handler */
1503         mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1504
1505         /* ctl callback handler */
1506         mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1507
1508         return 1;
1509 }
1510
1511 static struct scsiio_tracker *
1512 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1513 {
1514         struct scsi_cmnd *cmd;
1515
1516         if (WARN_ON(!smid) ||
1517             WARN_ON(smid >= ioc->hi_priority_smid))
1518                 return NULL;
1519
1520         cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
1521         if (cmd)
1522                 return scsi_cmd_priv(cmd);
1523
1524         return NULL;
1525 }
1526
1527 /**
1528  * _base_get_cb_idx - obtain the callback index
1529  * @ioc: per adapter object
1530  * @smid: system request message index
1531  *
1532  * Return: callback index.
1533  */
1534 static u8
1535 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1536 {
1537         int i;
1538         u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
1539         u8 cb_idx = 0xFF;
1540
1541         if (smid < ioc->hi_priority_smid) {
1542                 struct scsiio_tracker *st;
1543
1544                 if (smid < ctl_smid) {
1545                         st = _get_st_from_smid(ioc, smid);
1546                         if (st)
1547                                 cb_idx = st->cb_idx;
1548                 } else if (smid == ctl_smid)
1549                         cb_idx = ioc->ctl_cb_idx;
1550         } else if (smid < ioc->internal_smid) {
1551                 i = smid - ioc->hi_priority_smid;
1552                 cb_idx = ioc->hpr_lookup[i].cb_idx;
1553         } else if (smid <= ioc->hba_queue_depth) {
1554                 i = smid - ioc->internal_smid;
1555                 cb_idx = ioc->internal_lookup[i].cb_idx;
1556         }
1557         return cb_idx;
1558 }
1559
1560 /**
1561  * mpt3sas_base_pause_mq_polling - pause polling on the mq poll queues
1562  *                              when driver is flushing out the IOs.
1563  * @ioc: per adapter object
1564  *
1565  * Pause polling on the mq poll (io uring) queues when driver is flushing
1566  * out the IOs. Otherwise we may see the race condition of completing the same
1567  * IO from two paths.
1568  *
1569  * Returns nothing.
1570  */
1571 void
1572 mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc)
1573 {
1574         int iopoll_q_count =
1575             ioc->reply_queue_count - ioc->iopoll_q_start_index;
1576         int qid;
1577
1578         for (qid = 0; qid < iopoll_q_count; qid++)
1579                 atomic_set(&ioc->io_uring_poll_queues[qid].pause, 1);
1580
1581         /*
1582          * wait for current poll to complete.
1583          */
1584         for (qid = 0; qid < iopoll_q_count; qid++) {
1585                 while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) {
1586                         cpu_relax();
1587                         udelay(500);
1588                 }
1589         }
1590 }
1591
1592 /**
1593  * mpt3sas_base_resume_mq_polling - Resume polling on mq poll queues.
1594  * @ioc: per adapter object
1595  *
1596  * Returns nothing.
1597  */
1598 void
1599 mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc)
1600 {
1601         int iopoll_q_count =
1602             ioc->reply_queue_count - ioc->iopoll_q_start_index;
1603         int qid;
1604
1605         for (qid = 0; qid < iopoll_q_count; qid++)
1606                 atomic_set(&ioc->io_uring_poll_queues[qid].pause, 0);
1607 }
1608
1609 /**
1610  * mpt3sas_base_mask_interrupts - disable interrupts
1611  * @ioc: per adapter object
1612  *
1613  * Disabling ResetIRQ, Reply and Doorbell Interrupts
1614  */
1615 void
1616 mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1617 {
1618         u32 him_register;
1619
1620         ioc->mask_interrupts = 1;
1621         him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1622         him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1623         writel(him_register, &ioc->chip->HostInterruptMask);
1624         ioc->base_readl(&ioc->chip->HostInterruptMask);
1625 }
1626
1627 /**
1628  * mpt3sas_base_unmask_interrupts - enable interrupts
1629  * @ioc: per adapter object
1630  *
1631  * Enabling only Reply Interrupts
1632  */
1633 void
1634 mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1635 {
1636         u32 him_register;
1637
1638         him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1639         him_register &= ~MPI2_HIM_RIM;
1640         writel(him_register, &ioc->chip->HostInterruptMask);
1641         ioc->mask_interrupts = 0;
1642 }
1643
1644 union reply_descriptor {
1645         u64 word;
1646         struct {
1647                 u32 low;
1648                 u32 high;
1649         } u;
1650 };
1651
1652 static u32 base_mod64(u64 dividend, u32 divisor)
1653 {
1654         u32 remainder;
1655
1656         if (!divisor)
1657                 pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
1658         remainder = do_div(dividend, divisor);
1659         return remainder;
1660 }
1661
1662 /**
1663  * _base_process_reply_queue - Process reply descriptors from reply
1664  *              descriptor post queue.
1665  * @reply_q: per IRQ's reply queue object.
1666  *
1667  * Return: number of reply descriptors processed from reply
1668  *              descriptor queue.
1669  */
1670 static int
1671 _base_process_reply_queue(struct adapter_reply_queue *reply_q)
1672 {
1673         union reply_descriptor rd;
1674         u64 completed_cmds;
1675         u8 request_descript_type;
1676         u16 smid;
1677         u8 cb_idx;
1678         u32 reply;
1679         u8 msix_index = reply_q->msix_index;
1680         struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1681         Mpi2ReplyDescriptorsUnion_t *rpf;
1682         u8 rc;
1683
1684         completed_cmds = 0;
1685         if (!atomic_add_unless(&reply_q->busy, 1, 1))
1686                 return completed_cmds;
1687
1688         rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1689         request_descript_type = rpf->Default.ReplyFlags
1690              & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1691         if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1692                 atomic_dec(&reply_q->busy);
1693                 return completed_cmds;
1694         }
1695
1696         cb_idx = 0xFF;
1697         do {
1698                 rd.word = le64_to_cpu(rpf->Words);
1699                 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1700                         goto out;
1701                 reply = 0;
1702                 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1703                 if (request_descript_type ==
1704                     MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1705                     request_descript_type ==
1706                     MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1707                     request_descript_type ==
1708                     MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1709                         cb_idx = _base_get_cb_idx(ioc, smid);
1710                         if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1711                             (likely(mpt_callbacks[cb_idx] != NULL))) {
1712                                 rc = mpt_callbacks[cb_idx](ioc, smid,
1713                                     msix_index, 0);
1714                                 if (rc)
1715                                         mpt3sas_base_free_smid(ioc, smid);
1716                         }
1717                 } else if (request_descript_type ==
1718                     MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1719                         reply = le32_to_cpu(
1720                             rpf->AddressReply.ReplyFrameAddress);
1721                         if (reply > ioc->reply_dma_max_address ||
1722                             reply < ioc->reply_dma_min_address)
1723                                 reply = 0;
1724                         if (smid) {
1725                                 cb_idx = _base_get_cb_idx(ioc, smid);
1726                                 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1727                                     (likely(mpt_callbacks[cb_idx] != NULL))) {
1728                                         rc = mpt_callbacks[cb_idx](ioc, smid,
1729                                             msix_index, reply);
1730                                         if (reply)
1731                                                 _base_display_reply_info(ioc,
1732                                                     smid, msix_index, reply);
1733                                         if (rc)
1734                                                 mpt3sas_base_free_smid(ioc,
1735                                                     smid);
1736                                 }
1737                         } else {
1738                                 _base_async_event(ioc, msix_index, reply);
1739                         }
1740
1741                         /* reply free queue handling */
1742                         if (reply) {
1743                                 ioc->reply_free_host_index =
1744                                     (ioc->reply_free_host_index ==
1745                                     (ioc->reply_free_queue_depth - 1)) ?
1746                                     0 : ioc->reply_free_host_index + 1;
1747                                 ioc->reply_free[ioc->reply_free_host_index] =
1748                                     cpu_to_le32(reply);
1749                                 if (ioc->is_mcpu_endpoint)
1750                                         _base_clone_reply_to_sys_mem(ioc,
1751                                                 reply,
1752                                                 ioc->reply_free_host_index);
1753                                 writel(ioc->reply_free_host_index,
1754                                     &ioc->chip->ReplyFreeHostIndex);
1755                         }
1756                 }
1757
1758                 rpf->Words = cpu_to_le64(ULLONG_MAX);
1759                 reply_q->reply_post_host_index =
1760                     (reply_q->reply_post_host_index ==
1761                     (ioc->reply_post_queue_depth - 1)) ? 0 :
1762                     reply_q->reply_post_host_index + 1;
1763                 request_descript_type =
1764                     reply_q->reply_post_free[reply_q->reply_post_host_index].
1765                     Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1766                 completed_cmds++;
1767                 /* Update the reply post host index after continuously
1768                  * processing the threshold number of Reply Descriptors.
1769                  * So that FW can find enough entries to post the Reply
1770                  * Descriptors in the reply descriptor post queue.
1771                  */
1772                 if (completed_cmds >= ioc->thresh_hold) {
1773                         if (ioc->combined_reply_queue) {
1774                                 writel(reply_q->reply_post_host_index |
1775                                                 ((msix_index  & 7) <<
1776                                                  MPI2_RPHI_MSIX_INDEX_SHIFT),
1777                                     ioc->replyPostRegisterIndex[msix_index/8]);
1778                         } else {
1779                                 writel(reply_q->reply_post_host_index |
1780                                                 (msix_index <<
1781                                                  MPI2_RPHI_MSIX_INDEX_SHIFT),
1782                                                 &ioc->chip->ReplyPostHostIndex);
1783                         }
1784                         if (!reply_q->is_iouring_poll_q &&
1785                             !reply_q->irq_poll_scheduled) {
1786                                 reply_q->irq_poll_scheduled = true;
1787                                 irq_poll_sched(&reply_q->irqpoll);
1788                         }
1789                         atomic_dec(&reply_q->busy);
1790                         return completed_cmds;
1791                 }
1792                 if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1793                         goto out;
1794                 if (!reply_q->reply_post_host_index)
1795                         rpf = reply_q->reply_post_free;
1796                 else
1797                         rpf++;
1798         } while (1);
1799
1800  out:
1801
1802         if (!completed_cmds) {
1803                 atomic_dec(&reply_q->busy);
1804                 return completed_cmds;
1805         }
1806
1807         if (ioc->is_warpdrive) {
1808                 writel(reply_q->reply_post_host_index,
1809                 ioc->reply_post_host_index[msix_index]);
1810                 atomic_dec(&reply_q->busy);
1811                 return completed_cmds;
1812         }
1813
1814         /* Update Reply Post Host Index.
1815          * For those HBA's which support combined reply queue feature
1816          * 1. Get the correct Supplemental Reply Post Host Index Register.
1817          *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1818          *    Index Register address bank i.e replyPostRegisterIndex[],
1819          * 2. Then update this register with new reply host index value
1820          *    in ReplyPostIndex field and the MSIxIndex field with
1821          *    msix_index value reduced to a value between 0 and 7,
1822          *    using a modulo 8 operation. Since each Supplemental Reply Post
1823          *    Host Index Register supports 8 MSI-X vectors.
1824          *
1825          * For other HBA's just update the Reply Post Host Index register with
1826          * new reply host index value in ReplyPostIndex Field and msix_index
1827          * value in MSIxIndex field.
1828          */
1829         if (ioc->combined_reply_queue)
1830                 writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1831                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1832                         ioc->replyPostRegisterIndex[msix_index/8]);
1833         else
1834                 writel(reply_q->reply_post_host_index | (msix_index <<
1835                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1836                         &ioc->chip->ReplyPostHostIndex);
1837         atomic_dec(&reply_q->busy);
1838         return completed_cmds;
1839 }
1840
1841 /**
1842  * mpt3sas_blk_mq_poll - poll the blk mq poll queue
1843  * @shost: Scsi_Host object
1844  * @queue_num: hw ctx queue number
1845  *
1846  * Return number of entries that has been processed from poll queue.
1847  */
1848 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
1849 {
1850         struct MPT3SAS_ADAPTER *ioc =
1851             (struct MPT3SAS_ADAPTER *)shost->hostdata;
1852         struct adapter_reply_queue *reply_q;
1853         int num_entries = 0;
1854         int qid = queue_num - ioc->iopoll_q_start_index;
1855
1856         if (atomic_read(&ioc->io_uring_poll_queues[qid].pause) ||
1857             !atomic_add_unless(&ioc->io_uring_poll_queues[qid].busy, 1, 1))
1858                 return 0;
1859
1860         reply_q = ioc->io_uring_poll_queues[qid].reply_q;
1861
1862         num_entries = _base_process_reply_queue(reply_q);
1863         atomic_dec(&ioc->io_uring_poll_queues[qid].busy);
1864
1865         return num_entries;
1866 }
1867
1868 /**
1869  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1870  * @irq: irq number (not used)
1871  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1872  *
1873  * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1874  */
1875 static irqreturn_t
1876 _base_interrupt(int irq, void *bus_id)
1877 {
1878         struct adapter_reply_queue *reply_q = bus_id;
1879         struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1880
1881         if (ioc->mask_interrupts)
1882                 return IRQ_NONE;
1883         if (reply_q->irq_poll_scheduled)
1884                 return IRQ_HANDLED;
1885         return ((_base_process_reply_queue(reply_q) > 0) ?
1886                         IRQ_HANDLED : IRQ_NONE);
1887 }
1888
1889 /**
1890  * _base_irqpoll - IRQ poll callback handler
1891  * @irqpoll: irq_poll object
1892  * @budget: irq poll weight
1893  *
1894  * Return: number of reply descriptors processed
1895  */
1896 static int
1897 _base_irqpoll(struct irq_poll *irqpoll, int budget)
1898 {
1899         struct adapter_reply_queue *reply_q;
1900         int num_entries = 0;
1901
1902         reply_q = container_of(irqpoll, struct adapter_reply_queue,
1903                         irqpoll);
1904         if (reply_q->irq_line_enable) {
1905                 disable_irq_nosync(reply_q->os_irq);
1906                 reply_q->irq_line_enable = false;
1907         }
1908         num_entries = _base_process_reply_queue(reply_q);
1909         if (num_entries < budget) {
1910                 irq_poll_complete(irqpoll);
1911                 reply_q->irq_poll_scheduled = false;
1912                 reply_q->irq_line_enable = true;
1913                 enable_irq(reply_q->os_irq);
1914                 /*
1915                  * Go for one more round of processing the
1916                  * reply descriptor post queue in case the HBA
1917                  * Firmware has posted some reply descriptors
1918                  * while reenabling the IRQ.
1919                  */
1920                 _base_process_reply_queue(reply_q);
1921         }
1922
1923         return num_entries;
1924 }
1925
1926 /**
1927  * _base_init_irqpolls - initliaze IRQ polls
1928  * @ioc: per adapter object
1929  *
1930  * Return: nothing
1931  */
1932 static void
1933 _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
1934 {
1935         struct adapter_reply_queue *reply_q, *next;
1936
1937         if (list_empty(&ioc->reply_queue_list))
1938                 return;
1939
1940         list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1941                 if (reply_q->is_iouring_poll_q)
1942                         continue;
1943                 irq_poll_init(&reply_q->irqpoll,
1944                         ioc->hba_queue_depth/4, _base_irqpoll);
1945                 reply_q->irq_poll_scheduled = false;
1946                 reply_q->irq_line_enable = true;
1947                 reply_q->os_irq = pci_irq_vector(ioc->pdev,
1948                     reply_q->msix_index);
1949         }
1950 }
1951
1952 /**
1953  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1954  * @ioc: per adapter object
1955  *
1956  * Return: Whether or not MSI/X is enabled.
1957  */
1958 static inline int
1959 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1960 {
1961         return (ioc->facts.IOCCapabilities &
1962             MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1963 }
1964
1965 /**
1966  * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1967  * @ioc: per adapter object
1968  * @poll: poll over reply descriptor pools incase interrupt for
1969  *              timed-out SCSI command got delayed
1970  * Context: non-ISR context
1971  *
1972  * Called when a Task Management request has completed.
1973  */
1974 void
1975 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1976 {
1977         struct adapter_reply_queue *reply_q;
1978
1979         /* If MSIX capability is turned off
1980          * then multi-queues are not enabled
1981          */
1982         if (!_base_is_controller_msix_enabled(ioc))
1983                 return;
1984
1985         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1986                 if (ioc->shost_recovery || ioc->remove_host ||
1987                                 ioc->pci_error_recovery)
1988                         return;
1989                 /* TMs are on msix_index == 0 */
1990                 if (reply_q->msix_index == 0)
1991                         continue;
1992
1993                 if (reply_q->is_iouring_poll_q) {
1994                         _base_process_reply_queue(reply_q);
1995                         continue;
1996                 }
1997
1998                 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1999                 if (reply_q->irq_poll_scheduled) {
2000                         /* Calling irq_poll_disable will wait for any pending
2001                          * callbacks to have completed.
2002                          */
2003                         irq_poll_disable(&reply_q->irqpoll);
2004                         irq_poll_enable(&reply_q->irqpoll);
2005                         /* check how the scheduled poll has ended,
2006                          * clean up only if necessary
2007                          */
2008                         if (reply_q->irq_poll_scheduled) {
2009                                 reply_q->irq_poll_scheduled = false;
2010                                 reply_q->irq_line_enable = true;
2011                                 enable_irq(reply_q->os_irq);
2012                         }
2013                 }
2014
2015                 if (poll)
2016                         _base_process_reply_queue(reply_q);
2017         }
2018 }
2019
2020 /**
2021  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
2022  * @cb_idx: callback index
2023  */
2024 void
2025 mpt3sas_base_release_callback_handler(u8 cb_idx)
2026 {
2027         mpt_callbacks[cb_idx] = NULL;
2028 }
2029
2030 /**
2031  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
2032  * @cb_func: callback function
2033  *
2034  * Return: Index of @cb_func.
2035  */
2036 u8
2037 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
2038 {
2039         u8 cb_idx;
2040
2041         for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
2042                 if (mpt_callbacks[cb_idx] == NULL)
2043                         break;
2044
2045         mpt_callbacks[cb_idx] = cb_func;
2046         return cb_idx;
2047 }
2048
2049 /**
2050  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
2051  */
2052 void
2053 mpt3sas_base_initialize_callback_handler(void)
2054 {
2055         u8 cb_idx;
2056
2057         for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
2058                 mpt3sas_base_release_callback_handler(cb_idx);
2059 }
2060
2061
2062 /**
2063  * _base_build_zero_len_sge - build zero length sg entry
2064  * @ioc: per adapter object
2065  * @paddr: virtual address for SGE
2066  *
2067  * Create a zero length scatter gather entry to insure the IOCs hardware has
2068  * something to use if the target device goes brain dead and tries
2069  * to send data even when none is asked for.
2070  */
2071 static void
2072 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2073 {
2074         u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
2075             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
2076             MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
2077             MPI2_SGE_FLAGS_SHIFT);
2078         ioc->base_add_sg_single(paddr, flags_length, -1);
2079 }
2080
2081 /**
2082  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
2083  * @paddr: virtual address for SGE
2084  * @flags_length: SGE flags and data transfer length
2085  * @dma_addr: Physical address
2086  */
2087 static void
2088 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2089 {
2090         Mpi2SGESimple32_t *sgel = paddr;
2091
2092         flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
2093             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2094         sgel->FlagsLength = cpu_to_le32(flags_length);
2095         sgel->Address = cpu_to_le32(dma_addr);
2096 }
2097
2098
2099 /**
2100  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
2101  * @paddr: virtual address for SGE
2102  * @flags_length: SGE flags and data transfer length
2103  * @dma_addr: Physical address
2104  */
2105 static void
2106 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2107 {
2108         Mpi2SGESimple64_t *sgel = paddr;
2109
2110         flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
2111             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2112         sgel->FlagsLength = cpu_to_le32(flags_length);
2113         sgel->Address = cpu_to_le64(dma_addr);
2114 }
2115
2116 /**
2117  * _base_get_chain_buffer_tracker - obtain chain tracker
2118  * @ioc: per adapter object
2119  * @scmd: SCSI commands of the IO request
2120  *
2121  * Return: chain tracker from chain_lookup table using key as
2122  * smid and smid's chain_offset.
2123  */
2124 static struct chain_tracker *
2125 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
2126                                struct scsi_cmnd *scmd)
2127 {
2128         struct chain_tracker *chain_req;
2129         struct scsiio_tracker *st = scsi_cmd_priv(scmd);
2130         u16 smid = st->smid;
2131         u8 chain_offset =
2132            atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
2133
2134         if (chain_offset == ioc->chains_needed_per_io)
2135                 return NULL;
2136
2137         chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
2138         atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
2139         return chain_req;
2140 }
2141
2142
2143 /**
2144  * _base_build_sg - build generic sg
2145  * @ioc: per adapter object
2146  * @psge: virtual address for SGE
2147  * @data_out_dma: physical address for WRITES
2148  * @data_out_sz: data xfer size for WRITES
2149  * @data_in_dma: physical address for READS
2150  * @data_in_sz: data xfer size for READS
2151  */
2152 static void
2153 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
2154         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2155         size_t data_in_sz)
2156 {
2157         u32 sgl_flags;
2158
2159         if (!data_out_sz && !data_in_sz) {
2160                 _base_build_zero_len_sge(ioc, psge);
2161                 return;
2162         }
2163
2164         if (data_out_sz && data_in_sz) {
2165                 /* WRITE sgel first */
2166                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2167                     MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
2168                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2169                 ioc->base_add_sg_single(psge, sgl_flags |
2170                     data_out_sz, data_out_dma);
2171
2172                 /* incr sgel */
2173                 psge += ioc->sge_size;
2174
2175                 /* READ sgel last */
2176                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2177                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2178                     MPI2_SGE_FLAGS_END_OF_LIST);
2179                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2180                 ioc->base_add_sg_single(psge, sgl_flags |
2181                     data_in_sz, data_in_dma);
2182         } else if (data_out_sz) /* WRITE */ {
2183                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2184                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2185                     MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
2186                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2187                 ioc->base_add_sg_single(psge, sgl_flags |
2188                     data_out_sz, data_out_dma);
2189         } else if (data_in_sz) /* READ */ {
2190                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2191                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2192                     MPI2_SGE_FLAGS_END_OF_LIST);
2193                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2194                 ioc->base_add_sg_single(psge, sgl_flags |
2195                     data_in_sz, data_in_dma);
2196         }
2197 }
2198
2199 /* IEEE format sgls */
2200
2201 /**
2202  * _base_build_nvme_prp - This function is called for NVMe end devices to build
2203  *                        a native SGL (NVMe PRP).
2204  * @ioc: per adapter object
2205  * @smid: system request message index for getting asscociated SGL
2206  * @nvme_encap_request: the NVMe request msg frame pointer
2207  * @data_out_dma: physical address for WRITES
2208  * @data_out_sz: data xfer size for WRITES
2209  * @data_in_dma: physical address for READS
2210  * @data_in_sz: data xfer size for READS
2211  *
2212  * The native SGL is built starting in the first PRP
2213  * entry of the NVMe message (PRP1).  If the data buffer is small enough to be
2214  * described entirely using PRP1, then PRP2 is not used.  If needed, PRP2 is
2215  * used to describe a larger data buffer.  If the data buffer is too large to
2216  * describe using the two PRP entriess inside the NVMe message, then PRP1
2217  * describes the first data memory segment, and PRP2 contains a pointer to a PRP
2218  * list located elsewhere in memory to describe the remaining data memory
2219  * segments.  The PRP list will be contiguous.
2220  *
2221  * The native SGL for NVMe devices is a Physical Region Page (PRP).  A PRP
2222  * consists of a list of PRP entries to describe a number of noncontigous
2223  * physical memory segments as a single memory buffer, just as a SGL does.  Note
2224  * however, that this function is only used by the IOCTL call, so the memory
2225  * given will be guaranteed to be contiguous.  There is no need to translate
2226  * non-contiguous SGL into a PRP in this case.  All PRPs will describe
2227  * contiguous space that is one page size each.
2228  *
2229  * Each NVMe message contains two PRP entries.  The first (PRP1) either contains
2230  * a PRP list pointer or a PRP element, depending upon the command.  PRP2
2231  * contains the second PRP element if the memory being described fits within 2
2232  * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
2233  *
2234  * A PRP list pointer contains the address of a PRP list, structured as a linear
2235  * array of PRP entries.  Each PRP entry in this list describes a segment of
2236  * physical memory.
2237  *
2238  * Each 64-bit PRP entry comprises an address and an offset field.  The address
2239  * always points at the beginning of a 4KB physical memory page, and the offset
2240  * describes where within that 4KB page the memory segment begins.  Only the
2241  * first element in a PRP list may contain a non-zero offset, implying that all
2242  * memory segments following the first begin at the start of a 4KB page.
2243  *
2244  * Each PRP element normally describes 4KB of physical memory, with exceptions
2245  * for the first and last elements in the list.  If the memory being described
2246  * by the list begins at a non-zero offset within the first 4KB page, then the
2247  * first PRP element will contain a non-zero offset indicating where the region
2248  * begins within the 4KB page.  The last memory segment may end before the end
2249  * of the 4KB segment, depending upon the overall size of the memory being
2250  * described by the PRP list.
2251  *
2252  * Since PRP entries lack any indication of size, the overall data buffer length
2253  * is used to determine where the end of the data memory buffer is located, and
2254  * how many PRP entries are required to describe it.
2255  */
2256 static void
2257 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2258         Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
2259         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2260         size_t data_in_sz)
2261 {
2262         int             prp_size = NVME_PRP_SIZE;
2263         __le64          *prp_entry, *prp1_entry, *prp2_entry;
2264         __le64          *prp_page;
2265         dma_addr_t      prp_entry_dma, prp_page_dma, dma_addr;
2266         u32             offset, entry_len;
2267         u32             page_mask_result, page_mask;
2268         size_t          length;
2269         struct mpt3sas_nvme_cmd *nvme_cmd =
2270                 (void *)nvme_encap_request->NVMe_Command;
2271
2272         /*
2273          * Not all commands require a data transfer. If no data, just return
2274          * without constructing any PRP.
2275          */
2276         if (!data_in_sz && !data_out_sz)
2277                 return;
2278         prp1_entry = &nvme_cmd->prp1;
2279         prp2_entry = &nvme_cmd->prp2;
2280         prp_entry = prp1_entry;
2281         /*
2282          * For the PRP entries, use the specially allocated buffer of
2283          * contiguous memory.
2284          */
2285         prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
2286         prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2287
2288         /*
2289          * Check if we are within 1 entry of a page boundary we don't
2290          * want our first entry to be a PRP List entry.
2291          */
2292         page_mask = ioc->page_size - 1;
2293         page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
2294         if (!page_mask_result) {
2295                 /* Bump up to next page boundary. */
2296                 prp_page = (__le64 *)((u8 *)prp_page + prp_size);
2297                 prp_page_dma = prp_page_dma + prp_size;
2298         }
2299
2300         /*
2301          * Set PRP physical pointer, which initially points to the current PRP
2302          * DMA memory page.
2303          */
2304         prp_entry_dma = prp_page_dma;
2305
2306         /* Get physical address and length of the data buffer. */
2307         if (data_in_sz) {
2308                 dma_addr = data_in_dma;
2309                 length = data_in_sz;
2310         } else {
2311                 dma_addr = data_out_dma;
2312                 length = data_out_sz;
2313         }
2314
2315         /* Loop while the length is not zero. */
2316         while (length) {
2317                 /*
2318                  * Check if we need to put a list pointer here if we are at
2319                  * page boundary - prp_size (8 bytes).
2320                  */
2321                 page_mask_result = (prp_entry_dma + prp_size) & page_mask;
2322                 if (!page_mask_result) {
2323                         /*
2324                          * This is the last entry in a PRP List, so we need to
2325                          * put a PRP list pointer here.  What this does is:
2326                          *   - bump the current memory pointer to the next
2327                          *     address, which will be the next full page.
2328                          *   - set the PRP Entry to point to that page.  This
2329                          *     is now the PRP List pointer.
2330                          *   - bump the PRP Entry pointer the start of the
2331                          *     next page.  Since all of this PRP memory is
2332                          *     contiguous, no need to get a new page - it's
2333                          *     just the next address.
2334                          */
2335                         prp_entry_dma++;
2336                         *prp_entry = cpu_to_le64(prp_entry_dma);
2337                         prp_entry++;
2338                 }
2339
2340                 /* Need to handle if entry will be part of a page. */
2341                 offset = dma_addr & page_mask;
2342                 entry_len = ioc->page_size - offset;
2343
2344                 if (prp_entry == prp1_entry) {
2345                         /*
2346                          * Must fill in the first PRP pointer (PRP1) before
2347                          * moving on.
2348                          */
2349                         *prp1_entry = cpu_to_le64(dma_addr);
2350
2351                         /*
2352                          * Now point to the second PRP entry within the
2353                          * command (PRP2).
2354                          */
2355                         prp_entry = prp2_entry;
2356                 } else if (prp_entry == prp2_entry) {
2357                         /*
2358                          * Should the PRP2 entry be a PRP List pointer or just
2359                          * a regular PRP pointer?  If there is more than one
2360                          * more page of data, must use a PRP List pointer.
2361                          */
2362                         if (length > ioc->page_size) {
2363                                 /*
2364                                  * PRP2 will contain a PRP List pointer because
2365                                  * more PRP's are needed with this command. The
2366                                  * list will start at the beginning of the
2367                                  * contiguous buffer.
2368                                  */
2369                                 *prp2_entry = cpu_to_le64(prp_entry_dma);
2370
2371                                 /*
2372                                  * The next PRP Entry will be the start of the
2373                                  * first PRP List.
2374                                  */
2375                                 prp_entry = prp_page;
2376                         } else {
2377                                 /*
2378                                  * After this, the PRP Entries are complete.
2379                                  * This command uses 2 PRP's and no PRP list.
2380                                  */
2381                                 *prp2_entry = cpu_to_le64(dma_addr);
2382                         }
2383                 } else {
2384                         /*
2385                          * Put entry in list and bump the addresses.
2386                          *
2387                          * After PRP1 and PRP2 are filled in, this will fill in
2388                          * all remaining PRP entries in a PRP List, one per
2389                          * each time through the loop.
2390                          */
2391                         *prp_entry = cpu_to_le64(dma_addr);
2392                         prp_entry++;
2393                         prp_entry_dma++;
2394                 }
2395
2396                 /*
2397                  * Bump the phys address of the command's data buffer by the
2398                  * entry_len.
2399                  */
2400                 dma_addr += entry_len;
2401
2402                 /* Decrement length accounting for last partial page. */
2403                 if (entry_len > length)
2404                         length = 0;
2405                 else
2406                         length -= entry_len;
2407         }
2408 }
2409
2410 /**
2411  * base_make_prp_nvme - Prepare PRPs (Physical Region Page) -
2412  *                      SGLs specific to NVMe drives only
2413  *
2414  * @ioc:                per adapter object
2415  * @scmd:               SCSI command from the mid-layer
2416  * @mpi_request:        mpi request
2417  * @smid:               msg Index
2418  * @sge_count:          scatter gather element count.
2419  *
2420  * Return:              true: PRPs are built
2421  *                      false: IEEE SGLs needs to be built
2422  */
2423 static void
2424 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
2425                 struct scsi_cmnd *scmd,
2426                 Mpi25SCSIIORequest_t *mpi_request,
2427                 u16 smid, int sge_count)
2428 {
2429         int sge_len, num_prp_in_chain = 0;
2430         Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
2431         __le64 *curr_buff;
2432         dma_addr_t msg_dma, sge_addr, offset;
2433         u32 page_mask, page_mask_result;
2434         struct scatterlist *sg_scmd;
2435         u32 first_prp_len;
2436         int data_len = scsi_bufflen(scmd);
2437         u32 nvme_pg_size;
2438
2439         nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
2440         /*
2441          * Nvme has a very convoluted prp format.  One prp is required
2442          * for each page or partial page. Driver need to split up OS sg_list
2443          * entries if it is longer than one page or cross a page
2444          * boundary.  Driver also have to insert a PRP list pointer entry as
2445          * the last entry in each physical page of the PRP list.
2446          *
2447          * NOTE: The first PRP "entry" is actually placed in the first
2448          * SGL entry in the main message as IEEE 64 format.  The 2nd
2449          * entry in the main message is the chain element, and the rest
2450          * of the PRP entries are built in the contiguous pcie buffer.
2451          */
2452         page_mask = nvme_pg_size - 1;
2453
2454         /*
2455          * Native SGL is needed.
2456          * Put a chain element in main message frame that points to the first
2457          * chain buffer.
2458          *
2459          * NOTE:  The ChainOffset field must be 0 when using a chain pointer to
2460          *        a native SGL.
2461          */
2462
2463         /* Set main message chain element pointer */
2464         main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2465         /*
2466          * For NVMe the chain element needs to be the 2nd SG entry in the main
2467          * message.
2468          */
2469         main_chain_element = (Mpi25IeeeSgeChain64_t *)
2470                 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2471
2472         /*
2473          * For the PRP entries, use the specially allocated buffer of
2474          * contiguous memory.  Normal chain buffers can't be used
2475          * because each chain buffer would need to be the size of an OS
2476          * page (4k).
2477          */
2478         curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
2479         msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2480
2481         main_chain_element->Address = cpu_to_le64(msg_dma);
2482         main_chain_element->NextChainOffset = 0;
2483         main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2484                         MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2485                         MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2486
2487         /* Build first prp, sge need not to be page aligned*/
2488         ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2489         sg_scmd = scsi_sglist(scmd);
2490         sge_addr = sg_dma_address(sg_scmd);
2491         sge_len = sg_dma_len(sg_scmd);
2492
2493         offset = sge_addr & page_mask;
2494         first_prp_len = nvme_pg_size - offset;
2495
2496         ptr_first_sgl->Address = cpu_to_le64(sge_addr);
2497         ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
2498
2499         data_len -= first_prp_len;
2500
2501         if (sge_len > first_prp_len) {
2502                 sge_addr += first_prp_len;
2503                 sge_len -= first_prp_len;
2504         } else if (data_len && (sge_len == first_prp_len)) {
2505                 sg_scmd = sg_next(sg_scmd);
2506                 sge_addr = sg_dma_address(sg_scmd);
2507                 sge_len = sg_dma_len(sg_scmd);
2508         }
2509
2510         for (;;) {
2511                 offset = sge_addr & page_mask;
2512
2513                 /* Put PRP pointer due to page boundary*/
2514                 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
2515                 if (unlikely(!page_mask_result)) {
2516                         scmd_printk(KERN_NOTICE,
2517                                 scmd, "page boundary curr_buff: 0x%p\n",
2518                                 curr_buff);
2519                         msg_dma += 8;
2520                         *curr_buff = cpu_to_le64(msg_dma);
2521                         curr_buff++;
2522                         num_prp_in_chain++;
2523                 }
2524
2525                 *curr_buff = cpu_to_le64(sge_addr);
2526                 curr_buff++;
2527                 msg_dma += 8;
2528                 num_prp_in_chain++;
2529
2530                 sge_addr += nvme_pg_size;
2531                 sge_len -= nvme_pg_size;
2532                 data_len -= nvme_pg_size;
2533
2534                 if (data_len <= 0)
2535                         break;
2536
2537                 if (sge_len > 0)
2538                         continue;
2539
2540                 sg_scmd = sg_next(sg_scmd);
2541                 sge_addr = sg_dma_address(sg_scmd);
2542                 sge_len = sg_dma_len(sg_scmd);
2543         }
2544
2545         main_chain_element->Length =
2546                 cpu_to_le32(num_prp_in_chain * sizeof(u64));
2547         return;
2548 }
2549
2550 static bool
2551 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
2552         struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
2553 {
2554         u32 data_length = 0;
2555         bool build_prp = true;
2556
2557         data_length = scsi_bufflen(scmd);
2558         if (pcie_device &&
2559             (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
2560                 build_prp = false;
2561                 return build_prp;
2562         }
2563
2564         /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2565          * we built IEEE SGL
2566          */
2567         if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
2568                 build_prp = false;
2569
2570         return build_prp;
2571 }
2572
2573 /**
2574  * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
2575  * determine if the driver needs to build a native SGL.  If so, that native
2576  * SGL is built in the special contiguous buffers allocated especially for
2577  * PCIe SGL creation.  If the driver will not build a native SGL, return
2578  * TRUE and a normal IEEE SGL will be built.  Currently this routine
2579  * supports NVMe.
2580  * @ioc: per adapter object
2581  * @mpi_request: mf request pointer
2582  * @smid: system request message index
2583  * @scmd: scsi command
2584  * @pcie_device: points to the PCIe device's info
2585  *
2586  * Return: 0 if native SGL was built, 1 if no SGL was built
2587  */
2588 static int
2589 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
2590         Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
2591         struct _pcie_device *pcie_device)
2592 {
2593         int sges_left;
2594
2595         /* Get the SG list pointer and info. */
2596         sges_left = scsi_dma_map(scmd);
2597         if (sges_left < 0) {
2598                 sdev_printk(KERN_ERR, scmd->device,
2599                         "scsi_dma_map failed: request for %d bytes!\n",
2600                         scsi_bufflen(scmd));
2601                 return 1;
2602         }
2603
2604         /* Check if we need to build a native SG list. */
2605         if (!base_is_prp_possible(ioc, pcie_device,
2606                                 scmd, sges_left)) {
2607                 /* We built a native SG list, just return. */
2608                 goto out;
2609         }
2610
2611         /*
2612          * Build native NVMe PRP.
2613          */
2614         base_make_prp_nvme(ioc, scmd, mpi_request,
2615                         smid, sges_left);
2616
2617         return 0;
2618 out:
2619         scsi_dma_unmap(scmd);
2620         return 1;
2621 }
2622
2623 /**
2624  * _base_add_sg_single_ieee - add sg element for IEEE format
2625  * @paddr: virtual address for SGE
2626  * @flags: SGE flags
2627  * @chain_offset: number of 128 byte elements from start of segment
2628  * @length: data transfer length
2629  * @dma_addr: Physical address
2630  */
2631 static void
2632 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
2633         dma_addr_t dma_addr)
2634 {
2635         Mpi25IeeeSgeChain64_t *sgel = paddr;
2636
2637         sgel->Flags = flags;
2638         sgel->NextChainOffset = chain_offset;
2639         sgel->Length = cpu_to_le32(length);
2640         sgel->Address = cpu_to_le64(dma_addr);
2641 }
2642
2643 /**
2644  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
2645  * @ioc: per adapter object
2646  * @paddr: virtual address for SGE
2647  *
2648  * Create a zero length scatter gather entry to insure the IOCs hardware has
2649  * something to use if the target device goes brain dead and tries
2650  * to send data even when none is asked for.
2651  */
2652 static void
2653 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2654 {
2655         u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2656                 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2657                 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
2658
2659         _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
2660 }
2661
2662 /**
2663  * _base_build_sg_scmd - main sg creation routine
2664  *              pcie_device is unused here!
2665  * @ioc: per adapter object
2666  * @scmd: scsi command
2667  * @smid: system request message index
2668  * @unused: unused pcie_device pointer
2669  * Context: none.
2670  *
2671  * The main routine that builds scatter gather table from a given
2672  * scsi request sent via the .queuecommand main handler.
2673  *
2674  * Return: 0 success, anything else error
2675  */
2676 static int
2677 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
2678         struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
2679 {
2680         Mpi2SCSIIORequest_t *mpi_request;
2681         dma_addr_t chain_dma;
2682         struct scatterlist *sg_scmd;
2683         void *sg_local, *chain;
2684         u32 chain_offset;
2685         u32 chain_length;
2686         u32 chain_flags;
2687         int sges_left;
2688         u32 sges_in_segment;
2689         u32 sgl_flags;
2690         u32 sgl_flags_last_element;
2691         u32 sgl_flags_end_buffer;
2692         struct chain_tracker *chain_req;
2693
2694         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2695
2696         /* init scatter gather flags */
2697         sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
2698         if (scmd->sc_data_direction == DMA_TO_DEVICE)
2699                 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
2700         sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
2701             << MPI2_SGE_FLAGS_SHIFT;
2702         sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
2703             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
2704             << MPI2_SGE_FLAGS_SHIFT;
2705         sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2706
2707         sg_scmd = scsi_sglist(scmd);
2708         sges_left = scsi_dma_map(scmd);
2709         if (sges_left < 0) {
2710                 sdev_printk(KERN_ERR, scmd->device,
2711                  "scsi_dma_map failed: request for %d bytes!\n",
2712                  scsi_bufflen(scmd));
2713                 return -ENOMEM;
2714         }
2715
2716         sg_local = &mpi_request->SGL;
2717         sges_in_segment = ioc->max_sges_in_main_message;
2718         if (sges_left <= sges_in_segment)
2719                 goto fill_in_last_segment;
2720
2721         mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
2722             (sges_in_segment * ioc->sge_size))/4;
2723
2724         /* fill in main message segment when there is a chain following */
2725         while (sges_in_segment) {
2726                 if (sges_in_segment == 1)
2727                         ioc->base_add_sg_single(sg_local,
2728                             sgl_flags_last_element | sg_dma_len(sg_scmd),
2729                             sg_dma_address(sg_scmd));
2730                 else
2731                         ioc->base_add_sg_single(sg_local, sgl_flags |
2732                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2733                 sg_scmd = sg_next(sg_scmd);
2734                 sg_local += ioc->sge_size;
2735                 sges_left--;
2736                 sges_in_segment--;
2737         }
2738
2739         /* initializing the chain flags and pointers */
2740         chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
2741         chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2742         if (!chain_req)
2743                 return -1;
2744         chain = chain_req->chain_buffer;
2745         chain_dma = chain_req->chain_buffer_dma;
2746         do {
2747                 sges_in_segment = (sges_left <=
2748                     ioc->max_sges_in_chain_message) ? sges_left :
2749                     ioc->max_sges_in_chain_message;
2750                 chain_offset = (sges_left == sges_in_segment) ?
2751                     0 : (sges_in_segment * ioc->sge_size)/4;
2752                 chain_length = sges_in_segment * ioc->sge_size;
2753                 if (chain_offset) {
2754                         chain_offset = chain_offset <<
2755                             MPI2_SGE_CHAIN_OFFSET_SHIFT;
2756                         chain_length += ioc->sge_size;
2757                 }
2758                 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
2759                     chain_length, chain_dma);
2760                 sg_local = chain;
2761                 if (!chain_offset)
2762                         goto fill_in_last_segment;
2763
2764                 /* fill in chain segments */
2765                 while (sges_in_segment) {
2766                         if (sges_in_segment == 1)
2767                                 ioc->base_add_sg_single(sg_local,
2768                                     sgl_flags_last_element |
2769                                     sg_dma_len(sg_scmd),
2770                                     sg_dma_address(sg_scmd));
2771                         else
2772                                 ioc->base_add_sg_single(sg_local, sgl_flags |
2773                                     sg_dma_len(sg_scmd),
2774                                     sg_dma_address(sg_scmd));
2775                         sg_scmd = sg_next(sg_scmd);
2776                         sg_local += ioc->sge_size;
2777                         sges_left--;
2778                         sges_in_segment--;
2779                 }
2780
2781                 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2782                 if (!chain_req)
2783                         return -1;
2784                 chain = chain_req->chain_buffer;
2785                 chain_dma = chain_req->chain_buffer_dma;
2786         } while (1);
2787
2788
2789  fill_in_last_segment:
2790
2791         /* fill the last segment */
2792         while (sges_left) {
2793                 if (sges_left == 1)
2794                         ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2795                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2796                 else
2797                         ioc->base_add_sg_single(sg_local, sgl_flags |
2798                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2799                 sg_scmd = sg_next(sg_scmd);
2800                 sg_local += ioc->sge_size;
2801                 sges_left--;
2802         }
2803
2804         return 0;
2805 }
2806
2807 /**
2808  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2809  * @ioc: per adapter object
2810  * @scmd: scsi command
2811  * @smid: system request message index
2812  * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2813  * constructed on need.
2814  * Context: none.
2815  *
2816  * The main routine that builds scatter gather table from a given
2817  * scsi request sent via the .queuecommand main handler.
2818  *
2819  * Return: 0 success, anything else error
2820  */
2821 static int
2822 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2823         struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2824 {
2825         Mpi25SCSIIORequest_t *mpi_request;
2826         dma_addr_t chain_dma;
2827         struct scatterlist *sg_scmd;
2828         void *sg_local, *chain;
2829         u32 chain_offset;
2830         u32 chain_length;
2831         int sges_left;
2832         u32 sges_in_segment;
2833         u8 simple_sgl_flags;
2834         u8 simple_sgl_flags_last;
2835         u8 chain_sgl_flags;
2836         struct chain_tracker *chain_req;
2837
2838         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2839
2840         /* init scatter gather flags */
2841         simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2842             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2843         simple_sgl_flags_last = simple_sgl_flags |
2844             MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2845         chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2846             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2847
2848         /* Check if we need to build a native SG list. */
2849         if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2850                         smid, scmd, pcie_device) == 0)) {
2851                 /* We built a native SG list, just return. */
2852                 return 0;
2853         }
2854
2855         sg_scmd = scsi_sglist(scmd);
2856         sges_left = scsi_dma_map(scmd);
2857         if (sges_left < 0) {
2858                 sdev_printk(KERN_ERR, scmd->device,
2859                         "scsi_dma_map failed: request for %d bytes!\n",
2860                         scsi_bufflen(scmd));
2861                 return -ENOMEM;
2862         }
2863
2864         sg_local = &mpi_request->SGL;
2865         sges_in_segment = (ioc->request_sz -
2866                    offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2867         if (sges_left <= sges_in_segment)
2868                 goto fill_in_last_segment;
2869
2870         mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2871             (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2872
2873         /* fill in main message segment when there is a chain following */
2874         while (sges_in_segment > 1) {
2875                 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2876                     sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2877                 sg_scmd = sg_next(sg_scmd);
2878                 sg_local += ioc->sge_size_ieee;
2879                 sges_left--;
2880                 sges_in_segment--;
2881         }
2882
2883         /* initializing the pointers */
2884         chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2885         if (!chain_req)
2886                 return -1;
2887         chain = chain_req->chain_buffer;
2888         chain_dma = chain_req->chain_buffer_dma;
2889         do {
2890                 sges_in_segment = (sges_left <=
2891                     ioc->max_sges_in_chain_message) ? sges_left :
2892                     ioc->max_sges_in_chain_message;
2893                 chain_offset = (sges_left == sges_in_segment) ?
2894                     0 : sges_in_segment;
2895                 chain_length = sges_in_segment * ioc->sge_size_ieee;
2896                 if (chain_offset)
2897                         chain_length += ioc->sge_size_ieee;
2898                 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2899                     chain_offset, chain_length, chain_dma);
2900
2901                 sg_local = chain;
2902                 if (!chain_offset)
2903                         goto fill_in_last_segment;
2904
2905                 /* fill in chain segments */
2906                 while (sges_in_segment) {
2907                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2908                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2909                         sg_scmd = sg_next(sg_scmd);
2910                         sg_local += ioc->sge_size_ieee;
2911                         sges_left--;
2912                         sges_in_segment--;
2913                 }
2914
2915                 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2916                 if (!chain_req)
2917                         return -1;
2918                 chain = chain_req->chain_buffer;
2919                 chain_dma = chain_req->chain_buffer_dma;
2920         } while (1);
2921
2922
2923  fill_in_last_segment:
2924
2925         /* fill the last segment */
2926         while (sges_left > 0) {
2927                 if (sges_left == 1)
2928                         _base_add_sg_single_ieee(sg_local,
2929                             simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2930                             sg_dma_address(sg_scmd));
2931                 else
2932                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2933                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2934                 sg_scmd = sg_next(sg_scmd);
2935                 sg_local += ioc->sge_size_ieee;
2936                 sges_left--;
2937         }
2938
2939         return 0;
2940 }
2941
2942 /**
2943  * _base_build_sg_ieee - build generic sg for IEEE format
2944  * @ioc: per adapter object
2945  * @psge: virtual address for SGE
2946  * @data_out_dma: physical address for WRITES
2947  * @data_out_sz: data xfer size for WRITES
2948  * @data_in_dma: physical address for READS
2949  * @data_in_sz: data xfer size for READS
2950  */
2951 static void
2952 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2953         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2954         size_t data_in_sz)
2955 {
2956         u8 sgl_flags;
2957
2958         if (!data_out_sz && !data_in_sz) {
2959                 _base_build_zero_len_sge_ieee(ioc, psge);
2960                 return;
2961         }
2962
2963         if (data_out_sz && data_in_sz) {
2964                 /* WRITE sgel first */
2965                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2966                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2967                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2968                     data_out_dma);
2969
2970                 /* incr sgel */
2971                 psge += ioc->sge_size_ieee;
2972
2973                 /* READ sgel last */
2974                 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2975                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2976                     data_in_dma);
2977         } else if (data_out_sz) /* WRITE */ {
2978                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2979                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2980                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2981                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2982                     data_out_dma);
2983         } else if (data_in_sz) /* READ */ {
2984                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2985                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2986                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2987                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2988                     data_in_dma);
2989         }
2990 }
2991
2992 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2993
2994 /**
2995  * _base_config_dma_addressing - set dma addressing
2996  * @ioc: per adapter object
2997  * @pdev: PCI device struct
2998  *
2999  * Return: 0 for success, non-zero for failure.
3000  */
3001 static int
3002 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
3003 {
3004         struct sysinfo s;
3005
3006         if (ioc->is_mcpu_endpoint ||
3007             sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
3008             dma_get_required_mask(&pdev->dev) <= 32)
3009                 ioc->dma_mask = 32;
3010         /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
3011         else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
3012                 ioc->dma_mask = 63;
3013         else
3014                 ioc->dma_mask = 64;
3015
3016         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) ||
3017             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)))
3018                 return -ENODEV;
3019
3020         if (ioc->dma_mask > 32) {
3021                 ioc->base_add_sg_single = &_base_add_sg_single_64;
3022                 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
3023         } else {
3024                 ioc->base_add_sg_single = &_base_add_sg_single_32;
3025                 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
3026         }
3027
3028         si_meminfo(&s);
3029         ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
3030                 ioc->dma_mask, convert_to_kb(s.totalram));
3031
3032         return 0;
3033 }
3034
3035 /**
3036  * _base_check_enable_msix - checks MSIX capabable.
3037  * @ioc: per adapter object
3038  *
3039  * Check to see if card is capable of MSIX, and set number
3040  * of available msix vectors
3041  */
3042 static int
3043 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3044 {
3045         int base;
3046         u16 message_control;
3047
3048         /* Check whether controller SAS2008 B0 controller,
3049          * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
3050          */
3051         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
3052             ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
3053                 return -EINVAL;
3054         }
3055
3056         base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
3057         if (!base) {
3058                 dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
3059                 return -EINVAL;
3060         }
3061
3062         /* get msix vector count */
3063         /* NUMA_IO not supported for older controllers */
3064         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
3065             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
3066             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
3067             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
3068             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
3069             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
3070             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
3071                 ioc->msix_vector_count = 1;
3072         else {
3073                 pci_read_config_word(ioc->pdev, base + 2, &message_control);
3074                 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
3075         }
3076         dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
3077                                   ioc->msix_vector_count));
3078         return 0;
3079 }
3080
3081 /**
3082  * mpt3sas_base_free_irq - free irq
3083  * @ioc: per adapter object
3084  *
3085  * Freeing respective reply_queue from the list.
3086  */
3087 void
3088 mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
3089 {
3090         struct adapter_reply_queue *reply_q, *next;
3091
3092         if (list_empty(&ioc->reply_queue_list))
3093                 return;
3094
3095         list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
3096                 list_del(&reply_q->list);
3097                 if (reply_q->is_iouring_poll_q) {
3098                         kfree(reply_q);
3099                         continue;
3100                 }
3101
3102                 if (ioc->smp_affinity_enable)
3103                         irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3104                             reply_q->msix_index), NULL);
3105                 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
3106                          reply_q);
3107                 kfree(reply_q);
3108         }
3109 }
3110
3111 /**
3112  * _base_request_irq - request irq
3113  * @ioc: per adapter object
3114  * @index: msix index into vector table
3115  *
3116  * Inserting respective reply_queue into the list.
3117  */
3118 static int
3119 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
3120 {
3121         struct pci_dev *pdev = ioc->pdev;
3122         struct adapter_reply_queue *reply_q;
3123         int r, qid;
3124
3125         reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
3126         if (!reply_q) {
3127                 ioc_err(ioc, "unable to allocate memory %zu!\n",
3128                         sizeof(struct adapter_reply_queue));
3129                 return -ENOMEM;
3130         }
3131         reply_q->ioc = ioc;
3132         reply_q->msix_index = index;
3133
3134         atomic_set(&reply_q->busy, 0);
3135
3136         if (index >= ioc->iopoll_q_start_index) {
3137                 qid = index - ioc->iopoll_q_start_index;
3138                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-mq-poll%d",
3139                     ioc->driver_name, ioc->id, qid);
3140                 reply_q->is_iouring_poll_q = 1;
3141                 ioc->io_uring_poll_queues[qid].reply_q = reply_q;
3142                 goto out;
3143         }
3144
3145
3146         if (ioc->msix_enable)
3147                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
3148                     ioc->driver_name, ioc->id, index);
3149         else
3150                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
3151                     ioc->driver_name, ioc->id);
3152         r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
3153                         IRQF_SHARED, reply_q->name, reply_q);
3154         if (r) {
3155                 pr_err("%s: unable to allocate interrupt %d!\n",
3156                        reply_q->name, pci_irq_vector(pdev, index));
3157                 kfree(reply_q);
3158                 return -EBUSY;
3159         }
3160 out:
3161         INIT_LIST_HEAD(&reply_q->list);
3162         list_add_tail(&reply_q->list, &ioc->reply_queue_list);
3163         return 0;
3164 }
3165
3166 /**
3167  * _base_assign_reply_queues - assigning msix index for each cpu
3168  * @ioc: per adapter object
3169  *
3170  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
3171  *
3172  * It would nice if we could call irq_set_affinity, however it is not
3173  * an exported symbol
3174  */
3175 static void
3176 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
3177 {
3178         unsigned int cpu, nr_cpus, nr_msix, index = 0;
3179         struct adapter_reply_queue *reply_q;
3180         int local_numa_node;
3181         int iopoll_q_count = ioc->reply_queue_count -
3182             ioc->iopoll_q_start_index;
3183
3184         if (!_base_is_controller_msix_enabled(ioc))
3185                 return;
3186
3187         if (ioc->msix_load_balance)
3188                 return;
3189
3190         memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
3191
3192         nr_cpus = num_online_cpus();
3193         nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
3194                                                ioc->facts.MaxMSIxVectors);
3195         if (!nr_msix)
3196                 return;
3197
3198         if (ioc->smp_affinity_enable) {
3199
3200                 /*
3201                  * set irq affinity to local numa node for those irqs
3202                  * corresponding to high iops queues.
3203                  */
3204                 if (ioc->high_iops_queues) {
3205                         local_numa_node = dev_to_node(&ioc->pdev->dev);
3206                         for (index = 0; index < ioc->high_iops_queues;
3207                             index++) {
3208                                 irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3209                                     index), cpumask_of_node(local_numa_node));
3210                         }
3211                 }
3212
3213                 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3214                         const cpumask_t *mask;
3215
3216                         if (reply_q->msix_index < ioc->high_iops_queues ||
3217                             reply_q->msix_index >= ioc->iopoll_q_start_index)
3218                                 continue;
3219
3220                         mask = pci_irq_get_affinity(ioc->pdev,
3221                             reply_q->msix_index);
3222                         if (!mask) {
3223                                 ioc_warn(ioc, "no affinity for msi %x\n",
3224                                          reply_q->msix_index);
3225                                 goto fall_back;
3226                         }
3227
3228                         for_each_cpu_and(cpu, mask, cpu_online_mask) {
3229                                 if (cpu >= ioc->cpu_msix_table_sz)
3230                                         break;
3231                                 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3232                         }
3233                 }
3234                 return;
3235         }
3236
3237 fall_back:
3238         cpu = cpumask_first(cpu_online_mask);
3239         nr_msix -= (ioc->high_iops_queues - iopoll_q_count);
3240         index = 0;
3241
3242         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3243                 unsigned int i, group = nr_cpus / nr_msix;
3244
3245                 if (reply_q->msix_index < ioc->high_iops_queues ||
3246                     reply_q->msix_index >= ioc->iopoll_q_start_index)
3247                         continue;
3248
3249                 if (cpu >= nr_cpus)
3250                         break;
3251
3252                 if (index < nr_cpus % nr_msix)
3253                         group++;
3254
3255                 for (i = 0 ; i < group ; i++) {
3256                         ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3257                         cpu = cpumask_next(cpu, cpu_online_mask);
3258                 }
3259                 index++;
3260         }
3261 }
3262
3263 /**
3264  * _base_check_and_enable_high_iops_queues - enable high iops mode
3265  * @ioc: per adapter object
3266  * @hba_msix_vector_count: msix vectors supported by HBA
3267  *
3268  * Enable high iops queues only if
3269  *  - HBA is a SEA/AERO controller and
3270  *  - MSI-Xs vector supported by the HBA is 128 and
3271  *  - total CPU count in the system >=16 and
3272  *  - loaded driver with default max_msix_vectors module parameter and
3273  *  - system booted in non kdump mode
3274  *
3275  * Return: nothing.
3276  */
3277 static void
3278 _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
3279                 int hba_msix_vector_count)
3280 {
3281         u16 lnksta, speed;
3282
3283         /*
3284          * Disable high iops queues if io uring poll queues are enabled.
3285          */
3286         if (perf_mode == MPT_PERF_MODE_IOPS ||
3287             perf_mode == MPT_PERF_MODE_LATENCY ||
3288             ioc->io_uring_poll_queues) {
3289                 ioc->high_iops_queues = 0;
3290                 return;
3291         }
3292
3293         if (perf_mode == MPT_PERF_MODE_DEFAULT) {
3294
3295                 pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
3296                 speed = lnksta & PCI_EXP_LNKSTA_CLS;
3297
3298                 if (speed < 0x4) {
3299                         ioc->high_iops_queues = 0;
3300                         return;
3301                 }
3302         }
3303
3304         if (!reset_devices && ioc->is_aero_ioc &&
3305             hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
3306             num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
3307             max_msix_vectors == -1)
3308                 ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
3309         else
3310                 ioc->high_iops_queues = 0;
3311 }
3312
3313 /**
3314  * mpt3sas_base_disable_msix - disables msix
3315  * @ioc: per adapter object
3316  *
3317  */
3318 void
3319 mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
3320 {
3321         if (!ioc->msix_enable)
3322                 return;
3323         pci_free_irq_vectors(ioc->pdev);
3324         ioc->msix_enable = 0;
3325         kfree(ioc->io_uring_poll_queues);
3326 }
3327
3328 /**
3329  * _base_alloc_irq_vectors - allocate msix vectors
3330  * @ioc: per adapter object
3331  *
3332  */
3333 static int
3334 _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
3335 {
3336         int i, irq_flags = PCI_IRQ_MSIX;
3337         struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
3338         struct irq_affinity *descp = &desc;
3339         /*
3340          * Don't allocate msix vectors for poll_queues.
3341          * msix_vectors is always within a range of FW supported reply queue.
3342          */
3343         int nr_msix_vectors = ioc->iopoll_q_start_index;
3344
3345
3346         if (ioc->smp_affinity_enable)
3347                 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
3348         else
3349                 descp = NULL;
3350
3351         ioc_info(ioc, " %d %d %d\n", ioc->high_iops_queues,
3352             ioc->reply_queue_count, nr_msix_vectors);
3353
3354         i = pci_alloc_irq_vectors_affinity(ioc->pdev,
3355             ioc->high_iops_queues,
3356             nr_msix_vectors, irq_flags, descp);
3357
3358         return i;
3359 }
3360
3361 /**
3362  * _base_enable_msix - enables msix, failback to io_apic
3363  * @ioc: per adapter object
3364  *
3365  */
3366 static int
3367 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3368 {
3369         int r;
3370         int i, local_max_msix_vectors;
3371         u8 try_msix = 0;
3372         int iopoll_q_count = 0;
3373
3374         ioc->msix_load_balance = false;
3375
3376         if (msix_disable == -1 || msix_disable == 0)
3377                 try_msix = 1;
3378
3379         if (!try_msix)
3380                 goto try_ioapic;
3381
3382         if (_base_check_enable_msix(ioc) != 0)
3383                 goto try_ioapic;
3384
3385         ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
3386         pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
3387                 ioc->cpu_count, max_msix_vectors);
3388
3389         ioc->reply_queue_count =
3390                 min_t(int, ioc->cpu_count, ioc->msix_vector_count);
3391
3392         if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
3393                 local_max_msix_vectors = (reset_devices) ? 1 : 8;
3394         else
3395                 local_max_msix_vectors = max_msix_vectors;
3396
3397         if (local_max_msix_vectors == 0)
3398                 goto try_ioapic;
3399
3400         /*
3401          * Enable msix_load_balance only if combined reply queue mode is
3402          * disabled on SAS3 & above generation HBA devices.
3403          */
3404         if (!ioc->combined_reply_queue &&
3405             ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3406                 ioc_info(ioc,
3407                     "combined ReplyQueue is off, Enabling msix load balance\n");
3408                 ioc->msix_load_balance = true;
3409         }
3410
3411         /*
3412          * smp affinity setting is not need when msix load balance
3413          * is enabled.
3414          */
3415         if (ioc->msix_load_balance)
3416                 ioc->smp_affinity_enable = 0;
3417
3418         if (!ioc->smp_affinity_enable || ioc->reply_queue_count <= 1)
3419                 ioc->shost->host_tagset = 0;
3420
3421         /*
3422          * Enable io uring poll queues only if host_tagset is enabled.
3423          */
3424         if (ioc->shost->host_tagset)
3425                 iopoll_q_count = poll_queues;
3426
3427         if (iopoll_q_count) {
3428                 ioc->io_uring_poll_queues = kcalloc(iopoll_q_count,
3429                     sizeof(struct io_uring_poll_queue), GFP_KERNEL);
3430                 if (!ioc->io_uring_poll_queues)
3431                         iopoll_q_count = 0;
3432         }
3433
3434         if (ioc->is_aero_ioc)
3435                 _base_check_and_enable_high_iops_queues(ioc,
3436                     ioc->msix_vector_count);
3437
3438         /*
3439          * Add high iops queues count to reply queue count if high iops queues
3440          * are enabled.
3441          */
3442         ioc->reply_queue_count = min_t(int,
3443             ioc->reply_queue_count + ioc->high_iops_queues,
3444             ioc->msix_vector_count);
3445
3446         /*
3447          * Adjust the reply queue count incase reply queue count
3448          * exceeds the user provided MSIx vectors count.
3449          */
3450         if (local_max_msix_vectors > 0)
3451                 ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
3452                     ioc->reply_queue_count);
3453         /*
3454          * Add io uring poll queues count to reply queues count
3455          * if io uring is enabled in driver.
3456          */
3457         if (iopoll_q_count) {
3458                 if (ioc->reply_queue_count < (iopoll_q_count + MPT3_MIN_IRQS))
3459                         iopoll_q_count = 0;
3460                 ioc->reply_queue_count = min_t(int,
3461                     ioc->reply_queue_count + iopoll_q_count,
3462                     ioc->msix_vector_count);
3463         }
3464
3465         /*
3466          * Starting index of io uring poll queues in reply queue list.
3467          */
3468         ioc->iopoll_q_start_index =
3469             ioc->reply_queue_count - iopoll_q_count;
3470
3471         r = _base_alloc_irq_vectors(ioc);
3472         if (r < 0) {
3473                 ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
3474                 goto try_ioapic;
3475         }
3476
3477         /*
3478          * Adjust the reply queue count if the allocated
3479          * MSIx vectors is less then the requested number
3480          * of MSIx vectors.
3481          */
3482         if (r < ioc->iopoll_q_start_index) {
3483                 ioc->reply_queue_count = r + iopoll_q_count;
3484                 ioc->iopoll_q_start_index =
3485                     ioc->reply_queue_count - iopoll_q_count;
3486         }
3487
3488         ioc->msix_enable = 1;
3489         for (i = 0; i < ioc->reply_queue_count; i++) {
3490                 r = _base_request_irq(ioc, i);
3491                 if (r) {
3492                         mpt3sas_base_free_irq(ioc);
3493                         mpt3sas_base_disable_msix(ioc);
3494                         goto try_ioapic;
3495                 }
3496         }
3497
3498         ioc_info(ioc, "High IOPs queues : %s\n",
3499                         ioc->high_iops_queues ? "enabled" : "disabled");
3500
3501         return 0;
3502
3503 /* failback to io_apic interrupt routing */
3504  try_ioapic:
3505         ioc->high_iops_queues = 0;
3506         ioc_info(ioc, "High IOPs queues : disabled\n");
3507         ioc->reply_queue_count = 1;
3508         ioc->iopoll_q_start_index = ioc->reply_queue_count - 0;
3509         r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
3510         if (r < 0) {
3511                 dfailprintk(ioc,
3512                             ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
3513                                      r));
3514         } else
3515                 r = _base_request_irq(ioc, 0);
3516
3517         return r;
3518 }
3519
3520 /**
3521  * mpt3sas_base_unmap_resources - free controller resources
3522  * @ioc: per adapter object
3523  */
3524 static void
3525 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
3526 {
3527         struct pci_dev *pdev = ioc->pdev;
3528
3529         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3530
3531         mpt3sas_base_free_irq(ioc);
3532         mpt3sas_base_disable_msix(ioc);
3533
3534         kfree(ioc->replyPostRegisterIndex);
3535         ioc->replyPostRegisterIndex = NULL;
3536
3537
3538         if (ioc->chip_phys) {
3539                 iounmap(ioc->chip);
3540                 ioc->chip_phys = 0;
3541         }
3542
3543         if (pci_is_enabled(pdev)) {
3544                 pci_release_selected_regions(ioc->pdev, ioc->bars);
3545                 pci_disable_pcie_error_reporting(pdev);
3546                 pci_disable_device(pdev);
3547         }
3548 }
3549
3550 static int
3551 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3552
3553 /**
3554  * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state
3555  *     and if it is in fault state then issue diag reset.
3556  * @ioc: per adapter object
3557  *
3558  * Return: 0 for success, non-zero for failure.
3559  */
3560 int
3561 mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
3562 {
3563         u32 ioc_state;
3564         int rc = -EFAULT;
3565
3566         dinitprintk(ioc, pr_info("%s\n", __func__));
3567         if (ioc->pci_error_recovery)
3568                 return 0;
3569         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3570         dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
3571
3572         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3573                 mpt3sas_print_fault_code(ioc, ioc_state &
3574                     MPI2_DOORBELL_DATA_MASK);
3575                 mpt3sas_base_mask_interrupts(ioc);
3576                 rc = _base_diag_reset(ioc);
3577         } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
3578             MPI2_IOC_STATE_COREDUMP) {
3579                 mpt3sas_print_coredump_info(ioc, ioc_state &
3580                      MPI2_DOORBELL_DATA_MASK);
3581                 mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
3582                 mpt3sas_base_mask_interrupts(ioc);
3583                 rc = _base_diag_reset(ioc);
3584         }
3585
3586         return rc;
3587 }
3588
3589 /**
3590  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
3591  * @ioc: per adapter object
3592  *
3593  * Return: 0 for success, non-zero for failure.
3594  */
3595 int
3596 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
3597 {
3598         struct pci_dev *pdev = ioc->pdev;
3599         u32 memap_sz;
3600         u32 pio_sz;
3601         int i, r = 0, rc;
3602         u64 pio_chip = 0;
3603         phys_addr_t chip_phys = 0;
3604         struct adapter_reply_queue *reply_q;
3605         int iopoll_q_count = 0;
3606
3607         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3608
3609         ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3610         if (pci_enable_device_mem(pdev)) {
3611                 ioc_warn(ioc, "pci_enable_device_mem: failed\n");
3612                 ioc->bars = 0;
3613                 return -ENODEV;
3614         }
3615
3616
3617         if (pci_request_selected_regions(pdev, ioc->bars,
3618             ioc->driver_name)) {
3619                 ioc_warn(ioc, "pci_request_selected_regions: failed\n");
3620                 ioc->bars = 0;
3621                 r = -ENODEV;
3622                 goto out_fail;
3623         }
3624
3625 /* AER (Advanced Error Reporting) hooks */
3626         pci_enable_pcie_error_reporting(pdev);
3627
3628         pci_set_master(pdev);
3629
3630
3631         if (_base_config_dma_addressing(ioc, pdev) != 0) {
3632                 ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
3633                 r = -ENODEV;
3634                 goto out_fail;
3635         }
3636
3637         for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
3638              (!memap_sz || !pio_sz); i++) {
3639                 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
3640                         if (pio_sz)
3641                                 continue;
3642                         pio_chip = (u64)pci_resource_start(pdev, i);
3643                         pio_sz = pci_resource_len(pdev, i);
3644                 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3645                         if (memap_sz)
3646                                 continue;
3647                         ioc->chip_phys = pci_resource_start(pdev, i);
3648                         chip_phys = ioc->chip_phys;
3649                         memap_sz = pci_resource_len(pdev, i);
3650                         ioc->chip = ioremap(ioc->chip_phys, memap_sz);
3651                 }
3652         }
3653
3654         if (ioc->chip == NULL) {
3655                 ioc_err(ioc,
3656                     "unable to map adapter memory! or resource not found\n");
3657                 r = -EINVAL;
3658                 goto out_fail;
3659         }
3660
3661         mpt3sas_base_mask_interrupts(ioc);
3662
3663         r = _base_get_ioc_facts(ioc);
3664         if (r) {
3665                 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
3666                 if (rc || (_base_get_ioc_facts(ioc)))
3667                         goto out_fail;
3668         }
3669
3670         if (!ioc->rdpq_array_enable_assigned) {
3671                 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
3672                 ioc->rdpq_array_enable_assigned = 1;
3673         }
3674
3675         r = _base_enable_msix(ioc);
3676         if (r)
3677                 goto out_fail;
3678
3679         iopoll_q_count = ioc->reply_queue_count - ioc->iopoll_q_start_index;
3680         for (i = 0; i < iopoll_q_count; i++) {
3681                 atomic_set(&ioc->io_uring_poll_queues[i].busy, 0);
3682                 atomic_set(&ioc->io_uring_poll_queues[i].pause, 0);
3683         }
3684
3685         if (!ioc->is_driver_loading)
3686                 _base_init_irqpolls(ioc);
3687         /* Use the Combined reply queue feature only for SAS3 C0 & higher
3688          * revision HBAs and also only when reply queue count is greater than 8
3689          */
3690         if (ioc->combined_reply_queue) {
3691                 /* Determine the Supplemental Reply Post Host Index Registers
3692                  * Addresse. Supplemental Reply Post Host Index Registers
3693                  * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
3694                  * each register is at offset bytes of
3695                  * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
3696                  */
3697                 ioc->replyPostRegisterIndex = kcalloc(
3698                      ioc->combined_reply_index_count,
3699                      sizeof(resource_size_t *), GFP_KERNEL);
3700                 if (!ioc->replyPostRegisterIndex) {
3701                         ioc_err(ioc,
3702                             "allocation for replyPostRegisterIndex failed!\n");
3703                         r = -ENOMEM;
3704                         goto out_fail;
3705                 }
3706
3707                 for (i = 0; i < ioc->combined_reply_index_count; i++) {
3708                         ioc->replyPostRegisterIndex[i] = (resource_size_t *)
3709                              ((u8 __force *)&ioc->chip->Doorbell +
3710                              MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
3711                              (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
3712                 }
3713         }
3714
3715         if (ioc->is_warpdrive) {
3716                 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
3717                     &ioc->chip->ReplyPostHostIndex;
3718
3719                 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
3720                         ioc->reply_post_host_index[i] =
3721                         (resource_size_t __iomem *)
3722                         ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
3723                         * 4)));
3724         }
3725
3726         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3727                 if (reply_q->msix_index >= ioc->iopoll_q_start_index) {
3728                         pr_info("%s: enabled: index: %d\n",
3729                             reply_q->name, reply_q->msix_index);
3730                         continue;
3731                 }
3732
3733                 pr_info("%s: %s enabled: IRQ %d\n",
3734                         reply_q->name,
3735                         ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
3736                         pci_irq_vector(ioc->pdev, reply_q->msix_index));
3737         }
3738
3739         ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
3740                  &chip_phys, ioc->chip, memap_sz);
3741         ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
3742                  (unsigned long long)pio_chip, pio_sz);
3743
3744         /* Save PCI configuration state for recovery from PCI AER/EEH errors */
3745         pci_save_state(pdev);
3746         return 0;
3747
3748  out_fail:
3749         mpt3sas_base_unmap_resources(ioc);
3750         return r;
3751 }
3752
3753 /**
3754  * mpt3sas_base_get_msg_frame - obtain request mf pointer
3755  * @ioc: per adapter object
3756  * @smid: system request message index(smid zero is invalid)
3757  *
3758  * Return: virt pointer to message frame.
3759  */
3760 void *
3761 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3762 {
3763         return (void *)(ioc->request + (smid * ioc->request_sz));
3764 }
3765
3766 /**
3767  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
3768  * @ioc: per adapter object
3769  * @smid: system request message index
3770  *
3771  * Return: virt pointer to sense buffer.
3772  */
3773 void *
3774 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3775 {
3776         return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
3777 }
3778
3779 /**
3780  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
3781  * @ioc: per adapter object
3782  * @smid: system request message index
3783  *
3784  * Return: phys pointer to the low 32bit address of the sense buffer.
3785  */
3786 __le32
3787 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3788 {
3789         return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
3790             SCSI_SENSE_BUFFERSIZE));
3791 }
3792
3793 /**
3794  * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
3795  * @ioc: per adapter object
3796  * @smid: system request message index
3797  *
3798  * Return: virt pointer to a PCIe SGL.
3799  */
3800 void *
3801 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3802 {
3803         return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
3804 }
3805
3806 /**
3807  * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
3808  * @ioc: per adapter object
3809  * @smid: system request message index
3810  *
3811  * Return: phys pointer to the address of the PCIe buffer.
3812  */
3813 dma_addr_t
3814 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3815 {
3816         return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
3817 }
3818
3819 /**
3820  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3821  * @ioc: per adapter object
3822  * @phys_addr: lower 32 physical addr of the reply
3823  *
3824  * Converts 32bit lower physical addr into a virt address.
3825  */
3826 void *
3827 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
3828 {
3829         if (!phys_addr)
3830                 return NULL;
3831         return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3832 }
3833
3834 /**
3835  * _base_get_msix_index - get the msix index
3836  * @ioc: per adapter object
3837  * @scmd: scsi_cmnd object
3838  *
3839  * Return: msix index of general reply queues,
3840  * i.e. reply queue on which IO request's reply
3841  * should be posted by the HBA firmware.
3842  */
3843 static inline u8
3844 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
3845         struct scsi_cmnd *scmd)
3846 {
3847         /* Enables reply_queue load balancing */
3848         if (ioc->msix_load_balance)
3849                 return ioc->reply_queue_count ?
3850                     base_mod64(atomic64_add_return(1,
3851                     &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
3852
3853         if (scmd && ioc->shost->nr_hw_queues > 1) {
3854                 u32 tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
3855
3856                 return blk_mq_unique_tag_to_hwq(tag) +
3857                         ioc->high_iops_queues;
3858         }
3859
3860         return ioc->cpu_msix_table[raw_smp_processor_id()];
3861 }
3862
3863 /**
3864  * _base_get_high_iops_msix_index - get the msix index of
3865  *                              high iops queues
3866  * @ioc: per adapter object
3867  * @scmd: scsi_cmnd object
3868  *
3869  * Return: msix index of high iops reply queues.
3870  * i.e. high iops reply queue on which IO request's
3871  * reply should be posted by the HBA firmware.
3872  */
3873 static inline u8
3874 _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
3875         struct scsi_cmnd *scmd)
3876 {
3877         /**
3878          * Round robin the IO interrupts among the high iops
3879          * reply queues in terms of batch count 16 when outstanding
3880          * IOs on the target device is >=8.
3881          */
3882
3883         if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
3884                 return base_mod64((
3885                     atomic64_add_return(1, &ioc->high_iops_outstanding) /
3886                     MPT3SAS_HIGH_IOPS_BATCH_COUNT),
3887                     MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
3888
3889         return _base_get_msix_index(ioc, scmd);
3890 }
3891
3892 /**
3893  * mpt3sas_base_get_smid - obtain a free smid from internal queue
3894  * @ioc: per adapter object
3895  * @cb_idx: callback index
3896  *
3897  * Return: smid (zero is invalid)
3898  */
3899 u16
3900 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3901 {
3902         unsigned long flags;
3903         struct request_tracker *request;
3904         u16 smid;
3905
3906         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3907         if (list_empty(&ioc->internal_free_list)) {
3908                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3909                 ioc_err(ioc, "%s: smid not available\n", __func__);
3910                 return 0;
3911         }
3912
3913         request = list_entry(ioc->internal_free_list.next,
3914             struct request_tracker, tracker_list);
3915         request->cb_idx = cb_idx;
3916         smid = request->smid;
3917         list_del(&request->tracker_list);
3918         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3919         return smid;
3920 }
3921
3922 /**
3923  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
3924  * @ioc: per adapter object
3925  * @cb_idx: callback index
3926  * @scmd: pointer to scsi command object
3927  *
3928  * Return: smid (zero is invalid)
3929  */
3930 u16
3931 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
3932         struct scsi_cmnd *scmd)
3933 {
3934         struct scsiio_tracker *request = scsi_cmd_priv(scmd);
3935         u16 smid;
3936         u32 tag, unique_tag;
3937
3938         unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
3939         tag = blk_mq_unique_tag_to_tag(unique_tag);
3940
3941         /*
3942          * Store hw queue number corresponding to the tag.
3943          * This hw queue number is used later to determine
3944          * the unique_tag using the logic below. This unique_tag
3945          * is used to retrieve the scmd pointer corresponding
3946          * to tag using scsi_host_find_tag() API.
3947          *
3948          * tag = smid - 1;
3949          * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag;
3950          */
3951         ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag);
3952
3953         smid = tag + 1;
3954         request->cb_idx = cb_idx;
3955         request->smid = smid;
3956         request->scmd = scmd;
3957         INIT_LIST_HEAD(&request->chain_list);
3958         return smid;
3959 }
3960
3961 /**
3962  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
3963  * @ioc: per adapter object
3964  * @cb_idx: callback index
3965  *
3966  * Return: smid (zero is invalid)
3967  */
3968 u16
3969 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3970 {
3971         unsigned long flags;
3972         struct request_tracker *request;
3973         u16 smid;
3974
3975         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3976         if (list_empty(&ioc->hpr_free_list)) {
3977                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3978                 return 0;
3979         }
3980
3981         request = list_entry(ioc->hpr_free_list.next,
3982             struct request_tracker, tracker_list);
3983         request->cb_idx = cb_idx;
3984         smid = request->smid;
3985         list_del(&request->tracker_list);
3986         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3987         return smid;
3988 }
3989
3990 static void
3991 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
3992 {
3993         /*
3994          * See _wait_for_commands_to_complete() call with regards to this code.
3995          */
3996         if (ioc->shost_recovery && ioc->pending_io_count) {
3997                 ioc->pending_io_count = scsi_host_busy(ioc->shost);
3998                 if (ioc->pending_io_count == 0)
3999                         wake_up(&ioc->reset_wq);
4000         }
4001 }
4002
4003 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
4004                            struct scsiio_tracker *st)
4005 {
4006         if (WARN_ON(st->smid == 0))
4007                 return;
4008         st->cb_idx = 0xFF;
4009         st->direct_io = 0;
4010         st->scmd = NULL;
4011         atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
4012         st->smid = 0;
4013 }
4014
4015 /**
4016  * mpt3sas_base_free_smid - put smid back on free_list
4017  * @ioc: per adapter object
4018  * @smid: system request message index
4019  */
4020 void
4021 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4022 {
4023         unsigned long flags;
4024         int i;
4025
4026         if (smid < ioc->hi_priority_smid) {
4027                 struct scsiio_tracker *st;
4028                 void *request;
4029
4030                 st = _get_st_from_smid(ioc, smid);
4031                 if (!st) {
4032                         _base_recovery_check(ioc);
4033                         return;
4034                 }
4035
4036                 /* Clear MPI request frame */
4037                 request = mpt3sas_base_get_msg_frame(ioc, smid);
4038                 memset(request, 0, ioc->request_sz);
4039
4040                 mpt3sas_base_clear_st(ioc, st);
4041                 _base_recovery_check(ioc);
4042                 ioc->io_queue_num[smid - 1] = 0;
4043                 return;
4044         }
4045
4046         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4047         if (smid < ioc->internal_smid) {
4048                 /* hi-priority */
4049                 i = smid - ioc->hi_priority_smid;
4050                 ioc->hpr_lookup[i].cb_idx = 0xFF;
4051                 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
4052         } else if (smid <= ioc->hba_queue_depth) {
4053                 /* internal queue */
4054                 i = smid - ioc->internal_smid;
4055                 ioc->internal_lookup[i].cb_idx = 0xFF;
4056                 list_add(&ioc->internal_lookup[i].tracker_list,
4057                     &ioc->internal_free_list);
4058         }
4059         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4060 }
4061
4062 /**
4063  * _base_mpi_ep_writeq - 32 bit write to MMIO
4064  * @b: data payload
4065  * @addr: address in MMIO space
4066  * @writeq_lock: spin lock
4067  *
4068  * This special handling for MPI EP to take care of 32 bit
4069  * environment where its not quarenteed to send the entire word
4070  * in one transfer.
4071  */
4072 static inline void
4073 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
4074                                         spinlock_t *writeq_lock)
4075 {
4076         unsigned long flags;
4077
4078         spin_lock_irqsave(writeq_lock, flags);
4079         __raw_writel((u32)(b), addr);
4080         __raw_writel((u32)(b >> 32), (addr + 4));
4081         spin_unlock_irqrestore(writeq_lock, flags);
4082 }
4083
4084 /**
4085  * _base_writeq - 64 bit write to MMIO
4086  * @b: data payload
4087  * @addr: address in MMIO space
4088  * @writeq_lock: spin lock
4089  *
4090  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
4091  * care of 32 bit environment where its not quarenteed to send the entire word
4092  * in one transfer.
4093  */
4094 #if defined(writeq) && defined(CONFIG_64BIT)
4095 static inline void
4096 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
4097 {
4098         wmb();
4099         __raw_writeq(b, addr);
4100         barrier();
4101 }
4102 #else
4103 static inline void
4104 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
4105 {
4106         _base_mpi_ep_writeq(b, addr, writeq_lock);
4107 }
4108 #endif
4109
4110 /**
4111  * _base_set_and_get_msix_index - get the msix index and assign to msix_io
4112  *                                variable of scsi tracker
4113  * @ioc: per adapter object
4114  * @smid: system request message index
4115  *
4116  * Return: msix index.
4117  */
4118 static u8
4119 _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4120 {
4121         struct scsiio_tracker *st = NULL;
4122
4123         if (smid < ioc->hi_priority_smid)
4124                 st = _get_st_from_smid(ioc, smid);
4125
4126         if (st == NULL)
4127                 return  _base_get_msix_index(ioc, NULL);
4128
4129         st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
4130         return st->msix_io;
4131 }
4132
4133 /**
4134  * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
4135  * @ioc: per adapter object
4136  * @smid: system request message index
4137  * @handle: device handle
4138  */
4139 static void
4140 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
4141         u16 smid, u16 handle)
4142 {
4143         Mpi2RequestDescriptorUnion_t descriptor;
4144         u64 *request = (u64 *)&descriptor;
4145         void *mpi_req_iomem;
4146         __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4147
4148         _clone_sg_entries(ioc, (void *) mfp, smid);
4149         mpi_req_iomem = (void __force *)ioc->chip +
4150                         MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4151         _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4152                                         ioc->request_sz);
4153         descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4154         descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4155         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4156         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4157         descriptor.SCSIIO.LMID = 0;
4158         _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4159             &ioc->scsi_lookup_lock);
4160 }
4161
4162 /**
4163  * _base_put_smid_scsi_io - send SCSI_IO request to firmware
4164  * @ioc: per adapter object
4165  * @smid: system request message index
4166  * @handle: device handle
4167  */
4168 static void
4169 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
4170 {
4171         Mpi2RequestDescriptorUnion_t descriptor;
4172         u64 *request = (u64 *)&descriptor;
4173
4174
4175         descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4176         descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4177         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4178         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4179         descriptor.SCSIIO.LMID = 0;
4180         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4181             &ioc->scsi_lookup_lock);
4182 }
4183
4184 /**
4185  * _base_put_smid_fast_path - send fast path request to firmware
4186  * @ioc: per adapter object
4187  * @smid: system request message index
4188  * @handle: device handle
4189  */
4190 static void
4191 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4192         u16 handle)
4193 {
4194         Mpi2RequestDescriptorUnion_t descriptor;
4195         u64 *request = (u64 *)&descriptor;
4196
4197         descriptor.SCSIIO.RequestFlags =
4198             MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4199         descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4200         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4201         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4202         descriptor.SCSIIO.LMID = 0;
4203         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4204             &ioc->scsi_lookup_lock);
4205 }
4206
4207 /**
4208  * _base_put_smid_hi_priority - send Task Management request to firmware
4209  * @ioc: per adapter object
4210  * @smid: system request message index
4211  * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4212  */
4213 static void
4214 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4215         u16 msix_task)
4216 {
4217         Mpi2RequestDescriptorUnion_t descriptor;
4218         void *mpi_req_iomem;
4219         u64 *request;
4220
4221         if (ioc->is_mcpu_endpoint) {
4222                 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4223
4224                 /* TBD 256 is offset within sys register. */
4225                 mpi_req_iomem = (void __force *)ioc->chip
4226                                         + MPI_FRAME_START_OFFSET
4227                                         + (smid * ioc->request_sz);
4228                 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4229                                                         ioc->request_sz);
4230         }
4231
4232         request = (u64 *)&descriptor;
4233
4234         descriptor.HighPriority.RequestFlags =
4235             MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4236         descriptor.HighPriority.MSIxIndex =  msix_task;
4237         descriptor.HighPriority.SMID = cpu_to_le16(smid);
4238         descriptor.HighPriority.LMID = 0;
4239         descriptor.HighPriority.Reserved1 = 0;
4240         if (ioc->is_mcpu_endpoint)
4241                 _base_mpi_ep_writeq(*request,
4242                                 &ioc->chip->RequestDescriptorPostLow,
4243                                 &ioc->scsi_lookup_lock);
4244         else
4245                 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4246                     &ioc->scsi_lookup_lock);
4247 }
4248
4249 /**
4250  * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
4251  *  firmware
4252  * @ioc: per adapter object
4253  * @smid: system request message index
4254  */
4255 void
4256 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4257 {
4258         Mpi2RequestDescriptorUnion_t descriptor;
4259         u64 *request = (u64 *)&descriptor;
4260
4261         descriptor.Default.RequestFlags =
4262                 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
4263         descriptor.Default.MSIxIndex =  _base_set_and_get_msix_index(ioc, smid);
4264         descriptor.Default.SMID = cpu_to_le16(smid);
4265         descriptor.Default.LMID = 0;
4266         descriptor.Default.DescriptorTypeDependent = 0;
4267         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4268             &ioc->scsi_lookup_lock);
4269 }
4270
4271 /**
4272  * _base_put_smid_default - Default, primarily used for config pages
4273  * @ioc: per adapter object
4274  * @smid: system request message index
4275  */
4276 static void
4277 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4278 {
4279         Mpi2RequestDescriptorUnion_t descriptor;
4280         void *mpi_req_iomem;
4281         u64 *request;
4282
4283         if (ioc->is_mcpu_endpoint) {
4284                 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4285
4286                 _clone_sg_entries(ioc, (void *) mfp, smid);
4287                 /* TBD 256 is offset within sys register */
4288                 mpi_req_iomem = (void __force *)ioc->chip +
4289                         MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4290                 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4291                                                         ioc->request_sz);
4292         }
4293         request = (u64 *)&descriptor;
4294         descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4295         descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4296         descriptor.Default.SMID = cpu_to_le16(smid);
4297         descriptor.Default.LMID = 0;
4298         descriptor.Default.DescriptorTypeDependent = 0;
4299         if (ioc->is_mcpu_endpoint)
4300                 _base_mpi_ep_writeq(*request,
4301                                 &ioc->chip->RequestDescriptorPostLow,
4302                                 &ioc->scsi_lookup_lock);
4303         else
4304                 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4305                                 &ioc->scsi_lookup_lock);
4306 }
4307
4308 /**
4309  * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
4310  *   Atomic Request Descriptor
4311  * @ioc: per adapter object
4312  * @smid: system request message index
4313  * @handle: device handle, unused in this function, for function type match
4314  *
4315  * Return: nothing.
4316  */
4317 static void
4318 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4319         u16 handle)
4320 {
4321         Mpi26AtomicRequestDescriptor_t descriptor;
4322         u32 *request = (u32 *)&descriptor;
4323
4324         descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4325         descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4326         descriptor.SMID = cpu_to_le16(smid);
4327
4328         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4329 }
4330
4331 /**
4332  * _base_put_smid_fast_path_atomic - send fast path request to firmware
4333  * using Atomic Request Descriptor
4334  * @ioc: per adapter object
4335  * @smid: system request message index
4336  * @handle: device handle, unused in this function, for function type match
4337  * Return: nothing
4338  */
4339 static void
4340 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4341         u16 handle)
4342 {
4343         Mpi26AtomicRequestDescriptor_t descriptor;
4344         u32 *request = (u32 *)&descriptor;
4345
4346         descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4347         descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4348         descriptor.SMID = cpu_to_le16(smid);
4349
4350         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4351 }
4352
4353 /**
4354  * _base_put_smid_hi_priority_atomic - send Task Management request to
4355  * firmware using Atomic Request Descriptor
4356  * @ioc: per adapter object
4357  * @smid: system request message index
4358  * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4359  *
4360  * Return: nothing.
4361  */
4362 static void
4363 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4364         u16 msix_task)
4365 {
4366         Mpi26AtomicRequestDescriptor_t descriptor;
4367         u32 *request = (u32 *)&descriptor;
4368
4369         descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4370         descriptor.MSIxIndex = msix_task;
4371         descriptor.SMID = cpu_to_le16(smid);
4372
4373         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4374 }
4375
4376 /**
4377  * _base_put_smid_default_atomic - Default, primarily used for config pages
4378  * use Atomic Request Descriptor
4379  * @ioc: per adapter object
4380  * @smid: system request message index
4381  *
4382  * Return: nothing.
4383  */
4384 static void
4385 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4386 {
4387         Mpi26AtomicRequestDescriptor_t descriptor;
4388         u32 *request = (u32 *)&descriptor;
4389
4390         descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4391         descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4392         descriptor.SMID = cpu_to_le16(smid);
4393
4394         writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4395 }
4396
4397 /**
4398  * _base_display_OEMs_branding - Display branding string
4399  * @ioc: per adapter object
4400  */
4401 static void
4402 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
4403 {
4404         if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
4405                 return;
4406
4407         switch (ioc->pdev->subsystem_vendor) {
4408         case PCI_VENDOR_ID_INTEL:
4409                 switch (ioc->pdev->device) {
4410                 case MPI2_MFGPAGE_DEVID_SAS2008:
4411                         switch (ioc->pdev->subsystem_device) {
4412                         case MPT2SAS_INTEL_RMS2LL080_SSDID:
4413                                 ioc_info(ioc, "%s\n",
4414                                          MPT2SAS_INTEL_RMS2LL080_BRANDING);
4415                                 break;
4416                         case MPT2SAS_INTEL_RMS2LL040_SSDID:
4417                                 ioc_info(ioc, "%s\n",
4418                                          MPT2SAS_INTEL_RMS2LL040_BRANDING);
4419                                 break;
4420                         case MPT2SAS_INTEL_SSD910_SSDID:
4421                                 ioc_info(ioc, "%s\n",
4422                                          MPT2SAS_INTEL_SSD910_BRANDING);
4423                                 break;
4424                         default:
4425                                 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4426                                          ioc->pdev->subsystem_device);
4427                                 break;
4428                         }
4429                         break;
4430                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
4431                         switch (ioc->pdev->subsystem_device) {
4432                         case MPT2SAS_INTEL_RS25GB008_SSDID:
4433                                 ioc_info(ioc, "%s\n",
4434                                          MPT2SAS_INTEL_RS25GB008_BRANDING);
4435                                 break;
4436                         case MPT2SAS_INTEL_RMS25JB080_SSDID:
4437                                 ioc_info(ioc, "%s\n",
4438                                          MPT2SAS_INTEL_RMS25JB080_BRANDING);
4439                                 break;
4440                         case MPT2SAS_INTEL_RMS25JB040_SSDID:
4441                                 ioc_info(ioc, "%s\n",
4442                                          MPT2SAS_INTEL_RMS25JB040_BRANDING);
4443                                 break;
4444                         case MPT2SAS_INTEL_RMS25KB080_SSDID:
4445                                 ioc_info(ioc, "%s\n",
4446                                          MPT2SAS_INTEL_RMS25KB080_BRANDING);
4447                                 break;
4448                         case MPT2SAS_INTEL_RMS25KB040_SSDID:
4449                                 ioc_info(ioc, "%s\n",
4450                                          MPT2SAS_INTEL_RMS25KB040_BRANDING);
4451                                 break;
4452                         case MPT2SAS_INTEL_RMS25LB040_SSDID:
4453                                 ioc_info(ioc, "%s\n",
4454                                          MPT2SAS_INTEL_RMS25LB040_BRANDING);
4455                                 break;
4456                         case MPT2SAS_INTEL_RMS25LB080_SSDID:
4457                                 ioc_info(ioc, "%s\n",
4458                                          MPT2SAS_INTEL_RMS25LB080_BRANDING);
4459                                 break;
4460                         default:
4461                                 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4462                                          ioc->pdev->subsystem_device);
4463                                 break;
4464                         }
4465                         break;
4466                 case MPI25_MFGPAGE_DEVID_SAS3008:
4467                         switch (ioc->pdev->subsystem_device) {
4468                         case MPT3SAS_INTEL_RMS3JC080_SSDID:
4469                                 ioc_info(ioc, "%s\n",
4470                                          MPT3SAS_INTEL_RMS3JC080_BRANDING);
4471                                 break;
4472
4473                         case MPT3SAS_INTEL_RS3GC008_SSDID:
4474                                 ioc_info(ioc, "%s\n",
4475                                          MPT3SAS_INTEL_RS3GC008_BRANDING);
4476                                 break;
4477                         case MPT3SAS_INTEL_RS3FC044_SSDID:
4478                                 ioc_info(ioc, "%s\n",
4479                                          MPT3SAS_INTEL_RS3FC044_BRANDING);
4480                                 break;
4481                         case MPT3SAS_INTEL_RS3UC080_SSDID:
4482                                 ioc_info(ioc, "%s\n",
4483                                          MPT3SAS_INTEL_RS3UC080_BRANDING);
4484                                 break;
4485                         default:
4486                                 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4487                                          ioc->pdev->subsystem_device);
4488                                 break;
4489                         }
4490                         break;
4491                 default:
4492                         ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4493                                  ioc->pdev->subsystem_device);
4494                         break;
4495                 }
4496                 break;
4497         case PCI_VENDOR_ID_DELL:
4498                 switch (ioc->pdev->device) {
4499                 case MPI2_MFGPAGE_DEVID_SAS2008:
4500                         switch (ioc->pdev->subsystem_device) {
4501                         case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
4502                                 ioc_info(ioc, "%s\n",
4503                                          MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
4504                                 break;
4505                         case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
4506                                 ioc_info(ioc, "%s\n",
4507                                          MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
4508                                 break;
4509                         case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
4510                                 ioc_info(ioc, "%s\n",
4511                                          MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
4512                                 break;
4513                         case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
4514                                 ioc_info(ioc, "%s\n",
4515                                          MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
4516                                 break;
4517                         case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
4518                                 ioc_info(ioc, "%s\n",
4519                                          MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
4520                                 break;
4521                         case MPT2SAS_DELL_PERC_H200_SSDID:
4522                                 ioc_info(ioc, "%s\n",
4523                                          MPT2SAS_DELL_PERC_H200_BRANDING);
4524                                 break;
4525                         case MPT2SAS_DELL_6GBPS_SAS_SSDID:
4526                                 ioc_info(ioc, "%s\n",
4527                                          MPT2SAS_DELL_6GBPS_SAS_BRANDING);
4528                                 break;
4529                         default:
4530                                 ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
4531                                          ioc->pdev->subsystem_device);
4532                                 break;
4533                         }
4534                         break;
4535                 case MPI25_MFGPAGE_DEVID_SAS3008:
4536                         switch (ioc->pdev->subsystem_device) {
4537                         case MPT3SAS_DELL_12G_HBA_SSDID:
4538                                 ioc_info(ioc, "%s\n",
4539                                          MPT3SAS_DELL_12G_HBA_BRANDING);
4540                                 break;
4541                         default:
4542                                 ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
4543                                          ioc->pdev->subsystem_device);
4544                                 break;
4545                         }
4546                         break;
4547                 default:
4548                         ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
4549                                  ioc->pdev->subsystem_device);
4550                         break;
4551                 }
4552                 break;
4553         case PCI_VENDOR_ID_CISCO:
4554                 switch (ioc->pdev->device) {
4555                 case MPI25_MFGPAGE_DEVID_SAS3008:
4556                         switch (ioc->pdev->subsystem_device) {
4557                         case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
4558                                 ioc_info(ioc, "%s\n",
4559                                          MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
4560                                 break;
4561                         case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
4562                                 ioc_info(ioc, "%s\n",
4563                                          MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
4564                                 break;
4565                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4566                                 ioc_info(ioc, "%s\n",
4567                                          MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4568                                 break;
4569                         default:
4570                                 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4571                                          ioc->pdev->subsystem_device);
4572                                 break;
4573                         }
4574                         break;
4575                 case MPI25_MFGPAGE_DEVID_SAS3108_1:
4576                         switch (ioc->pdev->subsystem_device) {
4577                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
4578                                 ioc_info(ioc, "%s\n",
4579                                          MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
4580                                 break;
4581                         case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
4582                                 ioc_info(ioc, "%s\n",
4583                                          MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
4584                                 break;
4585                         default:
4586                                 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
4587                                          ioc->pdev->subsystem_device);
4588                                 break;
4589                         }
4590                         break;
4591                 default:
4592                         ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
4593                                  ioc->pdev->subsystem_device);
4594                         break;
4595                 }
4596                 break;
4597         case MPT2SAS_HP_3PAR_SSVID:
4598                 switch (ioc->pdev->device) {
4599                 case MPI2_MFGPAGE_DEVID_SAS2004:
4600                         switch (ioc->pdev->subsystem_device) {
4601                         case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
4602                                 ioc_info(ioc, "%s\n",
4603                                          MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
4604                                 break;
4605                         default:
4606                                 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4607                                          ioc->pdev->subsystem_device);
4608                                 break;
4609                         }
4610                         break;
4611                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
4612                         switch (ioc->pdev->subsystem_device) {
4613                         case MPT2SAS_HP_2_4_INTERNAL_SSDID:
4614                                 ioc_info(ioc, "%s\n",
4615                                          MPT2SAS_HP_2_4_INTERNAL_BRANDING);
4616                                 break;
4617                         case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
4618                                 ioc_info(ioc, "%s\n",
4619                                          MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
4620                                 break;
4621                         case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
4622                                 ioc_info(ioc, "%s\n",
4623                                          MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
4624                                 break;
4625                         case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
4626                                 ioc_info(ioc, "%s\n",
4627                                          MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
4628                                 break;
4629                         default:
4630                                 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
4631                                          ioc->pdev->subsystem_device);
4632                                 break;
4633                         }
4634                         break;
4635                 default:
4636                         ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
4637                                  ioc->pdev->subsystem_device);
4638                         break;
4639                 }
4640                 break;
4641         default:
4642                 break;
4643         }
4644 }
4645
4646 /**
4647  * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg
4648  *                              version from FW Image Header.
4649  * @ioc: per adapter object
4650  *
4651  * Return: 0 for success, non-zero for failure.
4652  */
4653         static int
4654 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
4655 {
4656         Mpi2FWImageHeader_t *fw_img_hdr;
4657         Mpi26ComponentImageHeader_t *cmp_img_hdr;
4658         Mpi25FWUploadRequest_t *mpi_request;
4659         Mpi2FWUploadReply_t mpi_reply;
4660         int r = 0, issue_diag_reset = 0;
4661         u32  package_version = 0;
4662         void *fwpkg_data = NULL;
4663         dma_addr_t fwpkg_data_dma;
4664         u16 smid, ioc_status;
4665         size_t data_length;
4666
4667         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4668
4669         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4670                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
4671                 return -EAGAIN;
4672         }
4673
4674         data_length = sizeof(Mpi2FWImageHeader_t);
4675         fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
4676                         &fwpkg_data_dma, GFP_KERNEL);
4677         if (!fwpkg_data) {
4678                 ioc_err(ioc,
4679                     "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
4680                         __FILE__, __LINE__, __func__);
4681                 return -ENOMEM;
4682         }
4683
4684         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4685         if (!smid) {
4686                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
4687                 r = -EAGAIN;
4688                 goto out;
4689         }
4690
4691         ioc->base_cmds.status = MPT3_CMD_PENDING;
4692         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4693         ioc->base_cmds.smid = smid;
4694         memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t));
4695         mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD;
4696         mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH;
4697         mpi_request->ImageSize = cpu_to_le32(data_length);
4698         ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
4699                         data_length);
4700         init_completion(&ioc->base_cmds.done);
4701         ioc->put_smid_default(ioc, smid);
4702         /* Wait for 15 seconds */
4703         wait_for_completion_timeout(&ioc->base_cmds.done,
4704                         FW_IMG_HDR_READ_TIMEOUT*HZ);
4705         ioc_info(ioc, "%s: complete\n", __func__);
4706         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4707                 ioc_err(ioc, "%s: timeout\n", __func__);
4708                 _debug_dump_mf(mpi_request,
4709                                 sizeof(Mpi25FWUploadRequest_t)/4);
4710                 issue_diag_reset = 1;
4711         } else {
4712                 memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t));
4713                 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) {
4714                         memcpy(&mpi_reply, ioc->base_cmds.reply,
4715                                         sizeof(Mpi2FWUploadReply_t));
4716                         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4717                                                 MPI2_IOCSTATUS_MASK;
4718                         if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4719                                 fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
4720                                 if (le32_to_cpu(fw_img_hdr->Signature) ==
4721                                     MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
4722                                         cmp_img_hdr =
4723                                             (Mpi26ComponentImageHeader_t *)
4724                                             (fwpkg_data);
4725                                         package_version =
4726                                             le32_to_cpu(
4727                                             cmp_img_hdr->ApplicationSpecific);
4728                                 } else
4729                                         package_version =
4730                                             le32_to_cpu(
4731                                             fw_img_hdr->PackageVersion.Word);
4732                                 if (package_version)
4733                                         ioc_info(ioc,
4734                                         "FW Package Ver(%02d.%02d.%02d.%02d)\n",
4735                                         ((package_version) & 0xFF000000) >> 24,
4736                                         ((package_version) & 0x00FF0000) >> 16,
4737                                         ((package_version) & 0x0000FF00) >> 8,
4738                                         (package_version) & 0x000000FF);
4739                         } else {
4740                                 _debug_dump_mf(&mpi_reply,
4741                                                 sizeof(Mpi2FWUploadReply_t)/4);
4742                         }
4743                 }
4744         }
4745         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4746 out:
4747         if (fwpkg_data)
4748                 dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
4749                                 fwpkg_data_dma);
4750         if (issue_diag_reset) {
4751                 if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED)
4752                         return -EFAULT;
4753                 if (mpt3sas_base_check_for_fault_and_issue_reset(ioc))
4754                         return -EFAULT;
4755                 r = -EAGAIN;
4756         }
4757         return r;
4758 }
4759
4760 /**
4761  * _base_display_ioc_capabilities - Display IOC's capabilities.
4762  * @ioc: per adapter object
4763  */
4764 static void
4765 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
4766 {
4767         int i = 0;
4768         char desc[16];
4769         u32 iounit_pg1_flags;
4770         u32 bios_version;
4771
4772         bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
4773         strncpy(desc, ioc->manu_pg0.ChipName, 16);
4774         ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
4775                  desc,
4776                  (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
4777                  (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
4778                  (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
4779                  ioc->facts.FWVersion.Word & 0x000000FF,
4780                  ioc->pdev->revision,
4781                  (bios_version & 0xFF000000) >> 24,
4782                  (bios_version & 0x00FF0000) >> 16,
4783                  (bios_version & 0x0000FF00) >> 8,
4784                  bios_version & 0x000000FF);
4785
4786         _base_display_OEMs_branding(ioc);
4787
4788         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4789                 pr_info("%sNVMe", i ? "," : "");
4790                 i++;
4791         }
4792
4793         ioc_info(ioc, "Protocol=(");
4794
4795         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
4796                 pr_cont("Initiator");
4797                 i++;
4798         }
4799
4800         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
4801                 pr_cont("%sTarget", i ? "," : "");
4802                 i++;
4803         }
4804
4805         i = 0;
4806         pr_cont("), Capabilities=(");
4807
4808         if (!ioc->hide_ir_msg) {
4809                 if (ioc->facts.IOCCapabilities &
4810                     MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
4811                         pr_cont("Raid");
4812                         i++;
4813                 }
4814         }
4815
4816         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
4817                 pr_cont("%sTLR", i ? "," : "");
4818                 i++;
4819         }
4820
4821         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
4822                 pr_cont("%sMulticast", i ? "," : "");
4823                 i++;
4824         }
4825
4826         if (ioc->facts.IOCCapabilities &
4827             MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
4828                 pr_cont("%sBIDI Target", i ? "," : "");
4829                 i++;
4830         }
4831
4832         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
4833                 pr_cont("%sEEDP", i ? "," : "");
4834                 i++;
4835         }
4836
4837         if (ioc->facts.IOCCapabilities &
4838             MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
4839                 pr_cont("%sSnapshot Buffer", i ? "," : "");
4840                 i++;
4841         }
4842
4843         if (ioc->facts.IOCCapabilities &
4844             MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
4845                 pr_cont("%sDiag Trace Buffer", i ? "," : "");
4846                 i++;
4847         }
4848
4849         if (ioc->facts.IOCCapabilities &
4850             MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
4851                 pr_cont("%sDiag Extended Buffer", i ? "," : "");
4852                 i++;
4853         }
4854
4855         if (ioc->facts.IOCCapabilities &
4856             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
4857                 pr_cont("%sTask Set Full", i ? "," : "");
4858                 i++;
4859         }
4860
4861         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4862         if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
4863                 pr_cont("%sNCQ", i ? "," : "");
4864                 i++;
4865         }
4866
4867         pr_cont(")\n");
4868 }
4869
4870 /**
4871  * mpt3sas_base_update_missing_delay - change the missing delay timers
4872  * @ioc: per adapter object
4873  * @device_missing_delay: amount of time till device is reported missing
4874  * @io_missing_delay: interval IO is returned when there is a missing device
4875  *
4876  * Passed on the command line, this function will modify the device missing
4877  * delay, as well as the io missing delay. This should be called at driver
4878  * load time.
4879  */
4880 void
4881 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
4882         u16 device_missing_delay, u8 io_missing_delay)
4883 {
4884         u16 dmd, dmd_new, dmd_orignal;
4885         u8 io_missing_delay_original;
4886         u16 sz;
4887         Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
4888         Mpi2ConfigReply_t mpi_reply;
4889         u8 num_phys = 0;
4890         u16 ioc_status;
4891
4892         mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
4893         if (!num_phys)
4894                 return;
4895
4896         sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
4897             sizeof(Mpi2SasIOUnit1PhyData_t));
4898         sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4899         if (!sas_iounit_pg1) {
4900                 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4901                         __FILE__, __LINE__, __func__);
4902                 goto out;
4903         }
4904         if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4905             sas_iounit_pg1, sz))) {
4906                 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4907                         __FILE__, __LINE__, __func__);
4908                 goto out;
4909         }
4910         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4911             MPI2_IOCSTATUS_MASK;
4912         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4913                 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4914                         __FILE__, __LINE__, __func__);
4915                 goto out;
4916         }
4917
4918         /* device missing delay */
4919         dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
4920         if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4921                 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4922         else
4923                 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4924         dmd_orignal = dmd;
4925         if (device_missing_delay > 0x7F) {
4926                 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
4927                     device_missing_delay;
4928                 dmd = dmd / 16;
4929                 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
4930         } else
4931                 dmd = device_missing_delay;
4932         sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
4933
4934         /* io missing delay */
4935         io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
4936         sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
4937
4938         if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
4939             sz)) {
4940                 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4941                         dmd_new = (dmd &
4942                             MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4943                 else
4944                         dmd_new =
4945                     dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4946                 ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
4947                          dmd_orignal, dmd_new);
4948                 ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
4949                          io_missing_delay_original,
4950                          io_missing_delay);
4951                 ioc->device_missing_delay = dmd_new;
4952                 ioc->io_missing_delay = io_missing_delay;
4953         }
4954
4955 out:
4956         kfree(sas_iounit_pg1);
4957 }
4958
4959 /**
4960  * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
4961  *    according to performance mode.
4962  * @ioc : per adapter object
4963  *
4964  * Return: zero on success; otherwise return EAGAIN error code asking the
4965  * caller to retry.
4966  */
4967 static int
4968 _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
4969 {
4970         Mpi2IOCPage1_t ioc_pg1;
4971         Mpi2ConfigReply_t mpi_reply;
4972         int rc;
4973
4974         rc = mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
4975         if (rc)
4976                 return rc;
4977         memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
4978
4979         switch (perf_mode) {
4980         case MPT_PERF_MODE_DEFAULT:
4981         case MPT_PERF_MODE_BALANCED:
4982                 if (ioc->high_iops_queues) {
4983                         ioc_info(ioc,
4984                                 "Enable interrupt coalescing only for first\t"
4985                                 "%d reply queues\n",
4986                                 MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
4987                         /*
4988                          * If 31st bit is zero then interrupt coalescing is
4989                          * enabled for all reply descriptor post queues.
4990                          * If 31st bit is set to one then user can
4991                          * enable/disable interrupt coalescing on per reply
4992                          * descriptor post queue group(8) basis. So to enable
4993                          * interrupt coalescing only on first reply descriptor
4994                          * post queue group 31st bit and zero th bit is enabled.
4995                          */
4996                         ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 |
4997                             ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
4998                         rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
4999                         if (rc)
5000                                 return rc;
5001                         ioc_info(ioc, "performance mode: balanced\n");
5002                         return 0;
5003                 }
5004                 fallthrough;
5005         case MPT_PERF_MODE_LATENCY:
5006                 /*
5007                  * Enable interrupt coalescing on all reply queues
5008                  * with timeout value 0xA
5009                  */
5010                 ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
5011                 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
5012                 ioc_pg1.ProductSpecific = 0;
5013                 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
5014                 if (rc)
5015                         return rc;
5016                 ioc_info(ioc, "performance mode: latency\n");
5017                 break;
5018         case MPT_PERF_MODE_IOPS:
5019                 /*
5020                  * Enable interrupt coalescing on all reply queues.
5021                  */
5022                 ioc_info(ioc,
5023                     "performance mode: iops with coalescing timeout: 0x%x\n",
5024                     le32_to_cpu(ioc_pg1.CoalescingTimeout));
5025                 ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
5026                 ioc_pg1.ProductSpecific = 0;
5027                 rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
5028                 if (rc)
5029                         return rc;
5030                 break;
5031         }
5032         return 0;
5033 }
5034
5035 /**
5036  * _base_get_event_diag_triggers - get event diag trigger values from
5037  *                              persistent pages
5038  * @ioc : per adapter object
5039  *
5040  * Return: nothing.
5041  */
5042 static int
5043 _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5044 {
5045         Mpi26DriverTriggerPage2_t trigger_pg2;
5046         struct SL_WH_EVENT_TRIGGER_T *event_tg;
5047         MPI26_DRIVER_MPI_EVENT_TIGGER_ENTRY *mpi_event_tg;
5048         Mpi2ConfigReply_t mpi_reply;
5049         int r = 0, i = 0;
5050         u16 count = 0;
5051         u16 ioc_status;
5052
5053         r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply,
5054             &trigger_pg2);
5055         if (r)
5056                 return r;
5057
5058         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5059             MPI2_IOCSTATUS_MASK;
5060         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5061                 dinitprintk(ioc,
5062                     ioc_err(ioc,
5063                     "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n",
5064                    __func__, ioc_status));
5065                 return 0;
5066         }
5067
5068         if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) {
5069                 count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger);
5070                 count = min_t(u16, NUM_VALID_ENTRIES, count);
5071                 ioc->diag_trigger_event.ValidEntries = count;
5072
5073                 event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0];
5074                 mpi_event_tg = &trigger_pg2.MPIEventTriggers[0];
5075                 for (i = 0; i < count; i++) {
5076                         event_tg->EventValue = le16_to_cpu(
5077                             mpi_event_tg->MPIEventCode);
5078                         event_tg->LogEntryQualifier = le16_to_cpu(
5079                             mpi_event_tg->MPIEventCodeSpecific);
5080                         event_tg++;
5081                         mpi_event_tg++;
5082                 }
5083         }
5084         return 0;
5085 }
5086
5087 /**
5088  * _base_get_scsi_diag_triggers - get scsi diag trigger values from
5089  *                              persistent pages
5090  * @ioc : per adapter object
5091  *
5092  * Return: 0 on success; otherwise return failure status.
5093  */
5094 static int
5095 _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5096 {
5097         Mpi26DriverTriggerPage3_t trigger_pg3;
5098         struct SL_WH_SCSI_TRIGGER_T *scsi_tg;
5099         MPI26_DRIVER_SCSI_SENSE_TIGGER_ENTRY *mpi_scsi_tg;
5100         Mpi2ConfigReply_t mpi_reply;
5101         int r = 0, i = 0;
5102         u16 count = 0;
5103         u16 ioc_status;
5104
5105         r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply,
5106             &trigger_pg3);
5107         if (r)
5108                 return r;
5109
5110         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5111             MPI2_IOCSTATUS_MASK;
5112         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5113                 dinitprintk(ioc,
5114                     ioc_err(ioc,
5115                     "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n",
5116                     __func__, ioc_status));
5117                 return 0;
5118         }
5119
5120         if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) {
5121                 count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger);
5122                 count = min_t(u16, NUM_VALID_ENTRIES, count);
5123                 ioc->diag_trigger_scsi.ValidEntries = count;
5124
5125                 scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0];
5126                 mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0];
5127                 for (i = 0; i < count; i++) {
5128                         scsi_tg->ASCQ = mpi_scsi_tg->ASCQ;
5129                         scsi_tg->ASC = mpi_scsi_tg->ASC;
5130                         scsi_tg->SenseKey = mpi_scsi_tg->SenseKey;
5131
5132                         scsi_tg++;
5133                         mpi_scsi_tg++;
5134                 }
5135         }
5136         return 0;
5137 }
5138
5139 /**
5140  * _base_get_mpi_diag_triggers - get mpi diag trigger values from
5141  *                              persistent pages
5142  * @ioc : per adapter object
5143  *
5144  * Return: 0 on success; otherwise return failure status.
5145  */
5146 static int
5147 _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5148 {
5149         Mpi26DriverTriggerPage4_t trigger_pg4;
5150         struct SL_WH_MPI_TRIGGER_T *status_tg;
5151         MPI26_DRIVER_IOCSTATUS_LOGINFO_TIGGER_ENTRY *mpi_status_tg;
5152         Mpi2ConfigReply_t mpi_reply;
5153         int r = 0, i = 0;
5154         u16 count = 0;
5155         u16 ioc_status;
5156
5157         r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply,
5158             &trigger_pg4);
5159         if (r)
5160                 return r;
5161
5162         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5163             MPI2_IOCSTATUS_MASK;
5164         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5165                 dinitprintk(ioc,
5166                     ioc_err(ioc,
5167                     "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n",
5168                     __func__, ioc_status));
5169                 return 0;
5170         }
5171
5172         if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) {
5173                 count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger);
5174                 count = min_t(u16, NUM_VALID_ENTRIES, count);
5175                 ioc->diag_trigger_mpi.ValidEntries = count;
5176
5177                 status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0];
5178                 mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0];
5179
5180                 for (i = 0; i < count; i++) {
5181                         status_tg->IOCStatus = le16_to_cpu(
5182                             mpi_status_tg->IOCStatus);
5183                         status_tg->IocLogInfo = le32_to_cpu(
5184                             mpi_status_tg->LogInfo);
5185
5186                         status_tg++;
5187                         mpi_status_tg++;
5188                 }
5189         }
5190         return 0;
5191 }
5192
5193 /**
5194  * _base_get_master_diag_triggers - get master diag trigger values from
5195  *                              persistent pages
5196  * @ioc : per adapter object
5197  *
5198  * Return: nothing.
5199  */
5200 static int
5201 _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5202 {
5203         Mpi26DriverTriggerPage1_t trigger_pg1;
5204         Mpi2ConfigReply_t mpi_reply;
5205         int r;
5206         u16 ioc_status;
5207
5208         r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply,
5209             &trigger_pg1);
5210         if (r)
5211                 return r;
5212
5213         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5214             MPI2_IOCSTATUS_MASK;
5215         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5216                 dinitprintk(ioc,
5217                     ioc_err(ioc,
5218                     "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n",
5219                    __func__, ioc_status));
5220                 return 0;
5221         }
5222
5223         if (le16_to_cpu(trigger_pg1.NumMasterTrigger))
5224                 ioc->diag_trigger_master.MasterData |=
5225                     le32_to_cpu(
5226                     trigger_pg1.MasterTriggers[0].MasterTriggerFlags);
5227         return 0;
5228 }
5229
5230 /**
5231  * _base_check_for_trigger_pages_support - checks whether HBA FW supports
5232  *                                      driver trigger pages or not
5233  * @ioc : per adapter object
5234  * @trigger_flags : address where trigger page0's TriggerFlags value is copied
5235  *
5236  * Return: trigger flags mask if HBA FW supports driver trigger pages;
5237  * otherwise returns %-EFAULT if driver trigger pages are not supported by FW or
5238  * return EAGAIN if diag reset occurred due to FW fault and asking the
5239  * caller to retry the command.
5240  *
5241  */
5242 static int
5243 _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc, u32 *trigger_flags)
5244 {
5245         Mpi26DriverTriggerPage0_t trigger_pg0;
5246         int r = 0;
5247         Mpi2ConfigReply_t mpi_reply;
5248         u16 ioc_status;
5249
5250         r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply,
5251             &trigger_pg0);
5252         if (r)
5253                 return r;
5254
5255         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
5256             MPI2_IOCSTATUS_MASK;
5257         if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
5258                 return -EFAULT;
5259
5260         *trigger_flags = le16_to_cpu(trigger_pg0.TriggerFlags);
5261         return 0;
5262 }
5263
5264 /**
5265  * _base_get_diag_triggers - Retrieve diag trigger values from
5266  *                              persistent pages.
5267  * @ioc : per adapter object
5268  *
5269  * Return: zero on success; otherwise return EAGAIN error codes
5270  * asking the caller to retry.
5271  */
5272 static int
5273 _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5274 {
5275         int trigger_flags;
5276         int r;
5277
5278         /*
5279          * Default setting of master trigger.
5280          */
5281         ioc->diag_trigger_master.MasterData =
5282             (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET);
5283
5284         r = _base_check_for_trigger_pages_support(ioc, &trigger_flags);
5285         if (r) {
5286                 if (r == -EAGAIN)
5287                         return r;
5288                 /*
5289                  * Don't go for error handling when FW doesn't support
5290                  * driver trigger pages.
5291                  */
5292                 return 0;
5293         }
5294
5295         ioc->supports_trigger_pages = 1;
5296
5297         /*
5298          * Retrieve master diag trigger values from driver trigger pg1
5299          * if master trigger bit enabled in TriggerFlags.
5300          */
5301         if ((u16)trigger_flags &
5302             MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID) {
5303                 r = _base_get_master_diag_triggers(ioc);
5304                 if (r)
5305                         return r;
5306         }
5307
5308         /*
5309          * Retrieve event diag trigger values from driver trigger pg2
5310          * if event trigger bit enabled in TriggerFlags.
5311          */
5312         if ((u16)trigger_flags &
5313             MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID) {
5314                 r = _base_get_event_diag_triggers(ioc);
5315                 if (r)
5316                         return r;
5317         }
5318
5319         /*
5320          * Retrieve scsi diag trigger values from driver trigger pg3
5321          * if scsi trigger bit enabled in TriggerFlags.
5322          */
5323         if ((u16)trigger_flags &
5324             MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID) {
5325                 r = _base_get_scsi_diag_triggers(ioc);
5326                 if (r)
5327                         return r;
5328         }
5329         /*
5330          * Retrieve mpi error diag trigger values from driver trigger pg4
5331          * if loginfo trigger bit enabled in TriggerFlags.
5332          */
5333         if ((u16)trigger_flags &
5334             MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID) {
5335                 r = _base_get_mpi_diag_triggers(ioc);
5336                 if (r)
5337                         return r;
5338         }
5339         return 0;
5340 }
5341
5342 /**
5343  * _base_update_diag_trigger_pages - Update the driver trigger pages after
5344  *                      online FW update, in case updated FW supports driver
5345  *                      trigger pages.
5346  * @ioc : per adapter object
5347  *
5348  * Return: nothing.
5349  */
5350 static void
5351 _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc)
5352 {
5353
5354         if (ioc->diag_trigger_master.MasterData)
5355                 mpt3sas_config_update_driver_trigger_pg1(ioc,
5356                     &ioc->diag_trigger_master, 1);
5357
5358         if (ioc->diag_trigger_event.ValidEntries)
5359                 mpt3sas_config_update_driver_trigger_pg2(ioc,
5360                     &ioc->diag_trigger_event, 1);
5361
5362         if (ioc->diag_trigger_scsi.ValidEntries)
5363                 mpt3sas_config_update_driver_trigger_pg3(ioc,
5364                     &ioc->diag_trigger_scsi, 1);
5365
5366         if (ioc->diag_trigger_mpi.ValidEntries)
5367                 mpt3sas_config_update_driver_trigger_pg4(ioc,
5368                     &ioc->diag_trigger_mpi, 1);
5369 }
5370
5371 /**
5372  * _base_assign_fw_reported_qd  - Get FW reported QD for SAS/SATA devices.
5373  *                              - On failure set default QD values.
5374  * @ioc : per adapter object
5375  *
5376  * Returns 0 for success, non-zero for failure.
5377  *
5378  */
5379 static int _base_assign_fw_reported_qd(struct MPT3SAS_ADAPTER *ioc)
5380 {
5381         Mpi2ConfigReply_t mpi_reply;
5382         Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
5383         Mpi26PCIeIOUnitPage1_t pcie_iounit_pg1;
5384         u16 depth;
5385         int sz;
5386         int rc = 0;
5387
5388         ioc->max_wideport_qd = MPT3SAS_SAS_QUEUE_DEPTH;
5389         ioc->max_narrowport_qd = MPT3SAS_SAS_QUEUE_DEPTH;
5390         ioc->max_sata_qd = MPT3SAS_SATA_QUEUE_DEPTH;
5391         ioc->max_nvme_qd = MPT3SAS_NVME_QUEUE_DEPTH;
5392         if (!ioc->is_gen35_ioc)
5393                 goto out;
5394         /* sas iounit page 1 */
5395         sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData);
5396         sas_iounit_pg1 = kzalloc(sizeof(Mpi2SasIOUnitPage1_t), GFP_KERNEL);
5397         if (!sas_iounit_pg1) {
5398                 pr_err("%s: failure at %s:%d/%s()!\n",
5399                     ioc->name, __FILE__, __LINE__, __func__);
5400                 return rc;
5401         }
5402         rc = mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
5403             sas_iounit_pg1, sz);
5404         if (rc) {
5405                 pr_err("%s: failure at %s:%d/%s()!\n",
5406                     ioc->name, __FILE__, __LINE__, __func__);
5407                 goto out;
5408         }
5409
5410         depth = le16_to_cpu(sas_iounit_pg1->SASWideMaxQueueDepth);
5411         ioc->max_wideport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH);
5412
5413         depth = le16_to_cpu(sas_iounit_pg1->SASNarrowMaxQueueDepth);
5414         ioc->max_narrowport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH);
5415
5416         depth = sas_iounit_pg1->SATAMaxQDepth;
5417         ioc->max_sata_qd = (depth ? depth : MPT3SAS_SATA_QUEUE_DEPTH);
5418
5419         /* pcie iounit page 1 */
5420         rc = mpt3sas_config_get_pcie_iounit_pg1(ioc, &mpi_reply,
5421             &pcie_iounit_pg1, sizeof(Mpi26PCIeIOUnitPage1_t));
5422         if (rc) {
5423                 pr_err("%s: failure at %s:%d/%s()!\n",
5424                     ioc->name, __FILE__, __LINE__, __func__);
5425                 goto out;
5426         }
5427         ioc->max_nvme_qd = (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) ?
5428             (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) :
5429             MPT3SAS_NVME_QUEUE_DEPTH;
5430 out:
5431         dinitprintk(ioc, pr_err(
5432             "MaxWidePortQD: 0x%x MaxNarrowPortQD: 0x%x MaxSataQD: 0x%x MaxNvmeQD: 0x%x\n",
5433             ioc->max_wideport_qd, ioc->max_narrowport_qd,
5434             ioc->max_sata_qd, ioc->max_nvme_qd));
5435         kfree(sas_iounit_pg1);
5436         return rc;
5437 }
5438
5439 /**
5440  * _base_static_config_pages - static start of day config pages
5441  * @ioc: per adapter object
5442  */
5443 static int
5444 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
5445 {
5446         Mpi2ConfigReply_t mpi_reply;
5447         u32 iounit_pg1_flags;
5448         int tg_flags = 0;
5449         int rc;
5450         ioc->nvme_abort_timeout = 30;
5451
5452         rc = mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply,
5453             &ioc->manu_pg0);
5454         if (rc)
5455                 return rc;
5456         if (ioc->ir_firmware) {
5457                 rc = mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
5458                     &ioc->manu_pg10);
5459                 if (rc)
5460                         return rc;
5461         }
5462         /*
5463          * Ensure correct T10 PI operation if vendor left EEDPTagMode
5464          * flag unset in NVDATA.
5465          */
5466         rc = mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply,
5467             &ioc->manu_pg11);
5468         if (rc)
5469                 return rc;
5470         if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
5471                 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
5472                     ioc->name);
5473                 ioc->manu_pg11.EEDPTagMode &= ~0x3;
5474                 ioc->manu_pg11.EEDPTagMode |= 0x1;
5475                 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
5476                     &ioc->manu_pg11);
5477         }
5478         if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
5479                 ioc->tm_custom_handling = 1;
5480         else {
5481                 ioc->tm_custom_handling = 0;
5482                 if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
5483                         ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
5484                 else if (ioc->manu_pg11.NVMeAbortTO >
5485                                         NVME_TASK_ABORT_MAX_TIMEOUT)
5486                         ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
5487                 else
5488                         ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
5489         }
5490         ioc->time_sync_interval =
5491             ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK;
5492         if (ioc->time_sync_interval) {
5493                 if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK)
5494                         ioc->time_sync_interval =
5495                             ioc->time_sync_interval * SECONDS_PER_HOUR;
5496                 else
5497                         ioc->time_sync_interval =
5498                             ioc->time_sync_interval * SECONDS_PER_MIN;
5499                 dinitprintk(ioc, ioc_info(ioc,
5500                     "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n",
5501                     ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval &
5502                     MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute"));
5503         } else {
5504                 if (ioc->is_gen35_ioc)
5505                         ioc_warn(ioc,
5506                             "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n");
5507         }
5508         rc = _base_assign_fw_reported_qd(ioc);
5509         if (rc)
5510                 return rc;
5511         rc = mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
5512         if (rc)
5513                 return rc;
5514         rc = mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
5515         if (rc)
5516                 return rc;
5517         rc = mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
5518         if (rc)
5519                 return rc;
5520         rc = mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
5521         if (rc)
5522                 return rc;
5523         rc = mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5524         if (rc)
5525                 return rc;
5526         rc = mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
5527         if (rc)
5528                 return rc;
5529         _base_display_ioc_capabilities(ioc);
5530
5531         /*
5532          * Enable task_set_full handling in iounit_pg1 when the
5533          * facts capabilities indicate that its supported.
5534          */
5535         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
5536         if ((ioc->facts.IOCCapabilities &
5537             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
5538                 iounit_pg1_flags &=
5539                     ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5540         else
5541                 iounit_pg1_flags |=
5542                     MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
5543         ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
5544         rc = mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
5545         if (rc)
5546                 return rc;
5547
5548         if (ioc->iounit_pg8.NumSensors)
5549                 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
5550         if (ioc->is_aero_ioc) {
5551                 rc = _base_update_ioc_page1_inlinewith_perf_mode(ioc);
5552                 if (rc)
5553                         return rc;
5554         }
5555         if (ioc->is_gen35_ioc) {
5556                 if (ioc->is_driver_loading) {
5557                         rc = _base_get_diag_triggers(ioc);
5558                         if (rc)
5559                                 return rc;
5560                 } else {
5561                         /*
5562                          * In case of online HBA FW update operation,
5563                          * check whether updated FW supports the driver trigger
5564                          * pages or not.
5565                          * - If previous FW has not supported driver trigger
5566                          *   pages and newer FW supports them then update these
5567                          *   pages with current diag trigger values.
5568                          * - If previous FW has supported driver trigger pages
5569                          *   and new FW doesn't support them then disable
5570                          *   support_trigger_pages flag.
5571                          */
5572                         _base_check_for_trigger_pages_support(ioc, &tg_flags);
5573                         if (!ioc->supports_trigger_pages && tg_flags != -EFAULT)
5574                                 _base_update_diag_trigger_pages(ioc);
5575                         else if (ioc->supports_trigger_pages &&
5576                             tg_flags == -EFAULT)
5577                                 ioc->supports_trigger_pages = 0;
5578                 }
5579         }
5580         return 0;
5581 }
5582
5583 /**
5584  * mpt3sas_free_enclosure_list - release memory
5585  * @ioc: per adapter object
5586  *
5587  * Free memory allocated during enclosure add.
5588  */
5589 void
5590 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc)
5591 {
5592         struct _enclosure_node *enclosure_dev, *enclosure_dev_next;
5593
5594         /* Free enclosure list */
5595         list_for_each_entry_safe(enclosure_dev,
5596                         enclosure_dev_next, &ioc->enclosure_list, list) {
5597                 list_del(&enclosure_dev->list);
5598                 kfree(enclosure_dev);
5599         }
5600 }
5601
5602 /**
5603  * _base_release_memory_pools - release memory
5604  * @ioc: per adapter object
5605  *
5606  * Free memory allocated from _base_allocate_memory_pools.
5607  */
5608 static void
5609 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
5610 {
5611         int i = 0;
5612         int j = 0;
5613         int dma_alloc_count = 0;
5614         struct chain_tracker *ct;
5615         int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
5616
5617         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5618
5619         if (ioc->request) {
5620                 dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
5621                     ioc->request,  ioc->request_dma);
5622                 dexitprintk(ioc,
5623                             ioc_info(ioc, "request_pool(0x%p): free\n",
5624                                      ioc->request));
5625                 ioc->request = NULL;
5626         }
5627
5628         if (ioc->sense) {
5629                 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
5630                 dma_pool_destroy(ioc->sense_dma_pool);
5631                 dexitprintk(ioc,
5632                             ioc_info(ioc, "sense_pool(0x%p): free\n",
5633                                      ioc->sense));
5634                 ioc->sense = NULL;
5635         }
5636
5637         if (ioc->reply) {
5638                 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
5639                 dma_pool_destroy(ioc->reply_dma_pool);
5640                 dexitprintk(ioc,
5641                             ioc_info(ioc, "reply_pool(0x%p): free\n",
5642                                      ioc->reply));
5643                 ioc->reply = NULL;
5644         }
5645
5646         if (ioc->reply_free) {
5647                 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
5648                     ioc->reply_free_dma);
5649                 dma_pool_destroy(ioc->reply_free_dma_pool);
5650                 dexitprintk(ioc,
5651                             ioc_info(ioc, "reply_free_pool(0x%p): free\n",
5652                                      ioc->reply_free));
5653                 ioc->reply_free = NULL;
5654         }
5655
5656         if (ioc->reply_post) {
5657                 dma_alloc_count = DIV_ROUND_UP(count,
5658                                 RDPQ_MAX_INDEX_IN_ONE_CHUNK);
5659                 for (i = 0; i < count; i++) {
5660                         if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
5661                             && dma_alloc_count) {
5662                                 if (ioc->reply_post[i].reply_post_free) {
5663                                         dma_pool_free(
5664                                             ioc->reply_post_free_dma_pool,
5665                                             ioc->reply_post[i].reply_post_free,
5666                                         ioc->reply_post[i].reply_post_free_dma);
5667                                         dexitprintk(ioc, ioc_info(ioc,
5668                                            "reply_post_free_pool(0x%p): free\n",
5669                                            ioc->reply_post[i].reply_post_free));
5670                                         ioc->reply_post[i].reply_post_free =
5671                                                                         NULL;
5672                                 }
5673                                 --dma_alloc_count;
5674                         }
5675                 }
5676                 dma_pool_destroy(ioc->reply_post_free_dma_pool);
5677                 if (ioc->reply_post_free_array &&
5678                         ioc->rdpq_array_enable) {
5679                         dma_pool_free(ioc->reply_post_free_array_dma_pool,
5680                             ioc->reply_post_free_array,
5681                             ioc->reply_post_free_array_dma);
5682                         ioc->reply_post_free_array = NULL;
5683                 }
5684                 dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
5685                 kfree(ioc->reply_post);
5686         }
5687
5688         if (ioc->pcie_sgl_dma_pool) {
5689                 for (i = 0; i < ioc->scsiio_depth; i++) {
5690                         dma_pool_free(ioc->pcie_sgl_dma_pool,
5691                                         ioc->pcie_sg_lookup[i].pcie_sgl,
5692                                         ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5693                         ioc->pcie_sg_lookup[i].pcie_sgl = NULL;
5694                 }
5695                 dma_pool_destroy(ioc->pcie_sgl_dma_pool);
5696         }
5697         if (ioc->config_page) {
5698                 dexitprintk(ioc,
5699                             ioc_info(ioc, "config_page(0x%p): free\n",
5700                                      ioc->config_page));
5701                 dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
5702                     ioc->config_page, ioc->config_page_dma);
5703         }
5704
5705         kfree(ioc->hpr_lookup);
5706         ioc->hpr_lookup = NULL;
5707         kfree(ioc->internal_lookup);
5708         ioc->internal_lookup = NULL;
5709         if (ioc->chain_lookup) {
5710                 for (i = 0; i < ioc->scsiio_depth; i++) {
5711                         for (j = ioc->chains_per_prp_buffer;
5712                             j < ioc->chains_needed_per_io; j++) {
5713                                 ct = &ioc->chain_lookup[i].chains_per_smid[j];
5714                                 if (ct && ct->chain_buffer)
5715                                         dma_pool_free(ioc->chain_dma_pool,
5716                                                 ct->chain_buffer,
5717                                                 ct->chain_buffer_dma);
5718                         }
5719                         kfree(ioc->chain_lookup[i].chains_per_smid);
5720                 }
5721                 dma_pool_destroy(ioc->chain_dma_pool);
5722                 kfree(ioc->chain_lookup);
5723                 ioc->chain_lookup = NULL;
5724         }
5725
5726         kfree(ioc->io_queue_num);
5727         ioc->io_queue_num = NULL;
5728 }
5729
5730 /**
5731  * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
5732  *      having same upper 32bits in their base memory address.
5733  * @reply_pool_start_address: Base address of a reply queue set
5734  * @pool_sz: Size of single Reply Descriptor Post Queues pool size
5735  *
5736  * Return: 1 if reply queues in a set have a same upper 32bits in their base
5737  * memory address, else 0.
5738  */
5739
5740 static int
5741 mpt3sas_check_same_4gb_region(dma_addr_t start_address, u32 pool_sz)
5742 {
5743         dma_addr_t end_address;
5744
5745         end_address = start_address + pool_sz - 1;
5746
5747         if (upper_32_bits(start_address) == upper_32_bits(end_address))
5748                 return 1;
5749         else
5750                 return 0;
5751 }
5752
5753 /**
5754  * _base_reduce_hba_queue_depth- Retry with reduced queue depth
5755  * @ioc: Adapter object
5756  *
5757  * Return: 0 for success, non-zero for failure.
5758  **/
5759 static inline int
5760 _base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc)
5761 {
5762         int reduce_sz = 64;
5763
5764         if ((ioc->hba_queue_depth - reduce_sz) >
5765             (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) {
5766                 ioc->hba_queue_depth -= reduce_sz;
5767                 return 0;
5768         } else
5769                 return -ENOMEM;
5770 }
5771
5772 /**
5773  * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory
5774  *                      for pcie sgl pools.
5775  * @ioc: Adapter object
5776  * @sz: DMA Pool size
5777  *
5778  * Return: 0 for success, non-zero for failure.
5779  */
5780
5781 static int
5782 _base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5783 {
5784         int i = 0, j = 0;
5785         struct chain_tracker *ct;
5786
5787         ioc->pcie_sgl_dma_pool =
5788             dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz,
5789             ioc->page_size, 0);
5790         if (!ioc->pcie_sgl_dma_pool) {
5791                 ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n");
5792                 return -ENOMEM;
5793         }
5794
5795         ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
5796         ioc->chains_per_prp_buffer =
5797             min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io);
5798         for (i = 0; i < ioc->scsiio_depth; i++) {
5799                 ioc->pcie_sg_lookup[i].pcie_sgl =
5800                     dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL,
5801                     &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5802                 if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
5803                         ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
5804                         return -EAGAIN;
5805                 }
5806
5807                 if (!mpt3sas_check_same_4gb_region(
5808                     ioc->pcie_sg_lookup[i].pcie_sgl_dma, sz)) {
5809                         ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n",
5810                             ioc->pcie_sg_lookup[i].pcie_sgl,
5811                             (unsigned long long)
5812                             ioc->pcie_sg_lookup[i].pcie_sgl_dma);
5813                         ioc->use_32bit_dma = true;
5814                         return -EAGAIN;
5815                 }
5816
5817                 for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
5818                         ct = &ioc->chain_lookup[i].chains_per_smid[j];
5819                         ct->chain_buffer =
5820                             ioc->pcie_sg_lookup[i].pcie_sgl +
5821                             (j * ioc->chain_segment_sz);
5822                         ct->chain_buffer_dma =
5823                             ioc->pcie_sg_lookup[i].pcie_sgl_dma +
5824                             (j * ioc->chain_segment_sz);
5825                 }
5826         }
5827         dinitprintk(ioc, ioc_info(ioc,
5828             "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
5829             ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
5830         dinitprintk(ioc, ioc_info(ioc,
5831             "Number of chains can fit in a PRP page(%d)\n",
5832             ioc->chains_per_prp_buffer));
5833         return 0;
5834 }
5835
5836 /**
5837  * _base_allocate_chain_dma_pool - Allocating DMA'able memory
5838  *                      for chain dma pool.
5839  * @ioc: Adapter object
5840  * @sz: DMA Pool size
5841  *
5842  * Return: 0 for success, non-zero for failure.
5843  */
5844 static int
5845 _base_allocate_chain_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5846 {
5847         int i = 0, j = 0;
5848         struct chain_tracker *ctr;
5849
5850         ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
5851             ioc->chain_segment_sz, 16, 0);
5852         if (!ioc->chain_dma_pool)
5853                 return -ENOMEM;
5854
5855         for (i = 0; i < ioc->scsiio_depth; i++) {
5856                 for (j = ioc->chains_per_prp_buffer;
5857                     j < ioc->chains_needed_per_io; j++) {
5858                         ctr = &ioc->chain_lookup[i].chains_per_smid[j];
5859                         ctr->chain_buffer = dma_pool_alloc(ioc->chain_dma_pool,
5860                             GFP_KERNEL, &ctr->chain_buffer_dma);
5861                         if (!ctr->chain_buffer)
5862                                 return -EAGAIN;
5863                         if (!mpt3sas_check_same_4gb_region(
5864                             ctr->chain_buffer_dma, ioc->chain_segment_sz)) {
5865                                 ioc_err(ioc,
5866                                     "Chain buffers are not in same 4G !!! Chain buff (0x%p) dma = (0x%llx)\n",
5867                                     ctr->chain_buffer,
5868                                     (unsigned long long)ctr->chain_buffer_dma);
5869                                 ioc->use_32bit_dma = true;
5870                                 return -EAGAIN;
5871                         }
5872                 }
5873         }
5874         dinitprintk(ioc, ioc_info(ioc,
5875             "chain_lookup depth (%d), frame_size(%d), pool_size(%d kB)\n",
5876             ioc->scsiio_depth, ioc->chain_segment_sz, ((ioc->scsiio_depth *
5877             (ioc->chains_needed_per_io - ioc->chains_per_prp_buffer) *
5878             ioc->chain_segment_sz))/1024));
5879         return 0;
5880 }
5881
5882 /**
5883  * _base_allocate_sense_dma_pool - Allocating DMA'able memory
5884  *                      for sense dma pool.
5885  * @ioc: Adapter object
5886  * @sz: DMA Pool size
5887  * Return: 0 for success, non-zero for failure.
5888  */
5889 static int
5890 _base_allocate_sense_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5891 {
5892         ioc->sense_dma_pool =
5893             dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4, 0);
5894         if (!ioc->sense_dma_pool)
5895                 return -ENOMEM;
5896         ioc->sense = dma_pool_alloc(ioc->sense_dma_pool,
5897             GFP_KERNEL, &ioc->sense_dma);
5898         if (!ioc->sense)
5899                 return -EAGAIN;
5900         if (!mpt3sas_check_same_4gb_region(ioc->sense_dma, sz)) {
5901                 dinitprintk(ioc, pr_err(
5902                     "Bad Sense Pool! sense (0x%p) sense_dma = (0x%llx)\n",
5903                     ioc->sense, (unsigned long long) ioc->sense_dma));
5904                 ioc->use_32bit_dma = true;
5905                 return -EAGAIN;
5906         }
5907         ioc_info(ioc,
5908             "sense pool(0x%p) - dma(0x%llx): depth(%d), element_size(%d), pool_size (%d kB)\n",
5909             ioc->sense, (unsigned long long)ioc->sense_dma,
5910             ioc->scsiio_depth, SCSI_SENSE_BUFFERSIZE, sz/1024);
5911         return 0;
5912 }
5913
5914 /**
5915  * _base_allocate_reply_pool - Allocating DMA'able memory
5916  *                      for reply pool.
5917  * @ioc: Adapter object
5918  * @sz: DMA Pool size
5919  * Return: 0 for success, non-zero for failure.
5920  */
5921 static int
5922 _base_allocate_reply_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5923 {
5924         /* reply pool, 4 byte align */
5925         ioc->reply_dma_pool = dma_pool_create("reply pool",
5926             &ioc->pdev->dev, sz, 4, 0);
5927         if (!ioc->reply_dma_pool)
5928                 return -ENOMEM;
5929         ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
5930             &ioc->reply_dma);
5931         if (!ioc->reply)
5932                 return -EAGAIN;
5933         if (!mpt3sas_check_same_4gb_region(ioc->reply_dma, sz)) {
5934                 dinitprintk(ioc, pr_err(
5935                     "Bad Reply Pool! Reply (0x%p) Reply dma = (0x%llx)\n",
5936                     ioc->reply, (unsigned long long) ioc->reply_dma));
5937                 ioc->use_32bit_dma = true;
5938                 return -EAGAIN;
5939         }
5940         ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
5941         ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
5942         ioc_info(ioc,
5943             "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n",
5944             ioc->reply, (unsigned long long)ioc->reply_dma,
5945             ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024);
5946         return 0;
5947 }
5948
5949 /**
5950  * _base_allocate_reply_free_dma_pool - Allocating DMA'able memory
5951  *                      for reply free dma pool.
5952  * @ioc: Adapter object
5953  * @sz: DMA Pool size
5954  * Return: 0 for success, non-zero for failure.
5955  */
5956 static int
5957 _base_allocate_reply_free_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
5958 {
5959         /* reply free queue, 16 byte align */
5960         ioc->reply_free_dma_pool = dma_pool_create(
5961             "reply_free pool", &ioc->pdev->dev, sz, 16, 0);
5962         if (!ioc->reply_free_dma_pool)
5963                 return -ENOMEM;
5964         ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool,
5965             GFP_KERNEL, &ioc->reply_free_dma);
5966         if (!ioc->reply_free)
5967                 return -EAGAIN;
5968         if (!mpt3sas_check_same_4gb_region(ioc->reply_free_dma, sz)) {
5969                 dinitprintk(ioc,
5970                     pr_err("Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n",
5971                     ioc->reply_free, (unsigned long long) ioc->reply_free_dma));
5972                 ioc->use_32bit_dma = true;
5973                 return -EAGAIN;
5974         }
5975         memset(ioc->reply_free, 0, sz);
5976         dinitprintk(ioc, ioc_info(ioc,
5977             "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
5978             ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
5979         dinitprintk(ioc, ioc_info(ioc,
5980             "reply_free_dma (0x%llx)\n",
5981             (unsigned long long)ioc->reply_free_dma));
5982         return 0;
5983 }
5984
5985 /**
5986  * _base_allocate_reply_post_free_array - Allocating DMA'able memory
5987  *                      for reply post free array.
5988  * @ioc: Adapter object
5989  * @reply_post_free_array_sz: DMA Pool size
5990  * Return: 0 for success, non-zero for failure.
5991  */
5992
5993 static int
5994 _base_allocate_reply_post_free_array(struct MPT3SAS_ADAPTER *ioc,
5995         u32 reply_post_free_array_sz)
5996 {
5997         ioc->reply_post_free_array_dma_pool =
5998             dma_pool_create("reply_post_free_array pool",
5999             &ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
6000         if (!ioc->reply_post_free_array_dma_pool)
6001                 return -ENOMEM;
6002         ioc->reply_post_free_array =
6003             dma_pool_alloc(ioc->reply_post_free_array_dma_pool,
6004             GFP_KERNEL, &ioc->reply_post_free_array_dma);
6005         if (!ioc->reply_post_free_array)
6006                 return -EAGAIN;
6007         if (!mpt3sas_check_same_4gb_region(ioc->reply_post_free_array_dma,
6008             reply_post_free_array_sz)) {
6009                 dinitprintk(ioc, pr_err(
6010                     "Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n",
6011                     ioc->reply_free,
6012                     (unsigned long long) ioc->reply_free_dma));
6013                 ioc->use_32bit_dma = true;
6014                 return -EAGAIN;
6015         }
6016         return 0;
6017 }
6018 /**
6019  * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
6020  *                     for reply queues.
6021  * @ioc: per adapter object
6022  * @sz: DMA Pool size
6023  * Return: 0 for success, non-zero for failure.
6024  */
6025 static int
6026 base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
6027 {
6028         int i = 0;
6029         u32 dma_alloc_count = 0;
6030         int reply_post_free_sz = ioc->reply_post_queue_depth *
6031                 sizeof(Mpi2DefaultReplyDescriptor_t);
6032         int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
6033
6034         ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
6035                         GFP_KERNEL);
6036         if (!ioc->reply_post)
6037                 return -ENOMEM;
6038         /*
6039          *  For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
6040          *  VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
6041          *  be within 4GB boundary i.e reply queues in a set must have same
6042          *  upper 32-bits in their memory address. so here driver is allocating
6043          *  the DMA'able memory for reply queues according.
6044          *  Driver uses limitation of
6045          *  VENTURA_SERIES to manage INVADER_SERIES as well.
6046          */
6047         dma_alloc_count = DIV_ROUND_UP(count,
6048                                 RDPQ_MAX_INDEX_IN_ONE_CHUNK);
6049         ioc->reply_post_free_dma_pool =
6050                 dma_pool_create("reply_post_free pool",
6051                     &ioc->pdev->dev, sz, 16, 0);
6052         if (!ioc->reply_post_free_dma_pool)
6053                 return -ENOMEM;
6054         for (i = 0; i < count; i++) {
6055                 if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
6056                         ioc->reply_post[i].reply_post_free =
6057                             dma_pool_zalloc(ioc->reply_post_free_dma_pool,
6058                                 GFP_KERNEL,
6059                                 &ioc->reply_post[i].reply_post_free_dma);
6060                         if (!ioc->reply_post[i].reply_post_free)
6061                                 return -ENOMEM;
6062                         /*
6063                          * Each set of RDPQ pool must satisfy 4gb boundary
6064                          * restriction.
6065                          * 1) Check if allocated resources for RDPQ pool are in
6066                          *      the same 4GB range.
6067                          * 2) If #1 is true, continue with 64 bit DMA.
6068                          * 3) If #1 is false, return 1. which means free all the
6069                          * resources and set DMA mask to 32 and allocate.
6070                          */
6071                         if (!mpt3sas_check_same_4gb_region(
6072                                 ioc->reply_post[i].reply_post_free_dma, sz)) {
6073                                 dinitprintk(ioc,
6074                                     ioc_err(ioc, "bad Replypost free pool(0x%p)"
6075                                     "reply_post_free_dma = (0x%llx)\n",
6076                                     ioc->reply_post[i].reply_post_free,
6077                                     (unsigned long long)
6078                                     ioc->reply_post[i].reply_post_free_dma));
6079                                 return -EAGAIN;
6080                         }
6081                         dma_alloc_count--;
6082
6083                 } else {
6084                         ioc->reply_post[i].reply_post_free =
6085                             (Mpi2ReplyDescriptorsUnion_t *)
6086                             ((long)ioc->reply_post[i-1].reply_post_free
6087                             + reply_post_free_sz);
6088                         ioc->reply_post[i].reply_post_free_dma =
6089                             (dma_addr_t)
6090                             (ioc->reply_post[i-1].reply_post_free_dma +
6091                             reply_post_free_sz);
6092                 }
6093         }
6094         return 0;
6095 }
6096
6097 /**
6098  * _base_allocate_memory_pools - allocate start of day memory pools
6099  * @ioc: per adapter object
6100  *
6101  * Return: 0 success, anything else error.
6102  */
6103 static int
6104 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
6105 {
6106         struct mpt3sas_facts *facts;
6107         u16 max_sge_elements;
6108         u16 chains_needed_per_io;
6109         u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
6110         u32 retry_sz;
6111         u32 rdpq_sz = 0, sense_sz = 0;
6112         u16 max_request_credit, nvme_blocks_needed;
6113         unsigned short sg_tablesize;
6114         u16 sge_size;
6115         int i;
6116         int ret = 0, rc = 0;
6117
6118         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6119
6120
6121         retry_sz = 0;
6122         facts = &ioc->facts;
6123
6124         /* command line tunables for max sgl entries */
6125         if (max_sgl_entries != -1)
6126                 sg_tablesize = max_sgl_entries;
6127         else {
6128                 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
6129                         sg_tablesize = MPT2SAS_SG_DEPTH;
6130                 else
6131                         sg_tablesize = MPT3SAS_SG_DEPTH;
6132         }
6133
6134         /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
6135         if (reset_devices)
6136                 sg_tablesize = min_t(unsigned short, sg_tablesize,
6137                    MPT_KDUMP_MIN_PHYS_SEGMENTS);
6138
6139         if (ioc->is_mcpu_endpoint)
6140                 ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
6141         else {
6142                 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
6143                         sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
6144                 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
6145                         sg_tablesize = min_t(unsigned short, sg_tablesize,
6146                                         SG_MAX_SEGMENTS);
6147                         ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
6148                                  sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
6149                 }
6150                 ioc->shost->sg_tablesize = sg_tablesize;
6151         }
6152
6153         ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
6154                 (facts->RequestCredit / 4));
6155         if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
6156                 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
6157                                 INTERNAL_SCSIIO_CMDS_COUNT)) {
6158                         ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
6159                                 facts->RequestCredit);
6160                         return -ENOMEM;
6161                 }
6162                 ioc->internal_depth = 10;
6163         }
6164
6165         ioc->hi_priority_depth = ioc->internal_depth - (5);
6166         /* command line tunables  for max controller queue depth */
6167         if (max_queue_depth != -1 && max_queue_depth != 0) {
6168                 max_request_credit = min_t(u16, max_queue_depth +
6169                         ioc->internal_depth, facts->RequestCredit);
6170                 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
6171                         max_request_credit =  MAX_HBA_QUEUE_DEPTH;
6172         } else if (reset_devices)
6173                 max_request_credit = min_t(u16, facts->RequestCredit,
6174                     (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
6175         else
6176                 max_request_credit = min_t(u16, facts->RequestCredit,
6177                     MAX_HBA_QUEUE_DEPTH);
6178
6179         /* Firmware maintains additional facts->HighPriorityCredit number of
6180          * credits for HiPriprity Request messages, so hba queue depth will be
6181          * sum of max_request_credit and high priority queue depth.
6182          */
6183         ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
6184
6185         /* request frame size */
6186         ioc->request_sz = facts->IOCRequestFrameSize * 4;
6187
6188         /* reply frame size */
6189         ioc->reply_sz = facts->ReplyFrameSize * 4;
6190
6191         /* chain segment size */
6192         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6193                 if (facts->IOCMaxChainSegmentSize)
6194                         ioc->chain_segment_sz =
6195                                         facts->IOCMaxChainSegmentSize *
6196                                         MAX_CHAIN_ELEMT_SZ;
6197                 else
6198                 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
6199                         ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
6200                                                     MAX_CHAIN_ELEMT_SZ;
6201         } else
6202                 ioc->chain_segment_sz = ioc->request_sz;
6203
6204         /* calculate the max scatter element size */
6205         sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
6206
6207  retry_allocation:
6208         total_sz = 0;
6209         /* calculate number of sg elements left over in the 1st frame */
6210         max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
6211             sizeof(Mpi2SGEIOUnion_t)) + sge_size);
6212         ioc->max_sges_in_main_message = max_sge_elements/sge_size;
6213
6214         /* now do the same for a chain buffer */
6215         max_sge_elements = ioc->chain_segment_sz - sge_size;
6216         ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
6217
6218         /*
6219          *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
6220          */
6221         chains_needed_per_io = ((ioc->shost->sg_tablesize -
6222            ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
6223             + 1;
6224         if (chains_needed_per_io > facts->MaxChainDepth) {
6225                 chains_needed_per_io = facts->MaxChainDepth;
6226                 ioc->shost->sg_tablesize = min_t(u16,
6227                 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
6228                 * chains_needed_per_io), ioc->shost->sg_tablesize);
6229         }
6230         ioc->chains_needed_per_io = chains_needed_per_io;
6231
6232         /* reply free queue sizing - taking into account for 64 FW events */
6233         ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
6234
6235         /* mCPU manage single counters for simplicity */
6236         if (ioc->is_mcpu_endpoint)
6237                 ioc->reply_post_queue_depth = ioc->reply_free_queue_depth;
6238         else {
6239                 /* calculate reply descriptor post queue depth */
6240                 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
6241                         ioc->reply_free_queue_depth +  1;
6242                 /* align the reply post queue on the next 16 count boundary */
6243                 if (ioc->reply_post_queue_depth % 16)
6244                         ioc->reply_post_queue_depth += 16 -
6245                                 (ioc->reply_post_queue_depth % 16);
6246         }
6247
6248         if (ioc->reply_post_queue_depth >
6249             facts->MaxReplyDescriptorPostQueueDepth) {
6250                 ioc->reply_post_queue_depth =
6251                                 facts->MaxReplyDescriptorPostQueueDepth -
6252                     (facts->MaxReplyDescriptorPostQueueDepth % 16);
6253                 ioc->hba_queue_depth =
6254                                 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
6255                 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
6256         }
6257
6258         ioc_info(ioc,
6259             "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
6260             "sge_per_io(%d), chains_per_io(%d)\n",
6261             ioc->max_sges_in_main_message,
6262             ioc->max_sges_in_chain_message,
6263             ioc->shost->sg_tablesize,
6264             ioc->chains_needed_per_io);
6265
6266         /* reply post queue, 16 byte align */
6267         reply_post_free_sz = ioc->reply_post_queue_depth *
6268             sizeof(Mpi2DefaultReplyDescriptor_t);
6269         rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
6270         if ((_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
6271             || (ioc->reply_queue_count < RDPQ_MAX_INDEX_IN_ONE_CHUNK))
6272                 rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
6273         ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
6274         if (ret == -EAGAIN) {
6275                 /*
6276                  * Free allocated bad RDPQ memory pools.
6277                  * Change dma coherent mask to 32 bit and reallocate RDPQ
6278                  */
6279                 _base_release_memory_pools(ioc);
6280                 ioc->use_32bit_dma = true;
6281                 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
6282                         ioc_err(ioc,
6283                             "32 DMA mask failed %s\n", pci_name(ioc->pdev));
6284                         return -ENODEV;
6285                 }
6286                 if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
6287                         return -ENOMEM;
6288         } else if (ret == -ENOMEM)
6289                 return -ENOMEM;
6290         total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
6291             DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
6292         ioc->scsiio_depth = ioc->hba_queue_depth -
6293             ioc->hi_priority_depth - ioc->internal_depth;
6294
6295         /* set the scsi host can_queue depth
6296          * with some internal commands that could be outstanding
6297          */
6298         ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
6299         dinitprintk(ioc,
6300                     ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
6301                              ioc->shost->can_queue));
6302
6303         /* contiguous pool for request and chains, 16 byte align, one extra "
6304          * "frame for smid=0
6305          */
6306         ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
6307         sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
6308
6309         /* hi-priority queue */
6310         sz += (ioc->hi_priority_depth * ioc->request_sz);
6311
6312         /* internal queue */
6313         sz += (ioc->internal_depth * ioc->request_sz);
6314
6315         ioc->request_dma_sz = sz;
6316         ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
6317                         &ioc->request_dma, GFP_KERNEL);
6318         if (!ioc->request) {
6319                 ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
6320                         ioc->hba_queue_depth, ioc->chains_needed_per_io,
6321                         ioc->request_sz, sz / 1024);
6322                 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
6323                         goto out;
6324                 retry_sz = 64;
6325                 ioc->hba_queue_depth -= retry_sz;
6326                 _base_release_memory_pools(ioc);
6327                 goto retry_allocation;
6328         }
6329
6330         if (retry_sz)
6331                 ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
6332                         ioc->hba_queue_depth, ioc->chains_needed_per_io,
6333                         ioc->request_sz, sz / 1024);
6334
6335         /* hi-priority queue */
6336         ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
6337             ioc->request_sz);
6338         ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
6339             ioc->request_sz);
6340
6341         /* internal queue */
6342         ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
6343             ioc->request_sz);
6344         ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
6345             ioc->request_sz);
6346
6347         ioc_info(ioc,
6348             "request pool(0x%p) - dma(0x%llx): "
6349             "depth(%d), frame_size(%d), pool_size(%d kB)\n",
6350             ioc->request, (unsigned long long) ioc->request_dma,
6351             ioc->hba_queue_depth, ioc->request_sz,
6352             (ioc->hba_queue_depth * ioc->request_sz) / 1024);
6353
6354         total_sz += sz;
6355
6356         dinitprintk(ioc,
6357                     ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
6358                              ioc->request, ioc->scsiio_depth));
6359
6360         ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
6361         sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
6362         ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
6363         if (!ioc->chain_lookup) {
6364                 ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
6365                 goto out;
6366         }
6367
6368         sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker);
6369         for (i = 0; i < ioc->scsiio_depth; i++) {
6370                 ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
6371                 if (!ioc->chain_lookup[i].chains_per_smid) {
6372                         ioc_err(ioc, "chain_lookup: kzalloc failed\n");
6373                         goto out;
6374                 }
6375         }
6376
6377         /* initialize hi-priority queue smid's */
6378         ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
6379             sizeof(struct request_tracker), GFP_KERNEL);
6380         if (!ioc->hpr_lookup) {
6381                 ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
6382                 goto out;
6383         }
6384         ioc->hi_priority_smid = ioc->scsiio_depth + 1;
6385         dinitprintk(ioc,
6386                     ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
6387                              ioc->hi_priority,
6388                              ioc->hi_priority_depth, ioc->hi_priority_smid));
6389
6390         /* initialize internal queue smid's */
6391         ioc->internal_lookup = kcalloc(ioc->internal_depth,
6392             sizeof(struct request_tracker), GFP_KERNEL);
6393         if (!ioc->internal_lookup) {
6394                 ioc_err(ioc, "internal_lookup: kcalloc failed\n");
6395                 goto out;
6396         }
6397         ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
6398         dinitprintk(ioc,
6399                     ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
6400                              ioc->internal,
6401                              ioc->internal_depth, ioc->internal_smid));
6402
6403         ioc->io_queue_num = kcalloc(ioc->scsiio_depth,
6404             sizeof(u16), GFP_KERNEL);
6405         if (!ioc->io_queue_num)
6406                 goto out;
6407         /*
6408          * The number of NVMe page sized blocks needed is:
6409          *     (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
6410          * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
6411          * that is placed in the main message frame.  8 is the size of each PRP
6412          * entry or PRP list pointer entry.  8 is subtracted from page_size
6413          * because of the PRP list pointer entry at the end of a page, so this
6414          * is not counted as a PRP entry.  The 1 added page is a round up.
6415          *
6416          * To avoid allocation failures due to the amount of memory that could
6417          * be required for NVMe PRP's, only each set of NVMe blocks will be
6418          * contiguous, so a new set is allocated for each possible I/O.
6419          */
6420
6421         ioc->chains_per_prp_buffer = 0;
6422         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
6423                 nvme_blocks_needed =
6424                         (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
6425                 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
6426                 nvme_blocks_needed++;
6427
6428                 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
6429                 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
6430                 if (!ioc->pcie_sg_lookup) {
6431                         ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
6432                         goto out;
6433                 }
6434                 sz = nvme_blocks_needed * ioc->page_size;
6435                 rc = _base_allocate_pcie_sgl_pool(ioc, sz);
6436                 if (rc == -ENOMEM)
6437                         return -ENOMEM;
6438                 else if (rc == -EAGAIN)
6439                         goto try_32bit_dma;
6440                 total_sz += sz * ioc->scsiio_depth;
6441         }
6442
6443         rc = _base_allocate_chain_dma_pool(ioc, ioc->chain_segment_sz);
6444         if (rc == -ENOMEM)
6445                 return -ENOMEM;
6446         else if (rc == -EAGAIN)
6447                 goto try_32bit_dma;
6448         total_sz += ioc->chain_segment_sz * ((ioc->chains_needed_per_io -
6449                 ioc->chains_per_prp_buffer) * ioc->scsiio_depth);
6450         dinitprintk(ioc,
6451             ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
6452             ioc->chain_depth, ioc->chain_segment_sz,
6453             (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
6454         /* sense buffers, 4 byte align */
6455         sense_sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
6456         rc = _base_allocate_sense_dma_pool(ioc, sense_sz);
6457         if (rc  == -ENOMEM)
6458                 return -ENOMEM;
6459         else if (rc == -EAGAIN)
6460                 goto try_32bit_dma;
6461         total_sz += sense_sz;
6462         ioc_info(ioc,
6463             "sense pool(0x%p)- dma(0x%llx): depth(%d),"
6464             "element_size(%d), pool_size(%d kB)\n",
6465             ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth,
6466             SCSI_SENSE_BUFFERSIZE, sz / 1024);
6467         /* reply pool, 4 byte align */
6468         sz = ioc->reply_free_queue_depth * ioc->reply_sz;
6469         rc = _base_allocate_reply_pool(ioc, sz);
6470         if (rc == -ENOMEM)
6471                 return -ENOMEM;
6472         else if (rc == -EAGAIN)
6473                 goto try_32bit_dma;
6474         total_sz += sz;
6475
6476         /* reply free queue, 16 byte align */
6477         sz = ioc->reply_free_queue_depth * 4;
6478         rc = _base_allocate_reply_free_dma_pool(ioc, sz);
6479         if (rc  == -ENOMEM)
6480                 return -ENOMEM;
6481         else if (rc == -EAGAIN)
6482                 goto try_32bit_dma;
6483         dinitprintk(ioc,
6484                     ioc_info(ioc, "reply_free_dma (0x%llx)\n",
6485                              (unsigned long long)ioc->reply_free_dma));
6486         total_sz += sz;
6487         if (ioc->rdpq_array_enable) {
6488                 reply_post_free_array_sz = ioc->reply_queue_count *
6489                     sizeof(Mpi2IOCInitRDPQArrayEntry);
6490                 rc = _base_allocate_reply_post_free_array(ioc,
6491                     reply_post_free_array_sz);
6492                 if (rc == -ENOMEM)
6493                         return -ENOMEM;
6494                 else if (rc == -EAGAIN)
6495                         goto try_32bit_dma;
6496         }
6497         ioc->config_page_sz = 512;
6498         ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
6499                         ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
6500         if (!ioc->config_page) {
6501                 ioc_err(ioc, "config page: dma_pool_alloc failed\n");
6502                 goto out;
6503         }
6504
6505         ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
6506             ioc->config_page, (unsigned long long)ioc->config_page_dma,
6507             ioc->config_page_sz);
6508         total_sz += ioc->config_page_sz;
6509
6510         ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
6511                  total_sz / 1024);
6512         ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
6513                  ioc->shost->can_queue, facts->RequestCredit);
6514         ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
6515                  ioc->shost->sg_tablesize);
6516         return 0;
6517
6518 try_32bit_dma:
6519         _base_release_memory_pools(ioc);
6520         if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) {
6521                 /* Change dma coherent mask to 32 bit and reallocate */
6522                 if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
6523                         pr_err("Setting 32 bit coherent DMA mask Failed %s\n",
6524                             pci_name(ioc->pdev));
6525                         return -ENODEV;
6526                 }
6527         } else if (_base_reduce_hba_queue_depth(ioc) != 0)
6528                 return -ENOMEM;
6529         goto retry_allocation;
6530
6531  out:
6532         return -ENOMEM;
6533 }
6534
6535 /**
6536  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
6537  * @ioc: Pointer to MPT_ADAPTER structure
6538  * @cooked: Request raw or cooked IOC state
6539  *
6540  * Return: all IOC Doorbell register bits if cooked==0, else just the
6541  * Doorbell bits in MPI_IOC_STATE_MASK.
6542  */
6543 u32
6544 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
6545 {
6546         u32 s, sc;
6547
6548         s = ioc->base_readl(&ioc->chip->Doorbell);
6549         sc = s & MPI2_IOC_STATE_MASK;
6550         return cooked ? sc : s;
6551 }
6552
6553 /**
6554  * _base_wait_on_iocstate - waiting on a particular ioc state
6555  * @ioc: ?
6556  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
6557  * @timeout: timeout in second
6558  *
6559  * Return: 0 for success, non-zero for failure.
6560  */
6561 static int
6562 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
6563 {
6564         u32 count, cntdn;
6565         u32 current_state;
6566
6567         count = 0;
6568         cntdn = 1000 * timeout;
6569         do {
6570                 current_state = mpt3sas_base_get_iocstate(ioc, 1);
6571                 if (current_state == ioc_state)
6572                         return 0;
6573                 if (count && current_state == MPI2_IOC_STATE_FAULT)
6574                         break;
6575                 if (count && current_state == MPI2_IOC_STATE_COREDUMP)
6576                         break;
6577
6578                 usleep_range(1000, 1500);
6579                 count++;
6580         } while (--cntdn);
6581
6582         return current_state;
6583 }
6584
6585 /**
6586  * _base_dump_reg_set - This function will print hexdump of register set.
6587  * @ioc: per adapter object
6588  *
6589  * Return: nothing.
6590  */
6591 static inline void
6592 _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
6593 {
6594         unsigned int i, sz = 256;
6595         u32 __iomem *reg = (u32 __iomem *)ioc->chip;
6596
6597         ioc_info(ioc, "System Register set:\n");
6598         for (i = 0; i < (sz / sizeof(u32)); i++)
6599                 pr_info("%08x: %08x\n", (i * 4), readl(&reg[i]));
6600 }
6601
6602 /**
6603  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
6604  * a write to the doorbell)
6605  * @ioc: per adapter object
6606  * @timeout: timeout in seconds
6607  *
6608  * Return: 0 for success, non-zero for failure.
6609  *
6610  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
6611  */
6612
6613 static int
6614 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6615 {
6616         u32 cntdn, count;
6617         u32 int_status;
6618
6619         count = 0;
6620         cntdn = 1000 * timeout;
6621         do {
6622                 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6623                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6624                         dhsprintk(ioc,
6625                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6626                                            __func__, count, timeout));
6627                         return 0;
6628                 }
6629
6630                 usleep_range(1000, 1500);
6631                 count++;
6632         } while (--cntdn);
6633
6634         ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6635                 __func__, count, int_status);
6636         return -EFAULT;
6637 }
6638
6639 static int
6640 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
6641 {
6642         u32 cntdn, count;
6643         u32 int_status;
6644
6645         count = 0;
6646         cntdn = 2000 * timeout;
6647         do {
6648                 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6649                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6650                         dhsprintk(ioc,
6651                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6652                                            __func__, count, timeout));
6653                         return 0;
6654                 }
6655
6656                 udelay(500);
6657                 count++;
6658         } while (--cntdn);
6659
6660         ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6661                 __func__, count, int_status);
6662         return -EFAULT;
6663
6664 }
6665
6666 /**
6667  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
6668  * @ioc: per adapter object
6669  * @timeout: timeout in second
6670  *
6671  * Return: 0 for success, non-zero for failure.
6672  *
6673  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
6674  * doorbell.
6675  */
6676 static int
6677 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
6678 {
6679         u32 cntdn, count;
6680         u32 int_status;
6681         u32 doorbell;
6682
6683         count = 0;
6684         cntdn = 1000 * timeout;
6685         do {
6686                 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
6687                 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
6688                         dhsprintk(ioc,
6689                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6690                                            __func__, count, timeout));
6691                         return 0;
6692                 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
6693                         doorbell = ioc->base_readl(&ioc->chip->Doorbell);
6694                         if ((doorbell & MPI2_IOC_STATE_MASK) ==
6695                             MPI2_IOC_STATE_FAULT) {
6696                                 mpt3sas_print_fault_code(ioc, doorbell);
6697                                 return -EFAULT;
6698                         }
6699                         if ((doorbell & MPI2_IOC_STATE_MASK) ==
6700                             MPI2_IOC_STATE_COREDUMP) {
6701                                 mpt3sas_print_coredump_info(ioc, doorbell);
6702                                 return -EFAULT;
6703                         }
6704                 } else if (int_status == 0xFFFFFFFF)
6705                         goto out;
6706
6707                 usleep_range(1000, 1500);
6708                 count++;
6709         } while (--cntdn);
6710
6711  out:
6712         ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
6713                 __func__, count, int_status);
6714         return -EFAULT;
6715 }
6716
6717 /**
6718  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
6719  * @ioc: per adapter object
6720  * @timeout: timeout in second
6721  *
6722  * Return: 0 for success, non-zero for failure.
6723  */
6724 static int
6725 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
6726 {
6727         u32 cntdn, count;
6728         u32 doorbell_reg;
6729
6730         count = 0;
6731         cntdn = 1000 * timeout;
6732         do {
6733                 doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
6734                 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
6735                         dhsprintk(ioc,
6736                                   ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
6737                                            __func__, count, timeout));
6738                         return 0;
6739                 }
6740
6741                 usleep_range(1000, 1500);
6742                 count++;
6743         } while (--cntdn);
6744
6745         ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
6746                 __func__, count, doorbell_reg);
6747         return -EFAULT;
6748 }
6749
6750 /**
6751  * _base_send_ioc_reset - send doorbell reset
6752  * @ioc: per adapter object
6753  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
6754  * @timeout: timeout in second
6755  *
6756  * Return: 0 for success, non-zero for failure.
6757  */
6758 static int
6759 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
6760 {
6761         u32 ioc_state;
6762         int r = 0;
6763         unsigned long flags;
6764
6765         if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
6766                 ioc_err(ioc, "%s: unknown reset_type\n", __func__);
6767                 return -EFAULT;
6768         }
6769
6770         if (!(ioc->facts.IOCCapabilities &
6771            MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
6772                 return -EFAULT;
6773
6774         ioc_info(ioc, "sending message unit reset !!\n");
6775
6776         writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
6777             &ioc->chip->Doorbell);
6778         if ((_base_wait_for_doorbell_ack(ioc, 15))) {
6779                 r = -EFAULT;
6780                 goto out;
6781         }
6782
6783         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
6784         if (ioc_state) {
6785                 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6786                         __func__, ioc_state);
6787                 r = -EFAULT;
6788                 goto out;
6789         }
6790  out:
6791         if (r != 0) {
6792                 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6793                 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6794                 /*
6795                  * Wait for IOC state CoreDump to clear only during
6796                  * HBA initialization & release time.
6797                  */
6798                 if ((ioc_state & MPI2_IOC_STATE_MASK) ==
6799                     MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 ||
6800                     ioc->fault_reset_work_q == NULL)) {
6801                         spin_unlock_irqrestore(
6802                             &ioc->ioc_reset_in_progress_lock, flags);
6803                         mpt3sas_print_coredump_info(ioc, ioc_state);
6804                         mpt3sas_base_wait_for_coredump_completion(ioc,
6805                             __func__);
6806                         spin_lock_irqsave(
6807                             &ioc->ioc_reset_in_progress_lock, flags);
6808                 }
6809                 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6810         }
6811         ioc_info(ioc, "message unit reset: %s\n",
6812                  r == 0 ? "SUCCESS" : "FAILED");
6813         return r;
6814 }
6815
6816 /**
6817  * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
6818  * @ioc: per adapter object
6819  * @timeout: timeout in seconds
6820  *
6821  * Return: Waits up to timeout seconds for the IOC to
6822  * become operational. Returns 0 if IOC is present
6823  * and operational; otherwise returns %-EFAULT.
6824  */
6825
6826 int
6827 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
6828 {
6829         int wait_state_count = 0;
6830         u32 ioc_state;
6831
6832         do {
6833                 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
6834                 if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
6835                         break;
6836
6837                 /*
6838                  * Watchdog thread will be started after IOC Initialization, so
6839                  * no need to wait here for IOC state to become operational
6840                  * when IOC Initialization is on. Instead the driver will
6841                  * return ETIME status, so that calling function can issue
6842                  * diag reset operation and retry the command.
6843                  */
6844                 if (ioc->is_driver_loading)
6845                         return -ETIME;
6846
6847                 ssleep(1);
6848                 ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
6849                                 __func__, ++wait_state_count);
6850         } while (--timeout);
6851         if (!timeout) {
6852                 ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
6853                 return -EFAULT;
6854         }
6855         if (wait_state_count)
6856                 ioc_info(ioc, "ioc is operational\n");
6857         return 0;
6858 }
6859
6860 /**
6861  * _base_handshake_req_reply_wait - send request thru doorbell interface
6862  * @ioc: per adapter object
6863  * @request_bytes: request length
6864  * @request: pointer having request payload
6865  * @reply_bytes: reply length
6866  * @reply: pointer to reply payload
6867  * @timeout: timeout in second
6868  *
6869  * Return: 0 for success, non-zero for failure.
6870  */
6871 static int
6872 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
6873         u32 *request, int reply_bytes, u16 *reply, int timeout)
6874 {
6875         MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
6876         int i;
6877         u8 failed;
6878         __le32 *mfp;
6879
6880         /* make sure doorbell is not in use */
6881         if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
6882                 ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
6883                 return -EFAULT;
6884         }
6885
6886         /* clear pending doorbell interrupts from previous state changes */
6887         if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
6888             MPI2_HIS_IOC2SYS_DB_STATUS)
6889                 writel(0, &ioc->chip->HostInterruptStatus);
6890
6891         /* send message to ioc */
6892         writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
6893             ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
6894             &ioc->chip->Doorbell);
6895
6896         if ((_base_spin_on_doorbell_int(ioc, 5))) {
6897                 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6898                         __LINE__);
6899                 return -EFAULT;
6900         }
6901         writel(0, &ioc->chip->HostInterruptStatus);
6902
6903         if ((_base_wait_for_doorbell_ack(ioc, 5))) {
6904                 ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
6905                         __LINE__);
6906                 return -EFAULT;
6907         }
6908
6909         /* send message 32-bits at a time */
6910         for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
6911                 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
6912                 if ((_base_wait_for_doorbell_ack(ioc, 5)))
6913                         failed = 1;
6914         }
6915
6916         if (failed) {
6917                 ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
6918                         __LINE__);
6919                 return -EFAULT;
6920         }
6921
6922         /* now wait for the reply */
6923         if ((_base_wait_for_doorbell_int(ioc, timeout))) {
6924                 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6925                         __LINE__);
6926                 return -EFAULT;
6927         }
6928
6929         /* read the first two 16-bits, it gives the total length of the reply */
6930         reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
6931             & MPI2_DOORBELL_DATA_MASK);
6932         writel(0, &ioc->chip->HostInterruptStatus);
6933         if ((_base_wait_for_doorbell_int(ioc, 5))) {
6934                 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6935                         __LINE__);
6936                 return -EFAULT;
6937         }
6938         reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
6939             & MPI2_DOORBELL_DATA_MASK);
6940         writel(0, &ioc->chip->HostInterruptStatus);
6941
6942         for (i = 2; i < default_reply->MsgLength * 2; i++)  {
6943                 if ((_base_wait_for_doorbell_int(ioc, 5))) {
6944                         ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
6945                                 __LINE__);
6946                         return -EFAULT;
6947                 }
6948                 if (i >=  reply_bytes/2) /* overflow case */
6949                         ioc->base_readl(&ioc->chip->Doorbell);
6950                 else
6951                         reply[i] = le16_to_cpu(
6952                             ioc->base_readl(&ioc->chip->Doorbell)
6953                             & MPI2_DOORBELL_DATA_MASK);
6954                 writel(0, &ioc->chip->HostInterruptStatus);
6955         }
6956
6957         _base_wait_for_doorbell_int(ioc, 5);
6958         if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
6959                 dhsprintk(ioc,
6960                           ioc_info(ioc, "doorbell is in use (line=%d)\n",
6961                                    __LINE__));
6962         }
6963         writel(0, &ioc->chip->HostInterruptStatus);
6964
6965         if (ioc->logging_level & MPT_DEBUG_INIT) {
6966                 mfp = (__le32 *)reply;
6967                 pr_info("\toffset:data\n");
6968                 for (i = 0; i < reply_bytes/4; i++)
6969                         ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
6970                             le32_to_cpu(mfp[i]));
6971         }
6972         return 0;
6973 }
6974
6975 /**
6976  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
6977  * @ioc: per adapter object
6978  * @mpi_reply: the reply payload from FW
6979  * @mpi_request: the request payload sent to FW
6980  *
6981  * The SAS IO Unit Control Request message allows the host to perform low-level
6982  * operations, such as resets on the PHYs of the IO Unit, also allows the host
6983  * to obtain the IOC assigned device handles for a device if it has other
6984  * identifying information about the device, in addition allows the host to
6985  * remove IOC resources associated with the device.
6986  *
6987  * Return: 0 for success, non-zero for failure.
6988  */
6989 int
6990 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
6991         Mpi2SasIoUnitControlReply_t *mpi_reply,
6992         Mpi2SasIoUnitControlRequest_t *mpi_request)
6993 {
6994         u16 smid;
6995         u8 issue_reset = 0;
6996         int rc;
6997         void *request;
6998
6999         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7000
7001         mutex_lock(&ioc->base_cmds.mutex);
7002
7003         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
7004                 ioc_err(ioc, "%s: base_cmd in use\n", __func__);
7005                 rc = -EAGAIN;
7006                 goto out;
7007         }
7008
7009         rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
7010         if (rc)
7011                 goto out;
7012
7013         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7014         if (!smid) {
7015                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7016                 rc = -EAGAIN;
7017                 goto out;
7018         }
7019
7020         rc = 0;
7021         ioc->base_cmds.status = MPT3_CMD_PENDING;
7022         request = mpt3sas_base_get_msg_frame(ioc, smid);
7023         ioc->base_cmds.smid = smid;
7024         memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
7025         if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
7026             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
7027                 ioc->ioc_link_reset_in_progress = 1;
7028         init_completion(&ioc->base_cmds.done);
7029         ioc->put_smid_default(ioc, smid);
7030         wait_for_completion_timeout(&ioc->base_cmds.done,
7031             msecs_to_jiffies(10000));
7032         if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
7033             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
7034             ioc->ioc_link_reset_in_progress)
7035                 ioc->ioc_link_reset_in_progress = 0;
7036         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7037                 mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
7038                     mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
7039                     issue_reset);
7040                 goto issue_host_reset;
7041         }
7042         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
7043                 memcpy(mpi_reply, ioc->base_cmds.reply,
7044                     sizeof(Mpi2SasIoUnitControlReply_t));
7045         else
7046                 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
7047         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7048         goto out;
7049
7050  issue_host_reset:
7051         if (issue_reset)
7052                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
7053         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7054         rc = -EFAULT;
7055  out:
7056         mutex_unlock(&ioc->base_cmds.mutex);
7057         return rc;
7058 }
7059
7060 /**
7061  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
7062  * @ioc: per adapter object
7063  * @mpi_reply: the reply payload from FW
7064  * @mpi_request: the request payload sent to FW
7065  *
7066  * The SCSI Enclosure Processor request message causes the IOC to
7067  * communicate with SES devices to control LED status signals.
7068  *
7069  * Return: 0 for success, non-zero for failure.
7070  */
7071 int
7072 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
7073         Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
7074 {
7075         u16 smid;
7076         u8 issue_reset = 0;
7077         int rc;
7078         void *request;
7079
7080         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7081
7082         mutex_lock(&ioc->base_cmds.mutex);
7083
7084         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
7085                 ioc_err(ioc, "%s: base_cmd in use\n", __func__);
7086                 rc = -EAGAIN;
7087                 goto out;
7088         }
7089
7090         rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
7091         if (rc)
7092                 goto out;
7093
7094         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7095         if (!smid) {
7096                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7097                 rc = -EAGAIN;
7098                 goto out;
7099         }
7100
7101         rc = 0;
7102         ioc->base_cmds.status = MPT3_CMD_PENDING;
7103         request = mpt3sas_base_get_msg_frame(ioc, smid);
7104         ioc->base_cmds.smid = smid;
7105         memset(request, 0, ioc->request_sz);
7106         memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
7107         init_completion(&ioc->base_cmds.done);
7108         ioc->put_smid_default(ioc, smid);
7109         wait_for_completion_timeout(&ioc->base_cmds.done,
7110             msecs_to_jiffies(10000));
7111         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7112                 mpt3sas_check_cmd_timeout(ioc,
7113                     ioc->base_cmds.status, mpi_request,
7114                     sizeof(Mpi2SepRequest_t)/4, issue_reset);
7115                 goto issue_host_reset;
7116         }
7117         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
7118                 memcpy(mpi_reply, ioc->base_cmds.reply,
7119                     sizeof(Mpi2SepReply_t));
7120         else
7121                 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
7122         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7123         goto out;
7124
7125  issue_host_reset:
7126         if (issue_reset)
7127                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
7128         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7129         rc = -EFAULT;
7130  out:
7131         mutex_unlock(&ioc->base_cmds.mutex);
7132         return rc;
7133 }
7134
7135 /**
7136  * _base_get_port_facts - obtain port facts reply and save in ioc
7137  * @ioc: per adapter object
7138  * @port: ?
7139  *
7140  * Return: 0 for success, non-zero for failure.
7141  */
7142 static int
7143 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
7144 {
7145         Mpi2PortFactsRequest_t mpi_request;
7146         Mpi2PortFactsReply_t mpi_reply;
7147         struct mpt3sas_port_facts *pfacts;
7148         int mpi_reply_sz, mpi_request_sz, r;
7149
7150         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7151
7152         mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
7153         mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
7154         memset(&mpi_request, 0, mpi_request_sz);
7155         mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
7156         mpi_request.PortNumber = port;
7157         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
7158             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
7159
7160         if (r != 0) {
7161                 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7162                 return r;
7163         }
7164
7165         pfacts = &ioc->pfacts[port];
7166         memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
7167         pfacts->PortNumber = mpi_reply.PortNumber;
7168         pfacts->VP_ID = mpi_reply.VP_ID;
7169         pfacts->VF_ID = mpi_reply.VF_ID;
7170         pfacts->MaxPostedCmdBuffers =
7171             le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
7172
7173         return 0;
7174 }
7175
7176 /**
7177  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
7178  * @ioc: per adapter object
7179  * @timeout:
7180  *
7181  * Return: 0 for success, non-zero for failure.
7182  */
7183 static int
7184 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
7185 {
7186         u32 ioc_state;
7187         int rc;
7188
7189         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7190
7191         if (ioc->pci_error_recovery) {
7192                 dfailprintk(ioc,
7193                             ioc_info(ioc, "%s: host in pci error recovery\n",
7194                                      __func__));
7195                 return -EFAULT;
7196         }
7197
7198         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7199         dhsprintk(ioc,
7200                   ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
7201                            __func__, ioc_state));
7202
7203         if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
7204             (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
7205                 return 0;
7206
7207         if (ioc_state & MPI2_DOORBELL_USED) {
7208                 dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
7209                 goto issue_diag_reset;
7210         }
7211
7212         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
7213                 mpt3sas_print_fault_code(ioc, ioc_state &
7214                     MPI2_DOORBELL_DATA_MASK);
7215                 goto issue_diag_reset;
7216         } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
7217             MPI2_IOC_STATE_COREDUMP) {
7218                 ioc_info(ioc,
7219                     "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
7220                     __func__, ioc_state);
7221                 return -EFAULT;
7222         }
7223
7224         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
7225         if (ioc_state) {
7226                 dfailprintk(ioc,
7227                             ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7228                                      __func__, ioc_state));
7229                 return -EFAULT;
7230         }
7231
7232  issue_diag_reset:
7233         rc = _base_diag_reset(ioc);
7234         return rc;
7235 }
7236
7237 /**
7238  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
7239  * @ioc: per adapter object
7240  *
7241  * Return: 0 for success, non-zero for failure.
7242  */
7243 static int
7244 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
7245 {
7246         Mpi2IOCFactsRequest_t mpi_request;
7247         Mpi2IOCFactsReply_t mpi_reply;
7248         struct mpt3sas_facts *facts;
7249         int mpi_reply_sz, mpi_request_sz, r;
7250
7251         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7252
7253         r = _base_wait_for_iocstate(ioc, 10);
7254         if (r) {
7255                 dfailprintk(ioc,
7256                             ioc_info(ioc, "%s: failed getting to correct state\n",
7257                                      __func__));
7258                 return r;
7259         }
7260         mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
7261         mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
7262         memset(&mpi_request, 0, mpi_request_sz);
7263         mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
7264         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
7265             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
7266
7267         if (r != 0) {
7268                 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7269                 return r;
7270         }
7271
7272         facts = &ioc->facts;
7273         memset(facts, 0, sizeof(struct mpt3sas_facts));
7274         facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
7275         facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
7276         facts->VP_ID = mpi_reply.VP_ID;
7277         facts->VF_ID = mpi_reply.VF_ID;
7278         facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
7279         facts->MaxChainDepth = mpi_reply.MaxChainDepth;
7280         facts->WhoInit = mpi_reply.WhoInit;
7281         facts->NumberOfPorts = mpi_reply.NumberOfPorts;
7282         facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
7283         if (ioc->msix_enable && (facts->MaxMSIxVectors <=
7284             MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))
7285                 ioc->combined_reply_queue = 0;
7286         facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
7287         facts->MaxReplyDescriptorPostQueueDepth =
7288             le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
7289         facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
7290         facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
7291         if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
7292                 ioc->ir_firmware = 1;
7293         if ((facts->IOCCapabilities &
7294               MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
7295                 ioc->rdpq_array_capable = 1;
7296         if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
7297             && ioc->is_aero_ioc)
7298                 ioc->atomic_desc_capable = 1;
7299         facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
7300         facts->IOCRequestFrameSize =
7301             le16_to_cpu(mpi_reply.IOCRequestFrameSize);
7302         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
7303                 facts->IOCMaxChainSegmentSize =
7304                         le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
7305         }
7306         facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
7307         facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
7308         ioc->shost->max_id = -1;
7309         facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
7310         facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
7311         facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
7312         facts->HighPriorityCredit =
7313             le16_to_cpu(mpi_reply.HighPriorityCredit);
7314         facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
7315         facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
7316         facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
7317
7318         /*
7319          * Get the Page Size from IOC Facts. If it's 0, default to 4k.
7320          */
7321         ioc->page_size = 1 << facts->CurrentHostPageSize;
7322         if (ioc->page_size == 1) {
7323                 ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
7324                 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
7325         }
7326         dinitprintk(ioc,
7327                     ioc_info(ioc, "CurrentHostPageSize(%d)\n",
7328                              facts->CurrentHostPageSize));
7329
7330         dinitprintk(ioc,
7331                     ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
7332                              facts->RequestCredit, facts->MaxChainDepth));
7333         dinitprintk(ioc,
7334                     ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
7335                              facts->IOCRequestFrameSize * 4,
7336                              facts->ReplyFrameSize * 4));
7337         return 0;
7338 }
7339
7340 /**
7341  * _base_send_ioc_init - send ioc_init to firmware
7342  * @ioc: per adapter object
7343  *
7344  * Return: 0 for success, non-zero for failure.
7345  */
7346 static int
7347 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
7348 {
7349         Mpi2IOCInitRequest_t mpi_request;
7350         Mpi2IOCInitReply_t mpi_reply;
7351         int i, r = 0;
7352         ktime_t current_time;
7353         u16 ioc_status;
7354         u32 reply_post_free_array_sz = 0;
7355
7356         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7357
7358         memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
7359         mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
7360         mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
7361         mpi_request.VF_ID = 0; /* TODO */
7362         mpi_request.VP_ID = 0;
7363         mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
7364         mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
7365         mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
7366
7367         if (_base_is_controller_msix_enabled(ioc))
7368                 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
7369         mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
7370         mpi_request.ReplyDescriptorPostQueueDepth =
7371             cpu_to_le16(ioc->reply_post_queue_depth);
7372         mpi_request.ReplyFreeQueueDepth =
7373             cpu_to_le16(ioc->reply_free_queue_depth);
7374
7375         mpi_request.SenseBufferAddressHigh =
7376             cpu_to_le32((u64)ioc->sense_dma >> 32);
7377         mpi_request.SystemReplyAddressHigh =
7378             cpu_to_le32((u64)ioc->reply_dma >> 32);
7379         mpi_request.SystemRequestFrameBaseAddress =
7380             cpu_to_le64((u64)ioc->request_dma);
7381         mpi_request.ReplyFreeQueueAddress =
7382             cpu_to_le64((u64)ioc->reply_free_dma);
7383
7384         if (ioc->rdpq_array_enable) {
7385                 reply_post_free_array_sz = ioc->reply_queue_count *
7386                     sizeof(Mpi2IOCInitRDPQArrayEntry);
7387                 memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz);
7388                 for (i = 0; i < ioc->reply_queue_count; i++)
7389                         ioc->reply_post_free_array[i].RDPQBaseAddress =
7390                             cpu_to_le64(
7391                                 (u64)ioc->reply_post[i].reply_post_free_dma);
7392                 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
7393                 mpi_request.ReplyDescriptorPostQueueAddress =
7394                     cpu_to_le64((u64)ioc->reply_post_free_array_dma);
7395         } else {
7396                 mpi_request.ReplyDescriptorPostQueueAddress =
7397                     cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
7398         }
7399
7400         /*
7401          * Set the flag to enable CoreDump state feature in IOC firmware.
7402          */
7403         mpi_request.ConfigurationFlags |=
7404             cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
7405
7406         /* This time stamp specifies number of milliseconds
7407          * since epoch ~ midnight January 1, 1970.
7408          */
7409         current_time = ktime_get_real();
7410         mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
7411
7412         if (ioc->logging_level & MPT_DEBUG_INIT) {
7413                 __le32 *mfp;
7414                 int i;
7415
7416                 mfp = (__le32 *)&mpi_request;
7417                 ioc_info(ioc, "\toffset:data\n");
7418                 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
7419                         ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
7420                             le32_to_cpu(mfp[i]));
7421         }
7422
7423         r = _base_handshake_req_reply_wait(ioc,
7424             sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
7425             sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
7426
7427         if (r != 0) {
7428                 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
7429                 return r;
7430         }
7431
7432         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
7433         if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
7434             mpi_reply.IOCLogInfo) {
7435                 ioc_err(ioc, "%s: failed\n", __func__);
7436                 r = -EIO;
7437         }
7438
7439         /* Reset TimeSync Counter*/
7440         ioc->timestamp_update_count = 0;
7441         return r;
7442 }
7443
7444 /**
7445  * mpt3sas_port_enable_done - command completion routine for port enable
7446  * @ioc: per adapter object
7447  * @smid: system request message index
7448  * @msix_index: MSIX table index supplied by the OS
7449  * @reply: reply message frame(lower 32bit addr)
7450  *
7451  * Return: 1 meaning mf should be freed from _base_interrupt
7452  *          0 means the mf is freed from this function.
7453  */
7454 u8
7455 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
7456         u32 reply)
7457 {
7458         MPI2DefaultReply_t *mpi_reply;
7459         u16 ioc_status;
7460
7461         if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
7462                 return 1;
7463
7464         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
7465         if (!mpi_reply)
7466                 return 1;
7467
7468         if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
7469                 return 1;
7470
7471         ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
7472         ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
7473         ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
7474         memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
7475         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7476         if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
7477                 ioc->port_enable_failed = 1;
7478
7479         if (ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE_ASYNC) {
7480                 ioc->port_enable_cmds.status &= ~MPT3_CMD_COMPLETE_ASYNC;
7481                 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
7482                         mpt3sas_port_enable_complete(ioc);
7483                         return 1;
7484                 } else {
7485                         ioc->start_scan_failed = ioc_status;
7486                         ioc->start_scan = 0;
7487                         return 1;
7488                 }
7489         }
7490         complete(&ioc->port_enable_cmds.done);
7491         return 1;
7492 }
7493
7494 /**
7495  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
7496  * @ioc: per adapter object
7497  *
7498  * Return: 0 for success, non-zero for failure.
7499  */
7500 static int
7501 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
7502 {
7503         Mpi2PortEnableRequest_t *mpi_request;
7504         Mpi2PortEnableReply_t *mpi_reply;
7505         int r = 0;
7506         u16 smid;
7507         u16 ioc_status;
7508
7509         ioc_info(ioc, "sending port enable !!\n");
7510
7511         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7512                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
7513                 return -EAGAIN;
7514         }
7515
7516         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7517         if (!smid) {
7518                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7519                 return -EAGAIN;
7520         }
7521
7522         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7523         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7524         ioc->port_enable_cmds.smid = smid;
7525         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7526         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7527
7528         init_completion(&ioc->port_enable_cmds.done);
7529         ioc->put_smid_default(ioc, smid);
7530         wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
7531         if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
7532                 ioc_err(ioc, "%s: timeout\n", __func__);
7533                 _debug_dump_mf(mpi_request,
7534                     sizeof(Mpi2PortEnableRequest_t)/4);
7535                 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
7536                         r = -EFAULT;
7537                 else
7538                         r = -ETIME;
7539                 goto out;
7540         }
7541
7542         mpi_reply = ioc->port_enable_cmds.reply;
7543         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
7544         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
7545                 ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
7546                         __func__, ioc_status);
7547                 r = -EFAULT;
7548                 goto out;
7549         }
7550
7551  out:
7552         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
7553         ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
7554         return r;
7555 }
7556
7557 /**
7558  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
7559  * @ioc: per adapter object
7560  *
7561  * Return: 0 for success, non-zero for failure.
7562  */
7563 int
7564 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
7565 {
7566         Mpi2PortEnableRequest_t *mpi_request;
7567         u16 smid;
7568
7569         ioc_info(ioc, "sending port enable !!\n");
7570
7571         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
7572                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
7573                 return -EAGAIN;
7574         }
7575
7576         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
7577         if (!smid) {
7578                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7579                 return -EAGAIN;
7580         }
7581         ioc->drv_internal_flags |= MPT_DRV_INTERNAL_FIRST_PE_ISSUED;
7582         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
7583         ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE_ASYNC;
7584         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7585         ioc->port_enable_cmds.smid = smid;
7586         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
7587         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
7588
7589         ioc->put_smid_default(ioc, smid);
7590         return 0;
7591 }
7592
7593 /**
7594  * _base_determine_wait_on_discovery - desposition
7595  * @ioc: per adapter object
7596  *
7597  * Decide whether to wait on discovery to complete. Used to either
7598  * locate boot device, or report volumes ahead of physical devices.
7599  *
7600  * Return: 1 for wait, 0 for don't wait.
7601  */
7602 static int
7603 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
7604 {
7605         /* We wait for discovery to complete if IR firmware is loaded.
7606          * The sas topology events arrive before PD events, so we need time to
7607          * turn on the bit in ioc->pd_handles to indicate PD
7608          * Also, it maybe required to report Volumes ahead of physical
7609          * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
7610          */
7611         if (ioc->ir_firmware)
7612                 return 1;
7613
7614         /* if no Bios, then we don't need to wait */
7615         if (!ioc->bios_pg3.BiosVersion)
7616                 return 0;
7617
7618         /* Bios is present, then we drop down here.
7619          *
7620          * If there any entries in the Bios Page 2, then we wait
7621          * for discovery to complete.
7622          */
7623
7624         /* Current Boot Device */
7625         if ((ioc->bios_pg2.CurrentBootDeviceForm &
7626             MPI2_BIOSPAGE2_FORM_MASK) ==
7627             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7628         /* Request Boot Device */
7629            (ioc->bios_pg2.ReqBootDeviceForm &
7630             MPI2_BIOSPAGE2_FORM_MASK) ==
7631             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
7632         /* Alternate Request Boot Device */
7633            (ioc->bios_pg2.ReqAltBootDeviceForm &
7634             MPI2_BIOSPAGE2_FORM_MASK) ==
7635             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
7636                 return 0;
7637
7638         return 1;
7639 }
7640
7641 /**
7642  * _base_unmask_events - turn on notification for this event
7643  * @ioc: per adapter object
7644  * @event: firmware event
7645  *
7646  * The mask is stored in ioc->event_masks.
7647  */
7648 static void
7649 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
7650 {
7651         u32 desired_event;
7652
7653         if (event >= 128)
7654                 return;
7655
7656         desired_event = (1 << (event % 32));
7657
7658         if (event < 32)
7659                 ioc->event_masks[0] &= ~desired_event;
7660         else if (event < 64)
7661                 ioc->event_masks[1] &= ~desired_event;
7662         else if (event < 96)
7663                 ioc->event_masks[2] &= ~desired_event;
7664         else if (event < 128)
7665                 ioc->event_masks[3] &= ~desired_event;
7666 }
7667
7668 /**
7669  * _base_event_notification - send event notification
7670  * @ioc: per adapter object
7671  *
7672  * Return: 0 for success, non-zero for failure.
7673  */
7674 static int
7675 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
7676 {
7677         Mpi2EventNotificationRequest_t *mpi_request;
7678         u16 smid;
7679         int r = 0;
7680         int i, issue_diag_reset = 0;
7681
7682         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7683
7684         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
7685                 ioc_err(ioc, "%s: internal command already in use\n", __func__);
7686                 return -EAGAIN;
7687         }
7688
7689         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
7690         if (!smid) {
7691                 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
7692                 return -EAGAIN;
7693         }
7694         ioc->base_cmds.status = MPT3_CMD_PENDING;
7695         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
7696         ioc->base_cmds.smid = smid;
7697         memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
7698         mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
7699         mpi_request->VF_ID = 0; /* TODO */
7700         mpi_request->VP_ID = 0;
7701         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
7702                 mpi_request->EventMasks[i] =
7703                     cpu_to_le32(ioc->event_masks[i]);
7704         init_completion(&ioc->base_cmds.done);
7705         ioc->put_smid_default(ioc, smid);
7706         wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
7707         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
7708                 ioc_err(ioc, "%s: timeout\n", __func__);
7709                 _debug_dump_mf(mpi_request,
7710                     sizeof(Mpi2EventNotificationRequest_t)/4);
7711                 if (ioc->base_cmds.status & MPT3_CMD_RESET)
7712                         r = -EFAULT;
7713                 else
7714                         issue_diag_reset = 1;
7715
7716         } else
7717                 dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
7718         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
7719
7720         if (issue_diag_reset) {
7721                 if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED)
7722                         return -EFAULT;
7723                 if (mpt3sas_base_check_for_fault_and_issue_reset(ioc))
7724                         return -EFAULT;
7725                 r = -EAGAIN;
7726         }
7727         return r;
7728 }
7729
7730 /**
7731  * mpt3sas_base_validate_event_type - validating event types
7732  * @ioc: per adapter object
7733  * @event_type: firmware event
7734  *
7735  * This will turn on firmware event notification when application
7736  * ask for that event. We don't mask events that are already enabled.
7737  */
7738 void
7739 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
7740 {
7741         int i, j;
7742         u32 event_mask, desired_event;
7743         u8 send_update_to_fw;
7744
7745         for (i = 0, send_update_to_fw = 0; i <
7746             MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
7747                 event_mask = ~event_type[i];
7748                 desired_event = 1;
7749                 for (j = 0; j < 32; j++) {
7750                         if (!(event_mask & desired_event) &&
7751                             (ioc->event_masks[i] & desired_event)) {
7752                                 ioc->event_masks[i] &= ~desired_event;
7753                                 send_update_to_fw = 1;
7754                         }
7755                         desired_event = (desired_event << 1);
7756                 }
7757         }
7758
7759         if (!send_update_to_fw)
7760                 return;
7761
7762         mutex_lock(&ioc->base_cmds.mutex);
7763         _base_event_notification(ioc);
7764         mutex_unlock(&ioc->base_cmds.mutex);
7765 }
7766
7767 /**
7768  * _base_diag_reset - the "big hammer" start of day reset
7769  * @ioc: per adapter object
7770  *
7771  * Return: 0 for success, non-zero for failure.
7772  */
7773 static int
7774 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
7775 {
7776         u32 host_diagnostic;
7777         u32 ioc_state;
7778         u32 count;
7779         u32 hcb_size;
7780
7781         ioc_info(ioc, "sending diag reset !!\n");
7782
7783         pci_cfg_access_lock(ioc->pdev);
7784
7785         drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
7786
7787         count = 0;
7788         do {
7789                 /* Write magic sequence to WriteSequence register
7790                  * Loop until in diagnostic mode
7791                  */
7792                 drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
7793                 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7794                 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
7795                 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
7796                 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
7797                 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
7798                 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
7799                 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
7800
7801                 /* wait 100 msec */
7802                 msleep(100);
7803
7804                 if (count++ > 20) {
7805                         ioc_info(ioc,
7806                             "Stop writing magic sequence after 20 retries\n");
7807                         _base_dump_reg_set(ioc);
7808                         goto out;
7809                 }
7810
7811                 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7812                 drsprintk(ioc,
7813                           ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
7814                                    count, host_diagnostic));
7815
7816         } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
7817
7818         hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
7819
7820         drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
7821         writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
7822              &ioc->chip->HostDiagnostic);
7823
7824         /*This delay allows the chip PCIe hardware time to finish reset tasks*/
7825         msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
7826
7827         /* Approximately 300 second max wait */
7828         for (count = 0; count < (300000000 /
7829                 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
7830
7831                 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
7832
7833                 if (host_diagnostic == 0xFFFFFFFF) {
7834                         ioc_info(ioc,
7835                             "Invalid host diagnostic register value\n");
7836                         _base_dump_reg_set(ioc);
7837                         goto out;
7838                 }
7839                 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
7840                         break;
7841
7842                 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
7843         }
7844
7845         if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
7846
7847                 drsprintk(ioc,
7848                           ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
7849                 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
7850                 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
7851                 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
7852
7853                 drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
7854                 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
7855                     &ioc->chip->HCBSize);
7856         }
7857
7858         drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
7859         writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
7860             &ioc->chip->HostDiagnostic);
7861
7862         drsprintk(ioc,
7863                   ioc_info(ioc, "disable writes to the diagnostic register\n"));
7864         writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
7865
7866         drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
7867         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
7868         if (ioc_state) {
7869                 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7870                         __func__, ioc_state);
7871                 _base_dump_reg_set(ioc);
7872                 goto out;
7873         }
7874
7875         pci_cfg_access_unlock(ioc->pdev);
7876         ioc_info(ioc, "diag reset: SUCCESS\n");
7877         return 0;
7878
7879  out:
7880         pci_cfg_access_unlock(ioc->pdev);
7881         ioc_err(ioc, "diag reset: FAILED\n");
7882         return -EFAULT;
7883 }
7884
7885 /**
7886  * mpt3sas_base_make_ioc_ready - put controller in READY state
7887  * @ioc: per adapter object
7888  * @type: FORCE_BIG_HAMMER or SOFT_RESET
7889  *
7890  * Return: 0 for success, non-zero for failure.
7891  */
7892 int
7893 mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
7894 {
7895         u32 ioc_state;
7896         int rc;
7897         int count;
7898
7899         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7900
7901         if (ioc->pci_error_recovery)
7902                 return 0;
7903
7904         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7905         dhsprintk(ioc,
7906                   ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
7907                            __func__, ioc_state));
7908
7909         /* if in RESET state, it should move to READY state shortly */
7910         count = 0;
7911         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
7912                 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
7913                     MPI2_IOC_STATE_READY) {
7914                         if (count++ == 10) {
7915                                 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
7916                                         __func__, ioc_state);
7917                                 return -EFAULT;
7918                         }
7919                         ssleep(1);
7920                         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
7921                 }
7922         }
7923
7924         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
7925                 return 0;
7926
7927         if (ioc_state & MPI2_DOORBELL_USED) {
7928                 ioc_info(ioc, "unexpected doorbell active!\n");
7929                 goto issue_diag_reset;
7930         }
7931
7932         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
7933                 mpt3sas_print_fault_code(ioc, ioc_state &
7934                     MPI2_DOORBELL_DATA_MASK);
7935                 goto issue_diag_reset;
7936         }
7937
7938         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
7939                 /*
7940                  * if host reset is invoked while watch dog thread is waiting
7941                  * for IOC state to be changed to Fault state then driver has
7942                  * to wait here for CoreDump state to clear otherwise reset
7943                  * will be issued to the FW and FW move the IOC state to
7944                  * reset state without copying the FW logs to coredump region.
7945                  */
7946                 if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
7947                         mpt3sas_print_coredump_info(ioc, ioc_state &
7948                             MPI2_DOORBELL_DATA_MASK);
7949                         mpt3sas_base_wait_for_coredump_completion(ioc,
7950                             __func__);
7951                 }
7952                 goto issue_diag_reset;
7953         }
7954
7955         if (type == FORCE_BIG_HAMMER)
7956                 goto issue_diag_reset;
7957
7958         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
7959                 if (!(_base_send_ioc_reset(ioc,
7960                     MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
7961                         return 0;
7962         }
7963
7964  issue_diag_reset:
7965         rc = _base_diag_reset(ioc);
7966         return rc;
7967 }
7968
7969 /**
7970  * _base_make_ioc_operational - put controller in OPERATIONAL state
7971  * @ioc: per adapter object
7972  *
7973  * Return: 0 for success, non-zero for failure.
7974  */
7975 static int
7976 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
7977 {
7978         int r, i, index, rc;
7979         unsigned long   flags;
7980         u32 reply_address;
7981         u16 smid;
7982         struct _tr_list *delayed_tr, *delayed_tr_next;
7983         struct _sc_list *delayed_sc, *delayed_sc_next;
7984         struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
7985         u8 hide_flag;
7986         struct adapter_reply_queue *reply_q;
7987         Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
7988
7989         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
7990
7991         /* clean the delayed target reset list */
7992         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
7993             &ioc->delayed_tr_list, list) {
7994                 list_del(&delayed_tr->list);
7995                 kfree(delayed_tr);
7996         }
7997
7998
7999         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
8000             &ioc->delayed_tr_volume_list, list) {
8001                 list_del(&delayed_tr->list);
8002                 kfree(delayed_tr);
8003         }
8004
8005         list_for_each_entry_safe(delayed_sc, delayed_sc_next,
8006             &ioc->delayed_sc_list, list) {
8007                 list_del(&delayed_sc->list);
8008                 kfree(delayed_sc);
8009         }
8010
8011         list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
8012             &ioc->delayed_event_ack_list, list) {
8013                 list_del(&delayed_event_ack->list);
8014                 kfree(delayed_event_ack);
8015         }
8016
8017         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
8018
8019         /* hi-priority queue */
8020         INIT_LIST_HEAD(&ioc->hpr_free_list);
8021         smid = ioc->hi_priority_smid;
8022         for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
8023                 ioc->hpr_lookup[i].cb_idx = 0xFF;
8024                 ioc->hpr_lookup[i].smid = smid;
8025                 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
8026                     &ioc->hpr_free_list);
8027         }
8028
8029         /* internal queue */
8030         INIT_LIST_HEAD(&ioc->internal_free_list);
8031         smid = ioc->internal_smid;
8032         for (i = 0; i < ioc->internal_depth; i++, smid++) {
8033                 ioc->internal_lookup[i].cb_idx = 0xFF;
8034                 ioc->internal_lookup[i].smid = smid;
8035                 list_add_tail(&ioc->internal_lookup[i].tracker_list,
8036                     &ioc->internal_free_list);
8037         }
8038
8039         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
8040
8041         /* initialize Reply Free Queue */
8042         for (i = 0, reply_address = (u32)ioc->reply_dma ;
8043             i < ioc->reply_free_queue_depth ; i++, reply_address +=
8044             ioc->reply_sz) {
8045                 ioc->reply_free[i] = cpu_to_le32(reply_address);
8046                 if (ioc->is_mcpu_endpoint)
8047                         _base_clone_reply_to_sys_mem(ioc,
8048                                         reply_address, i);
8049         }
8050
8051         /* initialize reply queues */
8052         if (ioc->is_driver_loading)
8053                 _base_assign_reply_queues(ioc);
8054
8055         /* initialize Reply Post Free Queue */
8056         index = 0;
8057         reply_post_free_contig = ioc->reply_post[0].reply_post_free;
8058         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
8059                 /*
8060                  * If RDPQ is enabled, switch to the next allocation.
8061                  * Otherwise advance within the contiguous region.
8062                  */
8063                 if (ioc->rdpq_array_enable) {
8064                         reply_q->reply_post_free =
8065                                 ioc->reply_post[index++].reply_post_free;
8066                 } else {
8067                         reply_q->reply_post_free = reply_post_free_contig;
8068                         reply_post_free_contig += ioc->reply_post_queue_depth;
8069                 }
8070
8071                 reply_q->reply_post_host_index = 0;
8072                 for (i = 0; i < ioc->reply_post_queue_depth; i++)
8073                         reply_q->reply_post_free[i].Words =
8074                             cpu_to_le64(ULLONG_MAX);
8075                 if (!_base_is_controller_msix_enabled(ioc))
8076                         goto skip_init_reply_post_free_queue;
8077         }
8078  skip_init_reply_post_free_queue:
8079
8080         r = _base_send_ioc_init(ioc);
8081         if (r) {
8082                 /*
8083                  * No need to check IOC state for fault state & issue
8084                  * diag reset during host reset. This check is need
8085                  * only during driver load time.
8086                  */
8087                 if (!ioc->is_driver_loading)
8088                         return r;
8089
8090                 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8091                 if (rc || (_base_send_ioc_init(ioc)))
8092                         return r;
8093         }
8094
8095         /* initialize reply free host index */
8096         ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
8097         writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
8098
8099         /* initialize reply post host index */
8100         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
8101                 if (ioc->combined_reply_queue)
8102                         writel((reply_q->msix_index & 7)<<
8103                            MPI2_RPHI_MSIX_INDEX_SHIFT,
8104                            ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
8105                 else
8106                         writel(reply_q->msix_index <<
8107                                 MPI2_RPHI_MSIX_INDEX_SHIFT,
8108                                 &ioc->chip->ReplyPostHostIndex);
8109
8110                 if (!_base_is_controller_msix_enabled(ioc))
8111                         goto skip_init_reply_post_host_index;
8112         }
8113
8114  skip_init_reply_post_host_index:
8115
8116         mpt3sas_base_unmask_interrupts(ioc);
8117
8118         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
8119                 r = _base_display_fwpkg_version(ioc);
8120                 if (r)
8121                         return r;
8122         }
8123
8124         r = _base_static_config_pages(ioc);
8125         if (r)
8126                 return r;
8127
8128         r = _base_event_notification(ioc);
8129         if (r)
8130                 return r;
8131
8132         if (!ioc->shost_recovery) {
8133
8134                 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
8135                     == 0x80) {
8136                         hide_flag = (u8) (
8137                             le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
8138                             MFG_PAGE10_HIDE_SSDS_MASK);
8139                         if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
8140                                 ioc->mfg_pg10_hide_flag = hide_flag;
8141                 }
8142
8143                 ioc->wait_for_discovery_to_complete =
8144                     _base_determine_wait_on_discovery(ioc);
8145
8146                 return r; /* scan_start and scan_finished support */
8147         }
8148
8149         r = _base_send_port_enable(ioc);
8150         if (r)
8151                 return r;
8152
8153         return r;
8154 }
8155
8156 /**
8157  * mpt3sas_base_free_resources - free resources controller resources
8158  * @ioc: per adapter object
8159  */
8160 void
8161 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
8162 {
8163         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8164
8165         /* synchronizing freeing resource with pci_access_mutex lock */
8166         mutex_lock(&ioc->pci_access_mutex);
8167         if (ioc->chip_phys && ioc->chip) {
8168                 mpt3sas_base_mask_interrupts(ioc);
8169                 ioc->shost_recovery = 1;
8170                 mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8171                 ioc->shost_recovery = 0;
8172         }
8173
8174         mpt3sas_base_unmap_resources(ioc);
8175         mutex_unlock(&ioc->pci_access_mutex);
8176         return;
8177 }
8178
8179 /**
8180  * mpt3sas_base_attach - attach controller instance
8181  * @ioc: per adapter object
8182  *
8183  * Return: 0 for success, non-zero for failure.
8184  */
8185 int
8186 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
8187 {
8188         int r, i, rc;
8189         int cpu_id, last_cpu_id = 0;
8190
8191         dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8192
8193         /* setup cpu_msix_table */
8194         ioc->cpu_count = num_online_cpus();
8195         for_each_online_cpu(cpu_id)
8196                 last_cpu_id = cpu_id;
8197         ioc->cpu_msix_table_sz = last_cpu_id + 1;
8198         ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
8199         ioc->reply_queue_count = 1;
8200         if (!ioc->cpu_msix_table) {
8201                 ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
8202                 r = -ENOMEM;
8203                 goto out_free_resources;
8204         }
8205
8206         if (ioc->is_warpdrive) {
8207                 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
8208                     sizeof(resource_size_t *), GFP_KERNEL);
8209                 if (!ioc->reply_post_host_index) {
8210                         ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
8211                         r = -ENOMEM;
8212                         goto out_free_resources;
8213                 }
8214         }
8215
8216         ioc->smp_affinity_enable = smp_affinity_enable;
8217
8218         ioc->rdpq_array_enable_assigned = 0;
8219         ioc->use_32bit_dma = false;
8220         ioc->dma_mask = 64;
8221         if (ioc->is_aero_ioc)
8222                 ioc->base_readl = &_base_readl_aero;
8223         else
8224                 ioc->base_readl = &_base_readl;
8225         r = mpt3sas_base_map_resources(ioc);
8226         if (r)
8227                 goto out_free_resources;
8228
8229         pci_set_drvdata(ioc->pdev, ioc->shost);
8230         r = _base_get_ioc_facts(ioc);
8231         if (r) {
8232                 rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8233                 if (rc || (_base_get_ioc_facts(ioc)))
8234                         goto out_free_resources;
8235         }
8236
8237         switch (ioc->hba_mpi_version_belonged) {
8238         case MPI2_VERSION:
8239                 ioc->build_sg_scmd = &_base_build_sg_scmd;
8240                 ioc->build_sg = &_base_build_sg;
8241                 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
8242                 ioc->get_msix_index_for_smlio = &_base_get_msix_index;
8243                 break;
8244         case MPI25_VERSION:
8245         case MPI26_VERSION:
8246                 /*
8247                  * In SAS3.0,
8248                  * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
8249                  * Target Status - all require the IEEE formatted scatter gather
8250                  * elements.
8251                  */
8252                 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
8253                 ioc->build_sg = &_base_build_sg_ieee;
8254                 ioc->build_nvme_prp = &_base_build_nvme_prp;
8255                 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
8256                 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
8257                 if (ioc->high_iops_queues)
8258                         ioc->get_msix_index_for_smlio =
8259                                         &_base_get_high_iops_msix_index;
8260                 else
8261                         ioc->get_msix_index_for_smlio = &_base_get_msix_index;
8262                 break;
8263         }
8264         if (ioc->atomic_desc_capable) {
8265                 ioc->put_smid_default = &_base_put_smid_default_atomic;
8266                 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
8267                 ioc->put_smid_fast_path =
8268                                 &_base_put_smid_fast_path_atomic;
8269                 ioc->put_smid_hi_priority =
8270                                 &_base_put_smid_hi_priority_atomic;
8271         } else {
8272                 ioc->put_smid_default = &_base_put_smid_default;
8273                 ioc->put_smid_fast_path = &_base_put_smid_fast_path;
8274                 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
8275                 if (ioc->is_mcpu_endpoint)
8276                         ioc->put_smid_scsi_io =
8277                                 &_base_put_smid_mpi_ep_scsi_io;
8278                 else
8279                         ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
8280         }
8281         /*
8282          * These function pointers for other requests that don't
8283          * the require IEEE scatter gather elements.
8284          *
8285          * For example Configuration Pages and SAS IOUNIT Control don't.
8286          */
8287         ioc->build_sg_mpi = &_base_build_sg;
8288         ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
8289
8290         r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET);
8291         if (r)
8292                 goto out_free_resources;
8293
8294         ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
8295             sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
8296         if (!ioc->pfacts) {
8297                 r = -ENOMEM;
8298                 goto out_free_resources;
8299         }
8300
8301         for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
8302                 r = _base_get_port_facts(ioc, i);
8303                 if (r) {
8304                         rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
8305                         if (rc || (_base_get_port_facts(ioc, i)))
8306                                 goto out_free_resources;
8307                 }
8308         }
8309
8310         r = _base_allocate_memory_pools(ioc);
8311         if (r)
8312                 goto out_free_resources;
8313
8314         if (irqpoll_weight > 0)
8315                 ioc->thresh_hold = irqpoll_weight;
8316         else
8317                 ioc->thresh_hold = ioc->hba_queue_depth/4;
8318
8319         _base_init_irqpolls(ioc);
8320         init_waitqueue_head(&ioc->reset_wq);
8321
8322         /* allocate memory pd handle bitmask list */
8323         ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8324         if (ioc->facts.MaxDevHandle % 8)
8325                 ioc->pd_handles_sz++;
8326         ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
8327             GFP_KERNEL);
8328         if (!ioc->pd_handles) {
8329                 r = -ENOMEM;
8330                 goto out_free_resources;
8331         }
8332         ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
8333             GFP_KERNEL);
8334         if (!ioc->blocking_handles) {
8335                 r = -ENOMEM;
8336                 goto out_free_resources;
8337         }
8338
8339         /* allocate memory for pending OS device add list */
8340         ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
8341         if (ioc->facts.MaxDevHandle % 8)
8342                 ioc->pend_os_device_add_sz++;
8343         ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
8344             GFP_KERNEL);
8345         if (!ioc->pend_os_device_add) {
8346                 r = -ENOMEM;
8347                 goto out_free_resources;
8348         }
8349
8350         ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
8351         ioc->device_remove_in_progress =
8352                 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
8353         if (!ioc->device_remove_in_progress) {
8354                 r = -ENOMEM;
8355                 goto out_free_resources;
8356         }
8357
8358         ioc->fwfault_debug = mpt3sas_fwfault_debug;
8359
8360         /* base internal command bits */
8361         mutex_init(&ioc->base_cmds.mutex);
8362         ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8363         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
8364
8365         /* port_enable command bits */
8366         ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8367         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
8368
8369         /* transport internal command bits */
8370         ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8371         ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
8372         mutex_init(&ioc->transport_cmds.mutex);
8373
8374         /* scsih internal command bits */
8375         ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8376         ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
8377         mutex_init(&ioc->scsih_cmds.mutex);
8378
8379         /* task management internal command bits */
8380         ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8381         ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
8382         mutex_init(&ioc->tm_cmds.mutex);
8383
8384         /* config page internal command bits */
8385         ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8386         ioc->config_cmds.status = MPT3_CMD_NOT_USED;
8387         mutex_init(&ioc->config_cmds.mutex);
8388
8389         /* ctl module internal command bits */
8390         ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
8391         ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
8392         ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
8393         mutex_init(&ioc->ctl_cmds.mutex);
8394
8395         if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
8396             !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
8397             !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
8398             !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
8399                 r = -ENOMEM;
8400                 goto out_free_resources;
8401         }
8402
8403         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
8404                 ioc->event_masks[i] = -1;
8405
8406         /* here we enable the events we care about */
8407         _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
8408         _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
8409         _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
8410         _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
8411         _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
8412         _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
8413         _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
8414         _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
8415         _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
8416         _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
8417         _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
8418         _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
8419         _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
8420         if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
8421                 if (ioc->is_gen35_ioc) {
8422                         _base_unmask_events(ioc,
8423                                 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
8424                         _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
8425                         _base_unmask_events(ioc,
8426                                 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
8427                 }
8428         }
8429         r = _base_make_ioc_operational(ioc);
8430         if (r == -EAGAIN) {
8431                 r = _base_make_ioc_operational(ioc);
8432                 if (r)
8433                         goto out_free_resources;
8434         }
8435
8436         /*
8437          * Copy current copy of IOCFacts in prev_fw_facts
8438          * and it will be used during online firmware upgrade.
8439          */
8440         memcpy(&ioc->prev_fw_facts, &ioc->facts,
8441             sizeof(struct mpt3sas_facts));
8442
8443         ioc->non_operational_loop = 0;
8444         ioc->ioc_coredump_loop = 0;
8445         ioc->got_task_abort_from_ioctl = 0;
8446         return 0;
8447
8448  out_free_resources:
8449
8450         ioc->remove_host = 1;
8451
8452         mpt3sas_base_free_resources(ioc);
8453         _base_release_memory_pools(ioc);
8454         pci_set_drvdata(ioc->pdev, NULL);
8455         kfree(ioc->cpu_msix_table);
8456         if (ioc->is_warpdrive)
8457                 kfree(ioc->reply_post_host_index);
8458         kfree(ioc->pd_handles);
8459         kfree(ioc->blocking_handles);
8460         kfree(ioc->device_remove_in_progress);
8461         kfree(ioc->pend_os_device_add);
8462         kfree(ioc->tm_cmds.reply);
8463         kfree(ioc->transport_cmds.reply);
8464         kfree(ioc->scsih_cmds.reply);
8465         kfree(ioc->config_cmds.reply);
8466         kfree(ioc->base_cmds.reply);
8467         kfree(ioc->port_enable_cmds.reply);
8468         kfree(ioc->ctl_cmds.reply);
8469         kfree(ioc->ctl_cmds.sense);
8470         kfree(ioc->pfacts);
8471         ioc->ctl_cmds.reply = NULL;
8472         ioc->base_cmds.reply = NULL;
8473         ioc->tm_cmds.reply = NULL;
8474         ioc->scsih_cmds.reply = NULL;
8475         ioc->transport_cmds.reply = NULL;
8476         ioc->config_cmds.reply = NULL;
8477         ioc->pfacts = NULL;
8478         return r;
8479 }
8480
8481
8482 /**
8483  * mpt3sas_base_detach - remove controller instance
8484  * @ioc: per adapter object
8485  */
8486 void
8487 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
8488 {
8489         dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
8490
8491         mpt3sas_base_stop_watchdog(ioc);
8492         mpt3sas_base_free_resources(ioc);
8493         _base_release_memory_pools(ioc);
8494         mpt3sas_free_enclosure_list(ioc);
8495         pci_set_drvdata(ioc->pdev, NULL);
8496         kfree(ioc->cpu_msix_table);
8497         if (ioc->is_warpdrive)
8498                 kfree(ioc->reply_post_host_index);
8499         kfree(ioc->pd_handles);
8500         kfree(ioc->blocking_handles);
8501         kfree(ioc->device_remove_in_progress);
8502         kfree(ioc->pend_os_device_add);
8503         kfree(ioc->pfacts);
8504         kfree(ioc->ctl_cmds.reply);
8505         kfree(ioc->ctl_cmds.sense);
8506         kfree(ioc->base_cmds.reply);
8507         kfree(ioc->port_enable_cmds.reply);
8508         kfree(ioc->tm_cmds.reply);
8509         kfree(ioc->transport_cmds.reply);
8510         kfree(ioc->scsih_cmds.reply);
8511         kfree(ioc->config_cmds.reply);
8512 }
8513
8514 /**
8515  * _base_pre_reset_handler - pre reset handler
8516  * @ioc: per adapter object
8517  */
8518 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc)
8519 {
8520         mpt3sas_scsih_pre_reset_handler(ioc);
8521         mpt3sas_ctl_pre_reset_handler(ioc);
8522         dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
8523 }
8524
8525 /**
8526  * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
8527  * @ioc: per adapter object
8528  */
8529 static void
8530 _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
8531 {
8532         dtmprintk(ioc,
8533             ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
8534         if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
8535                 ioc->transport_cmds.status |= MPT3_CMD_RESET;
8536                 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
8537                 complete(&ioc->transport_cmds.done);
8538         }
8539         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
8540                 ioc->base_cmds.status |= MPT3_CMD_RESET;
8541                 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
8542                 complete(&ioc->base_cmds.done);
8543         }
8544         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
8545                 ioc->port_enable_failed = 1;
8546                 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
8547                 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
8548                 if (ioc->is_driver_loading) {
8549                         ioc->start_scan_failed =
8550                                 MPI2_IOCSTATUS_INTERNAL_ERROR;
8551                         ioc->start_scan = 0;
8552                 } else {
8553                         complete(&ioc->port_enable_cmds.done);
8554                 }
8555         }
8556         if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
8557                 ioc->config_cmds.status |= MPT3_CMD_RESET;
8558                 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
8559                 ioc->config_cmds.smid = USHRT_MAX;
8560                 complete(&ioc->config_cmds.done);
8561         }
8562 }
8563
8564 /**
8565  * _base_clear_outstanding_commands - clear all outstanding commands
8566  * @ioc: per adapter object
8567  */
8568 static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
8569 {
8570         mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
8571         mpt3sas_ctl_clear_outstanding_ioctls(ioc);
8572         _base_clear_outstanding_mpt_commands(ioc);
8573 }
8574
8575 /**
8576  * _base_reset_done_handler - reset done handler
8577  * @ioc: per adapter object
8578  */
8579 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc)
8580 {
8581         mpt3sas_scsih_reset_done_handler(ioc);
8582         mpt3sas_ctl_reset_done_handler(ioc);
8583         dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
8584 }
8585
8586 /**
8587  * mpt3sas_wait_for_commands_to_complete - reset controller
8588  * @ioc: Pointer to MPT_ADAPTER structure
8589  *
8590  * This function is waiting 10s for all pending commands to complete
8591  * prior to putting controller in reset.
8592  */
8593 void
8594 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
8595 {
8596         u32 ioc_state;
8597
8598         ioc->pending_io_count = 0;
8599
8600         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8601         if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
8602                 return;
8603
8604         /* pending command count */
8605         ioc->pending_io_count = scsi_host_busy(ioc->shost);
8606
8607         if (!ioc->pending_io_count)
8608                 return;
8609
8610         /* wait for pending commands to complete */
8611         wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
8612 }
8613
8614 /**
8615  * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
8616  *     attributes during online firmware upgrade and update the corresponding
8617  *     IOC variables accordingly.
8618  *
8619  * @ioc: Pointer to MPT_ADAPTER structure
8620  */
8621 static int
8622 _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
8623 {
8624         u16 pd_handles_sz;
8625         void *pd_handles = NULL, *blocking_handles = NULL;
8626         void *pend_os_device_add = NULL, *device_remove_in_progress = NULL;
8627         struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
8628
8629         if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
8630                 pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
8631                 if (ioc->facts.MaxDevHandle % 8)
8632                         pd_handles_sz++;
8633
8634                 pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
8635                     GFP_KERNEL);
8636                 if (!pd_handles) {
8637                         ioc_info(ioc,
8638                             "Unable to allocate the memory for pd_handles of sz: %d\n",
8639                             pd_handles_sz);
8640                         return -ENOMEM;
8641                 }
8642                 memset(pd_handles + ioc->pd_handles_sz, 0,
8643                     (pd_handles_sz - ioc->pd_handles_sz));
8644                 ioc->pd_handles = pd_handles;
8645
8646                 blocking_handles = krealloc(ioc->blocking_handles,
8647                     pd_handles_sz, GFP_KERNEL);
8648                 if (!blocking_handles) {
8649                         ioc_info(ioc,
8650                             "Unable to allocate the memory for "
8651                             "blocking_handles of sz: %d\n",
8652                             pd_handles_sz);
8653                         return -ENOMEM;
8654                 }
8655                 memset(blocking_handles + ioc->pd_handles_sz, 0,
8656                     (pd_handles_sz - ioc->pd_handles_sz));
8657                 ioc->blocking_handles = blocking_handles;
8658                 ioc->pd_handles_sz = pd_handles_sz;
8659
8660                 pend_os_device_add = krealloc(ioc->pend_os_device_add,
8661                     pd_handles_sz, GFP_KERNEL);
8662                 if (!pend_os_device_add) {
8663                         ioc_info(ioc,
8664                             "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
8665                             pd_handles_sz);
8666                         return -ENOMEM;
8667                 }
8668                 memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
8669                     (pd_handles_sz - ioc->pend_os_device_add_sz));
8670                 ioc->pend_os_device_add = pend_os_device_add;
8671                 ioc->pend_os_device_add_sz = pd_handles_sz;
8672
8673                 device_remove_in_progress = krealloc(
8674                     ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
8675                 if (!device_remove_in_progress) {
8676                         ioc_info(ioc,
8677                             "Unable to allocate the memory for "
8678                             "device_remove_in_progress of sz: %d\n "
8679                             , pd_handles_sz);
8680                         return -ENOMEM;
8681                 }
8682                 memset(device_remove_in_progress +
8683                     ioc->device_remove_in_progress_sz, 0,
8684                     (pd_handles_sz - ioc->device_remove_in_progress_sz));
8685                 ioc->device_remove_in_progress = device_remove_in_progress;
8686                 ioc->device_remove_in_progress_sz = pd_handles_sz;
8687         }
8688
8689         memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
8690         return 0;
8691 }
8692
8693 /**
8694  * mpt3sas_base_hard_reset_handler - reset controller
8695  * @ioc: Pointer to MPT_ADAPTER structure
8696  * @type: FORCE_BIG_HAMMER or SOFT_RESET
8697  *
8698  * Return: 0 for success, non-zero for failure.
8699  */
8700 int
8701 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
8702         enum reset_type type)
8703 {
8704         int r;
8705         unsigned long flags;
8706         u32 ioc_state;
8707         u8 is_fault = 0, is_trigger = 0;
8708
8709         dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
8710
8711         if (ioc->pci_error_recovery) {
8712                 ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
8713                 r = 0;
8714                 goto out_unlocked;
8715         }
8716
8717         if (mpt3sas_fwfault_debug)
8718                 mpt3sas_halt_firmware(ioc);
8719
8720         /* wait for an active reset in progress to complete */
8721         mutex_lock(&ioc->reset_in_progress_mutex);
8722
8723         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8724         ioc->shost_recovery = 1;
8725         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8726
8727         if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8728             MPT3_DIAG_BUFFER_IS_REGISTERED) &&
8729             (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
8730             MPT3_DIAG_BUFFER_IS_RELEASED))) {
8731                 is_trigger = 1;
8732                 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
8733                 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT ||
8734                     (ioc_state & MPI2_IOC_STATE_MASK) ==
8735                     MPI2_IOC_STATE_COREDUMP) {
8736                         is_fault = 1;
8737                         ioc->htb_rel.trigger_info_dwords[1] =
8738                             (ioc_state & MPI2_DOORBELL_DATA_MASK);
8739                 }
8740         }
8741         _base_pre_reset_handler(ioc);
8742         mpt3sas_wait_for_commands_to_complete(ioc);
8743         mpt3sas_base_mask_interrupts(ioc);
8744         mpt3sas_base_pause_mq_polling(ioc);
8745         r = mpt3sas_base_make_ioc_ready(ioc, type);
8746         if (r)
8747                 goto out;
8748         _base_clear_outstanding_commands(ioc);
8749
8750         /* If this hard reset is called while port enable is active, then
8751          * there is no reason to call make_ioc_operational
8752          */
8753         if (ioc->is_driver_loading && ioc->port_enable_failed) {
8754                 ioc->remove_host = 1;
8755                 r = -EFAULT;
8756                 goto out;
8757         }
8758         r = _base_get_ioc_facts(ioc);
8759         if (r)
8760                 goto out;
8761
8762         r = _base_check_ioc_facts_changes(ioc);
8763         if (r) {
8764                 ioc_info(ioc,
8765                     "Some of the parameters got changed in this new firmware"
8766                     " image and it requires system reboot\n");
8767                 goto out;
8768         }
8769         if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
8770                 panic("%s: Issue occurred with flashing controller firmware."
8771                       "Please reboot the system and ensure that the correct"
8772                       " firmware version is running\n", ioc->name);
8773
8774         r = _base_make_ioc_operational(ioc);
8775         if (!r)
8776                 _base_reset_done_handler(ioc);
8777
8778  out:
8779         ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
8780
8781         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
8782         ioc->shost_recovery = 0;
8783         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
8784         ioc->ioc_reset_count++;
8785         mutex_unlock(&ioc->reset_in_progress_mutex);
8786         mpt3sas_base_resume_mq_polling(ioc);
8787
8788  out_unlocked:
8789         if ((r == 0) && is_trigger) {
8790                 if (is_fault)
8791                         mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
8792                 else
8793                         mpt3sas_trigger_master(ioc,
8794                             MASTER_TRIGGER_ADAPTER_RESET);
8795         }
8796         dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
8797         return r;
8798 }