drivers/scsi/mpt3sas/mpt3sas_base.c

   1 /*
   2  * This is the Fusion MPT base driver providing common API layer interface
   3  * for access to MPT (Message Passing Technology) firmware.
   4  *
   5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
   6  * Copyright (C) 2012-2014  LSI Corporation
   7  * Copyright (C) 2013-2014 Avago Technologies
   8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * NO WARRANTY
  21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25  * solely responsible for determining the appropriateness of using and
  26  * distributing the Program and assumes all risks associated with its
  27  * exercise of rights under this Agreement, including but not limited to
  28  * the risks and costs of program errors, damage to or loss of data,
  29  * programs or equipment, and unavailability or interruption of operations.
  30
  31  * DISCLAIMER OF LIABILITY
  32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39
  40  * You should have received a copy of the GNU General Public License
  41  * along with this program; if not, write to the Free Software
  42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
  43  * USA.
  44  */
  45
  46 #include <linux/kernel.h>
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/init.h>
  50 #include <linux/slab.h>
  51 #include <linux/types.h>
  52 #include <linux/pci.h>
  53 #include <linux/kdev_t.h>
  54 #include <linux/blkdev.h>
  55 #include <linux/delay.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/dma-mapping.h>
  58 #include <linux/io.h>
  59 #include <linux/time.h>
  60 #include <linux/ktime.h>
  61 #include <linux/kthread.h>
  62 #include <linux/aer.h>
  63
  64
  65 #include "mpt3sas_base.h"
  66
  67 static MPT_CALLBACK     mpt_callbacks[MPT_MAX_CALLBACKS];
  68
  69
  70 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  71
  72  /* maximum controller queue depth */
  73 #define MAX_HBA_QUEUE_DEPTH     30000
  74 #define MAX_CHAIN_DEPTH         100000
  75 static int max_queue_depth = -1;
  76 module_param(max_queue_depth, int, 0);
  77 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  78
  79 static int max_sgl_entries = -1;
  80 module_param(max_sgl_entries, int, 0);
  81 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  82
  83 static int msix_disable = -1;
  84 module_param(msix_disable, int, 0);
  85 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  86
  87 static int smp_affinity_enable = 1;
  88 module_param(smp_affinity_enable, int, S_IRUGO);
  89 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
  90
  91 static int max_msix_vectors = -1;
  92 module_param(max_msix_vectors, int, 0);
  93 MODULE_PARM_DESC(max_msix_vectors,
  94         " max msix vectors");
  95
  96 static int mpt3sas_fwfault_debug;
  97 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
  98         " enable detection of firmware fault and halt firmware - (default=0)");
  99
 100 static int
 101 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
 102
 103 /**
 104  * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
 105  *
 106  */
 107 static int
 108 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
 109 {
 110         int ret = param_set_int(val, kp);
 111         struct MPT3SAS_ADAPTER *ioc;
 112
 113         if (ret)
 114                 return ret;
 115
 116         /* global ioc spinlock to protect controller list on list operations */
 117         pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
 118         spin_lock(&gioc_lock);
 119         list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
 120                 ioc->fwfault_debug = mpt3sas_fwfault_debug;
 121         spin_unlock(&gioc_lock);
 122         return 0;
 123 }
 124 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
 125         param_get_int, &mpt3sas_fwfault_debug, 0644);
 126
 127 /**
 128  *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
 129  * @arg: input argument, used to derive ioc
 130  *
 131  * Return 0 if controller is removed from pci subsystem.
 132  * Return -1 for other case.
 133  */
 134 static int mpt3sas_remove_dead_ioc_func(void *arg)
 135 {
 136         struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
 137         struct pci_dev *pdev;
 138
 139         if ((ioc == NULL))
 140                 return -1;
 141
 142         pdev = ioc->pdev;
 143         if ((pdev == NULL))
 144                 return -1;
 145         pci_stop_and_remove_bus_device_locked(pdev);
 146         return 0;
 147 }
 148
 149 /**
 150  * _base_fault_reset_work - workq handling ioc fault conditions
 151  * @work: input argument, used to derive ioc
 152  * Context: sleep.
 153  *
 154  * Return nothing.
 155  */
 156 static void
 157 _base_fault_reset_work(struct work_struct *work)
 158 {
 159         struct MPT3SAS_ADAPTER *ioc =
 160             container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
 161         unsigned long    flags;
 162         u32 doorbell;
 163         int rc;
 164         struct task_struct *p;
 165
 166
 167         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 168         if (ioc->shost_recovery || ioc->pci_error_recovery)
 169                 goto rearm_timer;
 170         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 171
 172         doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 173         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
 174                 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
 175                     ioc->name);
 176
 177                 /* It may be possible that EEH recovery can resolve some of
 178                  * pci bus failure issues rather removing the dead ioc function
 179                  * by considering controller is in a non-operational state. So
 180                  * here priority is given to the EEH recovery. If it doesn't
 181                  * not resolve this issue, mpt3sas driver will consider this
 182                  * controller to non-operational state and remove the dead ioc
 183                  * function.
 184                  */
 185                 if (ioc->non_operational_loop++ < 5) {
 186                         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
 187                                                          flags);
 188                         goto rearm_timer;
 189                 }
 190
 191                 /*
 192                  * Call _scsih_flush_pending_cmds callback so that we flush all
 193                  * pending commands back to OS. This call is required to aovid
 194                  * deadlock at block layer. Dead IOC will fail to do diag reset,
 195                  * and this call is safe since dead ioc will never return any
 196                  * command back from HW.
 197                  */
 198                 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
 199                 /*
 200                  * Set remove_host flag early since kernel thread will
 201                  * take some time to execute.
 202                  */
 203                 ioc->remove_host = 1;
 204                 /*Remove the Dead Host */
 205                 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
 206                     "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
 207                 if (IS_ERR(p))
 208                         pr_err(MPT3SAS_FMT
 209                         "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
 210                         ioc->name, __func__);
 211                 else
 212                         pr_err(MPT3SAS_FMT
 213                         "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
 214                         ioc->name, __func__);
 215                 return; /* don't rearm timer */
 216         }
 217
 218         ioc->non_operational_loop = 0;
 219
 220         if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
 221                 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 222                 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
 223                     __func__, (rc == 0) ? "success" : "failed");
 224                 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 225                 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
 226                         mpt3sas_base_fault_info(ioc, doorbell &
 227                             MPI2_DOORBELL_DATA_MASK);
 228                 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
 229                     MPI2_IOC_STATE_OPERATIONAL)
 230                         return; /* don't rearm timer */
 231         }
 232
 233         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 234  rearm_timer:
 235         if (ioc->fault_reset_work_q)
 236                 queue_delayed_work(ioc->fault_reset_work_q,
 237                     &ioc->fault_reset_work,
 238                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 239         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 240 }
 241
 242 /**
 243  * mpt3sas_base_start_watchdog - start the fault_reset_work_q
 244  * @ioc: per adapter object
 245  * Context: sleep.
 246  *
 247  * Return nothing.
 248  */
 249 void
 250 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
 251 {
 252         unsigned long    flags;
 253
 254         if (ioc->fault_reset_work_q)
 255                 return;
 256
 257         /* initialize fault polling */
 258
 259         INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
 260         snprintf(ioc->fault_reset_work_q_name,
 261             sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
 262             ioc->driver_name, ioc->id);
 263         ioc->fault_reset_work_q =
 264                 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
 265         if (!ioc->fault_reset_work_q) {
 266                 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
 267                     ioc->name, __func__, __LINE__);
 268                         return;
 269         }
 270         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 271         if (ioc->fault_reset_work_q)
 272                 queue_delayed_work(ioc->fault_reset_work_q,
 273                     &ioc->fault_reset_work,
 274                     msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 275         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 276 }
 277
 278 /**
 279  * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
 280  * @ioc: per adapter object
 281  * Context: sleep.
 282  *
 283  * Return nothing.
 284  */
 285 void
 286 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
 287 {
 288         unsigned long flags;
 289         struct workqueue_struct *wq;
 290
 291         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 292         wq = ioc->fault_reset_work_q;
 293         ioc->fault_reset_work_q = NULL;
 294         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 295         if (wq) {
 296                 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
 297                         flush_workqueue(wq);
 298                 destroy_workqueue(wq);
 299         }
 300 }
 301
 302 /**
 303  * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
 304  * @ioc: per adapter object
 305  * @fault_code: fault code
 306  *
 307  * Return nothing.
 308  */
 309 void
 310 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
 311 {
 312         pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
 313             ioc->name, fault_code);
 314 }
 315
 316 /**
 317  * mpt3sas_halt_firmware - halt's mpt controller firmware
 318  * @ioc: per adapter object
 319  *
 320  * For debugging timeout related issues.  Writing 0xCOFFEE00
 321  * to the doorbell register will halt controller firmware. With
 322  * the purpose to stop both driver and firmware, the enduser can
 323  * obtain a ring buffer from controller UART.
 324  */
 325 void
 326 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
 327 {
 328         u32 doorbell;
 329
 330         if (!ioc->fwfault_debug)
 331                 return;
 332
 333         dump_stack();
 334
 335         doorbell = readl(&ioc->chip->Doorbell);
 336         if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
 337                 mpt3sas_base_fault_info(ioc , doorbell);
 338         else {
 339                 writel(0xC0FFEE00, &ioc->chip->Doorbell);
 340                 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
 341                         ioc->name);
 342         }
 343
 344         if (ioc->fwfault_debug == 2)
 345                 for (;;)
 346                         ;
 347         else
 348                 panic("panic in %s\n", __func__);
 349 }
 350
 351 /**
 352  * _base_sas_ioc_info - verbose translation of the ioc status
 353  * @ioc: per adapter object
 354  * @mpi_reply: reply mf payload returned from firmware
 355  * @request_hdr: request mf
 356  *
 357  * Return nothing.
 358  */
 359 static void
 360 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
 361         MPI2RequestHeader_t *request_hdr)
 362 {
 363         u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
 364             MPI2_IOCSTATUS_MASK;
 365         char *desc = NULL;
 366         u16 frame_sz;
 367         char *func_str = NULL;
 368
 369         /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
 370         if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
 371             request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
 372             request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
 373                 return;
 374
 375         if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
 376                 return;
 377
 378         switch (ioc_status) {
 379
 380 /****************************************************************************
 381 *  Common IOCStatus values for all replies
 382 ****************************************************************************/
 383
 384         case MPI2_IOCSTATUS_INVALID_FUNCTION:
 385                 desc = "invalid function";
 386                 break;
 387         case MPI2_IOCSTATUS_BUSY:
 388                 desc = "busy";
 389                 break;
 390         case MPI2_IOCSTATUS_INVALID_SGL:
 391                 desc = "invalid sgl";
 392                 break;
 393         case MPI2_IOCSTATUS_INTERNAL_ERROR:
 394                 desc = "internal error";
 395                 break;
 396         case MPI2_IOCSTATUS_INVALID_VPID:
 397                 desc = "invalid vpid";
 398                 break;
 399         case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
 400                 desc = "insufficient resources";
 401                 break;
 402         case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
 403                 desc = "insufficient power";
 404                 break;
 405         case MPI2_IOCSTATUS_INVALID_FIELD:
 406                 desc = "invalid field";
 407                 break;
 408         case MPI2_IOCSTATUS_INVALID_STATE:
 409                 desc = "invalid state";
 410                 break;
 411         case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
 412                 desc = "op state not supported";
 413                 break;
 414
 415 /****************************************************************************
 416 *  Config IOCStatus values
 417 ****************************************************************************/
 418
 419         case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
 420                 desc = "config invalid action";
 421                 break;
 422         case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
 423                 desc = "config invalid type";
 424                 break;
 425         case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
 426                 desc = "config invalid page";
 427                 break;
 428         case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
 429                 desc = "config invalid data";
 430                 break;
 431         case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
 432                 desc = "config no defaults";
 433                 break;
 434         case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
 435                 desc = "config cant commit";
 436                 break;
 437
 438 /****************************************************************************
 439 *  SCSI IO Reply
 440 ****************************************************************************/
 441
 442         case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
 443         case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
 444         case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
 445         case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
 446         case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
 447         case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
 448         case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
 449         case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
 450         case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
 451         case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
 452         case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
 453         case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
 454                 break;
 455
 456 /****************************************************************************
 457 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
 458 ****************************************************************************/
 459
 460         case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
 461                 desc = "eedp guard error";
 462                 break;
 463         case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
 464                 desc = "eedp ref tag error";
 465                 break;
 466         case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
 467                 desc = "eedp app tag error";
 468                 break;
 469
 470 /****************************************************************************
 471 *  SCSI Target values
 472 ****************************************************************************/
 473
 474         case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
 475                 desc = "target invalid io index";
 476                 break;
 477         case MPI2_IOCSTATUS_TARGET_ABORTED:
 478                 desc = "target aborted";
 479                 break;
 480         case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
 481                 desc = "target no conn retryable";
 482                 break;
 483         case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
 484                 desc = "target no connection";
 485                 break;
 486         case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
 487                 desc = "target xfer count mismatch";
 488                 break;
 489         case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
 490                 desc = "target data offset error";
 491                 break;
 492         case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
 493                 desc = "target too much write data";
 494                 break;
 495         case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
 496                 desc = "target iu too short";
 497                 break;
 498         case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
 499                 desc = "target ack nak timeout";
 500                 break;
 501         case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
 502                 desc = "target nak received";
 503                 break;
 504
 505 /****************************************************************************
 506 *  Serial Attached SCSI values
 507 ****************************************************************************/
 508
 509         case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
 510                 desc = "smp request failed";
 511                 break;
 512         case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
 513                 desc = "smp data overrun";
 514                 break;
 515
 516 /****************************************************************************
 517 *  Diagnostic Buffer Post / Diagnostic Release values
 518 ****************************************************************************/
 519
 520         case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
 521                 desc = "diagnostic released";
 522                 break;
 523         default:
 524                 break;
 525         }
 526
 527         if (!desc)
 528                 return;
 529
 530         switch (request_hdr->Function) {
 531         case MPI2_FUNCTION_CONFIG:
 532                 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
 533                 func_str = "config_page";
 534                 break;
 535         case MPI2_FUNCTION_SCSI_TASK_MGMT:
 536                 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
 537                 func_str = "task_mgmt";
 538                 break;
 539         case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
 540                 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
 541                 func_str = "sas_iounit_ctl";
 542                 break;
 543         case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
 544                 frame_sz = sizeof(Mpi2SepRequest_t);
 545                 func_str = "enclosure";
 546                 break;
 547         case MPI2_FUNCTION_IOC_INIT:
 548                 frame_sz = sizeof(Mpi2IOCInitRequest_t);
 549                 func_str = "ioc_init";
 550                 break;
 551         case MPI2_FUNCTION_PORT_ENABLE:
 552                 frame_sz = sizeof(Mpi2PortEnableRequest_t);
 553                 func_str = "port_enable";
 554                 break;
 555         case MPI2_FUNCTION_SMP_PASSTHROUGH:
 556                 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
 557                 func_str = "smp_passthru";
 558                 break;
 559         default:
 560                 frame_sz = 32;
 561                 func_str = "unknown";
 562                 break;
 563         }
 564
 565         pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
 566                 ioc->name, desc, ioc_status, request_hdr, func_str);
 567
 568         _debug_dump_mf(request_hdr, frame_sz/4);
 569 }
 570
 571 /**
 572  * _base_display_event_data - verbose translation of firmware asyn events
 573  * @ioc: per adapter object
 574  * @mpi_reply: reply mf payload returned from firmware
 575  *
 576  * Return nothing.
 577  */
 578 static void
 579 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
 580         Mpi2EventNotificationReply_t *mpi_reply)
 581 {
 582         char *desc = NULL;
 583         u16 event;
 584
 585         if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
 586                 return;
 587
 588         event = le16_to_cpu(mpi_reply->Event);
 589
 590         switch (event) {
 591         case MPI2_EVENT_LOG_DATA:
 592                 desc = "Log Data";
 593                 break;
 594         case MPI2_EVENT_STATE_CHANGE:
 595                 desc = "Status Change";
 596                 break;
 597         case MPI2_EVENT_HARD_RESET_RECEIVED:
 598                 desc = "Hard Reset Received";
 599                 break;
 600         case MPI2_EVENT_EVENT_CHANGE:
 601                 desc = "Event Change";
 602                 break;
 603         case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
 604                 desc = "Device Status Change";
 605                 break;
 606         case MPI2_EVENT_IR_OPERATION_STATUS:
 607                 if (!ioc->hide_ir_msg)
 608                         desc = "IR Operation Status";
 609                 break;
 610         case MPI2_EVENT_SAS_DISCOVERY:
 611         {
 612                 Mpi2EventDataSasDiscovery_t *event_data =
 613                     (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
 614                 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
 615                     (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
 616                     "start" : "stop");
 617                 if (event_data->DiscoveryStatus)
 618                         pr_info("discovery_status(0x%08x)",
 619                             le32_to_cpu(event_data->DiscoveryStatus));
 620                         pr_info("\n");
 621                 return;
 622         }
 623         case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
 624                 desc = "SAS Broadcast Primitive";
 625                 break;
 626         case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 627                 desc = "SAS Init Device Status Change";
 628                 break;
 629         case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
 630                 desc = "SAS Init Table Overflow";
 631                 break;
 632         case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 633                 desc = "SAS Topology Change List";
 634                 break;
 635         case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
 636                 desc = "SAS Enclosure Device Status Change";
 637                 break;
 638         case MPI2_EVENT_IR_VOLUME:
 639                 if (!ioc->hide_ir_msg)
 640                         desc = "IR Volume";
 641                 break;
 642         case MPI2_EVENT_IR_PHYSICAL_DISK:
 643                 if (!ioc->hide_ir_msg)
 644                         desc = "IR Physical Disk";
 645                 break;
 646         case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
 647                 if (!ioc->hide_ir_msg)
 648                         desc = "IR Configuration Change List";
 649                 break;
 650         case MPI2_EVENT_LOG_ENTRY_ADDED:
 651                 if (!ioc->hide_ir_msg)
 652                         desc = "Log Entry Added";
 653                 break;
 654         case MPI2_EVENT_TEMP_THRESHOLD:
 655                 desc = "Temperature Threshold";
 656                 break;
 657         case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
 658                 desc = "Active cable exception";
 659                 break;
 660         }
 661
 662         if (!desc)
 663                 return;
 664
 665         pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
 666 }
 667
 668 /**
 669  * _base_sas_log_info - verbose translation of firmware log info
 670  * @ioc: per adapter object
 671  * @log_info: log info
 672  *
 673  * Return nothing.
 674  */
 675 static void
 676 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
 677 {
 678         union loginfo_type {
 679                 u32     loginfo;
 680                 struct {
 681                         u32     subcode:16;
 682                         u32     code:8;
 683                         u32     originator:4;
 684                         u32     bus_type:4;
 685                 } dw;
 686         };
 687         union loginfo_type sas_loginfo;
 688         char *originator_str = NULL;
 689
 690         sas_loginfo.loginfo = log_info;
 691         if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
 692                 return;
 693
 694         /* each nexus loss loginfo */
 695         if (log_info == 0x31170000)
 696                 return;
 697
 698         /* eat the loginfos associated with task aborts */
 699         if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
 700             0x31140000 || log_info == 0x31130000))
 701                 return;
 702
 703         switch (sas_loginfo.dw.originator) {
 704         case 0:
 705                 originator_str = "IOP";
 706                 break;
 707         case 1:
 708                 originator_str = "PL";
 709                 break;
 710         case 2:
 711                 if (!ioc->hide_ir_msg)
 712                         originator_str = "IR";
 713                 else
 714                         originator_str = "WarpDrive";
 715                 break;
 716         }
 717
 718         pr_warn(MPT3SAS_FMT
 719                 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
 720                 ioc->name, log_info,
 721              originator_str, sas_loginfo.dw.code,
 722              sas_loginfo.dw.subcode);
 723 }
 724
 725 /**
 726  * _base_display_reply_info -
 727  * @ioc: per adapter object
 728  * @smid: system request message index
 729  * @msix_index: MSIX table index supplied by the OS
 730  * @reply: reply message frame(lower 32bit addr)
 731  *
 732  * Return nothing.
 733  */
 734 static void
 735 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
 736         u32 reply)
 737 {
 738         MPI2DefaultReply_t *mpi_reply;
 739         u16 ioc_status;
 740         u32 loginfo = 0;
 741
 742         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 743         if (unlikely(!mpi_reply)) {
 744                 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
 745                     ioc->name, __FILE__, __LINE__, __func__);
 746                 return;
 747         }
 748         ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
 749
 750         if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
 751             (ioc->logging_level & MPT_DEBUG_REPLY)) {
 752                 _base_sas_ioc_info(ioc , mpi_reply,
 753                    mpt3sas_base_get_msg_frame(ioc, smid));
 754         }
 755
 756         if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
 757                 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
 758                 _base_sas_log_info(ioc, loginfo);
 759         }
 760
 761         if (ioc_status || loginfo) {
 762                 ioc_status &= MPI2_IOCSTATUS_MASK;
 763                 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
 764         }
 765 }
 766
 767 /**
 768  * mpt3sas_base_done - base internal command completion routine
 769  * @ioc: per adapter object
 770  * @smid: system request message index
 771  * @msix_index: MSIX table index supplied by the OS
 772  * @reply: reply message frame(lower 32bit addr)
 773  *
 774  * Return 1 meaning mf should be freed from _base_interrupt
 775  *        0 means the mf is freed from this function.
 776  */
 777 u8
 778 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
 779         u32 reply)
 780 {
 781         MPI2DefaultReply_t *mpi_reply;
 782
 783         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 784         if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
 785                 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
 786
 787         if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
 788                 return 1;
 789
 790         ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
 791         if (mpi_reply) {
 792                 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
 793                 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
 794         }
 795         ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
 796
 797         complete(&ioc->base_cmds.done);
 798         return 1;
 799 }
 800
 801 /**
 802  * _base_async_event - main callback handler for firmware asyn events
 803  * @ioc: per adapter object
 804  * @msix_index: MSIX table index supplied by the OS
 805  * @reply: reply message frame(lower 32bit addr)
 806  *
 807  * Return 1 meaning mf should be freed from _base_interrupt
 808  *        0 means the mf is freed from this function.
 809  */
 810 static u8
 811 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
 812 {
 813         Mpi2EventNotificationReply_t *mpi_reply;
 814         Mpi2EventAckRequest_t *ack_request;
 815         u16 smid;
 816         struct _event_ack_list *delayed_event_ack;
 817
 818         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
 819         if (!mpi_reply)
 820                 return 1;
 821         if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
 822                 return 1;
 823
 824         _base_display_event_data(ioc, mpi_reply);
 825
 826         if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
 827                 goto out;
 828         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
 829         if (!smid) {
 830                 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
 831                                         GFP_ATOMIC);
 832                 if (!delayed_event_ack)
 833                         goto out;
 834                 INIT_LIST_HEAD(&delayed_event_ack->list);
 835                 delayed_event_ack->Event = mpi_reply->Event;
 836                 delayed_event_ack->EventContext = mpi_reply->EventContext;
 837                 list_add_tail(&delayed_event_ack->list,
 838                                 &ioc->delayed_event_ack_list);
 839                 dewtprintk(ioc, pr_info(MPT3SAS_FMT
 840                                 "DELAYED: EVENT ACK: event (0x%04x)\n",
 841                                 ioc->name, le16_to_cpu(mpi_reply->Event)));
 842                 goto out;
 843         }
 844
 845         ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
 846         memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
 847         ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
 848         ack_request->Event = mpi_reply->Event;
 849         ack_request->EventContext = mpi_reply->EventContext;
 850         ack_request->VF_ID = 0;  /* TODO */
 851         ack_request->VP_ID = 0;
 852         mpt3sas_base_put_smid_default(ioc, smid);
 853
 854  out:
 855
 856         /* scsih callback handler */
 857         mpt3sas_scsih_event_callback(ioc, msix_index, reply);
 858
 859         /* ctl callback handler */
 860         mpt3sas_ctl_event_callback(ioc, msix_index, reply);
 861
 862         return 1;
 863 }
 864
 865 /**
 866  * _base_get_cb_idx - obtain the callback index
 867  * @ioc: per adapter object
 868  * @smid: system request message index
 869  *
 870  * Return callback index.
 871  */
 872 static u8
 873 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 874 {
 875         int i;
 876         u8 cb_idx;
 877
 878         if (smid < ioc->hi_priority_smid) {
 879                 i = smid - 1;
 880                 cb_idx = ioc->scsi_lookup[i].cb_idx;
 881         } else if (smid < ioc->internal_smid) {
 882                 i = smid - ioc->hi_priority_smid;
 883                 cb_idx = ioc->hpr_lookup[i].cb_idx;
 884         } else if (smid <= ioc->hba_queue_depth) {
 885                 i = smid - ioc->internal_smid;
 886                 cb_idx = ioc->internal_lookup[i].cb_idx;
 887         } else
 888                 cb_idx = 0xFF;
 889         return cb_idx;
 890 }
 891
 892 /**
 893  * _base_mask_interrupts - disable interrupts
 894  * @ioc: per adapter object
 895  *
 896  * Disabling ResetIRQ, Reply and Doorbell Interrupts
 897  *
 898  * Return nothing.
 899  */
 900 static void
 901 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
 902 {
 903         u32 him_register;
 904
 905         ioc->mask_interrupts = 1;
 906         him_register = readl(&ioc->chip->HostInterruptMask);
 907         him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
 908         writel(him_register, &ioc->chip->HostInterruptMask);
 909         readl(&ioc->chip->HostInterruptMask);
 910 }
 911
 912 /**
 913  * _base_unmask_interrupts - enable interrupts
 914  * @ioc: per adapter object
 915  *
 916  * Enabling only Reply Interrupts
 917  *
 918  * Return nothing.
 919  */
 920 static void
 921 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
 922 {
 923         u32 him_register;
 924
 925         him_register = readl(&ioc->chip->HostInterruptMask);
 926         him_register &= ~MPI2_HIM_RIM;
 927         writel(him_register, &ioc->chip->HostInterruptMask);
 928         ioc->mask_interrupts = 0;
 929 }
 930
 931 union reply_descriptor {
 932         u64 word;
 933         struct {
 934                 u32 low;
 935                 u32 high;
 936         } u;
 937 };
 938
 939 /**
 940  * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
 941  * @irq: irq number (not used)
 942  * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
 943  * @r: pt_regs pointer (not used)
 944  *
 945  * Return IRQ_HANDLE if processed, else IRQ_NONE.
 946  */
 947 static irqreturn_t
 948 _base_interrupt(int irq, void *bus_id)
 949 {
 950         struct adapter_reply_queue *reply_q = bus_id;
 951         union reply_descriptor rd;
 952         u32 completed_cmds;
 953         u8 request_desript_type;
 954         u16 smid;
 955         u8 cb_idx;
 956         u32 reply;
 957         u8 msix_index = reply_q->msix_index;
 958         struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
 959         Mpi2ReplyDescriptorsUnion_t *rpf;
 960         u8 rc;
 961
 962         if (ioc->mask_interrupts)
 963                 return IRQ_NONE;
 964
 965         if (!atomic_add_unless(&reply_q->busy, 1, 1))
 966                 return IRQ_NONE;
 967
 968         rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
 969         request_desript_type = rpf->Default.ReplyFlags
 970              & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
 971         if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
 972                 atomic_dec(&reply_q->busy);
 973                 return IRQ_NONE;
 974         }
 975
 976         completed_cmds = 0;
 977         cb_idx = 0xFF;
 978         do {
 979                 rd.word = le64_to_cpu(rpf->Words);
 980                 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
 981                         goto out;
 982                 reply = 0;
 983                 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
 984                 if (request_desript_type ==
 985                     MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
 986                     request_desript_type ==
 987                     MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
 988                         cb_idx = _base_get_cb_idx(ioc, smid);
 989                         if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
 990                             (likely(mpt_callbacks[cb_idx] != NULL))) {
 991                                 rc = mpt_callbacks[cb_idx](ioc, smid,
 992                                     msix_index, 0);
 993                                 if (rc)
 994                                         mpt3sas_base_free_smid(ioc, smid);
 995                         }
 996                 } else if (request_desript_type ==
 997                     MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
 998                         reply = le32_to_cpu(
 999                             rpf->AddressReply.ReplyFrameAddress);
1000                         if (reply > ioc->reply_dma_max_address ||
1001                             reply < ioc->reply_dma_min_address)
1002                                 reply = 0;
1003                         if (smid) {
1004                                 cb_idx = _base_get_cb_idx(ioc, smid);
1005                                 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1006                                     (likely(mpt_callbacks[cb_idx] != NULL))) {
1007                                         rc = mpt_callbacks[cb_idx](ioc, smid,
1008                                             msix_index, reply);
1009                                         if (reply)
1010                                                 _base_display_reply_info(ioc,
1011                                                     smid, msix_index, reply);
1012                                         if (rc)
1013                                                 mpt3sas_base_free_smid(ioc,
1014                                                     smid);
1015                                 }
1016                         } else {
1017                                 _base_async_event(ioc, msix_index, reply);
1018                         }
1019
1020                         /* reply free queue handling */
1021                         if (reply) {
1022                                 ioc->reply_free_host_index =
1023                                     (ioc->reply_free_host_index ==
1024                                     (ioc->reply_free_queue_depth - 1)) ?
1025                                     0 : ioc->reply_free_host_index + 1;
1026                                 ioc->reply_free[ioc->reply_free_host_index] =
1027                                     cpu_to_le32(reply);
1028                                 wmb();
1029                                 writel(ioc->reply_free_host_index,
1030                                     &ioc->chip->ReplyFreeHostIndex);
1031                         }
1032                 }
1033
1034                 rpf->Words = cpu_to_le64(ULLONG_MAX);
1035                 reply_q->reply_post_host_index =
1036                     (reply_q->reply_post_host_index ==
1037                     (ioc->reply_post_queue_depth - 1)) ? 0 :
1038                     reply_q->reply_post_host_index + 1;
1039                 request_desript_type =
1040                     reply_q->reply_post_free[reply_q->reply_post_host_index].
1041                     Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1042                 completed_cmds++;
1043                 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1044                         goto out;
1045                 if (!reply_q->reply_post_host_index)
1046                         rpf = reply_q->reply_post_free;
1047                 else
1048                         rpf++;
1049         } while (1);
1050
1051  out:
1052
1053         if (!completed_cmds) {
1054                 atomic_dec(&reply_q->busy);
1055                 return IRQ_NONE;
1056         }
1057
1058         wmb();
1059         if (ioc->is_warpdrive) {
1060                 writel(reply_q->reply_post_host_index,
1061                 ioc->reply_post_host_index[msix_index]);
1062                 atomic_dec(&reply_q->busy);
1063                 return IRQ_HANDLED;
1064         }
1065
1066         /* Update Reply Post Host Index.
1067          * For those HBA's which support combined reply queue feature
1068          * 1. Get the correct Supplemental Reply Post Host Index Register.
1069          *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1070          *    Index Register address bank i.e replyPostRegisterIndex[],
1071          * 2. Then update this register with new reply host index value
1072          *    in ReplyPostIndex field and the MSIxIndex field with
1073          *    msix_index value reduced to a value between 0 and 7,
1074          *    using a modulo 8 operation. Since each Supplemental Reply Post
1075          *    Host Index Register supports 8 MSI-X vectors.
1076          *
1077          * For other HBA's just update the Reply Post Host Index register with
1078          * new reply host index value in ReplyPostIndex Field and msix_index
1079          * value in MSIxIndex field.
1080          */
1081         if (ioc->msix96_vector)
1082                 writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1083                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1084                         ioc->replyPostRegisterIndex[msix_index/8]);
1085         else
1086                 writel(reply_q->reply_post_host_index | (msix_index <<
1087                         MPI2_RPHI_MSIX_INDEX_SHIFT),
1088                         &ioc->chip->ReplyPostHostIndex);
1089         atomic_dec(&reply_q->busy);
1090         return IRQ_HANDLED;
1091 }
1092
1093 /**
1094  * _base_is_controller_msix_enabled - is controller support muli-reply queues
1095  * @ioc: per adapter object
1096  *
1097  */
1098 static inline int
1099 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1100 {
1101         return (ioc->facts.IOCCapabilities &
1102             MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1103 }
1104
1105 /**
1106  * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1107  * @ioc: per adapter object
1108  * Context: non ISR conext
1109  *
1110  * Called when a Task Management request has completed.
1111  *
1112  * Return nothing.
1113  */
1114 void
1115 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
1116 {
1117         struct adapter_reply_queue *reply_q;
1118
1119         /* If MSIX capability is turned off
1120          * then multi-queues are not enabled
1121          */
1122         if (!_base_is_controller_msix_enabled(ioc))
1123                 return;
1124
1125         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1126                 if (ioc->shost_recovery || ioc->remove_host ||
1127                                 ioc->pci_error_recovery)
1128                         return;
1129                 /* TMs are on msix_index == 0 */
1130                 if (reply_q->msix_index == 0)
1131                         continue;
1132                 synchronize_irq(reply_q->vector);
1133         }
1134 }
1135
1136 /**
1137  * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1138  * @cb_idx: callback index
1139  *
1140  * Return nothing.
1141  */
1142 void
1143 mpt3sas_base_release_callback_handler(u8 cb_idx)
1144 {
1145         mpt_callbacks[cb_idx] = NULL;
1146 }
1147
1148 /**
1149  * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1150  * @cb_func: callback function
1151  *
1152  * Returns cb_func.
1153  */
1154 u8
1155 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1156 {
1157         u8 cb_idx;
1158
1159         for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1160                 if (mpt_callbacks[cb_idx] == NULL)
1161                         break;
1162
1163         mpt_callbacks[cb_idx] = cb_func;
1164         return cb_idx;
1165 }
1166
1167 /**
1168  * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1169  *
1170  * Return nothing.
1171  */
1172 void
1173 mpt3sas_base_initialize_callback_handler(void)
1174 {
1175         u8 cb_idx;
1176
1177         for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1178                 mpt3sas_base_release_callback_handler(cb_idx);
1179 }
1180
1181
1182 /**
1183  * _base_build_zero_len_sge - build zero length sg entry
1184  * @ioc: per adapter object
1185  * @paddr: virtual address for SGE
1186  *
1187  * Create a zero length scatter gather entry to insure the IOCs hardware has
1188  * something to use if the target device goes brain dead and tries
1189  * to send data even when none is asked for.
1190  *
1191  * Return nothing.
1192  */
1193 static void
1194 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1195 {
1196         u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1197             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1198             MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1199             MPI2_SGE_FLAGS_SHIFT);
1200         ioc->base_add_sg_single(paddr, flags_length, -1);
1201 }
1202
1203 /**
1204  * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1205  * @paddr: virtual address for SGE
1206  * @flags_length: SGE flags and data transfer length
1207  * @dma_addr: Physical address
1208  *
1209  * Return nothing.
1210  */
1211 static void
1212 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1213 {
1214         Mpi2SGESimple32_t *sgel = paddr;
1215
1216         flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1217             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1218         sgel->FlagsLength = cpu_to_le32(flags_length);
1219         sgel->Address = cpu_to_le32(dma_addr);
1220 }
1221
1222
1223 /**
1224  * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1225  * @paddr: virtual address for SGE
1226  * @flags_length: SGE flags and data transfer length
1227  * @dma_addr: Physical address
1228  *
1229  * Return nothing.
1230  */
1231 static void
1232 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1233 {
1234         Mpi2SGESimple64_t *sgel = paddr;
1235
1236         flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1237             MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1238         sgel->FlagsLength = cpu_to_le32(flags_length);
1239         sgel->Address = cpu_to_le64(dma_addr);
1240 }
1241
1242 /**
1243  * _base_get_chain_buffer_tracker - obtain chain tracker
1244  * @ioc: per adapter object
1245  * @smid: smid associated to an IO request
1246  *
1247  * Returns chain tracker(from ioc->free_chain_list)
1248  */
1249 static struct chain_tracker *
1250 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1251 {
1252         struct chain_tracker *chain_req;
1253         unsigned long flags;
1254
1255         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1256         if (list_empty(&ioc->free_chain_list)) {
1257                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1258                 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1259                         "chain buffers not available\n", ioc->name));
1260                 return NULL;
1261         }
1262         chain_req = list_entry(ioc->free_chain_list.next,
1263             struct chain_tracker, tracker_list);
1264         list_del_init(&chain_req->tracker_list);
1265         list_add_tail(&chain_req->tracker_list,
1266             &ioc->scsi_lookup[smid - 1].chain_list);
1267         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1268         return chain_req;
1269 }
1270
1271
1272 /**
1273  * _base_build_sg - build generic sg
1274  * @ioc: per adapter object
1275  * @psge: virtual address for SGE
1276  * @data_out_dma: physical address for WRITES
1277  * @data_out_sz: data xfer size for WRITES
1278  * @data_in_dma: physical address for READS
1279  * @data_in_sz: data xfer size for READS
1280  *
1281  * Return nothing.
1282  */
1283 static void
1284 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1285         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1286         size_t data_in_sz)
1287 {
1288         u32 sgl_flags;
1289
1290         if (!data_out_sz && !data_in_sz) {
1291                 _base_build_zero_len_sge(ioc, psge);
1292                 return;
1293         }
1294
1295         if (data_out_sz && data_in_sz) {
1296                 /* WRITE sgel first */
1297                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1298                     MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1299                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1300                 ioc->base_add_sg_single(psge, sgl_flags |
1301                     data_out_sz, data_out_dma);
1302
1303                 /* incr sgel */
1304                 psge += ioc->sge_size;
1305
1306                 /* READ sgel last */
1307                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1308                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1309                     MPI2_SGE_FLAGS_END_OF_LIST);
1310                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1311                 ioc->base_add_sg_single(psge, sgl_flags |
1312                     data_in_sz, data_in_dma);
1313         } else if (data_out_sz) /* WRITE */ {
1314                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1315                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1316                     MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1317                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1318                 ioc->base_add_sg_single(psge, sgl_flags |
1319                     data_out_sz, data_out_dma);
1320         } else if (data_in_sz) /* READ */ {
1321                 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1322                     MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1323                     MPI2_SGE_FLAGS_END_OF_LIST);
1324                 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1325                 ioc->base_add_sg_single(psge, sgl_flags |
1326                     data_in_sz, data_in_dma);
1327         }
1328 }
1329
1330 /* IEEE format sgls */
1331
1332 /**
1333  * _base_add_sg_single_ieee - add sg element for IEEE format
1334  * @paddr: virtual address for SGE
1335  * @flags: SGE flags
1336  * @chain_offset: number of 128 byte elements from start of segment
1337  * @length: data transfer length
1338  * @dma_addr: Physical address
1339  *
1340  * Return nothing.
1341  */
1342 static void
1343 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1344         dma_addr_t dma_addr)
1345 {
1346         Mpi25IeeeSgeChain64_t *sgel = paddr;
1347
1348         sgel->Flags = flags;
1349         sgel->NextChainOffset = chain_offset;
1350         sgel->Length = cpu_to_le32(length);
1351         sgel->Address = cpu_to_le64(dma_addr);
1352 }
1353
1354 /**
1355  * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1356  * @ioc: per adapter object
1357  * @paddr: virtual address for SGE
1358  *
1359  * Create a zero length scatter gather entry to insure the IOCs hardware has
1360  * something to use if the target device goes brain dead and tries
1361  * to send data even when none is asked for.
1362  *
1363  * Return nothing.
1364  */
1365 static void
1366 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1367 {
1368         u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1369                 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1370                 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1371
1372         _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1373 }
1374
1375 /**
1376  * _base_build_sg_scmd - main sg creation routine
1377  * @ioc: per adapter object
1378  * @scmd: scsi command
1379  * @smid: system request message index
1380  * Context: none.
1381  *
1382  * The main routine that builds scatter gather table from a given
1383  * scsi request sent via the .queuecommand main handler.
1384  *
1385  * Returns 0 success, anything else error
1386  */
1387 static int
1388 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1389                 struct scsi_cmnd *scmd, u16 smid)
1390 {
1391         Mpi2SCSIIORequest_t *mpi_request;
1392         dma_addr_t chain_dma;
1393         struct scatterlist *sg_scmd;
1394         void *sg_local, *chain;
1395         u32 chain_offset;
1396         u32 chain_length;
1397         u32 chain_flags;
1398         int sges_left;
1399         u32 sges_in_segment;
1400         u32 sgl_flags;
1401         u32 sgl_flags_last_element;
1402         u32 sgl_flags_end_buffer;
1403         struct chain_tracker *chain_req;
1404
1405         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1406
1407         /* init scatter gather flags */
1408         sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1409         if (scmd->sc_data_direction == DMA_TO_DEVICE)
1410                 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1411         sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1412             << MPI2_SGE_FLAGS_SHIFT;
1413         sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1414             MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1415             << MPI2_SGE_FLAGS_SHIFT;
1416         sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1417
1418         sg_scmd = scsi_sglist(scmd);
1419         sges_left = scsi_dma_map(scmd);
1420         if (sges_left < 0) {
1421                 sdev_printk(KERN_ERR, scmd->device,
1422                  "pci_map_sg failed: request for %d bytes!\n",
1423                  scsi_bufflen(scmd));
1424                 return -ENOMEM;
1425         }
1426
1427         sg_local = &mpi_request->SGL;
1428         sges_in_segment = ioc->max_sges_in_main_message;
1429         if (sges_left <= sges_in_segment)
1430                 goto fill_in_last_segment;
1431
1432         mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1433             (sges_in_segment * ioc->sge_size))/4;
1434
1435         /* fill in main message segment when there is a chain following */
1436         while (sges_in_segment) {
1437                 if (sges_in_segment == 1)
1438                         ioc->base_add_sg_single(sg_local,
1439                             sgl_flags_last_element | sg_dma_len(sg_scmd),
1440                             sg_dma_address(sg_scmd));
1441                 else
1442                         ioc->base_add_sg_single(sg_local, sgl_flags |
1443                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1444                 sg_scmd = sg_next(sg_scmd);
1445                 sg_local += ioc->sge_size;
1446                 sges_left--;
1447                 sges_in_segment--;
1448         }
1449
1450         /* initializing the chain flags and pointers */
1451         chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1452         chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1453         if (!chain_req)
1454                 return -1;
1455         chain = chain_req->chain_buffer;
1456         chain_dma = chain_req->chain_buffer_dma;
1457         do {
1458                 sges_in_segment = (sges_left <=
1459                     ioc->max_sges_in_chain_message) ? sges_left :
1460                     ioc->max_sges_in_chain_message;
1461                 chain_offset = (sges_left == sges_in_segment) ?
1462                     0 : (sges_in_segment * ioc->sge_size)/4;
1463                 chain_length = sges_in_segment * ioc->sge_size;
1464                 if (chain_offset) {
1465                         chain_offset = chain_offset <<
1466                             MPI2_SGE_CHAIN_OFFSET_SHIFT;
1467                         chain_length += ioc->sge_size;
1468                 }
1469                 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1470                     chain_length, chain_dma);
1471                 sg_local = chain;
1472                 if (!chain_offset)
1473                         goto fill_in_last_segment;
1474
1475                 /* fill in chain segments */
1476                 while (sges_in_segment) {
1477                         if (sges_in_segment == 1)
1478                                 ioc->base_add_sg_single(sg_local,
1479                                     sgl_flags_last_element |
1480                                     sg_dma_len(sg_scmd),
1481                                     sg_dma_address(sg_scmd));
1482                         else
1483                                 ioc->base_add_sg_single(sg_local, sgl_flags |
1484                                     sg_dma_len(sg_scmd),
1485                                     sg_dma_address(sg_scmd));
1486                         sg_scmd = sg_next(sg_scmd);
1487                         sg_local += ioc->sge_size;
1488                         sges_left--;
1489                         sges_in_segment--;
1490                 }
1491
1492                 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1493                 if (!chain_req)
1494                         return -1;
1495                 chain = chain_req->chain_buffer;
1496                 chain_dma = chain_req->chain_buffer_dma;
1497         } while (1);
1498
1499
1500  fill_in_last_segment:
1501
1502         /* fill the last segment */
1503         while (sges_left) {
1504                 if (sges_left == 1)
1505                         ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1506                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1507                 else
1508                         ioc->base_add_sg_single(sg_local, sgl_flags |
1509                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1510                 sg_scmd = sg_next(sg_scmd);
1511                 sg_local += ioc->sge_size;
1512                 sges_left--;
1513         }
1514
1515         return 0;
1516 }
1517
1518 /**
1519  * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1520  * @ioc: per adapter object
1521  * @scmd: scsi command
1522  * @smid: system request message index
1523  * Context: none.
1524  *
1525  * The main routine that builds scatter gather table from a given
1526  * scsi request sent via the .queuecommand main handler.
1527  *
1528  * Returns 0 success, anything else error
1529  */
1530 static int
1531 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1532         struct scsi_cmnd *scmd, u16 smid)
1533 {
1534         Mpi2SCSIIORequest_t *mpi_request;
1535         dma_addr_t chain_dma;
1536         struct scatterlist *sg_scmd;
1537         void *sg_local, *chain;
1538         u32 chain_offset;
1539         u32 chain_length;
1540         int sges_left;
1541         u32 sges_in_segment;
1542         u8 simple_sgl_flags;
1543         u8 simple_sgl_flags_last;
1544         u8 chain_sgl_flags;
1545         struct chain_tracker *chain_req;
1546
1547         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1548
1549         /* init scatter gather flags */
1550         simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1551             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1552         simple_sgl_flags_last = simple_sgl_flags |
1553             MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1554         chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1555             MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1556
1557         sg_scmd = scsi_sglist(scmd);
1558         sges_left = scsi_dma_map(scmd);
1559         if (sges_left < 0) {
1560                 sdev_printk(KERN_ERR, scmd->device,
1561                         "pci_map_sg failed: request for %d bytes!\n",
1562                         scsi_bufflen(scmd));
1563                 return -ENOMEM;
1564         }
1565
1566         sg_local = &mpi_request->SGL;
1567         sges_in_segment = (ioc->request_sz -
1568             offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1569         if (sges_left <= sges_in_segment)
1570                 goto fill_in_last_segment;
1571
1572         mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1573             (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1574
1575         /* fill in main message segment when there is a chain following */
1576         while (sges_in_segment > 1) {
1577                 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1578                     sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1579                 sg_scmd = sg_next(sg_scmd);
1580                 sg_local += ioc->sge_size_ieee;
1581                 sges_left--;
1582                 sges_in_segment--;
1583         }
1584
1585         /* initializing the pointers */
1586         chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1587         if (!chain_req)
1588                 return -1;
1589         chain = chain_req->chain_buffer;
1590         chain_dma = chain_req->chain_buffer_dma;
1591         do {
1592                 sges_in_segment = (sges_left <=
1593                     ioc->max_sges_in_chain_message) ? sges_left :
1594                     ioc->max_sges_in_chain_message;
1595                 chain_offset = (sges_left == sges_in_segment) ?
1596                     0 : sges_in_segment;
1597                 chain_length = sges_in_segment * ioc->sge_size_ieee;
1598                 if (chain_offset)
1599                         chain_length += ioc->sge_size_ieee;
1600                 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1601                     chain_offset, chain_length, chain_dma);
1602
1603                 sg_local = chain;
1604                 if (!chain_offset)
1605                         goto fill_in_last_segment;
1606
1607                 /* fill in chain segments */
1608                 while (sges_in_segment) {
1609                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1610                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1611                         sg_scmd = sg_next(sg_scmd);
1612                         sg_local += ioc->sge_size_ieee;
1613                         sges_left--;
1614                         sges_in_segment--;
1615                 }
1616
1617                 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1618                 if (!chain_req)
1619                         return -1;
1620                 chain = chain_req->chain_buffer;
1621                 chain_dma = chain_req->chain_buffer_dma;
1622         } while (1);
1623
1624
1625  fill_in_last_segment:
1626
1627         /* fill the last segment */
1628         while (sges_left > 0) {
1629                 if (sges_left == 1)
1630                         _base_add_sg_single_ieee(sg_local,
1631                             simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1632                             sg_dma_address(sg_scmd));
1633                 else
1634                         _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1635                             sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1636                 sg_scmd = sg_next(sg_scmd);
1637                 sg_local += ioc->sge_size_ieee;
1638                 sges_left--;
1639         }
1640
1641         return 0;
1642 }
1643
1644 /**
1645  * _base_build_sg_ieee - build generic sg for IEEE format
1646  * @ioc: per adapter object
1647  * @psge: virtual address for SGE
1648  * @data_out_dma: physical address for WRITES
1649  * @data_out_sz: data xfer size for WRITES
1650  * @data_in_dma: physical address for READS
1651  * @data_in_sz: data xfer size for READS
1652  *
1653  * Return nothing.
1654  */
1655 static void
1656 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1657         dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1658         size_t data_in_sz)
1659 {
1660         u8 sgl_flags;
1661
1662         if (!data_out_sz && !data_in_sz) {
1663                 _base_build_zero_len_sge_ieee(ioc, psge);
1664                 return;
1665         }
1666
1667         if (data_out_sz && data_in_sz) {
1668                 /* WRITE sgel first */
1669                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1670                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1671                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1672                     data_out_dma);
1673
1674                 /* incr sgel */
1675                 psge += ioc->sge_size_ieee;
1676
1677                 /* READ sgel last */
1678                 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1679                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1680                     data_in_dma);
1681         } else if (data_out_sz) /* WRITE */ {
1682                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1683                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1684                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1685                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1686                     data_out_dma);
1687         } else if (data_in_sz) /* READ */ {
1688                 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1689                     MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1690                     MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1691                 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1692                     data_in_dma);
1693         }
1694 }
1695
1696 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1697
1698 /**
1699  * _base_config_dma_addressing - set dma addressing
1700  * @ioc: per adapter object
1701  * @pdev: PCI device struct
1702  *
1703  * Returns 0 for success, non-zero for failure.
1704  */
1705 static int
1706 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1707 {
1708         struct sysinfo s;
1709         u64 consistent_dma_mask;
1710         /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
1711         int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64;
1712
1713         if (ioc->dma_mask)
1714                 consistent_dma_mask = DMA_BIT_MASK(dma_mask);
1715         else
1716                 consistent_dma_mask = DMA_BIT_MASK(32);
1717
1718         if (sizeof(dma_addr_t) > 4) {
1719                 const uint64_t required_mask =
1720                     dma_get_required_mask(&pdev->dev);
1721                 if ((required_mask > DMA_BIT_MASK(32)) &&
1722                     !pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)) &&
1723                     !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
1724                         ioc->base_add_sg_single = &_base_add_sg_single_64;
1725                         ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1726                         ioc->dma_mask = dma_mask;
1727                         goto out;
1728                 }
1729         }
1730
1731         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1732             && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1733                 ioc->base_add_sg_single = &_base_add_sg_single_32;
1734                 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1735                 ioc->dma_mask = 32;
1736         } else
1737                 return -ENODEV;
1738
1739  out:
1740         si_meminfo(&s);
1741         pr_info(MPT3SAS_FMT
1742                 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1743                 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1744
1745         return 0;
1746 }
1747
1748 static int
1749 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1750                                       struct pci_dev *pdev)
1751 {
1752         if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) {
1753                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1754                         return -ENODEV;
1755         }
1756         return 0;
1757 }
1758
1759 /**
1760  * _base_check_enable_msix - checks MSIX capabable.
1761  * @ioc: per adapter object
1762  *
1763  * Check to see if card is capable of MSIX, and set number
1764  * of available msix vectors
1765  */
1766 static int
1767 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1768 {
1769         int base;
1770         u16 message_control;
1771
1772         /* Check whether controller SAS2008 B0 controller,
1773          * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1774          */
1775         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1776             ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1777                 return -EINVAL;
1778         }
1779
1780         base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1781         if (!base) {
1782                 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1783                         ioc->name));
1784                 return -EINVAL;
1785         }
1786
1787         /* get msix vector count */
1788         /* NUMA_IO not supported for older controllers */
1789         if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1790             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1791             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1792             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1793             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1794             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1795             ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1796                 ioc->msix_vector_count = 1;
1797         else {
1798                 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1799                 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1800         }
1801         dinitprintk(ioc, pr_info(MPT3SAS_FMT
1802                 "msix is supported, vector_count(%d)\n",
1803                 ioc->name, ioc->msix_vector_count));
1804         return 0;
1805 }
1806
1807 /**
1808  * _base_free_irq - free irq
1809  * @ioc: per adapter object
1810  *
1811  * Freeing respective reply_queue from the list.
1812  */
1813 static void
1814 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1815 {
1816         struct adapter_reply_queue *reply_q, *next;
1817
1818         if (list_empty(&ioc->reply_queue_list))
1819                 return;
1820
1821         list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1822                 list_del(&reply_q->list);
1823                 if (smp_affinity_enable) {
1824                         irq_set_affinity_hint(reply_q->vector, NULL);
1825                         free_cpumask_var(reply_q->affinity_hint);
1826                 }
1827                 free_irq(reply_q->vector, reply_q);
1828                 kfree(reply_q);
1829         }
1830 }
1831
1832 /**
1833  * _base_request_irq - request irq
1834  * @ioc: per adapter object
1835  * @index: msix index into vector table
1836  * @vector: irq vector
1837  *
1838  * Inserting respective reply_queue into the list.
1839  */
1840 static int
1841 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1842 {
1843         struct adapter_reply_queue *reply_q;
1844         int r;
1845
1846         reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1847         if (!reply_q) {
1848                 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1849                     ioc->name, (int)sizeof(struct adapter_reply_queue));
1850                 return -ENOMEM;
1851         }
1852         reply_q->ioc = ioc;
1853         reply_q->msix_index = index;
1854         reply_q->vector = vector;
1855
1856         if (smp_affinity_enable) {
1857                 if (!zalloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) {
1858                         kfree(reply_q);
1859                         return -ENOMEM;
1860                 }
1861         }
1862
1863         atomic_set(&reply_q->busy, 0);
1864         if (ioc->msix_enable)
1865                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1866                     ioc->driver_name, ioc->id, index);
1867         else
1868                 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1869                     ioc->driver_name, ioc->id);
1870         r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1871             reply_q);
1872         if (r) {
1873                 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1874                     reply_q->name, vector);
1875                 free_cpumask_var(reply_q->affinity_hint);
1876                 kfree(reply_q);
1877                 return -EBUSY;
1878         }
1879
1880         INIT_LIST_HEAD(&reply_q->list);
1881         list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1882         return 0;
1883 }
1884
1885 /**
1886  * _base_assign_reply_queues - assigning msix index for each cpu
1887  * @ioc: per adapter object
1888  *
1889  * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1890  *
1891  * It would nice if we could call irq_set_affinity, however it is not
1892  * an exported symbol
1893  */
1894 static void
1895 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1896 {
1897         unsigned int cpu, nr_cpus, nr_msix, index = 0;
1898         struct adapter_reply_queue *reply_q;
1899
1900         if (!_base_is_controller_msix_enabled(ioc))
1901                 return;
1902
1903         memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1904
1905         nr_cpus = num_online_cpus();
1906         nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1907                                                ioc->facts.MaxMSIxVectors);
1908         if (!nr_msix)
1909                 return;
1910
1911         cpu = cpumask_first(cpu_online_mask);
1912
1913         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1914
1915                 unsigned int i, group = nr_cpus / nr_msix;
1916
1917                 if (cpu >= nr_cpus)
1918                         break;
1919
1920                 if (index < nr_cpus % nr_msix)
1921                         group++;
1922
1923                 for (i = 0 ; i < group ; i++) {
1924                         ioc->cpu_msix_table[cpu] = index;
1925                         if (smp_affinity_enable)
1926                                 cpumask_or(reply_q->affinity_hint,
1927                                    reply_q->affinity_hint, get_cpu_mask(cpu));
1928                         cpu = cpumask_next(cpu, cpu_online_mask);
1929                 }
1930                 if (smp_affinity_enable)
1931                         if (irq_set_affinity_hint(reply_q->vector,
1932                                            reply_q->affinity_hint))
1933                                 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1934                                  "Err setting affinity hint to irq vector %d\n",
1935                                  ioc->name, reply_q->vector));
1936                 index++;
1937         }
1938 }
1939
1940 /**
1941  * _base_disable_msix - disables msix
1942  * @ioc: per adapter object
1943  *
1944  */
1945 static void
1946 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1947 {
1948         if (!ioc->msix_enable)
1949                 return;
1950         pci_disable_msix(ioc->pdev);
1951         ioc->msix_enable = 0;
1952 }
1953
1954 /**
1955  * _base_enable_msix - enables msix, failback to io_apic
1956  * @ioc: per adapter object
1957  *
1958  */
1959 static int
1960 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1961 {
1962         struct msix_entry *entries, *a;
1963         int r;
1964         int i;
1965         u8 try_msix = 0;
1966
1967         if (msix_disable == -1 || msix_disable == 0)
1968                 try_msix = 1;
1969
1970         if (!try_msix)
1971                 goto try_ioapic;
1972
1973         if (_base_check_enable_msix(ioc) != 0)
1974                 goto try_ioapic;
1975
1976         ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1977             ioc->msix_vector_count);
1978
1979         printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1980           ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1981           ioc->cpu_count, max_msix_vectors);
1982
1983         if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1984                 max_msix_vectors = 8;
1985
1986         if (max_msix_vectors > 0) {
1987                 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1988                         ioc->reply_queue_count);
1989                 ioc->msix_vector_count = ioc->reply_queue_count;
1990         } else if (max_msix_vectors == 0)
1991                 goto try_ioapic;
1992
1993         if (ioc->msix_vector_count < ioc->cpu_count)
1994                 smp_affinity_enable = 0;
1995
1996         entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1997             GFP_KERNEL);
1998         if (!entries) {
1999                 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2000                         "kcalloc failed @ at %s:%d/%s() !!!\n",
2001                         ioc->name, __FILE__, __LINE__, __func__));
2002                 goto try_ioapic;
2003         }
2004
2005         for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
2006                 a->entry = i;
2007
2008         r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
2009         if (r) {
2010                 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2011                         "pci_enable_msix_exact failed (r=%d) !!!\n",
2012                         ioc->name, r));
2013                 kfree(entries);
2014                 goto try_ioapic;
2015         }
2016
2017         ioc->msix_enable = 1;
2018         for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
2019                 r = _base_request_irq(ioc, i, a->vector);
2020                 if (r) {
2021                         _base_free_irq(ioc);
2022                         _base_disable_msix(ioc);
2023                         kfree(entries);
2024                         goto try_ioapic;
2025                 }
2026         }
2027
2028         kfree(entries);
2029         return 0;
2030
2031 /* failback to io_apic interrupt routing */
2032  try_ioapic:
2033
2034         ioc->reply_queue_count = 1;
2035         r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2036
2037         return r;
2038 }
2039
2040 /**
2041  * mpt3sas_base_unmap_resources - free controller resources
2042  * @ioc: per adapter object
2043  */
2044 static void
2045 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2046 {
2047         struct pci_dev *pdev = ioc->pdev;
2048
2049         dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2050                 ioc->name, __func__));
2051
2052         _base_free_irq(ioc);
2053         _base_disable_msix(ioc);
2054
2055         if (ioc->msix96_vector) {
2056                 kfree(ioc->replyPostRegisterIndex);
2057                 ioc->replyPostRegisterIndex = NULL;
2058         }
2059
2060         if (ioc->chip_phys) {
2061                 iounmap(ioc->chip);
2062                 ioc->chip_phys = 0;
2063         }
2064
2065         if (pci_is_enabled(pdev)) {
2066                 pci_release_selected_regions(ioc->pdev, ioc->bars);
2067                 pci_disable_pcie_error_reporting(pdev);
2068                 pci_disable_device(pdev);
2069         }
2070 }
2071
2072 /**
2073  * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2074  * @ioc: per adapter object
2075  *
2076  * Returns 0 for success, non-zero for failure.
2077  */
2078 int
2079 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2080 {
2081         struct pci_dev *pdev = ioc->pdev;
2082         u32 memap_sz;
2083         u32 pio_sz;
2084         int i, r = 0;
2085         u64 pio_chip = 0;
2086         u64 chip_phys = 0;
2087         struct adapter_reply_queue *reply_q;
2088
2089         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2090             ioc->name, __func__));
2091
2092         ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2093         if (pci_enable_device_mem(pdev)) {
2094                 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2095                         ioc->name);
2096                 ioc->bars = 0;
2097                 return -ENODEV;
2098         }
2099
2100
2101         if (pci_request_selected_regions(pdev, ioc->bars,
2102             ioc->driver_name)) {
2103                 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2104                         ioc->name);
2105                 ioc->bars = 0;
2106                 r = -ENODEV;
2107                 goto out_fail;
2108         }
2109
2110 /* AER (Advanced Error Reporting) hooks */
2111         pci_enable_pcie_error_reporting(pdev);
2112
2113         pci_set_master(pdev);
2114
2115
2116         if (_base_config_dma_addressing(ioc, pdev) != 0) {
2117                 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2118                     ioc->name, pci_name(pdev));
2119                 r = -ENODEV;
2120                 goto out_fail;
2121         }
2122
2123         for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2124              (!memap_sz || !pio_sz); i++) {
2125                 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2126                         if (pio_sz)
2127                                 continue;
2128                         pio_chip = (u64)pci_resource_start(pdev, i);
2129                         pio_sz = pci_resource_len(pdev, i);
2130                 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2131                         if (memap_sz)
2132                                 continue;
2133                         ioc->chip_phys = pci_resource_start(pdev, i);
2134                         chip_phys = (u64)ioc->chip_phys;
2135                         memap_sz = pci_resource_len(pdev, i);
2136                         ioc->chip = ioremap(ioc->chip_phys, memap_sz);
2137                 }
2138         }
2139
2140         if (ioc->chip == NULL) {
2141                 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2142                         " or resource not found\n", ioc->name);
2143                 r = -EINVAL;
2144                 goto out_fail;
2145         }
2146
2147         _base_mask_interrupts(ioc);
2148
2149         r = _base_get_ioc_facts(ioc);
2150         if (r)
2151                 goto out_fail;
2152
2153         if (!ioc->rdpq_array_enable_assigned) {
2154                 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2155                 ioc->rdpq_array_enable_assigned = 1;
2156         }
2157
2158         r = _base_enable_msix(ioc);
2159         if (r)
2160                 goto out_fail;
2161
2162         /* Use the Combined reply queue feature only for SAS3 C0 & higher
2163          * revision HBAs and also only when reply queue count is greater than 8
2164          */
2165         if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2166                 /* Determine the Supplemental Reply Post Host Index Registers
2167                  * Addresse. Supplemental Reply Post Host Index Registers
2168                  * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2169                  * each register is at offset bytes of
2170                  * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2171                  */
2172                 ioc->replyPostRegisterIndex = kcalloc(
2173                      MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2174                      sizeof(resource_size_t *), GFP_KERNEL);
2175                 if (!ioc->replyPostRegisterIndex) {
2176                         dfailprintk(ioc, printk(MPT3SAS_FMT
2177                         "allocation for reply Post Register Index failed!!!\n",
2178                                                                    ioc->name));
2179                         r = -ENOMEM;
2180                         goto out_fail;
2181                 }
2182
2183                 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2184                         ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2185                              ((u8 *)&ioc->chip->Doorbell +
2186                              MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2187                              (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2188                 }
2189         } else
2190                 ioc->msix96_vector = 0;
2191
2192         if (ioc->is_warpdrive) {
2193                 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
2194                     &ioc->chip->ReplyPostHostIndex;
2195
2196                 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
2197                         ioc->reply_post_host_index[i] =
2198                         (resource_size_t __iomem *)
2199                         ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
2200                         * 4)));
2201         }
2202
2203         list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2204                 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2205                     reply_q->name,  ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2206                     "IO-APIC enabled"), reply_q->vector);
2207
2208         pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2209             ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2210         pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2211             ioc->name, (unsigned long long)pio_chip, pio_sz);
2212
2213         /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2214         pci_save_state(pdev);
2215         return 0;
2216
2217  out_fail:
2218         mpt3sas_base_unmap_resources(ioc);
2219         return r;
2220 }
2221
2222 /**
2223  * mpt3sas_base_get_msg_frame - obtain request mf pointer
2224  * @ioc: per adapter object
2225  * @smid: system request message index(smid zero is invalid)
2226  *
2227  * Returns virt pointer to message frame.
2228  */
2229 void *
2230 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2231 {
2232         return (void *)(ioc->request + (smid * ioc->request_sz));
2233 }
2234
2235 /**
2236  * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2237  * @ioc: per adapter object
2238  * @smid: system request message index
2239  *
2240  * Returns virt pointer to sense buffer.
2241  */
2242 void *
2243 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2244 {
2245         return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2246 }
2247
2248 /**
2249  * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2250  * @ioc: per adapter object
2251  * @smid: system request message index
2252  *
2253  * Returns phys pointer to the low 32bit address of the sense buffer.
2254  */
2255 __le32
2256 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2257 {
2258         return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2259             SCSI_SENSE_BUFFERSIZE));
2260 }
2261
2262 /**
2263  * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2264  * @ioc: per adapter object
2265  * @phys_addr: lower 32 physical addr of the reply
2266  *
2267  * Converts 32bit lower physical addr into a virt address.
2268  */
2269 void *
2270 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2271 {
2272         if (!phys_addr)
2273                 return NULL;
2274         return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2275 }
2276
2277 static inline u8
2278 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2279 {
2280         return ioc->cpu_msix_table[raw_smp_processor_id()];
2281 }
2282
2283 /**
2284  * mpt3sas_base_get_smid - obtain a free smid from internal queue
2285  * @ioc: per adapter object
2286  * @cb_idx: callback index
2287  *
2288  * Returns smid (zero is invalid)
2289  */
2290 u16
2291 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2292 {
2293         unsigned long flags;
2294         struct request_tracker *request;
2295         u16 smid;
2296
2297         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2298         if (list_empty(&ioc->internal_free_list)) {
2299                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2300                 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2301                     ioc->name, __func__);
2302                 return 0;
2303         }
2304
2305         request = list_entry(ioc->internal_free_list.next,
2306             struct request_tracker, tracker_list);
2307         request->cb_idx = cb_idx;
2308         smid = request->smid;
2309         list_del(&request->tracker_list);
2310         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2311         return smid;
2312 }
2313
2314 /**
2315  * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2316  * @ioc: per adapter object
2317  * @cb_idx: callback index
2318  * @scmd: pointer to scsi command object
2319  *
2320  * Returns smid (zero is invalid)
2321  */
2322 u16
2323 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2324         struct scsi_cmnd *scmd)
2325 {
2326         unsigned long flags;
2327         struct scsiio_tracker *request;
2328         u16 smid;
2329
2330         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2331         if (list_empty(&ioc->free_list)) {
2332                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2333                 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2334                     ioc->name, __func__);
2335                 return 0;
2336         }
2337
2338         request = list_entry(ioc->free_list.next,
2339             struct scsiio_tracker, tracker_list);
2340         request->scmd = scmd;
2341         request->cb_idx = cb_idx;
2342         smid = request->smid;
2343         request->msix_io = _base_get_msix_index(ioc);
2344         list_del(&request->tracker_list);
2345         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2346         return smid;
2347 }
2348
2349 /**
2350  * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2351  * @ioc: per adapter object
2352  * @cb_idx: callback index
2353  *
2354  * Returns smid (zero is invalid)
2355  */
2356 u16
2357 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2358 {
2359         unsigned long flags;
2360         struct request_tracker *request;
2361         u16 smid;
2362
2363         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2364         if (list_empty(&ioc->hpr_free_list)) {
2365                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2366                 return 0;
2367         }
2368
2369         request = list_entry(ioc->hpr_free_list.next,
2370             struct request_tracker, tracker_list);
2371         request->cb_idx = cb_idx;
2372         smid = request->smid;
2373         list_del(&request->tracker_list);
2374         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2375         return smid;
2376 }
2377
2378 /**
2379  * mpt3sas_base_free_smid - put smid back on free_list
2380  * @ioc: per adapter object
2381  * @smid: system request message index
2382  *
2383  * Return nothing.
2384  */
2385 void
2386 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2387 {
2388         unsigned long flags;
2389         int i;
2390         struct chain_tracker *chain_req, *next;
2391
2392         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2393         if (smid < ioc->hi_priority_smid) {
2394                 /* scsiio queue */
2395                 i = smid - 1;
2396                 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2397                         list_for_each_entry_safe(chain_req, next,
2398                             &ioc->scsi_lookup[i].chain_list, tracker_list) {
2399                                 list_del_init(&chain_req->tracker_list);
2400                                 list_add(&chain_req->tracker_list,
2401                                     &ioc->free_chain_list);
2402                         }
2403                 }
2404                 ioc->scsi_lookup[i].cb_idx = 0xFF;
2405                 ioc->scsi_lookup[i].scmd = NULL;
2406                 ioc->scsi_lookup[i].direct_io = 0;
2407                 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2408                 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2409
2410                 /*
2411                  * See _wait_for_commands_to_complete() call with regards
2412                  * to this code.
2413                  */
2414                 if (ioc->shost_recovery && ioc->pending_io_count) {
2415                         if (ioc->pending_io_count == 1)
2416                                 wake_up(&ioc->reset_wq);
2417                         ioc->pending_io_count--;
2418                 }
2419                 return;
2420         } else if (smid < ioc->internal_smid) {
2421                 /* hi-priority */
2422                 i = smid - ioc->hi_priority_smid;
2423                 ioc->hpr_lookup[i].cb_idx = 0xFF;
2424                 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2425         } else if (smid <= ioc->hba_queue_depth) {
2426                 /* internal queue */
2427                 i = smid - ioc->internal_smid;
2428                 ioc->internal_lookup[i].cb_idx = 0xFF;
2429                 list_add(&ioc->internal_lookup[i].tracker_list,
2430                     &ioc->internal_free_list);
2431         }
2432         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2433 }
2434
2435 /**
2436  * _base_writeq - 64 bit write to MMIO
2437  * @ioc: per adapter object
2438  * @b: data payload
2439  * @addr: address in MMIO space
2440  * @writeq_lock: spin lock
2441  *
2442  * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2443  * care of 32 bit environment where its not quarenteed to send the entire word
2444  * in one transfer.
2445  */
2446 #if defined(writeq) && defined(CONFIG_64BIT)
2447 static inline void
2448 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2449 {
2450         writeq(cpu_to_le64(b), addr);
2451 }
2452 #else
2453 static inline void
2454 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2455 {
2456         unsigned long flags;
2457         __u64 data_out = cpu_to_le64(b);
2458
2459         spin_lock_irqsave(writeq_lock, flags);
2460         writel((u32)(data_out), addr);
2461         writel((u32)(data_out >> 32), (addr + 4));
2462         spin_unlock_irqrestore(writeq_lock, flags);
2463 }
2464 #endif
2465
2466 /**
2467  * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2468  * @ioc: per adapter object
2469  * @smid: system request message index
2470  * @handle: device handle
2471  *
2472  * Return nothing.
2473  */
2474 void
2475 mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2476 {
2477         Mpi2RequestDescriptorUnion_t descriptor;
2478         u64 *request = (u64 *)&descriptor;
2479
2480
2481         descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2482         descriptor.SCSIIO.MSIxIndex =  _base_get_msix_index(ioc);
2483         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2484         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2485         descriptor.SCSIIO.LMID = 0;
2486         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2487             &ioc->scsi_lookup_lock);
2488 }
2489
2490 /**
2491  * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2492  * @ioc: per adapter object
2493  * @smid: system request message index
2494  * @handle: device handle
2495  *
2496  * Return nothing.
2497  */
2498 void
2499 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2500         u16 handle)
2501 {
2502         Mpi2RequestDescriptorUnion_t descriptor;
2503         u64 *request = (u64 *)&descriptor;
2504
2505         descriptor.SCSIIO.RequestFlags =
2506             MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2507         descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2508         descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2509         descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2510         descriptor.SCSIIO.LMID = 0;
2511         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2512             &ioc->scsi_lookup_lock);
2513 }
2514
2515 /**
2516  * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2517  * @ioc: per adapter object
2518  * @smid: system request message index
2519  * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
2520  * Return nothing.
2521  */
2522 void
2523 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2524         u16 msix_task)
2525 {
2526         Mpi2RequestDescriptorUnion_t descriptor;
2527         u64 *request = (u64 *)&descriptor;
2528
2529         descriptor.HighPriority.RequestFlags =
2530             MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2531         descriptor.HighPriority.MSIxIndex =  msix_task;
2532         descriptor.HighPriority.SMID = cpu_to_le16(smid);
2533         descriptor.HighPriority.LMID = 0;
2534         descriptor.HighPriority.Reserved1 = 0;
2535         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2536             &ioc->scsi_lookup_lock);
2537 }
2538
2539 /**
2540  * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2541  * @ioc: per adapter object
2542  * @smid: system request message index
2543  *
2544  * Return nothing.
2545  */
2546 void
2547 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2548 {
2549         Mpi2RequestDescriptorUnion_t descriptor;
2550         u64 *request = (u64 *)&descriptor;
2551
2552         descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2553         descriptor.Default.MSIxIndex =  _base_get_msix_index(ioc);
2554         descriptor.Default.SMID = cpu_to_le16(smid);
2555         descriptor.Default.LMID = 0;
2556         descriptor.Default.DescriptorTypeDependent = 0;
2557         _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2558             &ioc->scsi_lookup_lock);
2559 }
2560
2561 /**
2562  * _base_display_OEMs_branding - Display branding string
2563  * @ioc: per adapter object
2564  *
2565  * Return nothing.
2566  */
2567 static void
2568 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
2569 {
2570         if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2571                 return;
2572
2573         switch (ioc->pdev->subsystem_vendor) {
2574         case PCI_VENDOR_ID_INTEL:
2575                 switch (ioc->pdev->device) {
2576                 case MPI2_MFGPAGE_DEVID_SAS2008:
2577                         switch (ioc->pdev->subsystem_device) {
2578                         case MPT2SAS_INTEL_RMS2LL080_SSDID:
2579                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2580                                     MPT2SAS_INTEL_RMS2LL080_BRANDING);
2581                                 break;
2582                         case MPT2SAS_INTEL_RMS2LL040_SSDID:
2583                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2584                                     MPT2SAS_INTEL_RMS2LL040_BRANDING);
2585                                 break;
2586                         case MPT2SAS_INTEL_SSD910_SSDID:
2587                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2588                                     MPT2SAS_INTEL_SSD910_BRANDING);
2589                                 break;
2590                         default:
2591                                 pr_info(MPT3SAS_FMT
2592                                  "Intel(R) Controller: Subsystem ID: 0x%X\n",
2593                                  ioc->name, ioc->pdev->subsystem_device);
2594                                 break;
2595                         }
2596                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2597                         switch (ioc->pdev->subsystem_device) {
2598                         case MPT2SAS_INTEL_RS25GB008_SSDID:
2599                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2600                                     MPT2SAS_INTEL_RS25GB008_BRANDING);
2601                                 break;
2602                         case MPT2SAS_INTEL_RMS25JB080_SSDID:
2603                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2604                                     MPT2SAS_INTEL_RMS25JB080_BRANDING);
2605                                 break;
2606                         case MPT2SAS_INTEL_RMS25JB040_SSDID:
2607                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2608                                     MPT2SAS_INTEL_RMS25JB040_BRANDING);
2609                                 break;
2610                         case MPT2SAS_INTEL_RMS25KB080_SSDID:
2611                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2612                                     MPT2SAS_INTEL_RMS25KB080_BRANDING);
2613                                 break;
2614                         case MPT2SAS_INTEL_RMS25KB040_SSDID:
2615                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2616                                     MPT2SAS_INTEL_RMS25KB040_BRANDING);
2617                                 break;
2618                         case MPT2SAS_INTEL_RMS25LB040_SSDID:
2619                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2620                                     MPT2SAS_INTEL_RMS25LB040_BRANDING);
2621                                 break;
2622                         case MPT2SAS_INTEL_RMS25LB080_SSDID:
2623                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2624                                     MPT2SAS_INTEL_RMS25LB080_BRANDING);
2625                                 break;
2626                         default:
2627                                 pr_info(MPT3SAS_FMT
2628                                  "Intel(R) Controller: Subsystem ID: 0x%X\n",
2629                                  ioc->name, ioc->pdev->subsystem_device);
2630                                 break;
2631                         }
2632                 case MPI25_MFGPAGE_DEVID_SAS3008:
2633                         switch (ioc->pdev->subsystem_device) {
2634                         case MPT3SAS_INTEL_RMS3JC080_SSDID:
2635                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2636                                         MPT3SAS_INTEL_RMS3JC080_BRANDING);
2637                                 break;
2638
2639                         case MPT3SAS_INTEL_RS3GC008_SSDID:
2640                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2641                                         MPT3SAS_INTEL_RS3GC008_BRANDING);
2642                                 break;
2643                         case MPT3SAS_INTEL_RS3FC044_SSDID:
2644                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2645                                         MPT3SAS_INTEL_RS3FC044_BRANDING);
2646                                 break;
2647                         case MPT3SAS_INTEL_RS3UC080_SSDID:
2648                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2649                                         MPT3SAS_INTEL_RS3UC080_BRANDING);
2650                                 break;
2651                         default:
2652                                 pr_info(MPT3SAS_FMT
2653                                  "Intel(R) Controller: Subsystem ID: 0x%X\n",
2654                                  ioc->name, ioc->pdev->subsystem_device);
2655                                 break;
2656                         }
2657                         break;
2658                 default:
2659                         pr_info(MPT3SAS_FMT
2660                          "Intel(R) Controller: Subsystem ID: 0x%X\n",
2661                          ioc->name, ioc->pdev->subsystem_device);
2662                         break;
2663                 }
2664                 break;
2665         case PCI_VENDOR_ID_DELL:
2666                 switch (ioc->pdev->device) {
2667                 case MPI2_MFGPAGE_DEVID_SAS2008:
2668                         switch (ioc->pdev->subsystem_device) {
2669                         case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2670                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2671                                  MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2672                                 break;
2673                         case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2674                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2675                                  MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2676                                 break;
2677                         case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2678                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2679                                  MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2680                                 break;
2681                         case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2682                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2683                                  MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2684                                 break;
2685                         case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2686                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2687                                  MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2688                                 break;
2689                         case MPT2SAS_DELL_PERC_H200_SSDID:
2690                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2691                                  MPT2SAS_DELL_PERC_H200_BRANDING);
2692                                 break;
2693                         case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2694                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2695                                  MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2696                                 break;
2697                         default:
2698                                 pr_info(MPT3SAS_FMT
2699                                    "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2700                                    ioc->name, ioc->pdev->subsystem_device);
2701                                 break;
2702                         }
2703                         break;
2704                 case MPI25_MFGPAGE_DEVID_SAS3008:
2705                         switch (ioc->pdev->subsystem_device) {
2706                         case MPT3SAS_DELL_12G_HBA_SSDID:
2707                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2708                                         MPT3SAS_DELL_12G_HBA_BRANDING);
2709                                 break;
2710                         default:
2711                                 pr_info(MPT3SAS_FMT
2712                                    "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2713                                    ioc->name, ioc->pdev->subsystem_device);
2714                                 break;
2715                         }
2716                         break;
2717                 default:
2718                         pr_info(MPT3SAS_FMT
2719                            "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
2720                            ioc->pdev->subsystem_device);
2721                         break;
2722                 }
2723                 break;
2724         case PCI_VENDOR_ID_CISCO:
2725                 switch (ioc->pdev->device) {
2726                 case MPI25_MFGPAGE_DEVID_SAS3008:
2727                         switch (ioc->pdev->subsystem_device) {
2728                         case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2729                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2730                                         MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2731                                 break;
2732                         case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2733                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2734                                         MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2735                                 break;
2736                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2737                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2738                                         MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2739                                 break;
2740                         default:
2741                                 pr_info(MPT3SAS_FMT
2742                                   "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2743                                   ioc->name, ioc->pdev->subsystem_device);
2744                                 break;
2745                         }
2746                         break;
2747                 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2748                         switch (ioc->pdev->subsystem_device) {
2749                         case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2750                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2751                                 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2752                                 break;
2753                         case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2754                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2755                                 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2756                                 );
2757                                 break;
2758                         default:
2759                                 pr_info(MPT3SAS_FMT
2760                                  "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2761                                  ioc->name, ioc->pdev->subsystem_device);
2762                                 break;
2763                         }
2764                         break;
2765                 default:
2766                         pr_info(MPT3SAS_FMT
2767                            "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2768                            ioc->name, ioc->pdev->subsystem_device);
2769                         break;
2770                 }
2771                 break;
2772         case MPT2SAS_HP_3PAR_SSVID:
2773                 switch (ioc->pdev->device) {
2774                 case MPI2_MFGPAGE_DEVID_SAS2004:
2775                         switch (ioc->pdev->subsystem_device) {
2776                         case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2777                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2778                                     MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2779                                 break;
2780                         default:
2781                                 pr_info(MPT3SAS_FMT
2782                                    "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2783                                    ioc->name, ioc->pdev->subsystem_device);
2784                                 break;
2785                         }
2786                 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2787                         switch (ioc->pdev->subsystem_device) {
2788                         case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2789                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2790                                     MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2791                                 break;
2792                         case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2793                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2794                                     MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2795                                 break;
2796                         case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2797                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2798                                  MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2799                                 break;
2800                         case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2801                                 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2802                                     MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2803                                 break;
2804                         default:
2805                                 pr_info(MPT3SAS_FMT
2806                                    "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2807                                    ioc->name, ioc->pdev->subsystem_device);
2808                                 break;
2809                         }
2810                 default:
2811                         pr_info(MPT3SAS_FMT
2812                            "HP SAS HBA: Subsystem ID: 0x%X\n",
2813                            ioc->name, ioc->pdev->subsystem_device);
2814                         break;
2815                 }
2816         default:
2817                 break;
2818         }
2819 }
2820
2821 /**
2822  * _base_display_ioc_capabilities - Disply IOC's capabilities.
2823  * @ioc: per adapter object
2824  *
2825  * Return nothing.
2826  */
2827 static void
2828 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2829 {
2830         int i = 0;
2831         char desc[16];
2832         u32 iounit_pg1_flags;
2833         u32 bios_version;
2834
2835         bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2836         strncpy(desc, ioc->manu_pg0.ChipName, 16);
2837         pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2838            "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2839             ioc->name, desc,
2840            (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2841            (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2842            (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2843            ioc->facts.FWVersion.Word & 0x000000FF,
2844            ioc->pdev->revision,
2845            (bios_version & 0xFF000000) >> 24,
2846            (bios_version & 0x00FF0000) >> 16,
2847            (bios_version & 0x0000FF00) >> 8,
2848             bios_version & 0x000000FF);
2849
2850         _base_display_OEMs_branding(ioc);
2851
2852         pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2853
2854         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2855                 pr_info("Initiator");
2856                 i++;
2857         }
2858
2859         if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2860                 pr_info("%sTarget", i ? "," : "");
2861                 i++;
2862         }
2863
2864         i = 0;
2865         pr_info("), ");
2866         pr_info("Capabilities=(");
2867
2868         if (!ioc->hide_ir_msg) {
2869                 if (ioc->facts.IOCCapabilities &
2870                     MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2871                         pr_info("Raid");
2872                         i++;
2873                 }
2874         }
2875
2876         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2877                 pr_info("%sTLR", i ? "," : "");
2878                 i++;
2879         }
2880
2881         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2882                 pr_info("%sMulticast", i ? "," : "");
2883                 i++;
2884         }
2885
2886         if (ioc->facts.IOCCapabilities &
2887             MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2888                 pr_info("%sBIDI Target", i ? "," : "");
2889                 i++;
2890         }
2891
2892         if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2893                 pr_info("%sEEDP", i ? "," : "");
2894                 i++;
2895         }
2896
2897         if (ioc->facts.IOCCapabilities &
2898             MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2899                 pr_info("%sSnapshot Buffer", i ? "," : "");
2900                 i++;
2901         }
2902
2903         if (ioc->facts.IOCCapabilities &
2904             MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2905                 pr_info("%sDiag Trace Buffer", i ? "," : "");
2906                 i++;
2907         }
2908
2909         if (ioc->facts.IOCCapabilities &
2910             MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2911                 pr_info("%sDiag Extended Buffer", i ? "," : "");
2912                 i++;
2913         }
2914
2915         if (ioc->facts.IOCCapabilities &
2916             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2917                 pr_info("%sTask Set Full", i ? "," : "");
2918                 i++;
2919         }
2920
2921         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2922         if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2923                 pr_info("%sNCQ", i ? "," : "");
2924                 i++;
2925         }
2926
2927         pr_info(")\n");
2928 }
2929
2930 /**
2931  * mpt3sas_base_update_missing_delay - change the missing delay timers
2932  * @ioc: per adapter object
2933  * @device_missing_delay: amount of time till device is reported missing
2934  * @io_missing_delay: interval IO is returned when there is a missing device
2935  *
2936  * Return nothing.
2937  *
2938  * Passed on the command line, this function will modify the device missing
2939  * delay, as well as the io missing delay. This should be called at driver
2940  * load time.
2941  */
2942 void
2943 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2944         u16 device_missing_delay, u8 io_missing_delay)
2945 {
2946         u16 dmd, dmd_new, dmd_orignal;
2947         u8 io_missing_delay_original;
2948         u16 sz;
2949         Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2950         Mpi2ConfigReply_t mpi_reply;
2951         u8 num_phys = 0;
2952         u16 ioc_status;
2953
2954         mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2955         if (!num_phys)
2956                 return;
2957
2958         sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2959             sizeof(Mpi2SasIOUnit1PhyData_t));
2960         sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2961         if (!sas_iounit_pg1) {
2962                 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2963                     ioc->name, __FILE__, __LINE__, __func__);
2964                 goto out;
2965         }
2966         if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2967             sas_iounit_pg1, sz))) {
2968                 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2969                     ioc->name, __FILE__, __LINE__, __func__);
2970                 goto out;
2971         }
2972         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2973             MPI2_IOCSTATUS_MASK;
2974         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2975                 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2976                     ioc->name, __FILE__, __LINE__, __func__);
2977                 goto out;
2978         }
2979
2980         /* device missing delay */
2981         dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2982         if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2983                 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2984         else
2985                 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2986         dmd_orignal = dmd;
2987         if (device_missing_delay > 0x7F) {
2988                 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2989                     device_missing_delay;
2990                 dmd = dmd / 16;
2991                 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2992         } else
2993                 dmd = device_missing_delay;
2994         sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2995
2996         /* io missing delay */
2997         io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2998         sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2999
3000         if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
3001             sz)) {
3002                 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
3003                         dmd_new = (dmd &
3004                             MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
3005                 else
3006                         dmd_new =
3007                     dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
3008                 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
3009                         ioc->name, dmd_orignal, dmd_new);
3010                 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
3011                         ioc->name, io_missing_delay_original,
3012                     io_missing_delay);
3013                 ioc->device_missing_delay = dmd_new;
3014                 ioc->io_missing_delay = io_missing_delay;
3015         }
3016
3017 out:
3018         kfree(sas_iounit_pg1);
3019 }
3020 /**
3021  * _base_static_config_pages - static start of day config pages
3022  * @ioc: per adapter object
3023  *
3024  * Return nothing.
3025  */
3026 static void
3027 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3028 {
3029         Mpi2ConfigReply_t mpi_reply;
3030         u32 iounit_pg1_flags;
3031
3032         mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3033         if (ioc->ir_firmware)
3034                 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3035                     &ioc->manu_pg10);
3036
3037         /*
3038          * Ensure correct T10 PI operation if vendor left EEDPTagMode
3039          * flag unset in NVDATA.
3040          */
3041         mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3042         if (ioc->manu_pg11.EEDPTagMode == 0) {
3043                 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3044                     ioc->name);
3045                 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3046                 ioc->manu_pg11.EEDPTagMode |= 0x1;
3047                 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3048                     &ioc->manu_pg11);
3049         }
3050
3051         mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3052         mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3053         mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3054         mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3055         mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3056         mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
3057         _base_display_ioc_capabilities(ioc);
3058
3059         /*
3060          * Enable task_set_full handling in iounit_pg1 when the
3061          * facts capabilities indicate that its supported.
3062          */
3063         iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3064         if ((ioc->facts.IOCCapabilities &
3065             MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3066                 iounit_pg1_flags &=
3067                     ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3068         else
3069                 iounit_pg1_flags |=
3070                     MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3071         ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3072         mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3073
3074         if (ioc->iounit_pg8.NumSensors)
3075                 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
3076 }
3077
3078 /**
3079  * _base_release_memory_pools - release memory
3080  * @ioc: per adapter object
3081  *
3082  * Free memory allocated from _base_allocate_memory_pools.
3083  *
3084  * Return nothing.
3085  */
3086 static void
3087 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3088 {
3089         int i = 0;
3090         struct reply_post_struct *rps;
3091
3092         dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3093             __func__));
3094
3095         if (ioc->request) {
3096                 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3097                     ioc->request,  ioc->request_dma);
3098                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3099                         "request_pool(0x%p): free\n",
3100                         ioc->name, ioc->request));
3101                 ioc->request = NULL;
3102         }
3103
3104         if (ioc->sense) {
3105                 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3106                 if (ioc->sense_dma_pool)
3107                         pci_pool_destroy(ioc->sense_dma_pool);
3108                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3109                         "sense_pool(0x%p): free\n",
3110                         ioc->name, ioc->sense));
3111                 ioc->sense = NULL;
3112         }
3113
3114         if (ioc->reply) {
3115                 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3116                 if (ioc->reply_dma_pool)
3117                         pci_pool_destroy(ioc->reply_dma_pool);
3118                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3119                         "reply_pool(0x%p): free\n",
3120                         ioc->name, ioc->reply));
3121                 ioc->reply = NULL;
3122         }
3123
3124         if (ioc->reply_free) {
3125                 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3126                     ioc->reply_free_dma);
3127                 if (ioc->reply_free_dma_pool)
3128                         pci_pool_destroy(ioc->reply_free_dma_pool);
3129                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3130                         "reply_free_pool(0x%p): free\n",
3131                         ioc->name, ioc->reply_free));
3132                 ioc->reply_free = NULL;
3133         }
3134
3135         if (ioc->reply_post) {
3136                 do {
3137                         rps = &ioc->reply_post[i];
3138                         if (rps->reply_post_free) {
3139                                 pci_pool_free(
3140                                     ioc->reply_post_free_dma_pool,
3141                                     rps->reply_post_free,
3142                                     rps->reply_post_free_dma);
3143                                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3144                                     "reply_post_free_pool(0x%p): free\n",
3145                                     ioc->name, rps->reply_post_free));
3146                                 rps->reply_post_free = NULL;
3147                         }
3148                 } while (ioc->rdpq_array_enable &&
3149                            (++i < ioc->reply_queue_count));
3150
3151                 if (ioc->reply_post_free_dma_pool)
3152                         pci_pool_destroy(ioc->reply_post_free_dma_pool);
3153                 kfree(ioc->reply_post);
3154         }
3155
3156         if (ioc->config_page) {
3157                 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3158                     "config_page(0x%p): free\n", ioc->name,
3159                     ioc->config_page));
3160                 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3161                     ioc->config_page, ioc->config_page_dma);
3162         }
3163
3164         if (ioc->scsi_lookup) {
3165                 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3166                 ioc->scsi_lookup = NULL;
3167         }
3168         kfree(ioc->hpr_lookup);
3169         ioc->hpr_lookup = NULL;
3170         kfree(ioc->internal_lookup);
3171         ioc->internal_lookup = NULL;
3172         if (ioc->chain_lookup) {
3173                 for (i = 0; i < ioc->chain_depth; i++) {
3174                         if (ioc->chain_lookup[i].chain_buffer)
3175                                 pci_pool_free(ioc->chain_dma_pool,
3176                                     ioc->chain_lookup[i].chain_buffer,
3177                                     ioc->chain_lookup[i].chain_buffer_dma);
3178                 }
3179                 if (ioc->chain_dma_pool)
3180                         pci_pool_destroy(ioc->chain_dma_pool);
3181                 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3182                 ioc->chain_lookup = NULL;
3183         }
3184 }
3185
3186 /**
3187  * _base_allocate_memory_pools - allocate start of day memory pools
3188  * @ioc: per adapter object
3189  *
3190  * Returns 0 success, anything else error
3191  */
3192 static int
3193 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3194 {
3195         struct mpt3sas_facts *facts;
3196         u16 max_sge_elements;
3197         u16 chains_needed_per_io;
3198         u32 sz, total_sz, reply_post_free_sz;
3199         u32 retry_sz;
3200         u16 max_request_credit;
3201         unsigned short sg_tablesize;
3202         u16 sge_size;
3203         int i;
3204
3205         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3206             __func__));
3207
3208
3209         retry_sz = 0;
3210         facts = &ioc->facts;
3211
3212         /* command line tunables for max sgl entries */
3213         if (max_sgl_entries != -1)
3214                 sg_tablesize = max_sgl_entries;
3215         else {
3216                 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3217                         sg_tablesize = MPT2SAS_SG_DEPTH;
3218                 else
3219                         sg_tablesize = MPT3SAS_SG_DEPTH;
3220         }
3221
3222         if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3223                 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3224         else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
3225                 sg_tablesize = min_t(unsigned short, sg_tablesize,
3226                                       SG_MAX_SEGMENTS);
3227                 pr_warn(MPT3SAS_FMT
3228                  "sg_tablesize(%u) is bigger than kernel"
3229                  " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
3230                  sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
3231         }
3232         ioc->shost->sg_tablesize = sg_tablesize;
3233
3234         ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3235                 (facts->RequestCredit / 4));
3236         if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3237                 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3238                                 INTERNAL_SCSIIO_CMDS_COUNT)) {
3239                         pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3240                             Credits, it has just %d number of credits\n",
3241                             ioc->name, facts->RequestCredit);
3242                         return -ENOMEM;
3243                 }
3244                 ioc->internal_depth = 10;
3245         }
3246
3247         ioc->hi_priority_depth = ioc->internal_depth - (5);
3248         /* command line tunables  for max controller queue depth */
3249         if (max_queue_depth != -1 && max_queue_depth != 0) {
3250                 max_request_credit = min_t(u16, max_queue_depth +
3251                         ioc->internal_depth, facts->RequestCredit);
3252                 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3253                         max_request_credit =  MAX_HBA_QUEUE_DEPTH;
3254         } else
3255                 max_request_credit = min_t(u16, facts->RequestCredit,
3256                     MAX_HBA_QUEUE_DEPTH);
3257
3258         /* Firmware maintains additional facts->HighPriorityCredit number of
3259          * credits for HiPriprity Request messages, so hba queue depth will be
3260          * sum of max_request_credit and high priority queue depth.
3261          */
3262         ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
3263
3264         /* request frame size */
3265         ioc->request_sz = facts->IOCRequestFrameSize * 4;
3266
3267         /* reply frame size */
3268         ioc->reply_sz = facts->ReplyFrameSize * 4;
3269
3270         /* chain segment size */
3271         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3272                 if (facts->IOCMaxChainSegmentSize)
3273                         ioc->chain_segment_sz =
3274                                         facts->IOCMaxChainSegmentSize *
3275                                         MAX_CHAIN_ELEMT_SZ;
3276                 else
3277                 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3278                         ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3279                                                     MAX_CHAIN_ELEMT_SZ;
3280         } else
3281                 ioc->chain_segment_sz = ioc->request_sz;
3282
3283         /* calculate the max scatter element size */
3284         sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3285
3286  retry_allocation:
3287         total_sz = 0;
3288         /* calculate number of sg elements left over in the 1st frame */
3289         max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3290             sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3291         ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3292
3293         /* now do the same for a chain buffer */
3294         max_sge_elements = ioc->chain_segment_sz - sge_size;
3295         ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3296
3297         /*
3298          *  MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3299          */
3300         chains_needed_per_io = ((ioc->shost->sg_tablesize -
3301            ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3302             + 1;
3303         if (chains_needed_per_io > facts->MaxChainDepth) {
3304                 chains_needed_per_io = facts->MaxChainDepth;
3305                 ioc->shost->sg_tablesize = min_t(u16,
3306                 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3307                 * chains_needed_per_io), ioc->shost->sg_tablesize);
3308         }
3309         ioc->chains_needed_per_io = chains_needed_per_io;
3310
3311         /* reply free queue sizing - taking into account for 64 FW events */
3312         ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3313
3314         /* calculate reply descriptor post queue depth */
3315         ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3316                                 ioc->reply_free_queue_depth +  1 ;
3317         /* align the reply post queue on the next 16 count boundary */
3318         if (ioc->reply_post_queue_depth % 16)
3319                 ioc->reply_post_queue_depth += 16 -
3320                 (ioc->reply_post_queue_depth % 16);
3321
3322         if (ioc->reply_post_queue_depth >
3323             facts->MaxReplyDescriptorPostQueueDepth) {
3324                 ioc->reply_post_queue_depth =
3325                                 facts->MaxReplyDescriptorPostQueueDepth -
3326                     (facts->MaxReplyDescriptorPostQueueDepth % 16);
3327                 ioc->hba_queue_depth =
3328                                 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3329                 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3330         }
3331
3332         dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3333             "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3334             "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3335             ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3336             ioc->chains_needed_per_io));
3337
3338         /* reply post queue, 16 byte align */
3339         reply_post_free_sz = ioc->reply_post_queue_depth *
3340             sizeof(Mpi2DefaultReplyDescriptor_t);
3341
3342         sz = reply_post_free_sz;
3343         if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3344                 sz *= ioc->reply_queue_count;
3345
3346         ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3347             (ioc->reply_queue_count):1,
3348             sizeof(struct reply_post_struct), GFP_KERNEL);
3349
3350         if (!ioc->reply_post) {
3351                 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3352                         ioc->name);
3353                 goto out;
3354         }
3355         ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3356             ioc->pdev, sz, 16, 0);
3357         if (!ioc->reply_post_free_dma_pool) {
3358                 pr_err(MPT3SAS_FMT
3359                  "reply_post_free pool: pci_pool_create failed\n",
3360                  ioc->name);
3361                 goto out;
3362         }
3363         i = 0;
3364         do {
3365                 ioc->reply_post[i].reply_post_free =
3366                     pci_pool_alloc(ioc->reply_post_free_dma_pool,
3367                     GFP_KERNEL,
3368                     &ioc->reply_post[i].reply_post_free_dma);
3369                 if (!ioc->reply_post[i].reply_post_free) {
3370                         pr_err(MPT3SAS_FMT
3371                         "reply_post_free pool: pci_pool_alloc failed\n",
3372                         ioc->name);
3373                         goto out;
3374                 }
3375                 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3376                 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3377                     "reply post free pool (0x%p): depth(%d),"
3378                     "element_size(%d), pool_size(%d kB)\n", ioc->name,
3379                     ioc->reply_post[i].reply_post_free,
3380                     ioc->reply_post_queue_depth, 8, sz/1024));
3381                 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3382                     "reply_post_free_dma = (0x%llx)\n", ioc->name,
3383                     (unsigned long long)
3384                     ioc->reply_post[i].reply_post_free_dma));
3385                 total_sz += sz;
3386         } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3387
3388         if (ioc->dma_mask > 32) {
3389                 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3390                         pr_warn(MPT3SAS_FMT
3391                             "no suitable consistent DMA mask for %s\n",
3392                             ioc->name, pci_name(ioc->pdev));
3393                         goto out;
3394                 }
3395         }
3396
3397         ioc->scsiio_depth = ioc->hba_queue_depth -
3398             ioc->hi_priority_depth - ioc->internal_depth;
3399
3400         /* set the scsi host can_queue depth
3401          * with some internal commands that could be outstanding
3402          */
3403         ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
3404         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3405                 "scsi host: can_queue depth (%d)\n",
3406                 ioc->name, ioc->shost->can_queue));
3407
3408
3409         /* contiguous pool for request and chains, 16 byte align, one extra "
3410          * "frame for smid=0
3411          */
3412         ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3413         sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3414
3415         /* hi-priority queue */
3416         sz += (ioc->hi_priority_depth * ioc->request_sz);
3417
3418         /* internal queue */
3419         sz += (ioc->internal_depth * ioc->request_sz);
3420
3421         ioc->request_dma_sz = sz;
3422         ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3423         if (!ioc->request) {
3424                 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3425                     "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3426                     "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3427                     ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3428                 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3429                         goto out;
3430                 retry_sz = 64;
3431                 ioc->hba_queue_depth -= retry_sz;
3432                 _base_release_memory_pools(ioc);
3433                 goto retry_allocation;
3434         }
3435
3436         if (retry_sz)
3437                 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3438                     "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3439                     "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3440                     ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3441
3442         /* hi-priority queue */
3443         ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3444             ioc->request_sz);
3445         ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3446             ioc->request_sz);
3447
3448         /* internal queue */
3449         ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3450             ioc->request_sz);
3451         ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3452             ioc->request_sz);
3453
3454         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3455                 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3456                 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3457             (ioc->hba_queue_depth * ioc->request_sz)/1024));
3458
3459         dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3460             ioc->name, (unsigned long long) ioc->request_dma));
3461         total_sz += sz;
3462
3463         sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3464         ioc->scsi_lookup_pages = get_order(sz);
3465         ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3466             GFP_KERNEL, ioc->scsi_lookup_pages);
3467         if (!ioc->scsi_lookup) {
3468                 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3469                         ioc->name, (int)sz);
3470                 goto out;
3471         }
3472
3473         dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3474                 ioc->name, ioc->request, ioc->scsiio_depth));
3475
3476         ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3477         sz = ioc->chain_depth * sizeof(struct chain_tracker);
3478         ioc->chain_pages = get_order(sz);
3479         ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3480             GFP_KERNEL, ioc->chain_pages);
3481         if (!ioc->chain_lookup) {
3482                 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3483                         ioc->name);
3484                 goto out;
3485         }
3486         ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3487             ioc->chain_segment_sz, 16, 0);
3488         if (!ioc->chain_dma_pool) {
3489                 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3490                         ioc->name);
3491                 goto out;
3492         }
3493         for (i = 0; i < ioc->chain_depth; i++) {
3494                 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3495                     ioc->chain_dma_pool , GFP_KERNEL,
3496                     &ioc->chain_lookup[i].chain_buffer_dma);
3497                 if (!ioc->chain_lookup[i].chain_buffer) {
3498                         ioc->chain_depth = i;
3499                         goto chain_done;
3500                 }
3501                 total_sz += ioc->chain_segment_sz;
3502         }
3503  chain_done:
3504         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3505                 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3506                 ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
3507                 ((ioc->chain_depth *  ioc->chain_segment_sz))/1024));
3508
3509         /* initialize hi-priority queue smid's */
3510         ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3511             sizeof(struct request_tracker), GFP_KERNEL);
3512         if (!ioc->hpr_lookup) {
3513                 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3514                     ioc->name);
3515                 goto out;
3516         }
3517         ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3518         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3519                 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3520                 ioc->name, ioc->hi_priority,
3521             ioc->hi_priority_depth, ioc->hi_priority_smid));
3522
3523         /* initialize internal queue smid's */
3524         ioc->internal_lookup = kcalloc(ioc->internal_depth,
3525             sizeof(struct request_tracker), GFP_KERNEL);
3526         if (!ioc->internal_lookup) {
3527                 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3528                     ioc->name);
3529                 goto out;
3530         }
3531         ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3532         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3533                 "internal(0x%p): depth(%d), start smid(%d)\n",
3534                 ioc->name, ioc->internal,
3535             ioc->internal_depth, ioc->internal_smid));
3536
3537         /* sense buffers, 4 byte align */
3538         sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3539         ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3540             0);
3541         if (!ioc->sense_dma_pool) {
3542                 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3543                     ioc->name);
3544                 goto out;
3545         }
3546         ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3547             &ioc->sense_dma);
3548         if (!ioc->sense) {
3549                 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3550                     ioc->name);
3551                 goto out;
3552         }
3553         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3554             "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3555             "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3556             SCSI_SENSE_BUFFERSIZE, sz/1024));
3557         dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3558             ioc->name, (unsigned long long)ioc->sense_dma));
3559         total_sz += sz;
3560
3561         /* reply pool, 4 byte align */
3562         sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3563         ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3564             0);
3565         if (!ioc->reply_dma_pool) {
3566                 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3567                     ioc->name);
3568                 goto out;
3569         }
3570         ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3571             &ioc->reply_dma);
3572         if (!ioc->reply) {
3573                 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3574                     ioc->name);
3575                 goto out;
3576         }
3577         ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3578         ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3579         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3580                 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3581                 ioc->name, ioc->reply,
3582             ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3583         dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3584             ioc->name, (unsigned long long)ioc->reply_dma));
3585         total_sz += sz;
3586
3587         /* reply free queue, 16 byte align */
3588         sz = ioc->reply_free_queue_depth * 4;
3589         ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3590             ioc->pdev, sz, 16, 0);
3591         if (!ioc->reply_free_dma_pool) {
3592                 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3593                         ioc->name);
3594                 goto out;
3595         }
3596         ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3597             &ioc->reply_free_dma);
3598         if (!ioc->reply_free) {
3599                 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3600                         ioc->name);
3601                 goto out;
3602         }
3603         memset(ioc->reply_free, 0, sz);
3604         dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3605             "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3606             ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3607         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3608                 "reply_free_dma (0x%llx)\n",
3609                 ioc->name, (unsigned long long)ioc->reply_free_dma));
3610         total_sz += sz;
3611
3612         ioc->config_page_sz = 512;
3613         ioc->config_page = pci_alloc_consistent(ioc->pdev,
3614             ioc->config_page_sz, &ioc->config_page_dma);
3615         if (!ioc->config_page) {
3616                 pr_err(MPT3SAS_FMT
3617                         "config page: pci_pool_alloc failed\n",
3618                         ioc->name);
3619                 goto out;
3620         }
3621         dinitprintk(ioc, pr_info(MPT3SAS_FMT
3622                 "config page(0x%p): size(%d)\n",
3623                 ioc->name, ioc->config_page, ioc->config_page_sz));
3624         dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3625                 ioc->name, (unsigned long long)ioc->config_page_dma));
3626         total_sz += ioc->config_page_sz;
3627
3628         pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3629             ioc->name, total_sz/1024);
3630         pr_info(MPT3SAS_FMT
3631                 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3632             ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3633         pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3634             ioc->name, ioc->shost->sg_tablesize);
3635         return 0;
3636
3637  out:
3638         return -ENOMEM;
3639 }
3640
3641 /**
3642  * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3643  * @ioc: Pointer to MPT_ADAPTER structure
3644  * @cooked: Request raw or cooked IOC state
3645  *
3646  * Returns all IOC Doorbell register bits if cooked==0, else just the
3647  * Doorbell bits in MPI_IOC_STATE_MASK.
3648  */
3649 u32
3650 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3651 {
3652         u32 s, sc;
3653
3654         s = readl(&ioc->chip->Doorbell);
3655         sc = s & MPI2_IOC_STATE_MASK;
3656         return cooked ? sc : s;
3657 }
3658
3659 /**
3660  * _base_wait_on_iocstate - waiting on a particular ioc state
3661  * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3662  * @timeout: timeout in second
3663  *
3664  * Returns 0 for success, non-zero for failure.
3665  */
3666 static int
3667 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
3668 {
3669         u32 count, cntdn;
3670         u32 current_state;
3671
3672         count = 0;
3673         cntdn = 1000 * timeout;
3674         do {
3675                 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3676                 if (current_state == ioc_state)
3677                         return 0;
3678                 if (count && current_state == MPI2_IOC_STATE_FAULT)
3679                         break;
3680
3681                 usleep_range(1000, 1500);
3682                 count++;
3683         } while (--cntdn);
3684
3685         return current_state;
3686 }
3687
3688 /**
3689  * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3690  * a write to the doorbell)
3691  * @ioc: per adapter object
3692  * @timeout: timeout in second
3693  *
3694  * Returns 0 for success, non-zero for failure.
3695  *
3696  * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3697  */
3698 static int
3699 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3700
3701 static int
3702 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
3703 {
3704         u32 cntdn, count;
3705         u32 int_status;
3706
3707         count = 0;
3708         cntdn = 1000 * timeout;
3709         do {
3710                 int_status = readl(&ioc->chip->HostInterruptStatus);
3711                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3712                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3713                                 "%s: successful count(%d), timeout(%d)\n",
3714                                 ioc->name, __func__, count, timeout));
3715                         return 0;
3716                 }
3717
3718                 usleep_range(1000, 1500);
3719                 count++;
3720         } while (--cntdn);
3721
3722         pr_err(MPT3SAS_FMT
3723                 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3724                 ioc->name, __func__, count, int_status);
3725         return -EFAULT;
3726 }
3727
3728 static int
3729 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
3730 {
3731         u32 cntdn, count;
3732         u32 int_status;
3733
3734         count = 0;
3735         cntdn = 2000 * timeout;
3736         do {
3737                 int_status = readl(&ioc->chip->HostInterruptStatus);
3738                 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3739                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3740                                 "%s: successful count(%d), timeout(%d)\n",
3741                                 ioc->name, __func__, count, timeout));
3742                         return 0;
3743                 }
3744
3745                 udelay(500);
3746                 count++;
3747         } while (--cntdn);
3748
3749         pr_err(MPT3SAS_FMT
3750                 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3751                 ioc->name, __func__, count, int_status);
3752         return -EFAULT;
3753
3754 }
3755
3756 /**
3757  * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3758  * @ioc: per adapter object
3759  * @timeout: timeout in second
3760  *
3761  * Returns 0 for success, non-zero for failure.
3762  *
3763  * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3764  * doorbell.
3765  */
3766 static int
3767 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
3768 {
3769         u32 cntdn, count;
3770         u32 int_status;
3771         u32 doorbell;
3772
3773         count = 0;
3774         cntdn = 1000 * timeout;
3775         do {
3776                 int_status = readl(&ioc->chip->HostInterruptStatus);
3777                 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3778                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3779                                 "%s: successful count(%d), timeout(%d)\n",
3780                                 ioc->name, __func__, count, timeout));
3781                         return 0;
3782                 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3783                         doorbell = readl(&ioc->chip->Doorbell);
3784                         if ((doorbell & MPI2_IOC_STATE_MASK) ==
3785                             MPI2_IOC_STATE_FAULT) {
3786                                 mpt3sas_base_fault_info(ioc , doorbell);
3787                                 return -EFAULT;
3788                         }
3789                 } else if (int_status == 0xFFFFFFFF)
3790                         goto out;
3791
3792                 usleep_range(1000, 1500);
3793                 count++;
3794         } while (--cntdn);
3795
3796  out:
3797         pr_err(MPT3SAS_FMT
3798          "%s: failed due to timeout count(%d), int_status(%x)!\n",
3799          ioc->name, __func__, count, int_status);
3800         return -EFAULT;
3801 }
3802
3803 /**
3804  * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3805  * @ioc: per adapter object
3806  * @timeout: timeout in second
3807  *
3808  * Returns 0 for success, non-zero for failure.
3809  *
3810  */
3811 static int
3812 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
3813 {
3814         u32 cntdn, count;
3815         u32 doorbell_reg;
3816
3817         count = 0;
3818         cntdn = 1000 * timeout;
3819         do {
3820                 doorbell_reg = readl(&ioc->chip->Doorbell);
3821                 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3822                         dhsprintk(ioc, pr_info(MPT3SAS_FMT
3823                                 "%s: successful count(%d), timeout(%d)\n",
3824                                 ioc->name, __func__, count, timeout));
3825                         return 0;
3826                 }
3827
3828                 usleep_range(1000, 1500);
3829                 count++;
3830         } while (--cntdn);
3831
3832         pr_err(MPT3SAS_FMT
3833                 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3834                 ioc->name, __func__, count, doorbell_reg);
3835         return -EFAULT;
3836 }
3837
3838 /**
3839  * _base_send_ioc_reset - send doorbell reset
3840  * @ioc: per adapter object
3841  * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3842  * @timeout: timeout in second
3843  *
3844  * Returns 0 for success, non-zero for failure.
3845  */
3846 static int
3847 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
3848 {
3849         u32 ioc_state;
3850         int r = 0;
3851
3852         if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3853                 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3854                     ioc->name, __func__);
3855                 return -EFAULT;
3856         }
3857
3858         if (!(ioc->facts.IOCCapabilities &
3859            MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3860                 return -EFAULT;
3861
3862         pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3863
3864         writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3865             &ioc->chip->Doorbell);
3866         if ((_base_wait_for_doorbell_ack(ioc, 15))) {
3867                 r = -EFAULT;
3868                 goto out;
3869         }
3870         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
3871         if (ioc_state) {
3872                 pr_err(MPT3SAS_FMT
3873                         "%s: failed going to ready state (ioc_state=0x%x)\n",
3874                         ioc->name, __func__, ioc_state);
3875                 r = -EFAULT;
3876                 goto out;
3877         }
3878  out:
3879         pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3880             ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3881         return r;
3882 }
3883
3884 /**
3885  * _base_handshake_req_reply_wait - send request thru doorbell interface
3886  * @ioc: per adapter object
3887  * @request_bytes: request length
3888  * @request: pointer having request payload
3889  * @reply_bytes: reply length
3890  * @reply: pointer to reply payload
3891  * @timeout: timeout in second
3892  *
3893  * Returns 0 for success, non-zero for failure.
3894  */
3895 static int
3896 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3897         u32 *request, int reply_bytes, u16 *reply, int timeout)
3898 {
3899         MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3900         int i;
3901         u8 failed;
3902         __le32 *mfp;
3903
3904         /* make sure doorbell is not in use */
3905         if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3906                 pr_err(MPT3SAS_FMT
3907                         "doorbell is in use (line=%d)\n",
3908                         ioc->name, __LINE__);
3909                 return -EFAULT;
3910         }
3911
3912         /* clear pending doorbell interrupts from previous state changes */
3913         if (readl(&ioc->chip->HostInterruptStatus) &
3914             MPI2_HIS_IOC2SYS_DB_STATUS)
3915                 writel(0, &ioc->chip->HostInterruptStatus);
3916
3917         /* send message to ioc */
3918         writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3919             ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3920             &ioc->chip->Doorbell);
3921
3922         if ((_base_spin_on_doorbell_int(ioc, 5))) {
3923                 pr_err(MPT3SAS_FMT
3924                         "doorbell handshake int failed (line=%d)\n",
3925                         ioc->name, __LINE__);
3926                 return -EFAULT;
3927         }
3928         writel(0, &ioc->chip->HostInterruptStatus);
3929
3930         if ((_base_wait_for_doorbell_ack(ioc, 5))) {
3931                 pr_err(MPT3SAS_FMT
3932                         "doorbell handshake ack failed (line=%d)\n",
3933                         ioc->name, __LINE__);
3934                 return -EFAULT;
3935         }
3936
3937         /* send message 32-bits at a time */
3938         for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3939                 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3940                 if ((_base_wait_for_doorbell_ack(ioc, 5)))
3941                         failed = 1;
3942         }
3943
3944         if (failed) {
3945                 pr_err(MPT3SAS_FMT
3946                         "doorbell handshake sending request failed (line=%d)\n",
3947                         ioc->name, __LINE__);
3948                 return -EFAULT;
3949         }
3950
3951         /* now wait for the reply */
3952         if ((_base_wait_for_doorbell_int(ioc, timeout))) {
3953                 pr_err(MPT3SAS_FMT
3954                         "doorbell handshake int failed (line=%d)\n",
3955                         ioc->name, __LINE__);
3956                 return -EFAULT;
3957         }
3958
3959         /* read the first two 16-bits, it gives the total length of the reply */
3960         reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3961             & MPI2_DOORBELL_DATA_MASK);
3962         writel(0, &ioc->chip->HostInterruptStatus);
3963         if ((_base_wait_for_doorbell_int(ioc, 5))) {
3964                 pr_err(MPT3SAS_FMT
3965                         "doorbell handshake int failed (line=%d)\n",
3966                         ioc->name, __LINE__);
3967                 return -EFAULT;
3968         }
3969         reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3970             & MPI2_DOORBELL_DATA_MASK);
3971         writel(0, &ioc->chip->HostInterruptStatus);
3972
3973         for (i = 2; i < default_reply->MsgLength * 2; i++)  {
3974                 if ((_base_wait_for_doorbell_int(ioc, 5))) {
3975                         pr_err(MPT3SAS_FMT
3976                                 "doorbell handshake int failed (line=%d)\n",
3977                                 ioc->name, __LINE__);
3978                         return -EFAULT;
3979                 }
3980                 if (i >=  reply_bytes/2) /* overflow case */
3981                         readl(&ioc->chip->Doorbell);
3982                 else
3983                         reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3984                             & MPI2_DOORBELL_DATA_MASK);
3985                 writel(0, &ioc->chip->HostInterruptStatus);
3986         }
3987
3988         _base_wait_for_doorbell_int(ioc, 5);
3989         if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
3990                 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3991                         "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3992         }
3993         writel(0, &ioc->chip->HostInterruptStatus);
3994
3995         if (ioc->logging_level & MPT_DEBUG_INIT) {
3996                 mfp = (__le32 *)reply;
3997                 pr_info("\toffset:data\n");
3998                 for (i = 0; i < reply_bytes/4; i++)
3999                         pr_info("\t[0x%02x]:%08x\n", i*4,
4000                             le32_to_cpu(mfp[i]));
4001         }
4002         return 0;
4003 }
4004
4005 /**
4006  * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
4007  * @ioc: per adapter object
4008  * @mpi_reply: the reply payload from FW
4009  * @mpi_request: the request payload sent to FW
4010  *
4011  * The SAS IO Unit Control Request message allows the host to perform low-level
4012  * operations, such as resets on the PHYs of the IO Unit, also allows the host
4013  * to obtain the IOC assigned device handles for a device if it has other
4014  * identifying information about the device, in addition allows the host to
4015  * remove IOC resources associated with the device.
4016  *
4017  * Returns 0 for success, non-zero for failure.
4018  */
4019 int
4020 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
4021         Mpi2SasIoUnitControlReply_t *mpi_reply,
4022         Mpi2SasIoUnitControlRequest_t *mpi_request)
4023 {
4024         u16 smid;
4025         u32 ioc_state;
4026         bool issue_reset = false;
4027         int rc;
4028         void *request;
4029         u16 wait_state_count;
4030
4031         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4032             __func__));
4033
4034         mutex_lock(&ioc->base_cmds.mutex);
4035
4036         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4037                 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4038                     ioc->name, __func__);
4039                 rc = -EAGAIN;
4040                 goto out;
4041         }
4042
4043         wait_state_count = 0;
4044         ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4045         while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4046                 if (wait_state_count++ == 10) {
4047                         pr_err(MPT3SAS_FMT
4048                             "%s: failed due to ioc not operational\n",
4049                             ioc->name, __func__);
4050                         rc = -EFAULT;
4051                         goto out;
4052                 }
4053                 ssleep(1);
4054                 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4055                 pr_info(MPT3SAS_FMT
4056                         "%s: waiting for operational state(count=%d)\n",
4057                         ioc->name, __func__, wait_state_count);
4058         }
4059
4060         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4061         if (!smid) {
4062                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4063                     ioc->name, __func__);
4064                 rc = -EAGAIN;
4065                 goto out;
4066         }
4067
4068         rc = 0;
4069         ioc->base_cmds.status = MPT3_CMD_PENDING;
4070         request = mpt3sas_base_get_msg_frame(ioc, smid);
4071         ioc->base_cmds.smid = smid;
4072         memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4073         if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4074             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4075                 ioc->ioc_link_reset_in_progress = 1;
4076         init_completion(&ioc->base_cmds.done);
4077         mpt3sas_base_put_smid_default(ioc, smid);
4078         wait_for_completion_timeout(&ioc->base_cmds.done,
4079             msecs_to_jiffies(10000));
4080         if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4081             mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4082             ioc->ioc_link_reset_in_progress)
4083                 ioc->ioc_link_reset_in_progress = 0;
4084         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4085                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4086                     ioc->name, __func__);
4087                 _debug_dump_mf(mpi_request,
4088                     sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4089                 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4090                         issue_reset = true;
4091                 goto issue_host_reset;
4092         }
4093         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4094                 memcpy(mpi_reply, ioc->base_cmds.reply,
4095                     sizeof(Mpi2SasIoUnitControlReply_t));
4096         else
4097                 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4098         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4099         goto out;
4100
4101  issue_host_reset:
4102         if (issue_reset)
4103                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
4104         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4105         rc = -EFAULT;
4106  out:
4107         mutex_unlock(&ioc->base_cmds.mutex);
4108         return rc;
4109 }
4110
4111 /**
4112  * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4113  * @ioc: per adapter object
4114  * @mpi_reply: the reply payload from FW
4115  * @mpi_request: the request payload sent to FW
4116  *
4117  * The SCSI Enclosure Processor request message causes the IOC to
4118  * communicate with SES devices to control LED status signals.
4119  *
4120  * Returns 0 for success, non-zero for failure.
4121  */
4122 int
4123 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4124         Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4125 {
4126         u16 smid;
4127         u32 ioc_state;
4128         bool issue_reset = false;
4129         int rc;
4130         void *request;
4131         u16 wait_state_count;
4132
4133         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4134             __func__));
4135
4136         mutex_lock(&ioc->base_cmds.mutex);
4137
4138         if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4139                 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4140                     ioc->name, __func__);
4141                 rc = -EAGAIN;
4142                 goto out;
4143         }
4144
4145         wait_state_count = 0;
4146         ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4147         while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4148                 if (wait_state_count++ == 10) {
4149                         pr_err(MPT3SAS_FMT
4150                             "%s: failed due to ioc not operational\n",
4151                             ioc->name, __func__);
4152                         rc = -EFAULT;
4153                         goto out;
4154                 }
4155                 ssleep(1);
4156                 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4157                 pr_info(MPT3SAS_FMT
4158                         "%s: waiting for operational state(count=%d)\n",
4159                         ioc->name,
4160                     __func__, wait_state_count);
4161         }
4162
4163         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4164         if (!smid) {
4165                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4166                     ioc->name, __func__);
4167                 rc = -EAGAIN;
4168                 goto out;
4169         }
4170
4171         rc = 0;
4172         ioc->base_cmds.status = MPT3_CMD_PENDING;
4173         request = mpt3sas_base_get_msg_frame(ioc, smid);
4174         ioc->base_cmds.smid = smid;
4175         memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4176         init_completion(&ioc->base_cmds.done);
4177         mpt3sas_base_put_smid_default(ioc, smid);
4178         wait_for_completion_timeout(&ioc->base_cmds.done,
4179             msecs_to_jiffies(10000));
4180         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4181                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4182                     ioc->name, __func__);
4183                 _debug_dump_mf(mpi_request,
4184                     sizeof(Mpi2SepRequest_t)/4);
4185                 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4186                         issue_reset = false;
4187                 goto issue_host_reset;
4188         }
4189         if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4190                 memcpy(mpi_reply, ioc->base_cmds.reply,
4191                     sizeof(Mpi2SepReply_t));
4192         else
4193                 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4194         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4195         goto out;
4196
4197  issue_host_reset:
4198         if (issue_reset)
4199                 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
4200         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4201         rc = -EFAULT;
4202  out:
4203         mutex_unlock(&ioc->base_cmds.mutex);
4204         return rc;
4205 }
4206
4207 /**
4208  * _base_get_port_facts - obtain port facts reply and save in ioc
4209  * @ioc: per adapter object
4210  *
4211  * Returns 0 for success, non-zero for failure.
4212  */
4213 static int
4214 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
4215 {
4216         Mpi2PortFactsRequest_t mpi_request;
4217         Mpi2PortFactsReply_t mpi_reply;
4218         struct mpt3sas_port_facts *pfacts;
4219         int mpi_reply_sz, mpi_request_sz, r;
4220
4221         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4222             __func__));
4223
4224         mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4225         mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4226         memset(&mpi_request, 0, mpi_request_sz);
4227         mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4228         mpi_request.PortNumber = port;
4229         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4230             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
4231
4232         if (r != 0) {
4233                 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4234                     ioc->name, __func__, r);
4235                 return r;
4236         }
4237
4238         pfacts = &ioc->pfacts[port];
4239         memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4240         pfacts->PortNumber = mpi_reply.PortNumber;
4241         pfacts->VP_ID = mpi_reply.VP_ID;
4242         pfacts->VF_ID = mpi_reply.VF_ID;
4243         pfacts->MaxPostedCmdBuffers =
4244             le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4245
4246         return 0;
4247 }
4248
4249 /**
4250  * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4251  * @ioc: per adapter object
4252  * @timeout:
4253  *
4254  * Returns 0 for success, non-zero for failure.
4255  */
4256 static int
4257 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
4258 {
4259         u32 ioc_state;
4260         int rc;
4261
4262         dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4263             __func__));
4264
4265         if (ioc->pci_error_recovery) {
4266                 dfailprintk(ioc, printk(MPT3SAS_FMT
4267                     "%s: host in pci error recovery\n", ioc->name, __func__));
4268                 return -EFAULT;
4269         }
4270
4271         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4272         dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4273             ioc->name, __func__, ioc_state));
4274
4275         if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4276             (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4277                 return 0;
4278
4279         if (ioc_state & MPI2_DOORBELL_USED) {
4280                 dhsprintk(ioc, printk(MPT3SAS_FMT
4281                     "unexpected doorbell active!\n", ioc->name));
4282                 goto issue_diag_reset;
4283         }
4284
4285         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4286                 mpt3sas_base_fault_info(ioc, ioc_state &
4287                     MPI2_DOORBELL_DATA_MASK);
4288                 goto issue_diag_reset;
4289         }
4290
4291         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
4292         if (ioc_state) {
4293                 dfailprintk(ioc, printk(MPT3SAS_FMT
4294                     "%s: failed going to ready state (ioc_state=0x%x)\n",
4295                     ioc->name, __func__, ioc_state));
4296                 return -EFAULT;
4297         }
4298
4299  issue_diag_reset:
4300         rc = _base_diag_reset(ioc);
4301         return rc;
4302 }
4303
4304 /**
4305  * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4306  * @ioc: per adapter object
4307  *
4308  * Returns 0 for success, non-zero for failure.
4309  */
4310 static int
4311 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
4312 {
4313         Mpi2IOCFactsRequest_t mpi_request;
4314         Mpi2IOCFactsReply_t mpi_reply;
4315         struct mpt3sas_facts *facts;
4316         int mpi_reply_sz, mpi_request_sz, r;
4317
4318         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4319             __func__));
4320
4321         r = _base_wait_for_iocstate(ioc, 10);
4322         if (r) {
4323                 dfailprintk(ioc, printk(MPT3SAS_FMT
4324                     "%s: failed getting to correct state\n",
4325                     ioc->name, __func__));
4326                 return r;
4327         }
4328         mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4329         mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4330         memset(&mpi_request, 0, mpi_request_sz);
4331         mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4332         r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4333             (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
4334
4335         if (r != 0) {
4336                 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4337                     ioc->name, __func__, r);
4338                 return r;
4339         }
4340
4341         facts = &ioc->facts;
4342         memset(facts, 0, sizeof(struct mpt3sas_facts));
4343         facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4344         facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4345         facts->VP_ID = mpi_reply.VP_ID;
4346         facts->VF_ID = mpi_reply.VF_ID;
4347         facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4348         facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4349         facts->WhoInit = mpi_reply.WhoInit;
4350         facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4351         facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4352         facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4353         facts->MaxReplyDescriptorPostQueueDepth =
4354             le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4355         facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4356         facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4357         if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4358                 ioc->ir_firmware = 1;
4359         if ((facts->IOCCapabilities &
4360               MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4361                 ioc->rdpq_array_capable = 1;
4362         facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4363         facts->IOCRequestFrameSize =
4364             le16_to_cpu(mpi_reply.IOCRequestFrameSize);
4365         if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4366                 facts->IOCMaxChainSegmentSize =
4367                         le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
4368         }
4369         facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4370         facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4371         ioc->shost->max_id = -1;
4372         facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4373         facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4374         facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4375         facts->HighPriorityCredit =
4376             le16_to_cpu(mpi_reply.HighPriorityCredit);
4377         facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4378         facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4379
4380         dinitprintk(ioc, pr_info(MPT3SAS_FMT
4381                 "hba queue depth(%d), max chains per io(%d)\n",
4382                 ioc->name, facts->RequestCredit,
4383             facts->MaxChainDepth));
4384         dinitprintk(ioc, pr_info(MPT3SAS_FMT
4385                 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4386             facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4387         return 0;
4388 }
4389
4390 /**
4391  * _base_send_ioc_init - send ioc_init to firmware
4392  * @ioc: per adapter object
4393  *
4394  * Returns 0 for success, non-zero for failure.
4395  */
4396 static int
4397 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
4398 {
4399         Mpi2IOCInitRequest_t mpi_request;
4400         Mpi2IOCInitReply_t mpi_reply;
4401         int i, r = 0;
4402         ktime_t current_time;
4403         u16 ioc_status;
4404         u32 reply_post_free_array_sz = 0;
4405         Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4406         dma_addr_t reply_post_free_array_dma;
4407
4408         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4409             __func__));
4410
4411         memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4412         mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4413         mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4414         mpi_request.VF_ID = 0; /* TODO */
4415         mpi_request.VP_ID = 0;
4416         mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
4417         mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4418
4419         if (_base_is_controller_msix_enabled(ioc))
4420                 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4421         mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4422         mpi_request.ReplyDescriptorPostQueueDepth =
4423             cpu_to_le16(ioc->reply_post_queue_depth);
4424         mpi_request.ReplyFreeQueueDepth =
4425             cpu_to_le16(ioc->reply_free_queue_depth);
4426
4427         mpi_request.SenseBufferAddressHigh =
4428             cpu_to_le32((u64)ioc->sense_dma >> 32);
4429         mpi_request.SystemReplyAddressHigh =
4430             cpu_to_le32((u64)ioc->reply_dma >> 32);
4431         mpi_request.SystemRequestFrameBaseAddress =
4432             cpu_to_le64((u64)ioc->request_dma);
4433         mpi_request.ReplyFreeQueueAddress =
4434             cpu_to_le64((u64)ioc->reply_free_dma);
4435
4436         if (ioc->rdpq_array_enable) {
4437                 reply_post_free_array_sz = ioc->reply_queue_count *
4438                     sizeof(Mpi2IOCInitRDPQArrayEntry);
4439                 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4440                         reply_post_free_array_sz, &reply_post_free_array_dma);
4441                 if (!reply_post_free_array) {
4442                         pr_err(MPT3SAS_FMT
4443                         "reply_post_free_array: pci_alloc_consistent failed\n",
4444                         ioc->name);
4445                         r = -ENOMEM;
4446                         goto out;
4447                 }
4448                 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4449                 for (i = 0; i < ioc->reply_queue_count; i++)
4450                         reply_post_free_array[i].RDPQBaseAddress =
4451                             cpu_to_le64(
4452                                 (u64)ioc->reply_post[i].reply_post_free_dma);
4453                 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4454                 mpi_request.ReplyDescriptorPostQueueAddress =
4455                     cpu_to_le64((u64)reply_post_free_array_dma);
4456         } else {
4457                 mpi_request.ReplyDescriptorPostQueueAddress =
4458                     cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4459         }
4460
4461         /* This time stamp specifies number of milliseconds
4462          * since epoch ~ midnight January 1, 1970.
4463          */
4464         current_time = ktime_get_real();
4465         mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
4466
4467         if (ioc->logging_level & MPT_DEBUG_INIT) {
4468                 __le32 *mfp;
4469                 int i;
4470
4471                 mfp = (__le32 *)&mpi_request;
4472                 pr_info("\toffset:data\n");
4473                 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4474                         pr_info("\t[0x%02x]:%08x\n", i*4,
4475                             le32_to_cpu(mfp[i]));
4476         }
4477
4478         r = _base_handshake_req_reply_wait(ioc,
4479             sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4480             sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
4481
4482         if (r != 0) {
4483                 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4484                     ioc->name, __func__, r);
4485                 goto out;
4486         }
4487
4488         ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4489         if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4490             mpi_reply.IOCLogInfo) {
4491                 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4492                 r = -EIO;
4493         }
4494
4495 out:
4496         if (reply_post_free_array)
4497                 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4498                                     reply_post_free_array,
4499                                     reply_post_free_array_dma);
4500         return r;
4501 }
4502
4503 /**
4504  * mpt3sas_port_enable_done - command completion routine for port enable
4505  * @ioc: per adapter object
4506  * @smid: system request message index
4507  * @msix_index: MSIX table index supplied by the OS
4508  * @reply: reply message frame(lower 32bit addr)
4509  *
4510  * Return 1 meaning mf should be freed from _base_interrupt
4511  *        0 means the mf is freed from this function.
4512  */
4513 u8
4514 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4515         u32 reply)
4516 {
4517         MPI2DefaultReply_t *mpi_reply;
4518         u16 ioc_status;
4519
4520         if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4521                 return 1;
4522
4523         mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4524         if (!mpi_reply)
4525                 return 1;
4526
4527         if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4528                 return 1;
4529
4530         ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4531         ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4532         ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4533         memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4534         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4535         if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4536                 ioc->port_enable_failed = 1;
4537
4538         if (ioc->is_driver_loading) {
4539                 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4540                         mpt3sas_port_enable_complete(ioc);
4541                         return 1;
4542                 } else {
4543                         ioc->start_scan_failed = ioc_status;
4544                         ioc->start_scan = 0;
4545                         return 1;
4546                 }
4547         }
4548         complete(&ioc->port_enable_cmds.done);
4549         return 1;
4550 }
4551
4552 /**
4553  * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4554  * @ioc: per adapter object
4555  *
4556  * Returns 0 for success, non-zero for failure.
4557  */
4558 static int
4559 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
4560 {
4561         Mpi2PortEnableRequest_t *mpi_request;
4562         Mpi2PortEnableReply_t *mpi_reply;
4563         int r = 0;
4564         u16 smid;
4565         u16 ioc_status;
4566
4567         pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4568
4569         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4570                 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4571                     ioc->name, __func__);
4572                 return -EAGAIN;
4573         }
4574
4575         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4576         if (!smid) {
4577                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4578                     ioc->name, __func__);
4579                 return -EAGAIN;
4580         }
4581
4582         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4583         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4584         ioc->port_enable_cmds.smid = smid;
4585         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4586         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4587
4588         init_completion(&ioc->port_enable_cmds.done);
4589         mpt3sas_base_put_smid_default(ioc, smid);
4590         wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
4591         if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4592                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4593                     ioc->name, __func__);
4594                 _debug_dump_mf(mpi_request,
4595                     sizeof(Mpi2PortEnableRequest_t)/4);
4596                 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4597                         r = -EFAULT;
4598                 else
4599                         r = -ETIME;
4600                 goto out;
4601         }
4602
4603         mpi_reply = ioc->port_enable_cmds.reply;
4604         ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4605         if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4606                 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4607                     ioc->name, __func__, ioc_status);
4608                 r = -EFAULT;
4609                 goto out;
4610         }
4611
4612  out:
4613         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4614         pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4615             "SUCCESS" : "FAILED"));
4616         return r;
4617 }
4618
4619 /**
4620  * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4621  * @ioc: per adapter object
4622  *
4623  * Returns 0 for success, non-zero for failure.
4624  */
4625 int
4626 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4627 {
4628         Mpi2PortEnableRequest_t *mpi_request;
4629         u16 smid;
4630
4631         pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4632
4633         if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4634                 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4635                     ioc->name, __func__);
4636                 return -EAGAIN;
4637         }
4638
4639         smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4640         if (!smid) {
4641                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4642                     ioc->name, __func__);
4643                 return -EAGAIN;
4644         }
4645
4646         ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4647         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4648         ioc->port_enable_cmds.smid = smid;
4649         memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4650         mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4651
4652         mpt3sas_base_put_smid_default(ioc, smid);
4653         return 0;
4654 }
4655
4656 /**
4657  * _base_determine_wait_on_discovery - desposition
4658  * @ioc: per adapter object
4659  *
4660  * Decide whether to wait on discovery to complete. Used to either
4661  * locate boot device, or report volumes ahead of physical devices.
4662  *
4663  * Returns 1 for wait, 0 for don't wait
4664  */
4665 static int
4666 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4667 {
4668         /* We wait for discovery to complete if IR firmware is loaded.
4669          * The sas topology events arrive before PD events, so we need time to
4670          * turn on the bit in ioc->pd_handles to indicate PD
4671          * Also, it maybe required to report Volumes ahead of physical
4672          * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4673          */
4674         if (ioc->ir_firmware)
4675                 return 1;
4676
4677         /* if no Bios, then we don't need to wait */
4678         if (!ioc->bios_pg3.BiosVersion)
4679                 return 0;
4680
4681         /* Bios is present, then we drop down here.
4682          *
4683          * If there any entries in the Bios Page 2, then we wait
4684          * for discovery to complete.
4685          */
4686
4687         /* Current Boot Device */
4688         if ((ioc->bios_pg2.CurrentBootDeviceForm &
4689             MPI2_BIOSPAGE2_FORM_MASK) ==
4690             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4691         /* Request Boot Device */
4692            (ioc->bios_pg2.ReqBootDeviceForm &
4693             MPI2_BIOSPAGE2_FORM_MASK) ==
4694             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4695         /* Alternate Request Boot Device */
4696            (ioc->bios_pg2.ReqAltBootDeviceForm &
4697             MPI2_BIOSPAGE2_FORM_MASK) ==
4698             MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4699                 return 0;
4700
4701         return 1;
4702 }
4703
4704 /**
4705  * _base_unmask_events - turn on notification for this event
4706  * @ioc: per adapter object
4707  * @event: firmware event
4708  *
4709  * The mask is stored in ioc->event_masks.
4710  */
4711 static void
4712 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4713 {
4714         u32 desired_event;
4715
4716         if (event >= 128)
4717                 return;
4718
4719         desired_event = (1 << (event % 32));
4720
4721         if (event < 32)
4722                 ioc->event_masks[0] &= ~desired_event;
4723         else if (event < 64)
4724                 ioc->event_masks[1] &= ~desired_event;
4725         else if (event < 96)
4726                 ioc->event_masks[2] &= ~desired_event;
4727         else if (event < 128)
4728                 ioc->event_masks[3] &= ~desired_event;
4729 }
4730
4731 /**
4732  * _base_event_notification - send event notification
4733  * @ioc: per adapter object
4734  *
4735  * Returns 0 for success, non-zero for failure.
4736  */
4737 static int
4738 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
4739 {
4740         Mpi2EventNotificationRequest_t *mpi_request;
4741         u16 smid;
4742         int r = 0;
4743         int i;
4744
4745         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4746             __func__));
4747
4748         if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4749                 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4750                     ioc->name, __func__);
4751                 return -EAGAIN;
4752         }
4753
4754         smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4755         if (!smid) {
4756                 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4757                     ioc->name, __func__);
4758                 return -EAGAIN;
4759         }
4760         ioc->base_cmds.status = MPT3_CMD_PENDING;
4761         mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4762         ioc->base_cmds.smid = smid;
4763         memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4764         mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4765         mpi_request->VF_ID = 0; /* TODO */
4766         mpi_request->VP_ID = 0;
4767         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4768                 mpi_request->EventMasks[i] =
4769                     cpu_to_le32(ioc->event_masks[i]);
4770         init_completion(&ioc->base_cmds.done);
4771         mpt3sas_base_put_smid_default(ioc, smid);
4772         wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4773         if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4774                 pr_err(MPT3SAS_FMT "%s: timeout\n",
4775                     ioc->name, __func__);
4776                 _debug_dump_mf(mpi_request,
4777                     sizeof(Mpi2EventNotificationRequest_t)/4);
4778                 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4779                         r = -EFAULT;
4780                 else
4781                         r = -ETIME;
4782         } else
4783                 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4784                     ioc->name, __func__));
4785         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4786         return r;
4787 }
4788
4789 /**
4790  * mpt3sas_base_validate_event_type - validating event types
4791  * @ioc: per adapter object
4792  * @event: firmware event
4793  *
4794  * This will turn on firmware event notification when application
4795  * ask for that event. We don't mask events that are already enabled.
4796  */
4797 void
4798 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4799 {
4800         int i, j;
4801         u32 event_mask, desired_event;
4802         u8 send_update_to_fw;
4803
4804         for (i = 0, send_update_to_fw = 0; i <
4805             MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4806                 event_mask = ~event_type[i];
4807                 desired_event = 1;
4808                 for (j = 0; j < 32; j++) {
4809                         if (!(event_mask & desired_event) &&
4810                             (ioc->event_masks[i] & desired_event)) {
4811                                 ioc->event_masks[i] &= ~desired_event;
4812                                 send_update_to_fw = 1;
4813                         }
4814                         desired_event = (desired_event << 1);
4815                 }
4816         }
4817
4818         if (!send_update_to_fw)
4819                 return;
4820
4821         mutex_lock(&ioc->base_cmds.mutex);
4822         _base_event_notification(ioc);
4823         mutex_unlock(&ioc->base_cmds.mutex);
4824 }
4825
4826 /**
4827  * _base_diag_reset - the "big hammer" start of day reset
4828  * @ioc: per adapter object
4829  *
4830  * Returns 0 for success, non-zero for failure.
4831  */
4832 static int
4833 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
4834 {
4835         u32 host_diagnostic;
4836         u32 ioc_state;
4837         u32 count;
4838         u32 hcb_size;
4839
4840         pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4841
4842         drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4843             ioc->name));
4844
4845         count = 0;
4846         do {
4847                 /* Write magic sequence to WriteSequence register
4848                  * Loop until in diagnostic mode
4849                  */
4850                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4851                         "write magic sequence\n", ioc->name));
4852                 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4853                 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4854                 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4855                 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4856                 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4857                 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4858                 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4859
4860                 /* wait 100 msec */
4861                 msleep(100);
4862
4863                 if (count++ > 20)
4864                         goto out;
4865
4866                 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4867                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4868                         "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4869                     ioc->name, count, host_diagnostic));
4870
4871         } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4872
4873         hcb_size = readl(&ioc->chip->HCBSize);
4874
4875         drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4876             ioc->name));
4877         writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4878              &ioc->chip->HostDiagnostic);
4879
4880         /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4881         msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4882
4883         /* Approximately 300 second max wait */
4884         for (count = 0; count < (300000000 /
4885                 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
4886
4887                 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4888
4889                 if (host_diagnostic == 0xFFFFFFFF)
4890                         goto out;
4891                 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4892                         break;
4893
4894                 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
4895         }
4896
4897         if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4898
4899                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4900                 "restart the adapter assuming the HCB Address points to good F/W\n",
4901                     ioc->name));
4902                 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4903                 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4904                 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4905
4906                 drsprintk(ioc, pr_info(MPT3SAS_FMT
4907                     "re-enable the HCDW\n", ioc->name));
4908                 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4909                     &ioc->chip->HCBSize);
4910         }
4911
4912         drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4913             ioc->name));
4914         writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4915             &ioc->chip->HostDiagnostic);
4916
4917         drsprintk(ioc, pr_info(MPT3SAS_FMT
4918                 "disable writes to the diagnostic register\n", ioc->name));
4919         writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4920
4921         drsprintk(ioc, pr_info(MPT3SAS_FMT
4922                 "Wait for FW to go to the READY state\n", ioc->name));
4923         ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
4924         if (ioc_state) {
4925                 pr_err(MPT3SAS_FMT
4926                         "%s: failed going to ready state (ioc_state=0x%x)\n",
4927                         ioc->name, __func__, ioc_state);
4928                 goto out;
4929         }
4930
4931         pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4932         return 0;
4933
4934  out:
4935         pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4936         return -EFAULT;
4937 }
4938
4939 /**
4940  * _base_make_ioc_ready - put controller in READY state
4941  * @ioc: per adapter object
4942  * @type: FORCE_BIG_HAMMER or SOFT_RESET
4943  *
4944  * Returns 0 for success, non-zero for failure.
4945  */
4946 static int
4947 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
4948 {
4949         u32 ioc_state;
4950         int rc;
4951         int count;
4952
4953         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4954             __func__));
4955
4956         if (ioc->pci_error_recovery)
4957                 return 0;
4958
4959         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4960         dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4961             ioc->name, __func__, ioc_state));
4962
4963         /* if in RESET state, it should move to READY state shortly */
4964         count = 0;
4965         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4966                 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4967                     MPI2_IOC_STATE_READY) {
4968                         if (count++ == 10) {
4969                                 pr_err(MPT3SAS_FMT
4970                                         "%s: failed going to ready state (ioc_state=0x%x)\n",
4971                                     ioc->name, __func__, ioc_state);
4972                                 return -EFAULT;
4973                         }
4974                         ssleep(1);
4975                         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4976                 }
4977         }
4978
4979         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4980                 return 0;
4981
4982         if (ioc_state & MPI2_DOORBELL_USED) {
4983                 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4984                         "unexpected doorbell active!\n",
4985                         ioc->name));
4986                 goto issue_diag_reset;
4987         }
4988
4989         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4990                 mpt3sas_base_fault_info(ioc, ioc_state &
4991                     MPI2_DOORBELL_DATA_MASK);
4992                 goto issue_diag_reset;
4993         }
4994
4995         if (type == FORCE_BIG_HAMMER)
4996                 goto issue_diag_reset;
4997
4998         if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4999                 if (!(_base_send_ioc_reset(ioc,
5000                     MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
5001                         return 0;
5002         }
5003
5004  issue_diag_reset:
5005         rc = _base_diag_reset(ioc);
5006         return rc;
5007 }
5008
5009 /**
5010  * _base_make_ioc_operational - put controller in OPERATIONAL state
5011  * @ioc: per adapter object
5012  *
5013  * Returns 0 for success, non-zero for failure.
5014  */
5015 static int
5016 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
5017 {
5018         int r, i, index;
5019         unsigned long   flags;
5020         u32 reply_address;
5021         u16 smid;
5022         struct _tr_list *delayed_tr, *delayed_tr_next;
5023         struct _sc_list *delayed_sc, *delayed_sc_next;
5024         struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
5025         u8 hide_flag;
5026         struct adapter_reply_queue *reply_q;
5027         Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
5028
5029         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5030             __func__));
5031
5032         /* clean the delayed target reset list */
5033         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5034             &ioc->delayed_tr_list, list) {
5035                 list_del(&delayed_tr->list);
5036                 kfree(delayed_tr);
5037         }
5038
5039
5040         list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5041             &ioc->delayed_tr_volume_list, list) {
5042                 list_del(&delayed_tr->list);
5043                 kfree(delayed_tr);
5044         }
5045
5046         list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5047             &ioc->delayed_sc_list, list) {
5048                 list_del(&delayed_sc->list);
5049                 kfree(delayed_sc);
5050         }
5051
5052         list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5053             &ioc->delayed_event_ack_list, list) {
5054                 list_del(&delayed_event_ack->list);
5055                 kfree(delayed_event_ack);
5056         }
5057
5058         /* initialize the scsi lookup free list */
5059         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5060         INIT_LIST_HEAD(&ioc->free_list);
5061         smid = 1;
5062         for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5063                 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5064                 ioc->scsi_lookup[i].cb_idx = 0xFF;
5065                 ioc->scsi_lookup[i].smid = smid;
5066                 ioc->scsi_lookup[i].scmd = NULL;
5067                 ioc->scsi_lookup[i].direct_io = 0;
5068                 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5069                     &ioc->free_list);
5070         }
5071
5072         /* hi-priority queue */
5073         INIT_LIST_HEAD(&ioc->hpr_free_list);
5074         smid = ioc->hi_priority_smid;
5075         for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5076                 ioc->hpr_lookup[i].cb_idx = 0xFF;
5077                 ioc->hpr_lookup[i].smid = smid;
5078                 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5079                     &ioc->hpr_free_list);
5080         }
5081
5082         /* internal queue */
5083         INIT_LIST_HEAD(&ioc->internal_free_list);
5084         smid = ioc->internal_smid;
5085         for (i = 0; i < ioc->internal_depth; i++, smid++) {
5086                 ioc->internal_lookup[i].cb_idx = 0xFF;
5087                 ioc->internal_lookup[i].smid = smid;
5088                 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5089                     &ioc->internal_free_list);
5090         }
5091
5092         /* chain pool */
5093         INIT_LIST_HEAD(&ioc->free_chain_list);
5094         for (i = 0; i < ioc->chain_depth; i++)
5095                 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5096                     &ioc->free_chain_list);
5097
5098         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5099
5100         /* initialize Reply Free Queue */
5101         for (i = 0, reply_address = (u32)ioc->reply_dma ;
5102             i < ioc->reply_free_queue_depth ; i++, reply_address +=
5103             ioc->reply_sz)
5104                 ioc->reply_free[i] = cpu_to_le32(reply_address);
5105
5106         /* initialize reply queues */
5107         if (ioc->is_driver_loading)
5108                 _base_assign_reply_queues(ioc);
5109
5110         /* initialize Reply Post Free Queue */
5111         index = 0;
5112         reply_post_free_contig = ioc->reply_post[0].reply_post_free;
5113         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5114                 /*
5115                  * If RDPQ is enabled, switch to the next allocation.
5116                  * Otherwise advance within the contiguous region.
5117                  */
5118                 if (ioc->rdpq_array_enable) {
5119                         reply_q->reply_post_free =
5120                                 ioc->reply_post[index++].reply_post_free;
5121                 } else {
5122                         reply_q->reply_post_free = reply_post_free_contig;
5123                         reply_post_free_contig += ioc->reply_post_queue_depth;
5124                 }
5125
5126                 reply_q->reply_post_host_index = 0;
5127                 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5128                         reply_q->reply_post_free[i].Words =
5129                             cpu_to_le64(ULLONG_MAX);
5130                 if (!_base_is_controller_msix_enabled(ioc))
5131                         goto skip_init_reply_post_free_queue;
5132         }
5133  skip_init_reply_post_free_queue:
5134
5135         r = _base_send_ioc_init(ioc);
5136         if (r)
5137                 return r;
5138
5139         /* initialize reply free host index */
5140         ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5141         writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5142
5143         /* initialize reply post host index */
5144         list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5145                 if (ioc->msix96_vector)
5146                         writel((reply_q->msix_index & 7)<<
5147                            MPI2_RPHI_MSIX_INDEX_SHIFT,
5148                            ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5149                 else
5150                         writel(reply_q->msix_index <<
5151                                 MPI2_RPHI_MSIX_INDEX_SHIFT,
5152                                 &ioc->chip->ReplyPostHostIndex);
5153
5154                 if (!_base_is_controller_msix_enabled(ioc))
5155                         goto skip_init_reply_post_host_index;
5156         }
5157
5158  skip_init_reply_post_host_index:
5159
5160         _base_unmask_interrupts(ioc);
5161         r = _base_event_notification(ioc);
5162         if (r)
5163                 return r;
5164
5165         _base_static_config_pages(ioc);
5166
5167         if (ioc->is_driver_loading) {
5168
5169                 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5170                     == 0x80) {
5171                         hide_flag = (u8) (
5172                             le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5173                             MFG_PAGE10_HIDE_SSDS_MASK);
5174                         if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5175                                 ioc->mfg_pg10_hide_flag = hide_flag;
5176                 }
5177
5178                 ioc->wait_for_discovery_to_complete =
5179                     _base_determine_wait_on_discovery(ioc);
5180
5181                 return r; /* scan_start and scan_finished support */
5182         }
5183
5184         r = _base_send_port_enable(ioc);
5185         if (r)
5186                 return r;
5187
5188         return r;
5189 }
5190
5191 /**
5192  * mpt3sas_base_free_resources - free resources controller resources
5193  * @ioc: per adapter object
5194  *
5195  * Return nothing.
5196  */
5197 void
5198 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5199 {
5200         dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5201             __func__));
5202
5203         /* synchronizing freeing resource with pci_access_mutex lock */
5204         mutex_lock(&ioc->pci_access_mutex);
5205         if (ioc->chip_phys && ioc->chip) {
5206                 _base_mask_interrupts(ioc);
5207                 ioc->shost_recovery = 1;
5208                 _base_make_ioc_ready(ioc, SOFT_RESET);
5209                 ioc->shost_recovery = 0;
5210         }
5211
5212         mpt3sas_base_unmap_resources(ioc);
5213         mutex_unlock(&ioc->pci_access_mutex);
5214         return;
5215 }
5216
5217 /**
5218  * mpt3sas_base_attach - attach controller instance
5219  * @ioc: per adapter object
5220  *
5221  * Returns 0 for success, non-zero for failure.
5222  */
5223 int
5224 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5225 {
5226         int r, i;
5227         int cpu_id, last_cpu_id = 0;
5228
5229         dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5230             __func__));
5231
5232         /* setup cpu_msix_table */
5233         ioc->cpu_count = num_online_cpus();
5234         for_each_online_cpu(cpu_id)
5235                 last_cpu_id = cpu_id;
5236         ioc->cpu_msix_table_sz = last_cpu_id + 1;
5237         ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5238         ioc->reply_queue_count = 1;
5239         if (!ioc->cpu_msix_table) {
5240                 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5241                         "allocation for cpu_msix_table failed!!!\n",
5242                         ioc->name));
5243                 r = -ENOMEM;
5244                 goto out_free_resources;
5245         }
5246
5247         if (ioc->is_warpdrive) {
5248                 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5249                     sizeof(resource_size_t *), GFP_KERNEL);
5250                 if (!ioc->reply_post_host_index) {
5251                         dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5252                                 "for cpu_msix_table failed!!!\n", ioc->name));
5253                         r = -ENOMEM;
5254                         goto out_free_resources;
5255                 }
5256         }
5257
5258         ioc->rdpq_array_enable_assigned = 0;
5259         ioc->dma_mask = 0;
5260         r = mpt3sas_base_map_resources(ioc);
5261         if (r)
5262                 goto out_free_resources;
5263
5264         pci_set_drvdata(ioc->pdev, ioc->shost);
5265         r = _base_get_ioc_facts(ioc);
5266         if (r)
5267                 goto out_free_resources;
5268
5269         switch (ioc->hba_mpi_version_belonged) {
5270         case MPI2_VERSION:
5271                 ioc->build_sg_scmd = &_base_build_sg_scmd;
5272                 ioc->build_sg = &_base_build_sg;
5273                 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5274                 break;
5275         case MPI25_VERSION:
5276         case MPI26_VERSION:
5277                 /*
5278                  * In SAS3.0,
5279                  * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5280                  * Target Status - all require the IEEE formated scatter gather
5281                  * elements.
5282                  */
5283                 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5284                 ioc->build_sg = &_base_build_sg_ieee;
5285                 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5286                 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5287                 break;
5288         }
5289
5290         /*
5291          * These function pointers for other requests that don't
5292          * the require IEEE scatter gather elements.
5293          *
5294          * For example Configuration Pages and SAS IOUNIT Control don't.
5295          */
5296         ioc->build_sg_mpi = &_base_build_sg;
5297         ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5298
5299         r = _base_make_ioc_ready(ioc, SOFT_RESET);
5300         if (r)
5301                 goto out_free_resources;
5302
5303         ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5304             sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5305         if (!ioc->pfacts) {
5306                 r = -ENOMEM;
5307                 goto out_free_resources;
5308         }
5309
5310         for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5311                 r = _base_get_port_facts(ioc, i);
5312                 if (r)
5313                         goto out_free_resources;
5314         }
5315
5316         r = _base_allocate_memory_pools(ioc);
5317         if (r)
5318                 goto out_free_resources;
5319
5320         init_waitqueue_head(&ioc->reset_wq);
5321
5322         /* allocate memory pd handle bitmask list */
5323         ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5324         if (ioc->facts.MaxDevHandle % 8)
5325                 ioc->pd_handles_sz++;
5326         ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5327             GFP_KERNEL);
5328         if (!ioc->pd_handles) {
5329                 r = -ENOMEM;
5330                 goto out_free_resources;
5331         }
5332         ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5333             GFP_KERNEL);
5334         if (!ioc->blocking_handles) {
5335                 r = -ENOMEM;
5336                 goto out_free_resources;
5337         }
5338
5339         ioc->fwfault_debug = mpt3sas_fwfault_debug;
5340
5341         /* base internal command bits */
5342         mutex_init(&ioc->base_cmds.mutex);
5343         ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5344         ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5345
5346         /* port_enable command bits */
5347         ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5348         ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5349
5350         /* transport internal command bits */
5351         ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5352         ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5353         mutex_init(&ioc->transport_cmds.mutex);
5354
5355         /* scsih internal command bits */
5356         ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5357         ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5358         mutex_init(&ioc->scsih_cmds.mutex);
5359
5360         /* task management internal command bits */
5361         ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5362         ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5363         mutex_init(&ioc->tm_cmds.mutex);
5364
5365         /* config page internal command bits */
5366         ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5367         ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5368         mutex_init(&ioc->config_cmds.mutex);
5369
5370         /* ctl module internal command bits */
5371         ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5372         ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5373         ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5374         mutex_init(&ioc->ctl_cmds.mutex);
5375
5376         if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5377             !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5378             !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5379             !ioc->ctl_cmds.sense) {
5380                 r = -ENOMEM;
5381                 goto out_free_resources;
5382         }
5383
5384         for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5385                 ioc->event_masks[i] = -1;
5386
5387         /* here we enable the events we care about */
5388         _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5389         _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5390         _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5391         _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5392         _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5393         _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5394         _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5395         _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5396         _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5397         _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
5398         _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
5399         if (ioc->hba_mpi_version_belonged == MPI26_VERSION)
5400                 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
5401
5402         r = _base_make_ioc_operational(ioc);
5403         if (r)
5404                 goto out_free_resources;
5405
5406         ioc->non_operational_loop = 0;
5407         return 0;
5408
5409  out_free_resources:
5410
5411         ioc->remove_host = 1;
5412
5413         mpt3sas_base_free_resources(ioc);
5414         _base_release_memory_pools(ioc);
5415         pci_set_drvdata(ioc->pdev, NULL);
5416         kfree(ioc->cpu_msix_table);
5417         if (ioc->is_warpdrive)
5418                 kfree(ioc->reply_post_host_index);
5419         kfree(ioc->pd_handles);
5420         kfree(ioc->blocking_handles);
5421         kfree(ioc->tm_cmds.reply);
5422         kfree(ioc->transport_cmds.reply);
5423         kfree(ioc->scsih_cmds.reply);
5424         kfree(ioc->config_cmds.reply);
5425         kfree(ioc->base_cmds.reply);
5426         kfree(ioc->port_enable_cmds.reply);
5427         kfree(ioc->ctl_cmds.reply);
5428         kfree(ioc->ctl_cmds.sense);
5429         kfree(ioc->pfacts);
5430         ioc->ctl_cmds.reply = NULL;
5431         ioc->base_cmds.reply = NULL;
5432         ioc->tm_cmds.reply = NULL;
5433         ioc->scsih_cmds.reply = NULL;
5434         ioc->transport_cmds.reply = NULL;
5435         ioc->config_cmds.reply = NULL;
5436         ioc->pfacts = NULL;
5437         return r;
5438 }
5439
5440
5441 /**
5442  * mpt3sas_base_detach - remove controller instance
5443  * @ioc: per adapter object
5444  *
5445  * Return nothing.
5446  */
5447 void
5448 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5449 {
5450         dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5451             __func__));
5452
5453         mpt3sas_base_stop_watchdog(ioc);
5454         mpt3sas_base_free_resources(ioc);
5455         _base_release_memory_pools(ioc);
5456         pci_set_drvdata(ioc->pdev, NULL);
5457         kfree(ioc->cpu_msix_table);
5458         if (ioc->is_warpdrive)
5459                 kfree(ioc->reply_post_host_index);
5460         kfree(ioc->pd_handles);
5461         kfree(ioc->blocking_handles);
5462         kfree(ioc->pfacts);
5463         kfree(ioc->ctl_cmds.reply);
5464         kfree(ioc->ctl_cmds.sense);
5465         kfree(ioc->base_cmds.reply);
5466         kfree(ioc->port_enable_cmds.reply);
5467         kfree(ioc->tm_cmds.reply);
5468         kfree(ioc->transport_cmds.reply);
5469         kfree(ioc->scsih_cmds.reply);
5470         kfree(ioc->config_cmds.reply);
5471 }
5472
5473 /**
5474  * _base_reset_handler - reset callback handler (for base)
5475  * @ioc: per adapter object
5476  * @reset_phase: phase
5477  *
5478  * The handler for doing any required cleanup or initialization.
5479  *
5480  * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5481  * MPT3_IOC_DONE_RESET
5482  *
5483  * Return nothing.
5484  */
5485 static void
5486 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5487 {
5488         mpt3sas_scsih_reset_handler(ioc, reset_phase);
5489         mpt3sas_ctl_reset_handler(ioc, reset_phase);
5490         switch (reset_phase) {
5491         case MPT3_IOC_PRE_RESET:
5492                 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5493                 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5494                 break;
5495         case MPT3_IOC_AFTER_RESET:
5496                 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5497                 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5498                 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5499                         ioc->transport_cmds.status |= MPT3_CMD_RESET;
5500                         mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5501                         complete(&ioc->transport_cmds.done);
5502                 }
5503                 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5504                         ioc->base_cmds.status |= MPT3_CMD_RESET;
5505                         mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5506                         complete(&ioc->base_cmds.done);
5507                 }
5508                 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5509                         ioc->port_enable_failed = 1;
5510                         ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5511                         mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5512                         if (ioc->is_driver_loading) {
5513                                 ioc->start_scan_failed =
5514                                     MPI2_IOCSTATUS_INTERNAL_ERROR;
5515                                 ioc->start_scan = 0;
5516                                 ioc->port_enable_cmds.status =
5517                                     MPT3_CMD_NOT_USED;
5518                         } else
5519                                 complete(&ioc->port_enable_cmds.done);
5520                 }
5521                 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5522                         ioc->config_cmds.status |= MPT3_CMD_RESET;
5523                         mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5524                         ioc->config_cmds.smid = USHRT_MAX;
5525                         complete(&ioc->config_cmds.done);
5526                 }
5527                 break;
5528         case MPT3_IOC_DONE_RESET:
5529                 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5530                         "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5531                 break;
5532         }
5533 }
5534
5535 /**
5536  * _wait_for_commands_to_complete - reset controller
5537  * @ioc: Pointer to MPT_ADAPTER structure
5538  *
5539  * This function waiting(3s) for all pending commands to complete
5540  * prior to putting controller in reset.
5541  */
5542 static void
5543 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
5544 {
5545         u32 ioc_state;
5546         unsigned long flags;
5547         u16 i;
5548
5549         ioc->pending_io_count = 0;
5550
5551         ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5552         if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5553                 return;
5554
5555         /* pending command count */
5556         spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5557         for (i = 0; i < ioc->scsiio_depth; i++)
5558                 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5559                         ioc->pending_io_count++;
5560         spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5561
5562         if (!ioc->pending_io_count)
5563                 return;
5564
5565         /* wait for pending commands to complete */
5566         wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5567 }
5568
5569 /**
5570  * mpt3sas_base_hard_reset_handler - reset controller
5571  * @ioc: Pointer to MPT_ADAPTER structure
5572  * @type: FORCE_BIG_HAMMER or SOFT_RESET
5573  *
5574  * Returns 0 for success, non-zero for failure.
5575  */
5576 int
5577 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
5578         enum reset_type type)
5579 {
5580         int r;
5581         unsigned long flags;
5582         u32 ioc_state;
5583         u8 is_fault = 0, is_trigger = 0;
5584
5585         dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5586             __func__));
5587
5588         if (ioc->pci_error_recovery) {
5589                 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5590                     ioc->name, __func__);
5591                 r = 0;
5592                 goto out_unlocked;
5593         }
5594
5595         if (mpt3sas_fwfault_debug)
5596                 mpt3sas_halt_firmware(ioc);
5597
5598         /* wait for an active reset in progress to complete */
5599         if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5600                 do {
5601                         ssleep(1);
5602                 } while (ioc->shost_recovery == 1);
5603                 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5604                     __func__));
5605                 return ioc->ioc_reset_in_progress_status;
5606         }
5607
5608         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5609         ioc->shost_recovery = 1;
5610         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5611
5612         if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5613             MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5614             (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5615             MPT3_DIAG_BUFFER_IS_RELEASED))) {
5616                 is_trigger = 1;
5617                 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5618                 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5619                         is_fault = 1;
5620         }
5621         _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5622         _wait_for_commands_to_complete(ioc);
5623         _base_mask_interrupts(ioc);
5624         r = _base_make_ioc_ready(ioc, type);
5625         if (r)
5626                 goto out;
5627         _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5628
5629         /* If this hard reset is called while port enable is active, then
5630          * there is no reason to call make_ioc_operational
5631          */
5632         if (ioc->is_driver_loading && ioc->port_enable_failed) {
5633                 ioc->remove_host = 1;
5634                 r = -EFAULT;
5635                 goto out;
5636         }
5637         r = _base_get_ioc_facts(ioc);
5638         if (r)
5639                 goto out;
5640
5641         if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5642                 panic("%s: Issue occurred with flashing controller firmware."
5643                       "Please reboot the system and ensure that the correct"
5644                       " firmware version is running\n", ioc->name);
5645
5646         r = _base_make_ioc_operational(ioc);
5647         if (!r)
5648                 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5649
5650  out:
5651         dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5652             ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5653
5654         spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5655         ioc->ioc_reset_in_progress_status = r;
5656         ioc->shost_recovery = 0;
5657         spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5658         ioc->ioc_reset_count++;
5659         mutex_unlock(&ioc->reset_in_progress_mutex);
5660
5661  out_unlocked:
5662         if ((r == 0) && is_trigger) {
5663                 if (is_fault)
5664                         mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5665                 else
5666                         mpt3sas_trigger_master(ioc,
5667                             MASTER_TRIGGER_ADAPTER_RESET);
5668         }
5669         dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5670             __func__));
5671         return r;
5672 }