drivers/scsi/mpt3sas/mpi/mpi2_ioc.h

   1 /*
   2  * Copyright 2000-2015 Avago Technologies.  All rights reserved.
   3  *
   4  *
   5  *          Name:  mpi2_ioc.h
   6  *         Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7  * Creation Date:  October 11, 2006
   8  *
   9  * mpi2_ioc.h Version:  02.00.27
  10  *
  11  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  12  *       prefix are for use only on MPI v2.5 products, and must not be used
  13  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
  14  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  15  *
  16  * Version History
  17  * ---------------
  18  *
  19  * Date      Version   Description
  20  * --------  --------  ------------------------------------------------------
  21  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  22  * 06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  23  *                     MaxTargets.
  24  *                     Added TotalImageSize field to FWDownload Request.
  25  *                     Added reserved words to FWUpload Request.
  26  * 06-26-07  02.00.02  Added IR Configuration Change List Event.
  27  * 08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  28  *                     request and replaced it with
  29  *                     ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  30  *                     Replaced the MinReplyQueueDepth field of the IOCFacts
  31  *                     reply with MaxReplyDescriptorPostQueueDepth.
  32  *                     Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  33  *                     depth for the Reply Descriptor Post Queue.
  34  *                     Added SASAddress field to Initiator Device Table
  35  *                     Overflow Event data.
  36  * 10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  37  *                     for SAS Initiator Device Status Change Event data.
  38  *                     Modified Reason Code defines for SAS Topology Change
  39  *                     List Event data, including adding a bit for PHY Vacant
  40  *                     status, and adding a mask for the Reason Code.
  41  *                     Added define for
  42  *                     MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  43  *                     Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  44  * 12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  45  *                     the IOCFacts Reply.
  46  *                     Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  47  *                     Moved MPI2_VERSION_UNION to mpi2.h.
  48  *                     Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  49  *                     instead of enables, and added SASBroadcastPrimitiveMasks
  50  *                     field.
  51  *                     Added Log Entry Added Event and related structure.
  52  * 02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  53  *                     Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  54  *                     Added MaxVolumes and MaxPersistentEntries fields to
  55  *                     IOCFacts reply.
  56  *                     Added ProtocalFlags and IOCCapabilities fields to
  57  *                     MPI2_FW_IMAGE_HEADER.
  58  *                     Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  59  * 03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  60  *                     a U16 (from a U32).
  61  *                     Removed extra 's' from EventMasks name.
  62  * 06-27-08  02.00.08  Fixed an offset in a comment.
  63  * 10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  64  *                     Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  65  *                     renamed MinReplyFrameSize to ReplyFrameSize.
  66  *                     Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  67  *                     Added two new RAIDOperation values for Integrated RAID
  68  *                     Operations Status Event data.
  69  *                     Added four new IR Configuration Change List Event data
  70  *                     ReasonCode values.
  71  *                     Added two new ReasonCode defines for SAS Device Status
  72  *                     Change Event data.
  73  *                     Added three new DiscoveryStatus bits for the SAS
  74  *                     Discovery event data.
  75  *                     Added Multiplexing Status Change bit to the PhyStatus
  76  *                     field of the SAS Topology Change List event data.
  77  *                     Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  78  *                     BootFlags are now product-specific.
  79  *                     Added defines for the indivdual signature bytes
  80  *                     for MPI2_INIT_IMAGE_FOOTER.
  81  * 01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  82  *                     Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  83  *                     define.
  84  *                     Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  85  *                     define.
  86  *                     Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  87  * 05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  88  *                     Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  89  *                     Added two new reason codes for SAS Device Status Change
  90  *                     Event.
  91  *                     Added new event: SAS PHY Counter.
  92  * 07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  93  *                     Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  94  *                     Added new product id family for 2208.
  95  * 10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  96  *                     Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  97  *                     Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  98  *                     Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  99  *                     Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
 100  *                     Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
 101  *                     Added Host Based Discovery Phy Event data.
 102  *                     Added defines for ProductID Product field
 103  *                     (MPI2_FW_HEADER_PID_).
 104  *                     Modified values for SAS ProductID Family
 105  *                     (MPI2_FW_HEADER_PID_FAMILY_).
 106  * 02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 107  *                     Added PowerManagementControl Request structures and
 108  *                     defines.
 109  * 05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 110  *                     Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 111  * 11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 112  * 02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 113  *                     SASNotifyPrimitiveMasks field to
 114  *                     MPI2_EVENT_NOTIFICATION_REQUEST.
 115  *                     Added Temperature Threshold Event.
 116  *                     Added Host Message Event.
 117  *                     Added Send Host Message request and reply.
 118  * 05-25-11  02.00.18  For Extended Image Header, added
 119  *                     MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 120  *                     MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 121  *                     Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 122  * 08-24-11  02.00.19  Added PhysicalPort field to
 123  *                     MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 124  *                     Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 125  * 11-18-11  02.00.20  Incorporating additions for MPI v2.5.
 126  * 03-29-12  02.00.21  Added a product specific range to event values.
 127  * 07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 128  *                     Added ElapsedSeconds field to
 129  *                     MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 130  * 08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
 131  *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
 132  *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
 133  *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
 134  *                      Added Encrypted Hash Extended Image.
 135  * 12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
 136  * 11-18-14  02.00.25  Updated copyright information.
 137  * 03-16-15  02.00.26  Updated for MPI v2.6.
 138  *                     Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
 139  *                     MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
 140  *                     Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
 141  *                     MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
 142  *                     Added MPI26_CTRL_OP_SHUTDOWN.
 143  * 08-25-15  02.00.27  Added IC ARCH Class based signature defines
 144  * --------------------------------------------------------------------------
 145  */
 146
 147 #ifndef MPI2_IOC_H
 148 #define MPI2_IOC_H
 149
 150 /*****************************************************************************
 151 *
 152 *              IOC Messages
 153 *
 154 *****************************************************************************/
 155
 156 /****************************************************************************
 157 * IOCInit message
 158 ****************************************************************************/
 159
 160 /*IOCInit Request message */
 161 typedef struct _MPI2_IOC_INIT_REQUEST {
 162         U8 WhoInit;             /*0x00 */
 163         U8 Reserved1;           /*0x01 */
 164         U8 ChainOffset;         /*0x02 */
 165         U8 Function;            /*0x03 */
 166         U16 Reserved2;          /*0x04 */
 167         U8 Reserved3;           /*0x06 */
 168         U8 MsgFlags;            /*0x07 */
 169         U8 VP_ID;               /*0x08 */
 170         U8 VF_ID;               /*0x09 */
 171         U16 Reserved4;          /*0x0A */
 172         U16 MsgVersion;         /*0x0C */
 173         U16 HeaderVersion;      /*0x0E */
 174         U32 Reserved5;          /*0x10 */
 175         U16 ConfigurationFlags; /* 0x14 */
 176         U8 HostPageSize;        /*0x16 */
 177         U8 HostMSIxVectors;     /*0x17 */
 178         U16 Reserved8;          /*0x18 */
 179         U16 SystemRequestFrameSize;     /*0x1A */
 180         U16 ReplyDescriptorPostQueueDepth;      /*0x1C */
 181         U16 ReplyFreeQueueDepth;        /*0x1E */
 182         U32 SenseBufferAddressHigh;     /*0x20 */
 183         U32 SystemReplyAddressHigh;     /*0x24 */
 184         U64 SystemRequestFrameBaseAddress;      /*0x28 */
 185         U64 ReplyDescriptorPostQueueAddress;    /*0x30 */
 186         U64 ReplyFreeQueueAddress;      /*0x38 */
 187         U64 TimeStamp;          /*0x40 */
 188 } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
 189         Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
 190
 191 /*WhoInit values */
 192 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 193 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 194 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 195 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 196 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 197 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 198
 199 /* MsgFlags */
 200 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 201
 202
 203 /*MsgVersion */
 204 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 205 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 206 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 207 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 208
 209 /*HeaderVersion */
 210 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 211 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 212 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 213 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 214
 215 /*minimum depth for a Reply Descriptor Post Queue */
 216 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 217
 218 /* Reply Descriptor Post Queue Array Entry */
 219 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
 220         U64                 RDPQBaseAddress;                    /* 0x00 */
 221         U32                 Reserved1;                          /* 0x08 */
 222         U32                 Reserved2;                          /* 0x0C */
 223 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 224 *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 225 Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
 226
 227
 228 /*IOCInit Reply message */
 229 typedef struct _MPI2_IOC_INIT_REPLY {
 230         U8 WhoInit;             /*0x00 */
 231         U8 Reserved1;           /*0x01 */
 232         U8 MsgLength;           /*0x02 */
 233         U8 Function;            /*0x03 */
 234         U16 Reserved2;          /*0x04 */
 235         U8 Reserved3;           /*0x06 */
 236         U8 MsgFlags;            /*0x07 */
 237         U8 VP_ID;               /*0x08 */
 238         U8 VF_ID;               /*0x09 */
 239         U16 Reserved4;          /*0x0A */
 240         U16 Reserved5;          /*0x0C */
 241         U16 IOCStatus;          /*0x0E */
 242         U32 IOCLogInfo;         /*0x10 */
 243 } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
 244         Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
 245
 246 /****************************************************************************
 247 * IOCFacts message
 248 ****************************************************************************/
 249
 250 /*IOCFacts Request message */
 251 typedef struct _MPI2_IOC_FACTS_REQUEST {
 252         U16 Reserved1;          /*0x00 */
 253         U8 ChainOffset;         /*0x02 */
 254         U8 Function;            /*0x03 */
 255         U16 Reserved2;          /*0x04 */
 256         U8 Reserved3;           /*0x06 */
 257         U8 MsgFlags;            /*0x07 */
 258         U8 VP_ID;               /*0x08 */
 259         U8 VF_ID;               /*0x09 */
 260         U16 Reserved4;          /*0x0A */
 261 } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
 262         Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
 263
 264 /*IOCFacts Reply message */
 265 typedef struct _MPI2_IOC_FACTS_REPLY {
 266         U16 MsgVersion;         /*0x00 */
 267         U8 MsgLength;           /*0x02 */
 268         U8 Function;            /*0x03 */
 269         U16 HeaderVersion;      /*0x04 */
 270         U8 IOCNumber;           /*0x06 */
 271         U8 MsgFlags;            /*0x07 */
 272         U8 VP_ID;               /*0x08 */
 273         U8 VF_ID;               /*0x09 */
 274         U16 Reserved1;          /*0x0A */
 275         U16 IOCExceptions;      /*0x0C */
 276         U16 IOCStatus;          /*0x0E */
 277         U32 IOCLogInfo;         /*0x10 */
 278         U8 MaxChainDepth;       /*0x14 */
 279         U8 WhoInit;             /*0x15 */
 280         U8 NumberOfPorts;       /*0x16 */
 281         U8 MaxMSIxVectors;      /*0x17 */
 282         U16 RequestCredit;      /*0x18 */
 283         U16 ProductID;          /*0x1A */
 284         U32 IOCCapabilities;    /*0x1C */
 285         MPI2_VERSION_UNION FWVersion;   /*0x20 */
 286         U16 IOCRequestFrameSize;        /*0x24 */
 287         U16 IOCMaxChainSegmentSize;     /*0x26 */
 288         U16 MaxInitiators;      /*0x28 */
 289         U16 MaxTargets;         /*0x2A */
 290         U16 MaxSasExpanders;    /*0x2C */
 291         U16 MaxEnclosures;      /*0x2E */
 292         U16 ProtocolFlags;      /*0x30 */
 293         U16 HighPriorityCredit; /*0x32 */
 294         U16 MaxReplyDescriptorPostQueueDepth;   /*0x34 */
 295         U8 ReplyFrameSize;      /*0x36 */
 296         U8 MaxVolumes;          /*0x37 */
 297         U16 MaxDevHandle;       /*0x38 */
 298         U16 MaxPersistentEntries;       /*0x3A */
 299         U16 MinDevHandle;       /*0x3C */
 300         U8 CurrentHostPageSize; /* 0x3E */
 301         U8 Reserved4;           /* 0x3F */
 302 } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
 303         Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
 304
 305 /*MsgVersion */
 306 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 307 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 308 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 309 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 310
 311 /*HeaderVersion */
 312 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 313 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 314 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 315 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 316
 317 /*IOCExceptions */
 318 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 319 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 320
 321 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 322 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 323 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 324 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 325 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 326
 327 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 328 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 329 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 330 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 331 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 332
 333 /*defines for WhoInit field are after the IOCInit Request */
 334
 335 /*ProductID field uses MPI2_FW_HEADER_PID_ */
 336
 337 /*IOCCapabilities */
 338 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ            (0x00080000)
 339 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
 340 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
 341 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 342 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 343 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 344 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 345 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 346 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 347 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 348 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 349 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 350 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 351 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 352 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 353 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 354
 355 /*ProtocolFlags */
 356 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 357 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 358
 359 /****************************************************************************
 360 * PortFacts message
 361 ****************************************************************************/
 362
 363 /*PortFacts Request message */
 364 typedef struct _MPI2_PORT_FACTS_REQUEST {
 365         U16 Reserved1;          /*0x00 */
 366         U8 ChainOffset;         /*0x02 */
 367         U8 Function;            /*0x03 */
 368         U16 Reserved2;          /*0x04 */
 369         U8 PortNumber;          /*0x06 */
 370         U8 MsgFlags;            /*0x07 */
 371         U8 VP_ID;               /*0x08 */
 372         U8 VF_ID;               /*0x09 */
 373         U16 Reserved3;          /*0x0A */
 374 } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
 375         Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
 376
 377 /*PortFacts Reply message */
 378 typedef struct _MPI2_PORT_FACTS_REPLY {
 379         U16 Reserved1;          /*0x00 */
 380         U8 MsgLength;           /*0x02 */
 381         U8 Function;            /*0x03 */
 382         U16 Reserved2;          /*0x04 */
 383         U8 PortNumber;          /*0x06 */
 384         U8 MsgFlags;            /*0x07 */
 385         U8 VP_ID;               /*0x08 */
 386         U8 VF_ID;               /*0x09 */
 387         U16 Reserved3;          /*0x0A */
 388         U16 Reserved4;          /*0x0C */
 389         U16 IOCStatus;          /*0x0E */
 390         U32 IOCLogInfo;         /*0x10 */
 391         U8 Reserved5;           /*0x14 */
 392         U8 PortType;            /*0x15 */
 393         U16 Reserved6;          /*0x16 */
 394         U16 MaxPostedCmdBuffers;        /*0x18 */
 395         U16 Reserved7;          /*0x1A */
 396 } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
 397         Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
 398
 399 /*PortType values */
 400 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 401 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 402 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 403 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 404 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 405
 406 /****************************************************************************
 407 * PortEnable message
 408 ****************************************************************************/
 409
 410 /*PortEnable Request message */
 411 typedef struct _MPI2_PORT_ENABLE_REQUEST {
 412         U16 Reserved1;          /*0x00 */
 413         U8 ChainOffset;         /*0x02 */
 414         U8 Function;            /*0x03 */
 415         U8 Reserved2;           /*0x04 */
 416         U8 PortFlags;           /*0x05 */
 417         U8 Reserved3;           /*0x06 */
 418         U8 MsgFlags;            /*0x07 */
 419         U8 VP_ID;               /*0x08 */
 420         U8 VF_ID;               /*0x09 */
 421         U16 Reserved4;          /*0x0A */
 422 } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
 423         Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
 424
 425 /*PortEnable Reply message */
 426 typedef struct _MPI2_PORT_ENABLE_REPLY {
 427         U16 Reserved1;          /*0x00 */
 428         U8 MsgLength;           /*0x02 */
 429         U8 Function;            /*0x03 */
 430         U8 Reserved2;           /*0x04 */
 431         U8 PortFlags;           /*0x05 */
 432         U8 Reserved3;           /*0x06 */
 433         U8 MsgFlags;            /*0x07 */
 434         U8 VP_ID;               /*0x08 */
 435         U8 VF_ID;               /*0x09 */
 436         U16 Reserved4;          /*0x0A */
 437         U16 Reserved5;          /*0x0C */
 438         U16 IOCStatus;          /*0x0E */
 439         U32 IOCLogInfo;         /*0x10 */
 440 } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
 441         Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
 442
 443 /****************************************************************************
 444 * EventNotification message
 445 ****************************************************************************/
 446
 447 /*EventNotification Request message */
 448 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 449
 450 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
 451         U16 Reserved1;          /*0x00 */
 452         U8 ChainOffset;         /*0x02 */
 453         U8 Function;            /*0x03 */
 454         U16 Reserved2;          /*0x04 */
 455         U8 Reserved3;           /*0x06 */
 456         U8 MsgFlags;            /*0x07 */
 457         U8 VP_ID;               /*0x08 */
 458         U8 VF_ID;               /*0x09 */
 459         U16 Reserved4;          /*0x0A */
 460         U32 Reserved5;          /*0x0C */
 461         U32 Reserved6;          /*0x10 */
 462         U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];      /*0x14 */
 463         U16 SASBroadcastPrimitiveMasks; /*0x24 */
 464         U16 SASNotifyPrimitiveMasks;    /*0x26 */
 465         U32 Reserved8;          /*0x28 */
 466 } MPI2_EVENT_NOTIFICATION_REQUEST,
 467         *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 468         Mpi2EventNotificationRequest_t,
 469         *pMpi2EventNotificationRequest_t;
 470
 471 /*EventNotification Reply message */
 472 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
 473         U16 EventDataLength;    /*0x00 */
 474         U8 MsgLength;           /*0x02 */
 475         U8 Function;            /*0x03 */
 476         U16 Reserved1;          /*0x04 */
 477         U8 AckRequired;         /*0x06 */
 478         U8 MsgFlags;            /*0x07 */
 479         U8 VP_ID;               /*0x08 */
 480         U8 VF_ID;               /*0x09 */
 481         U16 Reserved2;          /*0x0A */
 482         U16 Reserved3;          /*0x0C */
 483         U16 IOCStatus;          /*0x0E */
 484         U32 IOCLogInfo;         /*0x10 */
 485         U16 Event;              /*0x14 */
 486         U16 Reserved4;          /*0x16 */
 487         U32 EventContext;       /*0x18 */
 488         U32 EventData[1];       /*0x1C */
 489 } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 490         Mpi2EventNotificationReply_t,
 491         *pMpi2EventNotificationReply_t;
 492
 493 /*AckRequired */
 494 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 495 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 496
 497 /*Event */
 498 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 499 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 500 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 501 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 502 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E)    /*obsolete */
 503 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 504 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 505 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 506 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 507 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 508 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 509 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 510 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 511 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 512 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 513 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 514 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 515 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 516 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 517 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 518 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 519 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 520 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 521 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 522 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
 523 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION           (0x0034)
 524 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 525 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 526
 527 /*Log Entry Added Event data */
 528
 529 /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 530 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 531
 532 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
 533         U64 TimeStamp;          /*0x00 */
 534         U32 Reserved1;          /*0x08 */
 535         U16 LogSequence;        /*0x0C */
 536         U16 LogEntryQualifier;  /*0x0E */
 537         U8 VP_ID;               /*0x10 */
 538         U8 VF_ID;               /*0x11 */
 539         U16 Reserved2;          /*0x12 */
 540         U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];    /*0x14 */
 541 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 542         *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 543         Mpi2EventDataLogEntryAdded_t,
 544         *pMpi2EventDataLogEntryAdded_t;
 545
 546 /*GPIO Interrupt Event data */
 547
 548 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 549         U8 GPIONum;             /*0x00 */
 550         U8 Reserved1;           /*0x01 */
 551         U16 Reserved2;          /*0x02 */
 552 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 553         *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 554         Mpi2EventDataGpioInterrupt_t,
 555         *pMpi2EventDataGpioInterrupt_t;
 556
 557 /*Temperature Threshold Event data */
 558
 559 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 560         U16 Status;             /*0x00 */
 561         U8 SensorNum;           /*0x02 */
 562         U8 Reserved1;           /*0x03 */
 563         U16 CurrentTemperature; /*0x04 */
 564         U16 Reserved2;          /*0x06 */
 565         U32 Reserved3;          /*0x08 */
 566         U32 Reserved4;          /*0x0C */
 567 } MPI2_EVENT_DATA_TEMPERATURE,
 568         *PTR_MPI2_EVENT_DATA_TEMPERATURE,
 569         Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
 570
 571 /*Temperature Threshold Event data Status bits */
 572 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 573 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 574 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 575 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 576
 577 /*Host Message Event data */
 578
 579 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 580         U8 SourceVF_ID;         /*0x00 */
 581         U8 Reserved1;           /*0x01 */
 582         U16 Reserved2;          /*0x02 */
 583         U32 Reserved3;          /*0x04 */
 584         U32 HostData[1];        /*0x08 */
 585 } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 586         Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
 587
 588 /*Power Performance Change Event data */
 589
 590 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
 591         U8 CurrentPowerMode;    /*0x00 */
 592         U8 PreviousPowerMode;   /*0x01 */
 593         U16 Reserved1;          /*0x02 */
 594 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 595         *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 596         Mpi2EventDataPowerPerfChange_t,
 597         *pMpi2EventDataPowerPerfChange_t;
 598
 599 /*defines for CurrentPowerMode and PreviousPowerMode fields */
 600 #define MPI2_EVENT_PM_INIT_MASK              (0xC0)
 601 #define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
 602 #define MPI2_EVENT_PM_INIT_HOST              (0x40)
 603 #define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
 604 #define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
 605
 606 #define MPI2_EVENT_PM_MODE_MASK              (0x07)
 607 #define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
 608 #define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
 609 #define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
 610 #define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
 611 #define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
 612
 613 /* Active Cable Exception Event data */
 614
 615 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
 616         U32         ActiveCablePowerRequirement;        /* 0x00 */
 617         U8          ReasonCode;                         /* 0x04 */
 618         U8          ReceptacleID;                       /* 0x05 */
 619         U16         Reserved1;                          /* 0x06 */
 620 } MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
 621         *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
 622         Mpi26EventDataActiveCableExcept_t,
 623         *pMpi26EventDataActiveCableExcept_t;
 624
 625 /* defines for ReasonCode field */
 626 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER     (0x00)
 627
 628 /*Hard Reset Received Event data */
 629
 630 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
 631         U8 Reserved1;           /*0x00 */
 632         U8 Port;                /*0x01 */
 633         U16 Reserved2;          /*0x02 */
 634 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 635         *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 636         Mpi2EventDataHardResetReceived_t,
 637         *pMpi2EventDataHardResetReceived_t;
 638
 639 /*Task Set Full Event data */
 640 /*  this event is obsolete */
 641
 642 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
 643         U16 DevHandle;          /*0x00 */
 644         U16 CurrentDepth;       /*0x02 */
 645 } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 646         Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
 647
 648 /*SAS Device Status Change Event data */
 649
 650 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
 651         U16 TaskTag;            /*0x00 */
 652         U8 ReasonCode;          /*0x02 */
 653         U8 PhysicalPort;        /*0x03 */
 654         U8 ASC;                 /*0x04 */
 655         U8 ASCQ;                /*0x05 */
 656         U16 DevHandle;          /*0x06 */
 657         U32 Reserved2;          /*0x08 */
 658         U64 SASAddress;         /*0x0C */
 659         U8 LUN[8];              /*0x14 */
 660 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 661         *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 662         Mpi2EventDataSasDeviceStatusChange_t,
 663         *pMpi2EventDataSasDeviceStatusChange_t;
 664
 665 /*SAS Device Status Change Event data ReasonCode values */
 666 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 667 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 668 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 669 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 670 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 671 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 672 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 673 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 674 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 675 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 676 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 677 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 678 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 679
 680 /*Integrated RAID Operation Status Event data */
 681
 682 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
 683         U16 VolDevHandle;       /*0x00 */
 684         U16 Reserved1;          /*0x02 */
 685         U8 RAIDOperation;       /*0x04 */
 686         U8 PercentComplete;     /*0x05 */
 687         U16 Reserved2;          /*0x06 */
 688         U32 ElapsedSeconds;     /*0x08 */
 689 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 690         *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 691         Mpi2EventDataIrOperationStatus_t,
 692         *pMpi2EventDataIrOperationStatus_t;
 693
 694 /*Integrated RAID Operation Status Event data RAIDOperation values */
 695 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 696 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 697 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 698 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 699 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 700
 701 /*Integrated RAID Volume Event data */
 702
 703 typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
 704         U16 VolDevHandle;       /*0x00 */
 705         U8 ReasonCode;          /*0x02 */
 706         U8 Reserved1;           /*0x03 */
 707         U32 NewValue;           /*0x04 */
 708         U32 PreviousValue;      /*0x08 */
 709 } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
 710         Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
 711
 712 /*Integrated RAID Volume Event data ReasonCode values */
 713 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 714 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 715 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 716
 717 /*Integrated RAID Physical Disk Event data */
 718
 719 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
 720         U16 Reserved1;          /*0x00 */
 721         U8 ReasonCode;          /*0x02 */
 722         U8 PhysDiskNum;         /*0x03 */
 723         U16 PhysDiskDevHandle;  /*0x04 */
 724         U16 Reserved2;          /*0x06 */
 725         U16 Slot;               /*0x08 */
 726         U16 EnclosureHandle;    /*0x0A */
 727         U32 NewValue;           /*0x0C */
 728         U32 PreviousValue;      /*0x10 */
 729 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 730         *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 731         Mpi2EventDataIrPhysicalDisk_t,
 732         *pMpi2EventDataIrPhysicalDisk_t;
 733
 734 /*Integrated RAID Physical Disk Event data ReasonCode values */
 735 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 736 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 737 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 738
 739 /*Integrated RAID Configuration Change List Event data */
 740
 741 /*
 742  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 743  *one and check NumElements at runtime.
 744  */
 745 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 746 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 747 #endif
 748
 749 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
 750         U16 ElementFlags;       /*0x00 */
 751         U16 VolDevHandle;       /*0x02 */
 752         U8 ReasonCode;          /*0x04 */
 753         U8 PhysDiskNum;         /*0x05 */
 754         U16 PhysDiskDevHandle;  /*0x06 */
 755 } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 756         Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
 757
 758 /*IR Configuration Change List Event data ElementFlags values */
 759 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 760 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 761 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 762 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 763
 764 /*IR Configuration Change List Event data ReasonCode values */
 765 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 766 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 767 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 768 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 769 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 770 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 771 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 772 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 773 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 774
 775 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
 776         U8 NumElements;         /*0x00 */
 777         U8 Reserved1;           /*0x01 */
 778         U8 Reserved2;           /*0x02 */
 779         U8 ConfigNum;           /*0x03 */
 780         U32 Flags;              /*0x04 */
 781         MPI2_EVENT_IR_CONFIG_ELEMENT
 782                 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
 783 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 784         *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 785         Mpi2EventDataIrConfigChangeList_t,
 786         *pMpi2EventDataIrConfigChangeList_t;
 787
 788 /*IR Configuration Change List Event data Flags values */
 789 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 790
 791 /*SAS Discovery Event data */
 792
 793 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
 794         U8 Flags;               /*0x00 */
 795         U8 ReasonCode;          /*0x01 */
 796         U8 PhysicalPort;        /*0x02 */
 797         U8 Reserved1;           /*0x03 */
 798         U32 DiscoveryStatus;    /*0x04 */
 799 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 800         *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 801         Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
 802
 803 /*SAS Discovery Event data Flags values */
 804 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 805 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 806
 807 /*SAS Discovery Event data ReasonCode values */
 808 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 809 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 810
 811 /*SAS Discovery Event data DiscoveryStatus values */
 812 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 813 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 814 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 815 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 816 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 817 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 818 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 819 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 820 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 821 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 822 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 823 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 824 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 825 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 826 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 827 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 828 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 829 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 830 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 831 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 832
 833 /*SAS Broadcast Primitive Event data */
 834
 835 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
 836         U8 PhyNum;              /*0x00 */
 837         U8 Port;                /*0x01 */
 838         U8 PortWidth;           /*0x02 */
 839         U8 Primitive;           /*0x03 */
 840 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 841         *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 842         Mpi2EventDataSasBroadcastPrimitive_t,
 843         *pMpi2EventDataSasBroadcastPrimitive_t;
 844
 845 /*defines for the Primitive field */
 846 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 847 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 848 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 849 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 850 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 851 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 852 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 853 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 854
 855 /*SAS Notify Primitive Event data */
 856
 857 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 858         U8 PhyNum;              /*0x00 */
 859         U8 Port;                /*0x01 */
 860         U8 Reserved1;           /*0x02 */
 861         U8 Primitive;           /*0x03 */
 862 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 863         *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 864         Mpi2EventDataSasNotifyPrimitive_t,
 865         *pMpi2EventDataSasNotifyPrimitive_t;
 866
 867 /*defines for the Primitive field */
 868 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 869 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 870 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 871 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 872
 873 /*SAS Initiator Device Status Change Event data */
 874
 875 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
 876         U8 ReasonCode;          /*0x00 */
 877         U8 PhysicalPort;        /*0x01 */
 878         U16 DevHandle;          /*0x02 */
 879         U64 SASAddress;         /*0x04 */
 880 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 881         *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 882         Mpi2EventDataSasInitDevStatusChange_t,
 883         *pMpi2EventDataSasInitDevStatusChange_t;
 884
 885 /*SAS Initiator Device Status Change event ReasonCode values */
 886 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 887 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 888
 889 /*SAS Initiator Device Table Overflow Event data */
 890
 891 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
 892         U16 MaxInit;            /*0x00 */
 893         U16 CurrentInit;        /*0x02 */
 894         U64 SASAddress;         /*0x04 */
 895 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 896         *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 897         Mpi2EventDataSasInitTableOverflow_t,
 898         *pMpi2EventDataSasInitTableOverflow_t;
 899
 900 /*SAS Topology Change List Event data */
 901
 902 /*
 903  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 904  *one and check NumEntries at runtime.
 905  */
 906 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 907 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 908 #endif
 909
 910 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
 911         U16 AttachedDevHandle;  /*0x00 */
 912         U8 LinkRate;            /*0x02 */
 913         U8 PhyStatus;           /*0x03 */
 914 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 915         Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
 916
 917 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
 918         U16 EnclosureHandle;    /*0x00 */
 919         U16 ExpanderDevHandle;  /*0x02 */
 920         U8 NumPhys;             /*0x04 */
 921         U8 Reserved1;           /*0x05 */
 922         U16 Reserved2;          /*0x06 */
 923         U8 NumEntries;          /*0x08 */
 924         U8 StartPhyNum;         /*0x09 */
 925         U8 ExpStatus;           /*0x0A */
 926         U8 PhysicalPort;        /*0x0B */
 927         MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 928         PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT];     /*0x0C */
 929 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 930         *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 931         Mpi2EventDataSasTopologyChangeList_t,
 932         *pMpi2EventDataSasTopologyChangeList_t;
 933
 934 /*values for the ExpStatus field */
 935 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 936 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 937 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 938 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 939 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 940
 941 /*defines for the LinkRate field */
 942 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 943 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 944 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 945 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 946
 947 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 948 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 949 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 950 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 951 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 952 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 953 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 954 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 955 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 956 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 957 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
 958
 959 /*values for the PhyStatus field */
 960 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 961 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 962 /*values for the PhyStatus ReasonCode sub-field */
 963 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 964 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 965 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 966 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 967 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 968 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 969
 970 /*SAS Enclosure Device Status Change Event data */
 971
 972 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
 973         U16 EnclosureHandle;    /*0x00 */
 974         U8 ReasonCode;          /*0x02 */
 975         U8 PhysicalPort;        /*0x03 */
 976         U64 EnclosureLogicalID; /*0x04 */
 977         U16 NumSlots;           /*0x0C */
 978         U16 StartSlot;          /*0x0E */
 979         U32 PhyBits;            /*0x10 */
 980 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 981         *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 982         Mpi2EventDataSasEnclDevStatusChange_t,
 983         *pMpi2EventDataSasEnclDevStatusChange_t;
 984
 985 /*SAS Enclosure Device Status Change event ReasonCode values */
 986 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 987 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 988
 989 /*SAS PHY Counter Event data */
 990
 991 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 992         U64 TimeStamp;          /*0x00 */
 993         U32 Reserved1;          /*0x08 */
 994         U8 PhyEventCode;        /*0x0C */
 995         U8 PhyNum;              /*0x0D */
 996         U16 Reserved2;          /*0x0E */
 997         U32 PhyEventInfo;       /*0x10 */
 998         U8 CounterType;         /*0x14 */
 999         U8 ThresholdWindow;     /*0x15 */
1000         U8 TimeUnits;           /*0x16 */
1001         U8 Reserved3;           /*0x17 */
1002         U32 EventThreshold;     /*0x18 */
1003         U16 ThresholdFlags;     /*0x1C */
1004         U16 Reserved4;          /*0x1E */
1005 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1006         *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1007         Mpi2EventDataSasPhyCounter_t,
1008         *pMpi2EventDataSasPhyCounter_t;
1009
1010 /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1011  *for the PhyEventCode field */
1012
1013 /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1014  *for the CounterType field */
1015
1016 /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1017  *for the TimeUnits field */
1018
1019 /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1020  *for the ThresholdFlags field */
1021
1022 /*SAS Quiesce Event data */
1023
1024 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1025         U8 ReasonCode;          /*0x00 */
1026         U8 Reserved1;           /*0x01 */
1027         U16 Reserved2;          /*0x02 */
1028         U32 Reserved3;          /*0x04 */
1029 } MPI2_EVENT_DATA_SAS_QUIESCE,
1030         *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1031         Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1032
1033 /*SAS Quiesce Event data ReasonCode values */
1034 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1035 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1036
1037 /*Host Based Discovery Phy Event data */
1038
1039 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1040         U8 Flags;               /*0x00 */
1041         U8 NegotiatedLinkRate;  /*0x01 */
1042         U8 PhyNum;              /*0x02 */
1043         U8 PhysicalPort;        /*0x03 */
1044         U32 Reserved1;          /*0x04 */
1045         U8 InitialFrame[28];    /*0x08 */
1046 } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1047         Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1048
1049 /*values for the Flags field */
1050 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1051 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1052
1053 /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1054  *for the NegotiatedLinkRate field */
1055
1056 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1057         MPI2_EVENT_HBD_PHY_SAS Sas;
1058 } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1059         Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1060
1061 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1062         U8 DescriptorType;      /*0x00 */
1063         U8 Reserved1;           /*0x01 */
1064         U16 Reserved2;          /*0x02 */
1065         U32 Reserved3;          /*0x04 */
1066         MPI2_EVENT_HBD_DESCRIPTOR Descriptor;   /*0x08 */
1067 } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1068         Mpi2EventDataHbdPhy_t,
1069         *pMpi2EventDataMpi2EventDataHbdPhy_t;
1070
1071 /*values for the DescriptorType field */
1072 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
1073
1074 /****************************************************************************
1075 * EventAck message
1076 ****************************************************************************/
1077
1078 /*EventAck Request message */
1079 typedef struct _MPI2_EVENT_ACK_REQUEST {
1080         U16 Reserved1;          /*0x00 */
1081         U8 ChainOffset;         /*0x02 */
1082         U8 Function;            /*0x03 */
1083         U16 Reserved2;          /*0x04 */
1084         U8 Reserved3;           /*0x06 */
1085         U8 MsgFlags;            /*0x07 */
1086         U8 VP_ID;               /*0x08 */
1087         U8 VF_ID;               /*0x09 */
1088         U16 Reserved4;          /*0x0A */
1089         U16 Event;              /*0x0C */
1090         U16 Reserved5;          /*0x0E */
1091         U32 EventContext;       /*0x10 */
1092 } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1093         Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1094
1095 /*EventAck Reply message */
1096 typedef struct _MPI2_EVENT_ACK_REPLY {
1097         U16 Reserved1;          /*0x00 */
1098         U8 MsgLength;           /*0x02 */
1099         U8 Function;            /*0x03 */
1100         U16 Reserved2;          /*0x04 */
1101         U8 Reserved3;           /*0x06 */
1102         U8 MsgFlags;            /*0x07 */
1103         U8 VP_ID;               /*0x08 */
1104         U8 VF_ID;               /*0x09 */
1105         U16 Reserved4;          /*0x0A */
1106         U16 Reserved5;          /*0x0C */
1107         U16 IOCStatus;          /*0x0E */
1108         U32 IOCLogInfo;         /*0x10 */
1109 } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1110         Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1111
1112 /****************************************************************************
1113 * SendHostMessage message
1114 ****************************************************************************/
1115
1116 /*SendHostMessage Request message */
1117 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1118         U16 HostDataLength;     /*0x00 */
1119         U8 ChainOffset;         /*0x02 */
1120         U8 Function;            /*0x03 */
1121         U16 Reserved1;          /*0x04 */
1122         U8 Reserved2;           /*0x06 */
1123         U8 MsgFlags;            /*0x07 */
1124         U8 VP_ID;               /*0x08 */
1125         U8 VF_ID;               /*0x09 */
1126         U16 Reserved3;          /*0x0A */
1127         U8 Reserved4;           /*0x0C */
1128         U8 DestVF_ID;           /*0x0D */
1129         U16 Reserved5;          /*0x0E */
1130         U32 Reserved6;          /*0x10 */
1131         U32 Reserved7;          /*0x14 */
1132         U32 Reserved8;          /*0x18 */
1133         U32 Reserved9;          /*0x1C */
1134         U32 Reserved10;         /*0x20 */
1135         U32 HostData[1];        /*0x24 */
1136 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1137         *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1138         Mpi2SendHostMessageRequest_t,
1139         *pMpi2SendHostMessageRequest_t;
1140
1141 /*SendHostMessage Reply message */
1142 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1143         U16 HostDataLength;     /*0x00 */
1144         U8 MsgLength;           /*0x02 */
1145         U8 Function;            /*0x03 */
1146         U16 Reserved1;          /*0x04 */
1147         U8 Reserved2;           /*0x06 */
1148         U8 MsgFlags;            /*0x07 */
1149         U8 VP_ID;               /*0x08 */
1150         U8 VF_ID;               /*0x09 */
1151         U16 Reserved3;          /*0x0A */
1152         U16 Reserved4;          /*0x0C */
1153         U16 IOCStatus;          /*0x0E */
1154         U32 IOCLogInfo;         /*0x10 */
1155 } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1156         Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1157
1158 /****************************************************************************
1159 * FWDownload message
1160 ****************************************************************************/
1161
1162 /*MPI v2.0 FWDownload Request message */
1163 typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1164         U8 ImageType;           /*0x00 */
1165         U8 Reserved1;           /*0x01 */
1166         U8 ChainOffset;         /*0x02 */
1167         U8 Function;            /*0x03 */
1168         U16 Reserved2;          /*0x04 */
1169         U8 Reserved3;           /*0x06 */
1170         U8 MsgFlags;            /*0x07 */
1171         U8 VP_ID;               /*0x08 */
1172         U8 VF_ID;               /*0x09 */
1173         U16 Reserved4;          /*0x0A */
1174         U32 TotalImageSize;     /*0x0C */
1175         U32 Reserved5;          /*0x10 */
1176         MPI2_MPI_SGE_UNION SGL; /*0x14 */
1177 } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1178         Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1179
1180 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1181
1182 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1183 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1184 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1185 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1186 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1187 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1188 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1189 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1190 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C)
1191 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1192
1193 /*MPI v2.0 FWDownload TransactionContext Element */
1194 typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1195         U8 Reserved1;           /*0x00 */
1196         U8 ContextSize;         /*0x01 */
1197         U8 DetailsLength;       /*0x02 */
1198         U8 Flags;               /*0x03 */
1199         U32 Reserved2;          /*0x04 */
1200         U32 ImageOffset;        /*0x08 */
1201         U32 ImageSize;          /*0x0C */
1202 } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1203         Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1204
1205 /*MPI v2.5 FWDownload Request message */
1206 typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1207         U8 ImageType;           /*0x00 */
1208         U8 Reserved1;           /*0x01 */
1209         U8 ChainOffset;         /*0x02 */
1210         U8 Function;            /*0x03 */
1211         U16 Reserved2;          /*0x04 */
1212         U8 Reserved3;           /*0x06 */
1213         U8 MsgFlags;            /*0x07 */
1214         U8 VP_ID;               /*0x08 */
1215         U8 VF_ID;               /*0x09 */
1216         U16 Reserved4;          /*0x0A */
1217         U32 TotalImageSize;     /*0x0C */
1218         U32 Reserved5;          /*0x10 */
1219         U32 Reserved6;          /*0x14 */
1220         U32 ImageOffset;        /*0x18 */
1221         U32 ImageSize;          /*0x1C */
1222         MPI25_SGE_IO_UNION SGL; /*0x20 */
1223 } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1224         Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1225
1226 /*FWDownload Reply message */
1227 typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1228         U8 ImageType;           /*0x00 */
1229         U8 Reserved1;           /*0x01 */
1230         U8 MsgLength;           /*0x02 */
1231         U8 Function;            /*0x03 */
1232         U16 Reserved2;          /*0x04 */
1233         U8 Reserved3;           /*0x06 */
1234         U8 MsgFlags;            /*0x07 */
1235         U8 VP_ID;               /*0x08 */
1236         U8 VF_ID;               /*0x09 */
1237         U16 Reserved4;          /*0x0A */
1238         U16 Reserved5;          /*0x0C */
1239         U16 IOCStatus;          /*0x0E */
1240         U32 IOCLogInfo;         /*0x10 */
1241 } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1242         Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1243
1244 /****************************************************************************
1245 * FWUpload message
1246 ****************************************************************************/
1247
1248 /*MPI v2.0 FWUpload Request message */
1249 typedef struct _MPI2_FW_UPLOAD_REQUEST {
1250         U8 ImageType;           /*0x00 */
1251         U8 Reserved1;           /*0x01 */
1252         U8 ChainOffset;         /*0x02 */
1253         U8 Function;            /*0x03 */
1254         U16 Reserved2;          /*0x04 */
1255         U8 Reserved3;           /*0x06 */
1256         U8 MsgFlags;            /*0x07 */
1257         U8 VP_ID;               /*0x08 */
1258         U8 VF_ID;               /*0x09 */
1259         U16 Reserved4;          /*0x0A */
1260         U32 Reserved5;          /*0x0C */
1261         U32 Reserved6;          /*0x10 */
1262         MPI2_MPI_SGE_UNION SGL; /*0x14 */
1263 } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1264         Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1265
1266 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1267 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1268 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1269 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1270 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1271 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1272 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1273 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1274 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1275 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1276 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP         (0x0D)
1277
1278 /*MPI v2.0 FWUpload TransactionContext Element */
1279 typedef struct _MPI2_FW_UPLOAD_TCSGE {
1280         U8 Reserved1;           /*0x00 */
1281         U8 ContextSize;         /*0x01 */
1282         U8 DetailsLength;       /*0x02 */
1283         U8 Flags;               /*0x03 */
1284         U32 Reserved2;          /*0x04 */
1285         U32 ImageOffset;        /*0x08 */
1286         U32 ImageSize;          /*0x0C */
1287 } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1288         Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1289
1290 /*MPI v2.5 FWUpload Request message */
1291 typedef struct _MPI25_FW_UPLOAD_REQUEST {
1292         U8 ImageType;           /*0x00 */
1293         U8 Reserved1;           /*0x01 */
1294         U8 ChainOffset;         /*0x02 */
1295         U8 Function;            /*0x03 */
1296         U16 Reserved2;          /*0x04 */
1297         U8 Reserved3;           /*0x06 */
1298         U8 MsgFlags;            /*0x07 */
1299         U8 VP_ID;               /*0x08 */
1300         U8 VF_ID;               /*0x09 */
1301         U16 Reserved4;          /*0x0A */
1302         U32 Reserved5;          /*0x0C */
1303         U32 Reserved6;          /*0x10 */
1304         U32 Reserved7;          /*0x14 */
1305         U32 ImageOffset;        /*0x18 */
1306         U32 ImageSize;          /*0x1C */
1307         MPI25_SGE_IO_UNION SGL; /*0x20 */
1308 } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1309         Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1310
1311 /*FWUpload Reply message */
1312 typedef struct _MPI2_FW_UPLOAD_REPLY {
1313         U8 ImageType;           /*0x00 */
1314         U8 Reserved1;           /*0x01 */
1315         U8 MsgLength;           /*0x02 */
1316         U8 Function;            /*0x03 */
1317         U16 Reserved2;          /*0x04 */
1318         U8 Reserved3;           /*0x06 */
1319         U8 MsgFlags;            /*0x07 */
1320         U8 VP_ID;               /*0x08 */
1321         U8 VF_ID;               /*0x09 */
1322         U16 Reserved4;          /*0x0A */
1323         U16 Reserved5;          /*0x0C */
1324         U16 IOCStatus;          /*0x0E */
1325         U32 IOCLogInfo;         /*0x10 */
1326         U32 ActualImageSize;    /*0x14 */
1327 } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1328         Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1329
1330 /*FW Image Header */
1331 typedef struct _MPI2_FW_IMAGE_HEADER {
1332         U32 Signature;          /*0x00 */
1333         U32 Signature0;         /*0x04 */
1334         U32 Signature1;         /*0x08 */
1335         U32 Signature2;         /*0x0C */
1336         MPI2_VERSION_UNION MPIVersion;  /*0x10 */
1337         MPI2_VERSION_UNION FWVersion;   /*0x14 */
1338         MPI2_VERSION_UNION NVDATAVersion;       /*0x18 */
1339         MPI2_VERSION_UNION PackageVersion;      /*0x1C */
1340         U16 VendorID;           /*0x20 */
1341         U16 ProductID;          /*0x22 */
1342         U16 ProtocolFlags;      /*0x24 */
1343         U16 Reserved26;         /*0x26 */
1344         U32 IOCCapabilities;    /*0x28 */
1345         U32 ImageSize;          /*0x2C */
1346         U32 NextImageHeaderOffset;      /*0x30 */
1347         U32 Checksum;           /*0x34 */
1348         U32 Reserved38;         /*0x38 */
1349         U32 Reserved3C;         /*0x3C */
1350         U32 Reserved40;         /*0x40 */
1351         U32 Reserved44;         /*0x44 */
1352         U32 Reserved48;         /*0x48 */
1353         U32 Reserved4C;         /*0x4C */
1354         U32 Reserved50;         /*0x50 */
1355         U32 Reserved54;         /*0x54 */
1356         U32 Reserved58;         /*0x58 */
1357         U32 Reserved5C;         /*0x5C */
1358         U32 BootFlags;          /*0x60 */
1359         U32 FirmwareVersionNameWhat;    /*0x64 */
1360         U8 FirmwareVersionName[32];     /*0x68 */
1361         U32 VendorNameWhat;     /*0x88 */
1362         U8 VendorName[32];      /*0x8C */
1363         U32 PackageNameWhat;    /*0x88 */
1364         U8 PackageName[32];     /*0x8C */
1365         U32 ReservedD0;         /*0xD0 */
1366         U32 ReservedD4;         /*0xD4 */
1367         U32 ReservedD8;         /*0xD8 */
1368         U32 ReservedDC;         /*0xDC */
1369         U32 ReservedE0;         /*0xE0 */
1370         U32 ReservedE4;         /*0xE4 */
1371         U32 ReservedE8;         /*0xE8 */
1372         U32 ReservedEC;         /*0xEC */
1373         U32 ReservedF0;         /*0xF0 */
1374         U32 ReservedF4;         /*0xF4 */
1375         U32 ReservedF8;         /*0xF8 */
1376         U32 ReservedFC;         /*0xFC */
1377 } MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1378         Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1379
1380 /*Signature field */
1381 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1382 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1383 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1384 #define MPI26_FW_HEADER_SIGNATURE               (0xEB000000)
1385
1386 /*Signature0 field */
1387 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1388 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1389 /* Last byte is defined by architecture */
1390 #define MPI26_FW_HEADER_SIGNATURE0_BASE         (0x5AEAA500)
1391 #define MPI26_FW_HEADER_SIGNATURE0_ARC_0        (0x5A)
1392 #define MPI26_FW_HEADER_SIGNATURE0_ARC_1        (0x00)
1393 #define MPI26_FW_HEADER_SIGNATURE0_ARC_2        (0x01)
1394 /* legacy (0x5AEAA55A) */
1395 #define MPI26_FW_HEADER_SIGNATURE0 \
1396         (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
1397 #define MPI26_FW_HEADER_SIGNATURE0_3516 \
1398         (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1399
1400 /*Signature1 field */
1401 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1402 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1403 #define MPI26_FW_HEADER_SIGNATURE1              (0xA55AEAA5)
1404
1405 /*Signature2 field */
1406 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1407 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1408 #define MPI26_FW_HEADER_SIGNATURE2              (0x5AA55AEA)
1409
1410 /*defines for using the ProductID field */
1411 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1412 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1413
1414 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1415 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1416 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1417 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1418
1419 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1420 /*SAS ProductID Family bits */
1421 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1422 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1423 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS     (0x0021)
1424 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS     (0x0028)
1425 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS     (0x0031)
1426
1427 /*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1428
1429 /*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1430
1431 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1432 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1433 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET        (0x60)
1434 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1435
1436 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1437
1438 #define MPI2_FW_HEADER_SIZE                     (0x100)
1439
1440 /*Extended Image Header */
1441 typedef struct _MPI2_EXT_IMAGE_HEADER {
1442         U8 ImageType;           /*0x00 */
1443         U8 Reserved1;           /*0x01 */
1444         U16 Reserved2;          /*0x02 */
1445         U32 Checksum;           /*0x04 */
1446         U32 ImageSize;          /*0x08 */
1447         U32 NextImageHeaderOffset;      /*0x0C */
1448         U32 PackageVersion;     /*0x10 */
1449         U32 Reserved3;          /*0x14 */
1450         U32 Reserved4;          /*0x18 */
1451         U32 Reserved5;          /*0x1C */
1452         U8 IdentifyString[32];  /*0x20 */
1453 } MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1454         Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1455
1456 /*useful offsets */
1457 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1458 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1459 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1460
1461 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1462
1463 /*defines for the ImageType field */
1464 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1465 #define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1466 #define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1467 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1468 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1469 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1470 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1471 #define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1472 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)
1473 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1474 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1475
1476 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1477
1478 /*FLASH Layout Extended Image Data */
1479
1480 /*
1481  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1482  *one and check RegionsPerLayout at runtime.
1483  */
1484 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1485 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1486 #endif
1487
1488 /*
1489  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1490  *one and check NumberOfLayouts at runtime.
1491  */
1492 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1493 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1494 #endif
1495
1496 typedef struct _MPI2_FLASH_REGION {
1497         U8 RegionType;          /*0x00 */
1498         U8 Reserved1;           /*0x01 */
1499         U16 Reserved2;          /*0x02 */
1500         U32 RegionOffset;       /*0x04 */
1501         U32 RegionSize;         /*0x08 */
1502         U32 Reserved3;          /*0x0C */
1503 } MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1504         Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1505
1506 typedef struct _MPI2_FLASH_LAYOUT {
1507         U32 FlashSize;          /*0x00 */
1508         U32 Reserved1;          /*0x04 */
1509         U32 Reserved2;          /*0x08 */
1510         U32 Reserved3;          /*0x0C */
1511         MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1512 } MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1513         Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1514
1515 typedef struct _MPI2_FLASH_LAYOUT_DATA {
1516         U8 ImageRevision;       /*0x00 */
1517         U8 Reserved1;           /*0x01 */
1518         U8 SizeOfRegion;        /*0x02 */
1519         U8 Reserved2;           /*0x03 */
1520         U16 NumberOfLayouts;    /*0x04 */
1521         U16 RegionsPerLayout;   /*0x06 */
1522         U16 MinimumSectorAlignment;     /*0x08 */
1523         U16 Reserved3;          /*0x0A */
1524         U32 Reserved4;          /*0x0C */
1525         MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1526 } MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1527         Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1528
1529 /*defines for the RegionType field */
1530 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1531 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1532 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1533 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1534 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1535 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1536 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1537 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1538 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1539 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK     (0x0A)
1540 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
1541 #define MPI2_FLASH_REGION_CBB_BACKUP            (0x0D)
1542
1543 /*ImageRevision */
1544 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1545
1546 /*Supported Devices Extended Image Data */
1547
1548 /*
1549  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1550  *one and check NumberOfDevices at runtime.
1551  */
1552 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1553 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1554 #endif
1555
1556 typedef struct _MPI2_SUPPORTED_DEVICE {
1557         U16 DeviceID;           /*0x00 */
1558         U16 VendorID;           /*0x02 */
1559         U16 DeviceIDMask;       /*0x04 */
1560         U16 Reserved1;          /*0x06 */
1561         U8 LowPCIRev;           /*0x08 */
1562         U8 HighPCIRev;          /*0x09 */
1563         U16 Reserved2;          /*0x0A */
1564         U32 Reserved3;          /*0x0C */
1565 } MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1566         Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1567
1568 typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1569         U8 ImageRevision;       /*0x00 */
1570         U8 Reserved1;           /*0x01 */
1571         U8 NumberOfDevices;     /*0x02 */
1572         U8 Reserved2;           /*0x03 */
1573         U32 Reserved3;          /*0x04 */
1574         MPI2_SUPPORTED_DEVICE
1575         SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1576 } MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1577         Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1578
1579 /*ImageRevision */
1580 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1581
1582 /*Init Extended Image Data */
1583
1584 typedef struct _MPI2_INIT_IMAGE_FOOTER {
1585         U32 BootFlags;          /*0x00 */
1586         U32 ImageSize;          /*0x04 */
1587         U32 Signature0;         /*0x08 */
1588         U32 Signature1;         /*0x0C */
1589         U32 Signature2;         /*0x10 */
1590         U32 ResetVector;        /*0x14 */
1591 } MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1592         Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1593
1594 /*defines for the BootFlags field */
1595 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1596
1597 /*defines for the ImageSize field */
1598 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1599
1600 /*defines for the Signature0 field */
1601 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1602 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1603
1604 /*defines for the Signature1 field */
1605 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1606 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1607
1608 /*defines for the Signature2 field */
1609 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1610 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1611
1612 /*Signature fields as individual bytes */
1613 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1614 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1615 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1616 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1617
1618 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1619 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1620 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1621 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1622
1623 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1624 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1625 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1626 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1627
1628 /*defines for the ResetVector field */
1629 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1630
1631
1632 /* Encrypted Hash Extended Image Data */
1633
1634 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1635         U8              HashImageType;          /* 0x00 */
1636         U8              HashAlgorithm;          /* 0x01 */
1637         U8              EncryptionAlgorithm;    /* 0x02 */
1638         U8              Reserved1;              /* 0x03 */
1639         U32             Reserved2;              /* 0x04 */
1640         U32             EncryptedHash[1];       /* 0x08 */ /* variable length */
1641 } MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1642 Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1643
1644 /* values for HashImageType */
1645 #define MPI25_HASH_IMAGE_TYPE_UNUSED            (0x00)
1646 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE          (0x01)
1647 #define MPI25_HASH_IMAGE_TYPE_BIOS              (0x02)
1648
1649 /* values for HashAlgorithm */
1650 #define MPI25_HASH_ALGORITHM_UNUSED             (0x00)
1651 #define MPI25_HASH_ALGORITHM_SHA256             (0x01)
1652
1653 /* values for EncryptionAlgorithm */
1654 #define MPI25_ENCRYPTION_ALG_UNUSED             (0x00)
1655 #define MPI25_ENCRYPTION_ALG_RSA256             (0x01)
1656
1657 typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1658         U8                              ImageVersion;           /* 0x00 */
1659         U8                              NumHash;                /* 0x01 */
1660         U16                             Reserved1;              /* 0x02 */
1661         U32                             Reserved2;              /* 0x04 */
1662         MPI25_ENCRYPTED_HASH_ENTRY      EncryptedHashEntry[1];  /* 0x08 */
1663 } MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1664 Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1665
1666
1667 /****************************************************************************
1668 * PowerManagementControl message
1669 ****************************************************************************/
1670
1671 /*PowerManagementControl Request message */
1672 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1673         U8 Feature;             /*0x00 */
1674         U8 Reserved1;           /*0x01 */
1675         U8 ChainOffset;         /*0x02 */
1676         U8 Function;            /*0x03 */
1677         U16 Reserved2;          /*0x04 */
1678         U8 Reserved3;           /*0x06 */
1679         U8 MsgFlags;            /*0x07 */
1680         U8 VP_ID;               /*0x08 */
1681         U8 VF_ID;               /*0x09 */
1682         U16 Reserved4;          /*0x0A */
1683         U8 Parameter1;          /*0x0C */
1684         U8 Parameter2;          /*0x0D */
1685         U8 Parameter3;          /*0x0E */
1686         U8 Parameter4;          /*0x0F */
1687         U32 Reserved5;          /*0x10 */
1688         U32 Reserved6;          /*0x14 */
1689 } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1690         Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1691
1692 /*defines for the Feature field */
1693 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1694 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1695 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)  /*obsolete */
1696 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1697 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05)
1698 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1699 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1700
1701 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1702 /*Parameter1 contains a PHY number */
1703 /*Parameter2 indicates power condition action using these defines */
1704 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1705 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1706 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1707 /*Parameter3 and Parameter4 are reserved */
1708
1709 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1710  * Feature */
1711 /*Parameter1 contains SAS port width modulation group number */
1712 /*Parameter2 indicates IOC action using these defines */
1713 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1714 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1715 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1716 /*Parameter3 indicates desired modulation level using these defines */
1717 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1718 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1719 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1720 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1721 /*Parameter4 is reserved */
1722
1723 /*this next set (_PCIE_LINK) is obsolete */
1724 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1725 /*Parameter1 indicates desired PCIe link speed using these defines */
1726 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)  /*obsolete */
1727 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)  /*obsolete */
1728 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)  /*obsolete */
1729 /*Parameter2 indicates desired PCIe link width using these defines */
1730 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)  /*obsolete */
1731 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)  /*obsolete */
1732 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)  /*obsolete */
1733 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)  /*obsolete */
1734 /*Parameter3 and Parameter4 are reserved */
1735
1736 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1737 /*Parameter1 indicates desired IOC hardware clock speed using these defines */
1738 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1739 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1740 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1741 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1742 /*Parameter2, Parameter3, and Parameter4 are reserved */
1743
1744 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1745 /*Parameter1 indicates host action regarding global power management mode */
1746 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
1747 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
1748 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
1749 /*Parameter2 indicates the requested global power management mode */
1750 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
1751 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
1752 #define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
1753 /*Parameter3 and Parameter4 are reserved */
1754
1755 /*PowerManagementControl Reply message */
1756 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1757         U8 Feature;             /*0x00 */
1758         U8 Reserved1;           /*0x01 */
1759         U8 MsgLength;           /*0x02 */
1760         U8 Function;            /*0x03 */
1761         U16 Reserved2;          /*0x04 */
1762         U8 Reserved3;           /*0x06 */
1763         U8 MsgFlags;            /*0x07 */
1764         U8 VP_ID;               /*0x08 */
1765         U8 VF_ID;               /*0x09 */
1766         U16 Reserved4;          /*0x0A */
1767         U16 Reserved5;          /*0x0C */
1768         U16 IOCStatus;          /*0x0E */
1769         U32 IOCLogInfo;         /*0x10 */
1770 } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1771         Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1772
1773 /****************************************************************************
1774 *  IO Unit Control messages (MPI v2.6 and later only.)
1775 ****************************************************************************/
1776
1777 /* IO Unit Control Request Message */
1778 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
1779         U8                      Operation;          /* 0x00 */
1780         U8                      Reserved1;          /* 0x01 */
1781         U8                      ChainOffset;        /* 0x02 */
1782         U8                      Function;           /* 0x03 */
1783         U16                     DevHandle;          /* 0x04 */
1784         U8                      IOCParameter;       /* 0x06 */
1785         U8                      MsgFlags;           /* 0x07 */
1786         U8                      VP_ID;              /* 0x08 */
1787         U8                      VF_ID;              /* 0x09 */
1788         U16                     Reserved3;          /* 0x0A */
1789         U16                     Reserved4;          /* 0x0C */
1790         U8                      PhyNum;             /* 0x0E */
1791         U8                      PrimFlags;          /* 0x0F */
1792         U32                     Primitive;          /* 0x10 */
1793         U8                      LookupMethod;       /* 0x14 */
1794         U8                      Reserved5;          /* 0x15 */
1795         U16                     SlotNumber;         /* 0x16 */
1796         U64                     LookupAddress;      /* 0x18 */
1797         U32                     IOCParameterValue;  /* 0x20 */
1798         U32                     Reserved7;          /* 0x24 */
1799         U32                     Reserved8;          /* 0x28 */
1800 } MPI26_IOUNIT_CONTROL_REQUEST,
1801         *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1802         Mpi26IoUnitControlRequest_t,
1803         *pMpi26IoUnitControlRequest_t;
1804
1805 /* values for the Operation field */
1806 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT              (0x02)
1807 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET                (0x06)
1808 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET                (0x07)
1809 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG               (0x08)
1810 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG              (0x09)
1811 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE                (0x0A)
1812 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY              (0x0B)
1813 #define MPI26_CTRL_OP_REMOVE_DEVICE                     (0x0D)
1814 #define MPI26_CTRL_OP_LOOKUP_MAPPING                    (0x0E)
1815 #define MPI26_CTRL_OP_SET_IOC_PARAMETER                 (0x0F)
1816 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE                  (0x10)
1817 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE                 (0x11)
1818 #define MPI26_CTRL_OP_ENABLE_FP_ALL                     (0x12)
1819 #define MPI26_CTRL_OP_DISABLE_FP_ALL                    (0x13)
1820 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ                    (0x14)
1821 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ                   (0x15)
1822 #define MPI26_CTRL_OP_SHUTDOWN                          (0x16)
1823 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION     (0x17)
1824 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION    (0x18)
1825 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION      (0x19)
1826 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN              (0x80)
1827
1828 /* values for the PrimFlags field */
1829 #define MPI26_CTRL_PRIMFLAGS_SINGLE                     (0x08)
1830 #define MPI26_CTRL_PRIMFLAGS_TRIPLE                     (0x02)
1831 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT                  (0x01)
1832
1833 /* values for the LookupMethod field */
1834 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS           (0x01)
1835 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT         (0x02)
1836 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME        (0x03)
1837
1838
1839 /* IO Unit Control Reply Message */
1840 typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
1841         U8                      Operation;          /* 0x00 */
1842         U8                      Reserved1;          /* 0x01 */
1843         U8                      MsgLength;          /* 0x02 */
1844         U8                      Function;           /* 0x03 */
1845         U16                     DevHandle;          /* 0x04 */
1846         U8                      IOCParameter;       /* 0x06 */
1847         U8                      MsgFlags;           /* 0x07 */
1848         U8                      VP_ID;              /* 0x08 */
1849         U8                      VF_ID;              /* 0x09 */
1850         U16                     Reserved3;          /* 0x0A */
1851         U16                     Reserved4;          /* 0x0C */
1852         U16                     IOCStatus;          /* 0x0E */
1853         U32                     IOCLogInfo;         /* 0x10 */
1854 } MPI26_IOUNIT_CONTROL_REPLY,
1855         *PTR_MPI26_IOUNIT_CONTROL_REPLY,
1856         Mpi26IoUnitControlReply_t,
1857         *pMpi26IoUnitControlReply_t;
1858
1859
1860 #endif