2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2009-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 * FILE: megaraid_sas_fusion.h
22 * Authors: Avago Technologies
25 * Kashyap Desai <kashyap.desai@avagotech.com>
26 * Sumit Saxena <sumit.saxena@avagotech.com>
28 * Send feedback to: megaraidlinux.pdl@avagotech.com
30 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
31 * San Jose, California 95131
34 #ifndef _MEGARAID_SAS_FUSION_H_
35 #define _MEGARAID_SAS_FUSION_H_
38 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
40 #define MEGASAS_MAX_CHAIN_SHIFT 5
41 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
42 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
43 #define MEGASAS_256K_IO 128
44 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
45 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
46 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
47 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
48 #define MEGASAS_LOAD_BALANCE_FLAG 0x1
49 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
50 #define HOST_DIAG_WRITE_ENABLE 0x80
51 #define HOST_DIAG_RESET_ADAPTER 0x4
52 #define MEGASAS_FUSION_MAX_RESET_TRIES 3
53 #define MAX_MSIX_QUEUES_FUSION 128
56 #define MPI2_TYPE_CUDA 0x2
57 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
58 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
59 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
60 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
61 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
62 #define MR_RL_WRITE_THROUGH_MODE 0x00
63 #define MR_RL_WRITE_BACK_MODE 0x01
66 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
67 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
68 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
69 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
70 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
71 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
72 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
74 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
75 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
81 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
82 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
83 enum MR_RAID_FLAGS_IO_SUB_TYPE {
84 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
85 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
86 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
87 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
88 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
89 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
90 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
94 * Request descriptor types
96 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
97 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
98 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
99 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
101 #define MEGASAS_FP_CMD_LEN 16
102 #define MEGASAS_FUSION_IN_RESET 0
103 #define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1
104 #define THRESHOLD_REPLY_COUNT 50
105 #define RAID_1_PEER_CMDS 2
106 #define JBOD_MAPS_COUNT 2
109 * Raid Context structure which describes MegaRAID specific IO Parameters
110 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
113 struct RAID_CONTEXT {
114 #if defined(__BIG_ENDIAN_BITFIELD)
122 __le16 timeout_value;
125 __le16 virtual_disk_tgt_id;
126 __le64 reg_lock_row_lba;
127 __le32 reg_lock_length;
133 __le16 config_seq_num;
141 * Raid Context structure which describes ventura MegaRAID specific
142 * IO Paramenters ,This resides at offset 0x60 where the SGL normally
143 * starts in MPT IO Frames
145 struct RAID_CONTEXT_G35 {
146 #define RAID_CONTEXT_NSEG_MASK 0x00F0
147 #define RAID_CONTEXT_NSEG_SHIFT 4
148 #define RAID_CONTEXT_TYPE_MASK 0x000F
149 #define RAID_CONTEXT_TYPE_SHIFT 0
151 u16 timeout_value; /* 0x02 -0x03 */
152 u16 routing_flags; // 0x04 -0x05 routing flags
153 u16 virtual_disk_tgt_id; /* 0x06 -0x07 */
154 u64 reg_lock_row_lba; /* 0x08 - 0x0F */
155 u32 reg_lock_length; /* 0x10 - 0x13 */
157 u16 next_lmid; /* 0x14 - 0x15 */
158 u16 peer_smid; /* used for the raid 1/10 fp writes */
160 u8 ex_status; /* 0x16 : OUT */
161 u8 status; /* 0x17 status */
162 u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4],
163 * resvd[3:1], preferredCpu[0]
165 u8 span_arm; /* 0x1C span[7:5], arm[4:0] */
166 u16 config_seq_num; /* 0x1A -0x1B */
170 * ---------------------------------
171 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
172 * ---------------------------------
173 * Byte0 | numSGE[7]- numSGE[0] |
174 * ---------------------------------
175 * Byte1 |SD | resvd | numSGE 8-11 |
176 * --------------------------------
178 #define NUM_SGE_MASK_LOWER 0xFF
179 #define NUM_SGE_MASK_UPPER 0x0F
180 #define NUM_SGE_SHIFT_UPPER 8
181 #define STREAM_DETECT_SHIFT 7
182 #define STREAM_DETECT_MASK 0x80
184 #if defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
185 u16 stream_detected:1;
191 u16 stream_detected:1;
196 u8 resvd2[2]; /* 0x1E-0x1F */
199 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1
200 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2
201 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3
202 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4
203 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5
204 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6
205 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7
206 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8
207 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00
208 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12
209 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
211 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
214 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
215 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
216 & NUM_SGE_MASK_UPPER);
219 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
223 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
224 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
228 #define SET_STREAM_DETECTED(rctx_g35) \
229 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
231 #define CLEAR_STREAM_DETECTED(rctx_g35) \
232 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
234 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
236 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
239 union RAID_CONTEXT_UNION {
240 struct RAID_CONTEXT raid_context;
241 struct RAID_CONTEXT_G35 raid_context_g35;
244 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
245 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
247 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
248 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
250 /* number of bits per index in U32 TrackStream */
251 #define BITS_PER_INDEX_STREAM 4
252 #define INVALID_STREAM_NUM 16
253 #define MR_STREAM_BITMAP 0x76543210
254 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
255 #define ZERO_LAST_STREAM 0x0fffffff
256 #define MAX_STREAMS_TRACKED 8
259 * define region lock types
262 REGION_TYPE_UNUSED = 0,
263 REGION_TYPE_SHARED_READ = 1,
264 REGION_TYPE_SHARED_WRITE = 2,
265 REGION_TYPE_EXCLUSIVE = 3,
269 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
270 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
271 #define MPI2_VERSION_MAJOR (0x02)
272 #define MPI2_VERSION_MINOR (0x00)
273 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
274 #define MPI2_VERSION_MAJOR_SHIFT (8)
275 #define MPI2_VERSION_MINOR_MASK (0x00FF)
276 #define MPI2_VERSION_MINOR_SHIFT (0)
277 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
279 #define MPI2_HEADER_VERSION_UNIT (0x10)
280 #define MPI2_HEADER_VERSION_DEV (0x00)
281 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
282 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
283 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
284 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
285 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
286 MPI2_HEADER_VERSION_DEV)
287 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
288 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
289 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
290 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
291 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
293 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
294 /* EEDP escape mode */
295 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
296 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
297 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
298 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
299 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
300 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
301 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
302 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
303 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
304 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
305 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
306 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
307 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
308 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
309 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
310 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
311 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
312 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
313 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
314 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
315 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
317 struct MPI25_IEEE_SGE_CHAIN64 {
325 struct MPI2_SGE_SIMPLE_UNION {
333 struct MPI2_SCSI_IO_CDB_EEDP32 {
334 u8 CDB[20]; /* 0x00 */
335 __be32 PrimaryReferenceTag; /* 0x14 */
336 __be16 PrimaryApplicationTag; /* 0x18 */
337 __be16 PrimaryApplicationTagMask; /* 0x1A */
338 __le32 TransferLength; /* 0x1C */
341 struct MPI2_SGE_CHAIN_UNION {
351 struct MPI2_IEEE_SGE_SIMPLE32 {
356 struct MPI2_IEEE_SGE_CHAIN32 {
361 struct MPI2_IEEE_SGE_SIMPLE64 {
369 struct MPI2_IEEE_SGE_CHAIN64 {
377 union MPI2_IEEE_SGE_SIMPLE_UNION {
378 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
379 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
382 union MPI2_IEEE_SGE_CHAIN_UNION {
383 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
384 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
387 union MPI2_SGE_IO_UNION {
388 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
389 struct MPI2_SGE_CHAIN_UNION MpiChain;
390 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
391 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
394 union MPI2_SCSI_IO_CDB_UNION {
396 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
397 struct MPI2_SGE_SIMPLE_UNION SGE;
400 /****************************************************************************
401 * SCSI Task Management messages
402 ****************************************************************************/
404 /*SCSI Task Management Request Message */
405 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
406 u16 DevHandle; /*0x00 */
407 u8 ChainOffset; /*0x02 */
408 u8 Function; /*0x03 */
409 u8 Reserved1; /*0x04 */
410 u8 TaskType; /*0x05 */
411 u8 Reserved2; /*0x06 */
412 u8 MsgFlags; /*0x07 */
415 u16 Reserved3; /*0x0A */
417 u32 Reserved4[7]; /*0x14 */
418 u16 TaskMID; /*0x30 */
419 u16 Reserved5; /*0x32 */
423 /*SCSI Task Management Reply Message */
424 struct MPI2_SCSI_TASK_MANAGE_REPLY {
425 u16 DevHandle; /*0x00 */
426 u8 MsgLength; /*0x02 */
427 u8 Function; /*0x03 */
428 u8 ResponseCode; /*0x04 */
429 u8 TaskType; /*0x05 */
430 u8 Reserved1; /*0x06 */
431 u8 MsgFlags; /*0x07 */
434 u16 Reserved2; /*0x0A */
435 u16 Reserved3; /*0x0C */
436 u16 IOCStatus; /*0x0E */
437 u32 IOCLogInfo; /*0x10 */
438 u32 TerminationCount; /*0x14 */
439 u32 ResponseInfo; /*0x18 */
442 struct MR_TM_REQUEST {
450 /* SCSI Task Management Request Message */
451 struct MR_TASK_MANAGE_REQUEST {
452 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
453 struct MR_TM_REQUEST TmRequest;
456 #if defined(__BIG_ENDIAN_BITFIELD)
467 struct MR_TM_REPLY TMReply;
471 /* TaskType values */
473 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
474 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
475 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
476 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
477 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
478 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
479 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
480 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
481 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
483 /* ResponseCode values */
485 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
486 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
487 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
488 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
489 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
490 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
491 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
492 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
495 * RAID SCSI IO Request Message
496 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
498 struct MPI2_RAID_SCSI_IO_REQUEST {
499 __le16 DevHandle; /* 0x00 */
500 u8 ChainOffset; /* 0x02 */
501 u8 Function; /* 0x03 */
502 __le16 Reserved1; /* 0x04 */
503 u8 Reserved2; /* 0x06 */
504 u8 MsgFlags; /* 0x07 */
507 __le16 Reserved3; /* 0x0A */
508 __le32 SenseBufferLowAddress; /* 0x0C */
509 __le16 SGLFlags; /* 0x10 */
510 u8 SenseBufferLength; /* 0x12 */
511 u8 Reserved4; /* 0x13 */
512 u8 SGLOffset0; /* 0x14 */
513 u8 SGLOffset1; /* 0x15 */
514 u8 SGLOffset2; /* 0x16 */
515 u8 SGLOffset3; /* 0x17 */
516 __le32 SkipCount; /* 0x18 */
517 __le32 DataLength; /* 0x1C */
518 __le32 BidirectionalDataLength; /* 0x20 */
519 __le16 IoFlags; /* 0x24 */
520 __le16 EEDPFlags; /* 0x26 */
521 __le32 EEDPBlockSize; /* 0x28 */
522 __le32 SecondaryReferenceTag; /* 0x2C */
523 __le16 SecondaryApplicationTag; /* 0x30 */
524 __le16 ApplicationTagTranslationMask; /* 0x32 */
525 u8 LUN[8]; /* 0x34 */
526 __le32 Control; /* 0x3C */
527 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
528 union RAID_CONTEXT_UNION RaidContext; /* 0x60 */
529 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
533 * MPT RAID MFA IO Descriptor.
535 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
537 u32 MessageAddress1:24;
541 /* Default Request Descriptor */
542 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
543 u8 RequestFlags; /* 0x00 */
544 u8 MSIxIndex; /* 0x01 */
545 __le16 SMID; /* 0x02 */
546 __le16 LMID; /* 0x04 */
547 __le16 DescriptorTypeDependent; /* 0x06 */
550 /* High Priority Request Descriptor */
551 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
552 u8 RequestFlags; /* 0x00 */
553 u8 MSIxIndex; /* 0x01 */
554 __le16 SMID; /* 0x02 */
555 __le16 LMID; /* 0x04 */
556 __le16 Reserved1; /* 0x06 */
559 /* SCSI IO Request Descriptor */
560 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
561 u8 RequestFlags; /* 0x00 */
562 u8 MSIxIndex; /* 0x01 */
563 __le16 SMID; /* 0x02 */
564 __le16 LMID; /* 0x04 */
565 __le16 DevHandle; /* 0x06 */
568 /* SCSI Target Request Descriptor */
569 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
570 u8 RequestFlags; /* 0x00 */
571 u8 MSIxIndex; /* 0x01 */
572 __le16 SMID; /* 0x02 */
573 __le16 LMID; /* 0x04 */
574 __le16 IoIndex; /* 0x06 */
577 /* RAID Accelerator Request Descriptor */
578 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
579 u8 RequestFlags; /* 0x00 */
580 u8 MSIxIndex; /* 0x01 */
581 __le16 SMID; /* 0x02 */
582 __le16 LMID; /* 0x04 */
583 __le16 Reserved; /* 0x06 */
586 /* union of Request Descriptors */
587 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
588 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
589 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
590 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
591 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
592 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
593 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
603 /* Default Reply Descriptor */
604 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
605 u8 ReplyFlags; /* 0x00 */
606 u8 MSIxIndex; /* 0x01 */
607 __le16 DescriptorTypeDependent1; /* 0x02 */
608 __le32 DescriptorTypeDependent2; /* 0x04 */
611 /* Address Reply Descriptor */
612 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
613 u8 ReplyFlags; /* 0x00 */
614 u8 MSIxIndex; /* 0x01 */
615 __le16 SMID; /* 0x02 */
616 __le32 ReplyFrameAddress; /* 0x04 */
619 /* SCSI IO Success Reply Descriptor */
620 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
621 u8 ReplyFlags; /* 0x00 */
622 u8 MSIxIndex; /* 0x01 */
623 __le16 SMID; /* 0x02 */
624 __le16 TaskTag; /* 0x04 */
625 __le16 Reserved1; /* 0x06 */
628 /* TargetAssist Success Reply Descriptor */
629 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
630 u8 ReplyFlags; /* 0x00 */
631 u8 MSIxIndex; /* 0x01 */
632 __le16 SMID; /* 0x02 */
633 u8 SequenceNumber; /* 0x04 */
634 u8 Reserved1; /* 0x05 */
635 __le16 IoIndex; /* 0x06 */
638 /* Target Command Buffer Reply Descriptor */
639 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
640 u8 ReplyFlags; /* 0x00 */
641 u8 MSIxIndex; /* 0x01 */
644 __le16 InitiatorDevHandle; /* 0x04 */
645 __le16 IoIndex; /* 0x06 */
648 /* RAID Accelerator Success Reply Descriptor */
649 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
650 u8 ReplyFlags; /* 0x00 */
651 u8 MSIxIndex; /* 0x01 */
652 __le16 SMID; /* 0x02 */
653 __le32 Reserved; /* 0x04 */
656 /* union of Reply Descriptors */
657 union MPI2_REPLY_DESCRIPTORS_UNION {
658 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
659 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
660 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
661 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
662 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
663 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
664 RAIDAcceleratorSuccess;
668 /* IOCInit Request message */
669 struct MPI2_IOC_INIT_REQUEST {
670 u8 WhoInit; /* 0x00 */
671 u8 Reserved1; /* 0x01 */
672 u8 ChainOffset; /* 0x02 */
673 u8 Function; /* 0x03 */
674 __le16 Reserved2; /* 0x04 */
675 u8 Reserved3; /* 0x06 */
676 u8 MsgFlags; /* 0x07 */
679 __le16 Reserved4; /* 0x0A */
680 __le16 MsgVersion; /* 0x0C */
681 __le16 HeaderVersion; /* 0x0E */
682 u32 Reserved5; /* 0x10 */
683 __le16 Reserved6; /* 0x14 */
684 u8 HostPageSize; /* 0x16 */
685 u8 HostMSIxVectors; /* 0x17 */
686 __le16 Reserved8; /* 0x18 */
687 __le16 SystemRequestFrameSize; /* 0x1A */
688 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */
689 __le16 ReplyFreeQueueDepth; /* 0x1E */
690 __le32 SenseBufferAddressHigh; /* 0x20 */
691 __le32 SystemReplyAddressHigh; /* 0x24 */
692 __le64 SystemRequestFrameBaseAddress; /* 0x28 */
693 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */
694 __le64 ReplyFreeQueueAddress; /* 0x38 */
695 __le64 TimeStamp; /* 0x40 */
699 #define MR_PD_INVALID 0xFFFF
700 #define MR_DEVHANDLE_INVALID 0xFFFF
701 #define MAX_SPAN_DEPTH 8
702 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
703 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
704 #define MAX_ROW_SIZE 32
705 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
706 #define MAX_LOGICAL_DRIVES 64
707 #define MAX_LOGICAL_DRIVES_EXT 256
708 #define MAX_LOGICAL_DRIVES_DYN 512
709 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
710 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
711 #define MAX_ARRAYS 128
712 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
713 #define MAX_ARRAYS_EXT 256
714 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
715 #define MAX_API_ARRAYS_DYN 512
716 #define MAX_PHYSICAL_DEVICES 256
717 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
718 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
719 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
720 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
721 #define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103
722 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
723 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
724 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
726 struct MR_DEV_HANDLE_INFO {
733 struct MR_ARRAY_INFO {
734 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
737 struct MR_QUAD_ELEMENT {
745 struct MR_SPAN_INFO {
748 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
760 struct MR_SPAN_BLOCK_INFO {
762 struct MR_LD_SPAN span;
763 struct MR_SPAN_INFO block_span_info;
766 #define MR_RAID_CTX_CPUSEL_0 0
767 #define MR_RAID_CTX_CPUSEL_1 1
768 #define MR_RAID_CTX_CPUSEL_2 2
769 #define MR_RAID_CTX_CPUSEL_3 3
770 #define MR_RAID_CTX_CPUSEL_FCFS 0xF
772 struct MR_CPU_AFFINITY_MASK {
775 #ifndef MFI_BIG_ENDIAN
795 struct MR_IO_AFFINITY {
798 struct MR_CPU_AFFINITY_MASK pdRead;
799 struct MR_CPU_AFFINITY_MASK pdWrite;
800 struct MR_CPU_AFFINITY_MASK ldRead;
801 struct MR_CPU_AFFINITY_MASK ldWrite;
805 u8 maxCores; /* Total cores + HW Path in ROC */
811 #if defined(__BIG_ENDIAN_BITFIELD)
813 u32 fp_cache_bypass_capable:1;
814 u32 fp_rmw_capable:1;
815 u32 disable_coalescing:1;
816 u32 fpBypassRegionLock:1;
818 u32 fpNonRWCapable:1;
819 u32 fpReadAcrossStripe:1;
820 u32 fpWriteAcrossStripe:1;
822 u32 fpWriteCapable:1;
823 u32 encryptionType:8;
835 u32 encryptionType:8;
836 u32 fpWriteCapable:1;
838 u32 fpWriteAcrossStripe:1;
839 u32 fpReadAcrossStripe:1;
840 u32 fpNonRWCapable:1;
842 u32 fpBypassRegionLock:1;
843 u32 disable_coalescing:1;
844 u32 fp_rmw_capable:1;
845 u32 fp_cache_bypass_capable:1;
861 u8 regTypeReqOnWrite;
867 u32 ldSyncRequired:1;
871 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
872 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
873 /* Ox2D This LD accept priority boost of this type */
874 u8 ld_accept_priority_type;
875 u8 reserved2[2]; /* 0x2E - 0x2F */
876 /* 0x30 - 0x33, Logical block size for the LD */
877 u32 logical_block_length;
879 #ifndef MFI_BIG_ENDIAN
880 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
882 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
883 * BLOCK EXPONENT from READ CAPACITY 16
885 u32 ld_logical_block_exp:4;
886 u32 reserved1:24; /* 0x34 */
888 u32 reserved1:24; /* 0x34 */
889 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
890 * BLOCK EXPONENT from READ CAPACITY 16
892 u32 ld_logical_block_exp:4;
893 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
897 /* 0x38 - 0x3f, This will determine which
898 * core will process LD IO and PD IO.
900 struct MR_IO_AFFINITY cpuAffinity;
901 /* Bit definiations are specified by MR_IO_AFFINITY */
902 u8 reserved3[0x80 - 0x40]; /* 0x40 - 0x7f */
905 struct MR_LD_SPAN_MAP {
906 struct MR_LD_RAID ldRaid;
907 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
908 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
911 struct MR_FW_RAID_MAP {
926 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
930 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
931 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
932 struct MR_LD_SPAN_MAP ldSpanMap[1];
935 struct IO_REQUEST_INFO {
948 u8 span_arm; /* span[7:5], arm[4:0] */
950 u16 r1_alt_dev_handle; /* raid 1/10 only */
954 struct MR_LD_TARGET_SYNC {
961 * RAID Map descriptor Types.
962 * Each element should uniquely idetify one data structure in the RAID map
964 enum MR_RAID_MAP_DESC_TYPE {
965 /* MR_DEV_HANDLE_INFO data */
966 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0,
967 /* target to Ld num Index map */
968 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1,
969 /* MR_ARRAY_INFO data */
970 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2,
971 /* MR_LD_SPAN_MAP data */
972 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3,
973 RAID_MAP_DESC_TYPE_COUNT,
977 * This table defines the offset, size and num elements of each descriptor
978 * type in the RAID Map buffer
980 struct MR_RAID_MAP_DESC_TABLE {
981 /* Raid map descriptor type */
982 u32 raid_map_desc_type;
983 /* Offset into the RAID map buffer where
984 * descriptor data is saved
986 u32 raid_map_desc_offset;
990 u32 raid_map_desc_buffer_size;
991 /* Number of elements contained in the
994 u32 raid_map_desc_elements;
998 * Dynamic Raid Map Structure.
1000 struct MR_FW_RAID_MAP_DYNAMIC {
1001 u32 raid_map_size; /* total size of RAID Map structure */
1002 u32 desc_table_offset;/* Offset of desc table into RAID map*/
1003 u32 desc_table_size; /* Total Size of desc table */
1004 /* Total Number of elements in the desc table */
1005 u32 desc_table_num_elements;
1007 u32 reserved2[3]; /*future use */
1008 /* timeout value used by driver in FP IOs */
1009 u8 fp_pd_io_timeout_sec;
1011 /* when this seqNum increments, driver needs to
1012 * release RMW buffers asap
1015 u16 ld_count; /* count of lds. */
1016 u16 ar_count; /* count of arrays */
1017 u16 span_count; /* count of spans */
1020 * The below structure of pointers is only to be used by the driver.
1021 * This is added in the ,API to reduce the amount of code changes
1022 * needed in the driver to support dynamic RAID map Firmware should
1023 * not update these pointers while preparing the raid map
1027 struct MR_DEV_HANDLE_INFO *dev_hndl_info;
1028 u16 *ld_tgt_id_to_ld;
1029 struct MR_ARRAY_INFO *ar_map_info;
1030 struct MR_LD_SPAN_MAP *ld_span_map;
1032 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1035 * RAID Map descriptor table defines the layout of data in the RAID Map.
1036 * The size of the descriptor table itself could change.
1038 /* Variable Size descriptor Table. */
1039 struct MR_RAID_MAP_DESC_TABLE
1040 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1041 /* Variable Size buffer containing all data */
1042 u32 raid_map_desc_data[1];
1043 }; /* Dynamicaly sized RAID MAp structure */
1045 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1046 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1047 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1048 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1049 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1050 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1051 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1053 #define MPI2_SGE_FLAGS_SHIFT (0x02)
1054 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1055 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1056 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1058 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1059 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1060 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1061 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1063 struct megasas_register_set;
1064 struct megasas_instance;
1074 struct megasas_cmd_fusion {
1075 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
1076 dma_addr_t io_request_phys_addr;
1078 union MPI2_SGE_IO_UNION *sg_frame;
1079 dma_addr_t sg_frame_phys_addr;
1082 dma_addr_t sense_phys_addr;
1084 struct list_head list;
1085 struct scsi_cmnd *scmd;
1086 struct megasas_instance *instance;
1088 u8 retry_for_fw_reset;
1089 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1092 * Context for a MFI frame.
1093 * Used to get the mfi cmd from list when a MFI cmd is completed
1098 struct completion done;
1100 u16 r1_alt_dev_handle; /* raid 1/10 only*/
1101 bool cmd_completed; /* raid 1/10 fp writes status holder */
1105 struct LD_LOAD_BALANCE_INFO {
1108 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1109 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
1112 /* SPAN_SET is info caclulated from span info from Raid map per LD */
1113 typedef struct _LD_SPAN_SET {
1118 u64 data_strip_start;
1122 u8 strip_offset[MAX_SPAN_DEPTH];
1123 u32 span_row_data_width;
1126 } LD_SPAN_SET, *PLD_SPAN_SET;
1128 typedef struct LOG_BLOCK_SPAN_INFO {
1129 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1130 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1132 struct MR_FW_RAID_MAP_ALL {
1133 struct MR_FW_RAID_MAP raidMap;
1134 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1135 } __attribute__ ((packed));
1137 struct MR_DRV_RAID_MAP {
1138 /* total size of this structure, including this field.
1139 * This feild will be manupulated by driver for ext raid map,
1140 * else pick the value from firmware raid map.
1147 __le32 maxSpanDepth;
1155 /* timeout value used by driver in FP IOs*/
1156 u8 fpPdIoTimeoutSec;
1164 struct MR_DEV_HANDLE_INFO
1165 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1166 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1167 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1168 struct MR_LD_SPAN_MAP ldSpanMap[1];
1172 /* Driver raid map size is same as raid map ext
1173 * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1174 * And it is mainly for code re-use purpose.
1176 struct MR_DRV_RAID_MAP_ALL {
1178 struct MR_DRV_RAID_MAP raidMap;
1179 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1184 struct MR_FW_RAID_MAP_EXT {
1185 /* Not usred in new map */
1199 u8 fpPdIoTimeoutSec;
1207 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1208 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1209 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
1210 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1214 * * define MR_PD_CFG_SEQ structure for system PDs
1216 struct MR_PD_CFG_SEQ {
1220 #if defined(__BIG_ENDIAN_BITFIELD)
1232 struct MR_PD_CFG_SEQ_NUM_SYNC {
1235 struct MR_PD_CFG_SEQ seq[1];
1238 /* stream detection */
1239 struct STREAM_DETECT {
1240 u64 next_seq_lba; /* next LBA to match sequential access */
1241 struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1242 struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1243 u32 count_cmds_in_stream; /* count of host commands in this stream */
1244 u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1245 u8 is_read; /* SCSI OpCode for this stream */
1246 u8 group_depth; /* total number of host commands in group */
1247 /* TRUE if cannot add any more commands to this group */
1249 u8 reserved[7]; /* pad to 64-bit alignment */
1252 struct LD_STREAM_DETECT {
1253 bool write_back; /* TRUE if WB, FALSE if WT */
1254 bool fp_write_enabled;
1256 bool fp_cache_bypass_capable;
1257 u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1258 /* this is the array of stream detect structures (one per stream) */
1259 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1262 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1263 u64 RDPQBaseAddress;
1268 struct fusion_context {
1269 struct megasas_cmd_fusion **cmd_list;
1270 dma_addr_t req_frames_desc_phys;
1271 u8 *req_frames_desc;
1273 struct dma_pool *io_request_frames_pool;
1274 dma_addr_t io_request_frames_phys;
1275 u8 *io_request_frames;
1277 struct dma_pool *sg_dma_pool;
1278 struct dma_pool *sense_dma_pool;
1280 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1281 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1282 struct dma_pool *reply_frames_desc_pool;
1284 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1287 u32 request_alloc_sz;
1289 u32 io_frames_alloc_sz;
1291 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1292 dma_addr_t rdpq_phys;
1293 u16 max_sge_in_main_msg;
1294 u16 max_sge_in_chain;
1296 u8 chain_offset_io_request;
1297 u8 chain_offset_mfi_pthru;
1299 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1300 dma_addr_t ld_map_phys[2];
1302 /*Non dma-able memory. Driver local copy.*/
1303 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1311 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
1312 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1314 struct LD_LOAD_BALANCE_INFO *load_balance_info;
1315 u32 load_balance_info_pages;
1316 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
1317 struct LD_STREAM_DETECT **stream_detect_by_ld;
1328 void megasas_free_cmds_fusion(struct megasas_instance *instance);
1329 int megasas_ioc_init_fusion(struct megasas_instance *instance);
1330 u8 megasas_get_map_info(struct megasas_instance *instance);
1331 int megasas_sync_map_info(struct megasas_instance *instance);
1332 void megasas_release_fusion(struct megasas_instance *instance);
1333 void megasas_reset_reply_desc(struct megasas_instance *instance);
1334 int megasas_check_mpio_paths(struct megasas_instance *instance,
1335 struct scsi_cmnd *scmd);
1336 void megasas_fusion_ocr_wq(struct work_struct *work);
1338 #endif /* _MEGARAID_SAS_FUSION_H_ */