1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux MegaRAID driver for SAS based RAID controllers
5 * Copyright (c) 2003-2013 LSI Corporation
6 * Copyright (c) 2013-2016 Avago Technologies
7 * Copyright (c) 2016-2018 Broadcom Inc.
11 * Authors: Broadcom Inc.
12 * Kashyap Desai <kashyap.desai@broadcom.com>
13 * Sumit Saxena <sumit.saxena@broadcom.com>
15 * Send feedback to: megaraidlinux.pdl@broadcom.com
18 #ifndef LSI_MEGARAID_SAS_H
19 #define LSI_MEGARAID_SAS_H
22 * MegaRAID SAS Driver meta data
24 #define MEGASAS_VERSION "07.714.04.00-rc1"
25 #define MEGASAS_RELDATE "Apr 14, 2020"
27 #define MEGASAS_MSIX_NAME_LEN 32
32 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
33 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
34 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
35 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
36 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
37 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
38 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
39 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
40 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
41 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
42 #define PCI_DEVICE_ID_LSI_FURY 0x005f
43 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
44 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
45 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
46 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
47 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
48 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
49 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
50 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
51 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
52 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
53 #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1
54 #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2
55 #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5
56 #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6
57 #define PCI_DEVICE_ID_LSI_AERO_10E0 0x10e0
58 #define PCI_DEVICE_ID_LSI_AERO_10E3 0x10e3
59 #define PCI_DEVICE_ID_LSI_AERO_10E4 0x10e4
60 #define PCI_DEVICE_ID_LSI_AERO_10E7 0x10e7
65 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
66 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
67 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
68 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
69 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
70 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
71 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
76 #define MEGARAID_INTRUDER_SSDID1 0x9371
77 #define MEGARAID_INTRUDER_SSDID2 0x9390
78 #define MEGARAID_INTRUDER_SSDID3 0x9370
83 #define MEGARAID_INTEL_RS3DC080_BRANDING \
84 "Intel(R) RAID Controller RS3DC080"
85 #define MEGARAID_INTEL_RS3DC040_BRANDING \
86 "Intel(R) RAID Controller RS3DC040"
87 #define MEGARAID_INTEL_RS3SC008_BRANDING \
88 "Intel(R) RAID Controller RS3SC008"
89 #define MEGARAID_INTEL_RS3MC044_BRANDING \
90 "Intel(R) RAID Controller RS3MC044"
91 #define MEGARAID_INTEL_RS3WC080_BRANDING \
92 "Intel(R) RAID Controller RS3WC080"
93 #define MEGARAID_INTEL_RS3WC040_BRANDING \
94 "Intel(R) RAID Controller RS3WC040"
95 #define MEGARAID_INTEL_RMS3BC160_BRANDING \
96 "Intel(R) Integrated RAID Module RMS3BC160"
99 * =====================================
100 * MegaRAID SAS MFI firmware definitions
101 * =====================================
105 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
106 * protocol between the software and firmware. Commands are issued using
111 * FW posts its state in upper 4 bits of outbound_msg_0 register
113 #define MFI_STATE_MASK 0xF0000000
114 #define MFI_STATE_UNDEFINED 0x00000000
115 #define MFI_STATE_BB_INIT 0x10000000
116 #define MFI_STATE_FW_INIT 0x40000000
117 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
118 #define MFI_STATE_FW_INIT_2 0x70000000
119 #define MFI_STATE_DEVICE_SCAN 0x80000000
120 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
121 #define MFI_STATE_FLUSH_CACHE 0xA0000000
122 #define MFI_STATE_READY 0xB0000000
123 #define MFI_STATE_OPERATIONAL 0xC0000000
124 #define MFI_STATE_FAULT 0xF0000000
125 #define MFI_STATE_FORCE_OCR 0x00000080
126 #define MFI_STATE_DMADONE 0x00000008
127 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
128 #define MFI_RESET_REQUIRED 0x00000001
129 #define MFI_RESET_ADAPTER 0x00000002
130 #define MEGAMFI_FRAME_SIZE 64
132 #define MFI_STATE_FAULT_CODE 0x0FFF0000
133 #define MFI_STATE_FAULT_SUBCODE 0x0000FF00
135 * During FW init, clear pending cmds & reset state using inbound_msg_0
137 * ABORT : Abort all pending cmds
138 * READY : Move from OPERATIONAL to READY state; discard queue info
139 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
140 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
141 * HOTPLUG : Resume from Hotplug
142 * MFI_STOP_ADP : Send signal to FW to stop processing
143 * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
145 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
146 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
147 #define DIAG_WRITE_ENABLE (0x00000080)
148 #define DIAG_RESET_ADAPTER (0x00000004)
150 #define MFI_ADP_RESET 0x00000040
151 #define MFI_INIT_ABORT 0x00000001
152 #define MFI_INIT_READY 0x00000002
153 #define MFI_INIT_MFIMODE 0x00000004
154 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
155 #define MFI_INIT_HOTPLUG 0x00000010
156 #define MFI_STOP_ADP 0x00000020
157 #define MFI_RESET_FLAGS MFI_INIT_READY| \
160 #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100
161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
166 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
167 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
168 #define MFI_FRAME_SGL32 0x0000
169 #define MFI_FRAME_SGL64 0x0002
170 #define MFI_FRAME_SENSE32 0x0000
171 #define MFI_FRAME_SENSE64 0x0004
172 #define MFI_FRAME_DIR_NONE 0x0000
173 #define MFI_FRAME_DIR_WRITE 0x0008
174 #define MFI_FRAME_DIR_READ 0x0010
175 #define MFI_FRAME_DIR_BOTH 0x0018
176 #define MFI_FRAME_IEEE 0x0020
178 /* Driver internal */
179 #define DRV_DCMD_POLLED_MODE 0x1
180 #define DRV_DCMD_SKIP_REFIRE 0x2
183 * Definition for cmd_status
185 #define MFI_CMD_STATUS_POLL_MODE 0xFF
188 * MFI command opcodes
192 MFI_CMD_LD_READ = 0x1,
193 MFI_CMD_LD_WRITE = 0x2,
194 MFI_CMD_LD_SCSI_IO = 0x3,
195 MFI_CMD_PD_SCSI_IO = 0x4,
201 MFI_CMD_TOOLBOX = 0xa,
203 MFI_CMD_INVALID = 0xff
206 #define MR_DCMD_CTRL_GET_INFO 0x01010000
207 #define MR_DCMD_LD_GET_LIST 0x03010000
208 #define MR_DCMD_LD_LIST_QUERY 0x03010100
210 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
211 #define MR_FLUSH_CTRL_CACHE 0x01
212 #define MR_FLUSH_DISK_CACHE 0x02
214 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
215 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
216 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
218 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
219 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
220 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
221 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
223 #define MR_DCMD_CLUSTER 0x08000000
224 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
225 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
226 #define MR_DCMD_PD_LIST_QUERY 0x02010100
228 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
229 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
230 #define MR_DCMD_PD_GET_INFO 0x02020000
235 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
239 * MFI command completion codes
243 MFI_STAT_INVALID_CMD = 0x01,
244 MFI_STAT_INVALID_DCMD = 0x02,
245 MFI_STAT_INVALID_PARAMETER = 0x03,
246 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
247 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
248 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
249 MFI_STAT_APP_IN_USE = 0x07,
250 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
251 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
252 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
253 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
254 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
255 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
256 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
257 MFI_STAT_FLASH_BUSY = 0x0f,
258 MFI_STAT_FLASH_ERROR = 0x10,
259 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
260 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
261 MFI_STAT_FLASH_NOT_OPEN = 0x13,
262 MFI_STAT_FLASH_NOT_STARTED = 0x14,
263 MFI_STAT_FLUSH_FAILED = 0x15,
264 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
265 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
266 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
267 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
268 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
269 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
270 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
271 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
272 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
273 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
274 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
275 MFI_STAT_MFC_HW_ERROR = 0x21,
276 MFI_STAT_NO_HW_PRESENT = 0x22,
277 MFI_STAT_NOT_FOUND = 0x23,
278 MFI_STAT_NOT_IN_ENCL = 0x24,
279 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
280 MFI_STAT_PD_TYPE_WRONG = 0x26,
281 MFI_STAT_PR_DISABLED = 0x27,
282 MFI_STAT_ROW_INDEX_INVALID = 0x28,
283 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
284 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
285 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
286 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
287 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
288 MFI_STAT_SCSI_IO_FAILED = 0x2e,
289 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
290 MFI_STAT_SHUTDOWN_FAILED = 0x30,
291 MFI_STAT_TIME_NOT_SET = 0x31,
292 MFI_STAT_WRONG_STATE = 0x32,
293 MFI_STAT_LD_OFFLINE = 0x33,
294 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
295 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
296 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
297 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
298 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
299 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
301 MFI_STAT_INVALID_STATUS = 0xFF
305 MFI_EVT_CLASS_DEBUG = -2,
306 MFI_EVT_CLASS_PROGRESS = -1,
307 MFI_EVT_CLASS_INFO = 0,
308 MFI_EVT_CLASS_WARNING = 1,
309 MFI_EVT_CLASS_CRITICAL = 2,
310 MFI_EVT_CLASS_FATAL = 3,
311 MFI_EVT_CLASS_DEAD = 4
315 * Crash dump related defines
317 #define MAX_CRASH_DUMP_SIZE 512
318 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
320 enum MR_FW_CRASH_DUMP_STATE {
328 enum _MR_CRASH_BUF_STATUS {
329 MR_CRASH_BUF_TURN_OFF = 0,
330 MR_CRASH_BUF_TURN_ON = 1,
334 * Number of mailbox bytes in DCMD message frame
336 #define MFI_MBOX_SIZE 12
340 MR_EVT_CLASS_DEBUG = -2,
341 MR_EVT_CLASS_PROGRESS = -1,
342 MR_EVT_CLASS_INFO = 0,
343 MR_EVT_CLASS_WARNING = 1,
344 MR_EVT_CLASS_CRITICAL = 2,
345 MR_EVT_CLASS_FATAL = 3,
346 MR_EVT_CLASS_DEAD = 4,
352 MR_EVT_LOCALE_LD = 0x0001,
353 MR_EVT_LOCALE_PD = 0x0002,
354 MR_EVT_LOCALE_ENCL = 0x0004,
355 MR_EVT_LOCALE_BBU = 0x0008,
356 MR_EVT_LOCALE_SAS = 0x0010,
357 MR_EVT_LOCALE_CTRL = 0x0020,
358 MR_EVT_LOCALE_CONFIG = 0x0040,
359 MR_EVT_LOCALE_CLUSTER = 0x0080,
360 MR_EVT_LOCALE_ALL = 0xffff,
367 MR_EVT_ARGS_CDB_SENSE,
369 MR_EVT_ARGS_LD_COUNT,
371 MR_EVT_ARGS_LD_OWNER,
372 MR_EVT_ARGS_LD_LBA_PD_LBA,
374 MR_EVT_ARGS_LD_STATE,
375 MR_EVT_ARGS_LD_STRIP,
379 MR_EVT_ARGS_PD_LBA_LD,
381 MR_EVT_ARGS_PD_STATE,
388 MR_EVT_ARGS_PD_SPARE,
389 MR_EVT_ARGS_PD_INDEX,
390 MR_EVT_ARGS_DIAG_PASS,
391 MR_EVT_ARGS_DIAG_FAIL,
392 MR_EVT_ARGS_PD_LBA_LBA,
393 MR_EVT_ARGS_PORT_PHY,
394 MR_EVT_ARGS_PD_MISSING,
395 MR_EVT_ARGS_PD_ADDRESS,
397 MR_EVT_ARGS_CONNECTOR,
400 MR_EVT_ARGS_PD_PATHINFO,
401 MR_EVT_ARGS_PD_POWER_STATE,
406 #define SGE_BUFFER_SIZE 4096
407 #define MEGASAS_CLUSTER_ID_SIZE 16
409 * define constants for device list query options
411 enum MR_PD_QUERY_TYPE {
412 MR_PD_QUERY_TYPE_ALL = 0,
413 MR_PD_QUERY_TYPE_STATE = 1,
414 MR_PD_QUERY_TYPE_POWER_STATE = 2,
415 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
416 MR_PD_QUERY_TYPE_SPEED = 4,
417 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
420 enum MR_LD_QUERY_TYPE {
421 MR_LD_QUERY_TYPE_ALL = 0,
422 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
423 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
424 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
425 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
429 #define MR_EVT_CFG_CLEARED 0x0004
430 #define MR_EVT_LD_STATE_CHANGE 0x0051
431 #define MR_EVT_PD_INSERTED 0x005b
432 #define MR_EVT_PD_REMOVED 0x0070
433 #define MR_EVT_LD_CREATED 0x008a
434 #define MR_EVT_LD_DELETED 0x008b
435 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
436 #define MR_EVT_LD_OFFLINE 0x00fc
437 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
438 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
441 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
442 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
443 MR_PD_STATE_HOT_SPARE = 0x02,
444 MR_PD_STATE_OFFLINE = 0x10,
445 MR_PD_STATE_FAILED = 0x11,
446 MR_PD_STATE_REBUILD = 0x14,
447 MR_PD_STATE_ONLINE = 0x18,
448 MR_PD_STATE_COPYBACK = 0x20,
449 MR_PD_STATE_SYSTEM = 0x40,
461 * define the DDF Type bit structure
463 union MR_PD_DDF_TYPE {
467 #ifndef __BIG_ENDIAN_BITFIELD
496 * defines the progress structure
503 u16 elapsedSecsForLastPercent;
510 * defines the physical drive progress structure
512 struct MR_PD_PROGRESS {
514 #ifndef __BIG_ENDIAN_BITFIELD
532 union MR_PROGRESS rbld;
533 union MR_PROGRESS patrol;
535 union MR_PROGRESS clear;
536 union MR_PROGRESS erase;
540 #ifndef __BIG_ENDIAN_BITFIELD
557 union MR_PROGRESS reserved[3];
568 u8 connectedPortBitmap;
569 u8 connectedPortNumbers;
576 u32 lastPredFailEventSeqNum;
579 u8 disabledForRemoval;
581 union MR_PD_DDF_TYPE state;
585 #ifndef __BIG_ENDIAN_BITFIELD
588 u8 widePortCapable:1;
590 u8 widePortCapable:1;
595 u8 connectorIndex[2];
609 u8 enclConnectorIndex;
612 struct MR_PD_PROGRESS progInfo;
613 u8 badBlockTableFull;
614 u8 unusableInCurrentConfig;
619 u16 copyBackPartnerId;
620 u16 enclPartnerDeviceId;
622 #ifndef __BIG_ENDIAN_BITFIELD
643 u8 bridgeProductIdentification[16];
644 u8 bridgeProductRevisionLevel[4];
649 u8 emulatedBlockSize;
650 u16 userDataBlockSize;
654 #ifndef __BIG_ENDIAN_BITFIELD
660 u32 commissionedSpare:1;
661 u32 emergencySpare:1;
662 u32 ineligibleForSSCD:1;
663 u32 ineligibleForLd:1;
664 u32 useSSEraseType:1;
666 u32 supportScsiUnmap:1;
670 u32 supportScsiUnmap:1;
672 u32 useSSEraseType:1;
673 u32 ineligibleForLd:1;
674 u32 ineligibleForSSCD:1;
675 u32 emergencySpare:1;
676 u32 commissionedSpare:1;
685 u64 shieldDiagCompletionTime;
692 #ifndef __BIG_ENDIAN_BITFIELD
693 u32 bbmErrCountSupported:1;
697 u32 bbmErrCountSupported:1;
701 u8 reserved1[512-428];
705 * Definition of structure used to expose attributes of VD or JBOD
706 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
707 * is fired by driver)
709 struct MR_TARGET_PROPERTIES {
718 * defines the physical drive address structure
720 struct MR_PD_ADDRESS {
731 u8 enclConnectorIndex;
736 u8 connectedPortBitmap;
737 u8 connectedPortNumbers;
743 * defines the physical drive list structure
748 struct MR_PD_ADDRESS addr[1];
751 struct megasas_pd_list {
758 * defines the logical drive reference structure
770 * defines the logical drive list structure
780 } ldList[MAX_LOGICAL_DRIVES_EXT];
783 struct MR_LD_TARGETID_LIST {
787 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
790 struct MR_HOST_DEVICE_LIST_ENTRY {
794 #if defined(__BIG_ENDIAN_BITFIELD)
811 struct MR_HOST_DEVICE_LIST {
815 struct MR_HOST_DEVICE_LIST_ENTRY host_device_list[1];
818 #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) + \
819 (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) * \
820 (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
824 * SAS controller properties
826 struct megasas_ctrl_prop {
829 u16 pred_fail_poll_interval;
830 u16 intr_throttle_count;
831 u16 intr_throttle_timeouts;
837 u8 cache_flush_interval;
843 u8 disable_auto_rebuild;
844 u8 disable_battery_warn;
846 u16 ecc_bucket_leak_rate;
847 u8 restore_hotspare_on_insertion;
848 u8 expose_encl_devices;
849 u8 maintainPdFailHistory;
850 u8 disallowHostRequestReordering;
853 u8 disableAutoDetectBackplane;
858 * Add properties that can be controlled by
859 * a bit in the following structure.
862 #if defined(__BIG_ENDIAN_BITFIELD)
865 u32 disableSpinDownHS:1;
866 u32 allowBootWithPinnedCache:1;
867 u32 disableOnlineCtrlReset:1;
868 u32 enableSecretKeyControl:1;
869 u32 autoEnhancedImport:1;
870 u32 enableSpinDownUnconfigured:1;
871 u32 SSDPatrolReadEnabled:1;
872 u32 SSDSMARTerEnabled:1;
875 u32 prCorrectUnconfiguredAreas:1;
876 u32 SMARTerEnabled:1;
877 u32 copyBackDisabled:1;
879 u32 copyBackDisabled:1;
880 u32 SMARTerEnabled:1;
881 u32 prCorrectUnconfiguredAreas:1;
884 u32 SSDSMARTerEnabled:1;
885 u32 SSDPatrolReadEnabled:1;
886 u32 enableSpinDownUnconfigured:1;
887 u32 autoEnhancedImport:1;
888 u32 enableSecretKeyControl:1;
889 u32 disableOnlineCtrlReset:1;
890 u32 allowBootWithPinnedCache:1;
891 u32 disableSpinDownHS:1;
901 #if defined(__BIG_ENDIAN_BITFIELD)
903 u16 enable_fw_dev_list:1;
905 u16 enable_snap_dump:1;
909 u16 enable_snap_dump:1;
911 u16 enable_fw_dev_list:1;
914 } on_off_properties2;
921 * SAS controller information
923 struct megasas_ctrl_info {
926 * PCI device information
932 __le16 sub_vendor_id;
933 __le16 sub_device_id;
936 } __attribute__ ((packed)) pci;
939 * Host interface information
953 } __attribute__ ((packed)) host_interface;
956 * Device (backend) interface information
969 } __attribute__ ((packed)) device_interface;
972 * List of components residing in flash. All str are null terminated
974 __le32 image_check_word;
975 __le32 image_component_count;
984 } __attribute__ ((packed)) image_component[8];
987 * List of flash components that have been flashed on the card, but
988 * are not in use, pending reset of the adapter. This list will be
989 * empty if a flash operation has not occurred. All stings are null
992 __le32 pending_image_component_count;
1001 } __attribute__ ((packed)) pending_image_component[8];
1008 char product_name[80];
1012 * Other physical/controller/operation information. Indicates the
1013 * presence of the hardware
1023 } __attribute__ ((packed)) hw_present;
1025 __le32 current_fw_time;
1028 * Maximum data transfer sizes
1030 __le16 max_concurrent_cmds;
1031 __le16 max_sge_count;
1032 __le32 max_request_size;
1035 * Logical and physical device counts
1037 __le16 ld_present_count;
1038 __le16 ld_degraded_count;
1039 __le16 ld_offline_count;
1041 __le16 pd_present_count;
1042 __le16 pd_disk_present_count;
1043 __le16 pd_disk_pred_failure_count;
1044 __le16 pd_disk_failed_count;
1047 * Memory size information
1056 __le16 mem_correctable_error_count;
1057 __le16 mem_uncorrectable_error_count;
1060 * Cluster information
1062 u8 cluster_permitted;
1066 * Additional max data transfer sizes
1068 __le16 max_strips_per_io;
1071 * Controller capabilities structures
1078 u32 raid_level_1E:1;
1082 } __attribute__ ((packed)) raid_levels;
1091 u32 alarm_control:1;
1092 u32 cluster_supported:1;
1094 u32 spanning_allowed:1;
1095 u32 dedicated_hotspares:1;
1096 u32 revertible_hotspares:1;
1097 u32 foreign_config_import:1;
1098 u32 self_diagnostic:1;
1099 u32 mixed_redundancy_arr:1;
1100 u32 global_hot_spares:1;
1103 } __attribute__ ((packed)) adapter_operations;
1110 u32 access_policy:1;
1111 u32 disk_cache_policy:1;
1114 } __attribute__ ((packed)) ld_operations;
1122 } __attribute__ ((packed)) stripe_sz_ops;
1127 u32 force_offline:1;
1128 u32 force_rebuild:1;
1131 } __attribute__ ((packed)) pd_operations;
1135 u32 ctrl_supports_sas:1;
1136 u32 ctrl_supports_sata:1;
1137 u32 allow_mix_in_encl:1;
1138 u32 allow_mix_in_ld:1;
1139 u32 allow_sata_in_cluster:1;
1142 } __attribute__ ((packed)) pd_mix_support;
1145 * Define ECC single-bit-error bucket information
1147 u8 ecc_bucket_count;
1151 * Include the controller properties (changeable items)
1153 struct megasas_ctrl_prop properties;
1156 * Define FW pkg version (set in envt v'bles on OEM basis)
1158 char package_version[0x60];
1162 * If adapterOperations.supportMoreThan8Phys is set,
1163 * and deviceInterface.portCount is greater than 8,
1164 * SAS Addrs for first 8 ports shall be populated in
1165 * deviceInterface.portAddr, and the rest shall be
1166 * populated in deviceInterfacePortAddr2.
1168 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
1169 u8 reserved3[128]; /*6e0h */
1172 u16 minPdRaidLevel_0:4;
1173 u16 maxPdRaidLevel_0:12;
1175 u16 minPdRaidLevel_1:4;
1176 u16 maxPdRaidLevel_1:12;
1178 u16 minPdRaidLevel_5:4;
1179 u16 maxPdRaidLevel_5:12;
1181 u16 minPdRaidLevel_1E:4;
1182 u16 maxPdRaidLevel_1E:12;
1184 u16 minPdRaidLevel_6:4;
1185 u16 maxPdRaidLevel_6:12;
1187 u16 minPdRaidLevel_10:4;
1188 u16 maxPdRaidLevel_10:12;
1190 u16 minPdRaidLevel_50:4;
1191 u16 maxPdRaidLevel_50:12;
1193 u16 minPdRaidLevel_60:4;
1194 u16 maxPdRaidLevel_60:12;
1196 u16 minPdRaidLevel_1E_RLQ0:4;
1197 u16 maxPdRaidLevel_1E_RLQ0:12;
1199 u16 minPdRaidLevel_1E0_RLQ0:4;
1200 u16 maxPdRaidLevel_1E0_RLQ0:12;
1205 __le16 maxPds; /*780h */
1206 __le16 maxDedHSPs; /*782h */
1207 __le16 maxGlobalHSP; /*784h */
1208 __le16 ddfSize; /*786h */
1209 u8 maxLdsPerArray; /*788h */
1210 u8 partitionsInDDF; /*789h */
1211 u8 lockKeyBinding; /*78ah */
1212 u8 maxPITsPerLd; /*78bh */
1213 u8 maxViewsPerLd; /*78ch */
1214 u8 maxTargetId; /*78dh */
1215 __le16 maxBvlVdSize; /*78eh */
1217 __le16 maxConfigurableSSCSize; /*790h */
1218 __le16 currentSSCsize; /*792h */
1220 char expanderFwVersion[12]; /*794h */
1222 __le16 PFKTrialTimeRemaining; /*7A0h */
1224 __le16 cacheMemorySize; /*7A2h */
1227 #if defined(__BIG_ENDIAN_BITFIELD)
1229 u32 activePassive:2;
1230 u32 supportConfigAutoBalance:1;
1232 u32 supportDataLDonSSCArray:1;
1233 u32 supportPointInTimeProgress:1;
1234 u32 supportUnevenSpans:1;
1235 u32 dedicatedHotSparesLimited:1;
1237 u32 supportEmulatedDrives:1;
1238 u32 supportResetNow:1;
1239 u32 realTimeScheduler:1;
1240 u32 supportSSDPatrolRead:1;
1241 u32 supportPerfTuning:1;
1242 u32 disableOnlinePFKChange:1;
1244 u32 supportBootTimePFKChange:1;
1245 u32 supportSetLinkSpeed:1;
1246 u32 supportEmergencySpares:1;
1247 u32 supportSuspendResumeBGops:1;
1248 u32 blockSSDWriteCacheChange:1;
1249 u32 supportShieldState:1;
1250 u32 supportLdBBMInfo:1;
1251 u32 supportLdPIType3:1;
1252 u32 supportLdPIType2:1;
1253 u32 supportLdPIType1:1;
1254 u32 supportPIcontroller:1;
1256 u32 supportPIcontroller:1;
1257 u32 supportLdPIType1:1;
1258 u32 supportLdPIType2:1;
1259 u32 supportLdPIType3:1;
1260 u32 supportLdBBMInfo:1;
1261 u32 supportShieldState:1;
1262 u32 blockSSDWriteCacheChange:1;
1263 u32 supportSuspendResumeBGops:1;
1264 u32 supportEmergencySpares:1;
1265 u32 supportSetLinkSpeed:1;
1266 u32 supportBootTimePFKChange:1;
1268 u32 disableOnlinePFKChange:1;
1269 u32 supportPerfTuning:1;
1270 u32 supportSSDPatrolRead:1;
1271 u32 realTimeScheduler:1;
1273 u32 supportResetNow:1;
1274 u32 supportEmulatedDrives:1;
1276 u32 dedicatedHotSparesLimited:1;
1279 u32 supportUnevenSpans:1;
1280 u32 supportPointInTimeProgress:1;
1281 u32 supportDataLDonSSCArray:1;
1283 u32 supportConfigAutoBalance:1;
1284 u32 activePassive:2;
1287 } adapterOperations2;
1289 u8 driverVersion[32]; /*7A8h */
1290 u8 maxDAPdCountSpinup60; /*7C8h */
1291 u8 temperatureROC; /*7C9h */
1292 u8 temperatureCtrl; /*7CAh */
1293 u8 reserved4; /*7CBh */
1294 __le16 maxConfigurablePds; /*7CCh */
1297 u8 reserved5[2]; /*0x7CDh */
1300 * HA cluster information
1303 #if defined(__BIG_ENDIAN_BITFIELD)
1306 u32 premiumFeatureMismatch:1;
1307 u32 ctrlPropIncompatible:1;
1308 u32 fwVersionMismatch:1;
1309 u32 hwIncompatible:1;
1310 u32 peerIsIncompatible:1;
1311 u32 peerIsPresent:1;
1313 u32 peerIsPresent:1;
1314 u32 peerIsIncompatible:1;
1315 u32 hwIncompatible:1;
1316 u32 fwVersionMismatch:1;
1317 u32 ctrlPropIncompatible:1;
1318 u32 premiumFeatureMismatch:1;
1324 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1326 u8 maxVFsSupported; /*0x7E4*/
1327 u8 numVFsEnabled; /*0x7E5*/
1328 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1329 u8 reserved; /*0x7E7*/
1333 #if defined(__BIG_ENDIAN_BITFIELD)
1335 u32 useSeqNumJbodFP:1;
1336 u32 supportExtendedSSCSize:1;
1337 u32 supportDiskCacheSettingForSysPDs:1;
1338 u32 supportCPLDUpdate:1;
1339 u32 supportTTYLogCompression:1;
1340 u32 discardCacheDuringLDDelete:1;
1341 u32 supportSecurityonJBOD:1;
1342 u32 supportCacheBypassModes:1;
1343 u32 supportDisableSESMonitoring:1;
1344 u32 supportForceFlash:1;
1345 u32 supportNVDRAM:1;
1346 u32 supportDrvActivityLEDSetting:1;
1347 u32 supportAllowedOpsforDrvRemoval:1;
1348 u32 supportHOQRebuild:1;
1349 u32 supportForceTo512e:1;
1350 u32 supportNVCacheErase:1;
1351 u32 supportDebugQueue:1;
1352 u32 supportSwZone:1;
1353 u32 supportCrashDump:1;
1354 u32 supportMaxExtLDs:1;
1355 u32 supportT10RebuildAssist:1;
1356 u32 supportDisableImmediateIO:1;
1357 u32 supportThermalPollInterval:1;
1358 u32 supportPersonalityChange:2;
1360 u32 supportPersonalityChange:2;
1361 u32 supportThermalPollInterval:1;
1362 u32 supportDisableImmediateIO:1;
1363 u32 supportT10RebuildAssist:1;
1364 u32 supportMaxExtLDs:1;
1365 u32 supportCrashDump:1;
1366 u32 supportSwZone:1;
1367 u32 supportDebugQueue:1;
1368 u32 supportNVCacheErase:1;
1369 u32 supportForceTo512e:1;
1370 u32 supportHOQRebuild:1;
1371 u32 supportAllowedOpsforDrvRemoval:1;
1372 u32 supportDrvActivityLEDSetting:1;
1373 u32 supportNVDRAM:1;
1374 u32 supportForceFlash:1;
1375 u32 supportDisableSESMonitoring:1;
1376 u32 supportCacheBypassModes:1;
1377 u32 supportSecurityonJBOD:1;
1378 u32 discardCacheDuringLDDelete:1;
1379 u32 supportTTYLogCompression:1;
1380 u32 supportCPLDUpdate:1;
1381 u32 supportDiskCacheSettingForSysPDs:1;
1382 u32 supportExtendedSSCSize:1;
1383 u32 useSeqNumJbodFP:1;
1386 } adapterOperations3;
1389 #if defined(__BIG_ENDIAN_BITFIELD)
1391 /* Indicates whether the CPLD image is part of
1392 * the package and stored in flash
1400 /* Null terminated string. Has the version
1401 * information if cpld_in_flash = FALSE
1403 u8 userCodeDefinition[12];
1404 } cpld; /* Valid only if upgradableCPLD is TRUE */
1407 #if defined(__BIG_ENDIAN_BITFIELD)
1409 u16 support_nvme_passthru:1;
1410 u16 support_pl_debug_info:1;
1411 u16 support_flash_comp_info:1;
1412 u16 support_host_info:1;
1413 u16 support_dual_fw_update:1;
1414 u16 support_ssc_rev3:1;
1415 u16 fw_swaps_bbu_vpd_info:1;
1416 u16 support_pd_map_target_id:1;
1417 u16 support_ses_ctrl_in_multipathcfg:1;
1418 u16 image_upload_supported:1;
1419 u16 support_encrypted_mfc:1;
1420 u16 supported_enc_algo:1;
1421 u16 support_ibutton_less:1;
1422 u16 ctrl_info_ext_supported:1;
1425 u16 ctrl_info_ext_supported:1;
1426 u16 support_ibutton_less:1;
1427 u16 supported_enc_algo:1;
1428 u16 support_encrypted_mfc:1;
1429 u16 image_upload_supported:1;
1430 /* FW supports LUN based association and target port based */
1431 u16 support_ses_ctrl_in_multipathcfg:1;
1432 /* association for the SES device connected in multipath mode */
1433 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1434 u16 support_pd_map_target_id:1;
1435 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1436 * provide the data in little endian order
1438 u16 fw_swaps_bbu_vpd_info:1;
1439 u16 support_ssc_rev3:1;
1440 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1441 u16 support_dual_fw_update:1;
1442 /* FW supports dual firmware update feature */
1443 u16 support_host_info:1;
1444 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1445 u16 support_flash_comp_info:1;
1446 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1447 u16 support_pl_debug_info:1;
1448 /* FW supports retrieval of PL debug information through apps */
1449 u16 support_nvme_passthru:1;
1450 /* FW supports NVMe passthru commands */
1453 } adapter_operations4;
1454 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1462 #if defined(__BIG_ENDIAN_BITFIELD)
1464 u32 support_pci_lane_margining: 1;
1465 u32 support_psoc_update:1;
1466 u32 support_force_personality_change:1;
1467 u32 support_fde_type_mix:1;
1468 u32 support_snap_dump:1;
1469 u32 support_nvme_tm:1;
1470 u32 support_oce_only:1;
1471 u32 support_ext_mfg_vpd:1;
1473 u32 support_cvhealth_info:1;
1474 u32 support_profile_change:2;
1475 u32 mr_config_ext2_supported:1;
1477 u32 mr_config_ext2_supported:1;
1478 u32 support_profile_change:2;
1479 u32 support_cvhealth_info:1;
1481 u32 support_ext_mfg_vpd:1;
1482 u32 support_oce_only:1;
1483 u32 support_nvme_tm:1;
1484 u32 support_snap_dump:1;
1485 u32 support_fde_type_mix:1;
1486 u32 support_force_personality_change:1;
1487 u32 support_psoc_update:1;
1488 u32 support_pci_lane_margining: 1;
1491 } adapter_operations5;
1493 u32 rsvdForAdptOp[63];
1497 u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1498 u8 MaxResetTO; /* Max Supported Reset timeout in seconds. */
1503 * ===============================
1504 * MegaRAID SAS driver definitions
1505 * ===============================
1507 #define MEGASAS_MAX_PD_CHANNELS 2
1508 #define MEGASAS_MAX_LD_CHANNELS 2
1509 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1510 MEGASAS_MAX_LD_CHANNELS)
1511 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1512 #define MEGASAS_DEFAULT_INIT_ID -1
1513 #define MEGASAS_MAX_LUN 8
1514 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1515 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1516 MEGASAS_MAX_DEV_PER_CHANNEL)
1517 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1518 MEGASAS_MAX_DEV_PER_CHANNEL)
1520 #define MEGASAS_MAX_SECTORS (2*1024)
1521 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1522 #define MEGASAS_DBG_LVL 1
1524 #define MEGASAS_FW_BUSY 1
1526 /* Driver's internal Logging levels*/
1527 #define OCR_DEBUG (1 << 0)
1528 #define TM_DEBUG (1 << 1)
1529 #define LD_PD_DEBUG (1 << 2)
1531 #define SCAN_PD_CHANNEL 0x1
1532 #define SCAN_VD_CHANNEL 0x2
1534 #define MEGASAS_KDUMP_QUEUE_DEPTH 100
1535 #define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1536 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
1538 enum MR_SCSI_CMD_TYPE {
1539 READ_WRITE_LDIO = 0,
1540 NON_READ_WRITE_LDIO = 1,
1541 READ_WRITE_SYSPDIO = 2,
1542 NON_READ_WRITE_SYSPDIO = 3,
1545 enum DCMD_TIMEOUT_ACTION {
1551 enum FW_BOOT_CONTEXT {
1558 #define PTHRU_FRAME 1
1561 * When SCSI mid-layer calls driver's reset routine, driver waits for
1562 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1563 * that the driver cannot _actually_ abort or reset pending commands. While
1564 * it is waiting for the commands to complete, it prints a diagnostic message
1565 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1567 #define MEGASAS_RESET_WAIT_TIME 180
1568 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1569 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1570 #define MEGASAS_IOCTL_CMD 0
1571 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1572 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1573 #define MEGASAS_DEFAULT_TM_TIMEOUT 50
1575 * FW reports the maximum of number of commands that it can accept (maximum
1576 * commands that can be outstanding) at any time. The driver must report a
1577 * lower number to the mid layer because it can issue a few internal commands
1578 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1581 #define MEGASAS_INT_CMDS 32
1582 #define MEGASAS_SKINNY_INT_CMDS 5
1583 #define MEGASAS_FUSION_INTERNAL_CMDS 8
1584 #define MEGASAS_FUSION_IOCTL_CMDS 3
1585 #define MEGASAS_MFI_IOCTL_CMDS 27
1587 #define MEGASAS_MAX_MSIX_QUEUES 128
1589 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1590 * SGLs based on the size of dma_addr_t
1592 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1594 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1596 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1597 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1598 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1600 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1601 #define MFI_POLL_TIMEOUT_SECS 60
1602 #define MFI_IO_TIMEOUT_SECS 180
1603 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1604 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1605 #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF 1
1606 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1607 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1608 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1609 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1610 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1611 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1613 #define MFI_1068_PCSR_OFFSET 0x84
1614 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1615 #define MFI_1068_FW_READY 0xDDDD0000
1617 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1618 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1619 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1620 #define MR_MAX_MSIX_REG_ARRAY 16
1621 #define MR_RDPQ_MODE_OFFSET 0X00800000
1623 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1624 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1625 #define MR_MIN_MAP_SIZE 0x10000
1628 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1630 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
1632 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25)
1633 #define MR_INTR_COALESCING_SUPPORT_OFFSET (1 << 26)
1635 #define MEGASAS_WATCHDOG_THREAD_INTERVAL 1000
1636 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS 20
1637 #define MEGASAS_WATCHDOG_WAIT_COUNT 50
1639 enum MR_ADAPTER_TYPE {
1641 THUNDERBOLT_SERIES = 2,
1648 * register set for both 1068 and 1078 controllers
1649 * structure extended for 1078 registers
1652 struct megasas_register_set {
1653 u32 doorbell; /*0000h*/
1654 u32 fusion_seq_offset; /*0004h*/
1655 u32 fusion_host_diag; /*0008h*/
1656 u32 reserved_01; /*000Ch*/
1658 u32 inbound_msg_0; /*0010h*/
1659 u32 inbound_msg_1; /*0014h*/
1660 u32 outbound_msg_0; /*0018h*/
1661 u32 outbound_msg_1; /*001Ch*/
1663 u32 inbound_doorbell; /*0020h*/
1664 u32 inbound_intr_status; /*0024h*/
1665 u32 inbound_intr_mask; /*0028h*/
1667 u32 outbound_doorbell; /*002Ch*/
1668 u32 outbound_intr_status; /*0030h*/
1669 u32 outbound_intr_mask; /*0034h*/
1671 u32 reserved_1[2]; /*0038h*/
1673 u32 inbound_queue_port; /*0040h*/
1674 u32 outbound_queue_port; /*0044h*/
1676 u32 reserved_2[9]; /*0048h*/
1677 u32 reply_post_host_index; /*006Ch*/
1678 u32 reserved_2_2[12]; /*0070h*/
1680 u32 outbound_doorbell_clear; /*00A0h*/
1682 u32 reserved_3[3]; /*00A4h*/
1684 u32 outbound_scratch_pad_0; /*00B0h*/
1685 u32 outbound_scratch_pad_1; /*00B4h*/
1686 u32 outbound_scratch_pad_2; /*00B8h*/
1687 u32 outbound_scratch_pad_3; /*00BCh*/
1689 u32 inbound_low_queue_port ; /*00C0h*/
1691 u32 inbound_high_queue_port ; /*00C4h*/
1693 u32 inbound_single_queue_port; /*00C8h*/
1694 u32 res_6[11]; /*CCh*/
1697 u32 index_registers[807]; /*00CCh*/
1698 } __attribute__ ((packed));
1700 struct megasas_sge32 {
1705 } __attribute__ ((packed));
1707 struct megasas_sge64 {
1712 } __attribute__ ((packed));
1714 struct megasas_sge_skinny {
1722 struct megasas_sge32 sge32[1];
1723 struct megasas_sge64 sge64[1];
1724 struct megasas_sge_skinny sge_skinny[1];
1726 } __attribute__ ((packed));
1728 struct megasas_header {
1731 u8 sense_len; /*01h */
1732 u8 cmd_status; /*02h */
1733 u8 scsi_status; /*03h */
1735 u8 target_id; /*04h */
1737 u8 cdb_len; /*06h */
1738 u8 sge_count; /*07h */
1740 __le32 context; /*08h */
1741 __le32 pad_0; /*0Ch */
1743 __le16 flags; /*10h */
1744 __le16 timeout; /*12h */
1745 __le32 data_xferlen; /*14h */
1747 } __attribute__ ((packed));
1749 union megasas_sgl_frame {
1751 struct megasas_sge32 sge32[8];
1752 struct megasas_sge64 sge64[5];
1754 } __attribute__ ((packed));
1756 typedef union _MFI_CAPABILITIES {
1758 #if defined(__BIG_ENDIAN_BITFIELD)
1760 u32 support_fw_exposed_dev_list:1;
1761 u32 support_nvme_passthru:1;
1762 u32 support_64bit_mode:1;
1763 u32 support_pd_map_target_id:1;
1764 u32 support_qd_throttling:1;
1765 u32 support_fp_rlbypass:1;
1766 u32 support_vfid_in_ioframe:1;
1767 u32 support_ext_io_size:1;
1768 u32 support_ext_queue_depth:1;
1769 u32 security_protocol_cmds_fw:1;
1770 u32 support_core_affinity:1;
1771 u32 support_ndrive_r1_lb:1;
1772 u32 support_max_255lds:1;
1773 u32 support_fastpath_wb:1;
1774 u32 support_additional_msix:1;
1775 u32 support_fp_remote_lun:1;
1777 u32 support_fp_remote_lun:1;
1778 u32 support_additional_msix:1;
1779 u32 support_fastpath_wb:1;
1780 u32 support_max_255lds:1;
1781 u32 support_ndrive_r1_lb:1;
1782 u32 support_core_affinity:1;
1783 u32 security_protocol_cmds_fw:1;
1784 u32 support_ext_queue_depth:1;
1785 u32 support_ext_io_size:1;
1786 u32 support_vfid_in_ioframe:1;
1787 u32 support_fp_rlbypass:1;
1788 u32 support_qd_throttling:1;
1789 u32 support_pd_map_target_id:1;
1790 u32 support_64bit_mode:1;
1791 u32 support_nvme_passthru:1;
1792 u32 support_fw_exposed_dev_list:1;
1799 struct megasas_init_frame {
1802 u8 reserved_0; /*01h */
1803 u8 cmd_status; /*02h */
1805 u8 reserved_1; /*03h */
1806 MFI_CAPABILITIES driver_operations; /*04h*/
1808 __le32 context; /*08h */
1809 __le32 pad_0; /*0Ch */
1811 __le16 flags; /*10h */
1812 __le16 replyqueue_mask; /*12h */
1813 __le32 data_xfer_len; /*14h */
1815 __le32 queue_info_new_phys_addr_lo; /*18h */
1816 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1817 __le32 queue_info_old_phys_addr_lo; /*20h */
1818 __le32 queue_info_old_phys_addr_hi; /*24h */
1819 __le32 reserved_4[2]; /*28h */
1820 __le32 system_info_lo; /*30h */
1821 __le32 system_info_hi; /*34h */
1822 __le32 reserved_5[2]; /*38h */
1824 } __attribute__ ((packed));
1826 struct megasas_init_queue_info {
1828 __le32 init_flags; /*00h */
1829 __le32 reply_queue_entries; /*04h */
1831 __le32 reply_queue_start_phys_addr_lo; /*08h */
1832 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1833 __le32 producer_index_phys_addr_lo; /*10h */
1834 __le32 producer_index_phys_addr_hi; /*14h */
1835 __le32 consumer_index_phys_addr_lo; /*18h */
1836 __le32 consumer_index_phys_addr_hi; /*1Ch */
1838 } __attribute__ ((packed));
1840 struct megasas_io_frame {
1843 u8 sense_len; /*01h */
1844 u8 cmd_status; /*02h */
1845 u8 scsi_status; /*03h */
1847 u8 target_id; /*04h */
1848 u8 access_byte; /*05h */
1849 u8 reserved_0; /*06h */
1850 u8 sge_count; /*07h */
1852 __le32 context; /*08h */
1853 __le32 pad_0; /*0Ch */
1855 __le16 flags; /*10h */
1856 __le16 timeout; /*12h */
1857 __le32 lba_count; /*14h */
1859 __le32 sense_buf_phys_addr_lo; /*18h */
1860 __le32 sense_buf_phys_addr_hi; /*1Ch */
1862 __le32 start_lba_lo; /*20h */
1863 __le32 start_lba_hi; /*24h */
1865 union megasas_sgl sgl; /*28h */
1867 } __attribute__ ((packed));
1869 struct megasas_pthru_frame {
1872 u8 sense_len; /*01h */
1873 u8 cmd_status; /*02h */
1874 u8 scsi_status; /*03h */
1876 u8 target_id; /*04h */
1878 u8 cdb_len; /*06h */
1879 u8 sge_count; /*07h */
1881 __le32 context; /*08h */
1882 __le32 pad_0; /*0Ch */
1884 __le16 flags; /*10h */
1885 __le16 timeout; /*12h */
1886 __le32 data_xfer_len; /*14h */
1888 __le32 sense_buf_phys_addr_lo; /*18h */
1889 __le32 sense_buf_phys_addr_hi; /*1Ch */
1891 u8 cdb[16]; /*20h */
1892 union megasas_sgl sgl; /*30h */
1894 } __attribute__ ((packed));
1896 struct megasas_dcmd_frame {
1899 u8 reserved_0; /*01h */
1900 u8 cmd_status; /*02h */
1901 u8 reserved_1[4]; /*03h */
1902 u8 sge_count; /*07h */
1904 __le32 context; /*08h */
1905 __le32 pad_0; /*0Ch */
1907 __le16 flags; /*10h */
1908 __le16 timeout; /*12h */
1910 __le32 data_xfer_len; /*14h */
1911 __le32 opcode; /*18h */
1919 union megasas_sgl sgl; /*28h */
1921 } __attribute__ ((packed));
1923 struct megasas_abort_frame {
1926 u8 reserved_0; /*01h */
1927 u8 cmd_status; /*02h */
1929 u8 reserved_1; /*03h */
1930 __le32 reserved_2; /*04h */
1932 __le32 context; /*08h */
1933 __le32 pad_0; /*0Ch */
1935 __le16 flags; /*10h */
1936 __le16 reserved_3; /*12h */
1937 __le32 reserved_4; /*14h */
1939 __le32 abort_context; /*18h */
1940 __le32 pad_1; /*1Ch */
1942 __le32 abort_mfi_phys_addr_lo; /*20h */
1943 __le32 abort_mfi_phys_addr_hi; /*24h */
1945 __le32 reserved_5[6]; /*28h */
1947 } __attribute__ ((packed));
1949 struct megasas_smp_frame {
1952 u8 reserved_1; /*01h */
1953 u8 cmd_status; /*02h */
1954 u8 connection_status; /*03h */
1956 u8 reserved_2[3]; /*04h */
1957 u8 sge_count; /*07h */
1959 __le32 context; /*08h */
1960 __le32 pad_0; /*0Ch */
1962 __le16 flags; /*10h */
1963 __le16 timeout; /*12h */
1965 __le32 data_xfer_len; /*14h */
1966 __le64 sas_addr; /*18h */
1969 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1970 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1973 } __attribute__ ((packed));
1975 struct megasas_stp_frame {
1978 u8 reserved_1; /*01h */
1979 u8 cmd_status; /*02h */
1980 u8 reserved_2; /*03h */
1982 u8 target_id; /*04h */
1983 u8 reserved_3[2]; /*05h */
1984 u8 sge_count; /*07h */
1986 __le32 context; /*08h */
1987 __le32 pad_0; /*0Ch */
1989 __le16 flags; /*10h */
1990 __le16 timeout; /*12h */
1992 __le32 data_xfer_len; /*14h */
1994 __le16 fis[10]; /*18h */
1998 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1999 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
2002 } __attribute__ ((packed));
2004 union megasas_frame {
2006 struct megasas_header hdr;
2007 struct megasas_init_frame init;
2008 struct megasas_io_frame io;
2009 struct megasas_pthru_frame pthru;
2010 struct megasas_dcmd_frame dcmd;
2011 struct megasas_abort_frame abort;
2012 struct megasas_smp_frame smp;
2013 struct megasas_stp_frame stp;
2019 * struct MR_PRIV_DEVICE - sdev private hostdata
2020 * @is_tm_capable: firmware managed tm_capable flag
2021 * @tm_busy: TM request is in progress
2023 struct MR_PRIV_DEVICE {
2026 atomic_t r1_ldio_hint;
2029 u8 target_reset_tmo;
2033 union megasas_evt_class_locale {
2036 #ifndef __BIG_ENDIAN_BITFIELD
2045 } __attribute__ ((packed)) members;
2049 } __attribute__ ((packed));
2051 struct megasas_evt_log_info {
2052 __le32 newest_seq_num;
2053 __le32 oldest_seq_num;
2054 __le32 clear_seq_num;
2055 __le32 shutdown_seq_num;
2056 __le32 boot_seq_num;
2058 } __attribute__ ((packed));
2060 struct megasas_progress {
2063 __le16 elapsed_seconds;
2065 } __attribute__ ((packed));
2067 struct megasas_evtarg_ld {
2073 } __attribute__ ((packed));
2075 struct megasas_evtarg_pd {
2080 } __attribute__ ((packed));
2082 struct megasas_evt_detail {
2087 union megasas_evt_class_locale cl;
2093 struct megasas_evtarg_pd pd;
2099 } __attribute__ ((packed)) cdbSense;
2101 struct megasas_evtarg_ld ld;
2104 struct megasas_evtarg_ld ld;
2106 } __attribute__ ((packed)) ld_count;
2110 struct megasas_evtarg_ld ld;
2111 } __attribute__ ((packed)) ld_lba;
2114 struct megasas_evtarg_ld ld;
2117 } __attribute__ ((packed)) ld_owner;
2122 struct megasas_evtarg_ld ld;
2123 struct megasas_evtarg_pd pd;
2124 } __attribute__ ((packed)) ld_lba_pd_lba;
2127 struct megasas_evtarg_ld ld;
2128 struct megasas_progress prog;
2129 } __attribute__ ((packed)) ld_prog;
2132 struct megasas_evtarg_ld ld;
2135 } __attribute__ ((packed)) ld_state;
2139 struct megasas_evtarg_ld ld;
2140 } __attribute__ ((packed)) ld_strip;
2142 struct megasas_evtarg_pd pd;
2145 struct megasas_evtarg_pd pd;
2147 } __attribute__ ((packed)) pd_err;
2151 struct megasas_evtarg_pd pd;
2152 } __attribute__ ((packed)) pd_lba;
2156 struct megasas_evtarg_pd pd;
2157 struct megasas_evtarg_ld ld;
2158 } __attribute__ ((packed)) pd_lba_ld;
2161 struct megasas_evtarg_pd pd;
2162 struct megasas_progress prog;
2163 } __attribute__ ((packed)) pd_prog;
2166 struct megasas_evtarg_pd pd;
2169 } __attribute__ ((packed)) pd_state;
2176 } __attribute__ ((packed)) pci;
2184 } __attribute__ ((packed)) time;
2190 } __attribute__ ((packed)) ecc;
2198 char description[128];
2200 } __attribute__ ((packed));
2202 struct megasas_aen_event {
2203 struct delayed_work hotplug_work;
2204 struct megasas_instance *instance;
2207 struct megasas_irq_context {
2208 char name[MEGASAS_MSIX_NAME_LEN];
2209 struct megasas_instance *instance;
2212 struct irq_poll irqpoll;
2213 bool irq_poll_scheduled;
2214 bool irq_line_enable;
2217 struct MR_DRV_SYSTEM_INFO {
2234 /* JBOD Queue depth definitions */
2235 #define MEGASAS_SATA_QD 32
2236 #define MEGASAS_SAS_QD 256
2237 #define MEGASAS_DEFAULT_PD_QD 64
2238 #define MEGASAS_NVME_QD 64
2240 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
2241 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
2242 #define MR_DEFAULT_NVME_MDTS_KB 128
2243 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2245 /*Aero performance parameters*/
2246 #define MR_HIGH_IOPS_QUEUE_COUNT 8
2247 #define MR_DEVICE_HIGH_IOPS_DEPTH 8
2248 #define MR_HIGH_IOPS_BATCH_COUNT 16
2251 MR_BALANCED_PERF_MODE = 0,
2252 MR_IOPS_PERF_MODE = 1,
2253 MR_LATENCY_PERF_MODE = 2,
2256 #define MEGASAS_PERF_MODE_2STR(mode) \
2257 ((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
2258 (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
2259 (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
2262 enum MEGASAS_LD_TARGET_ID_STATUS {
2263 LD_TARGET_ID_INITIAL,
2264 LD_TARGET_ID_ACTIVE,
2265 LD_TARGET_ID_DELETED,
2268 #define MEGASAS_TARGET_ID(sdev) \
2269 (((sdev->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id)
2271 struct megasas_instance {
2273 unsigned int *reply_map;
2275 dma_addr_t producer_h;
2277 dma_addr_t consumer_h;
2278 struct MR_DRV_SYSTEM_INFO *system_info_buf;
2279 dma_addr_t system_info_h;
2280 struct MR_LD_VF_AFFILIATION *vf_affiliation;
2281 dma_addr_t vf_affiliation_h;
2282 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2283 dma_addr_t vf_affiliation_111_h;
2284 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2285 dma_addr_t hb_host_mem_h;
2286 struct MR_PD_INFO *pd_info;
2287 dma_addr_t pd_info_h;
2288 struct MR_TARGET_PROPERTIES *tgt_prop;
2289 dma_addr_t tgt_prop_h;
2291 __le32 *reply_queue;
2292 dma_addr_t reply_queue_h;
2294 u32 *crash_dump_buf;
2295 dma_addr_t crash_dump_h;
2297 struct MR_PD_LIST *pd_list_buf;
2298 dma_addr_t pd_list_buf_h;
2300 struct megasas_ctrl_info *ctrl_info_buf;
2301 dma_addr_t ctrl_info_buf_h;
2303 struct MR_LD_LIST *ld_list_buf;
2304 dma_addr_t ld_list_buf_h;
2306 struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2307 dma_addr_t ld_targetid_list_buf_h;
2309 struct MR_HOST_DEVICE_LIST *host_device_list_buf;
2310 dma_addr_t host_device_list_buf_h;
2312 struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2313 dma_addr_t snapdump_prop_h;
2315 void *crash_buf[MAX_CRASH_DUMP_SIZE];
2316 unsigned int fw_crash_buffer_size;
2317 unsigned int fw_crash_state;
2318 unsigned int fw_crash_buffer_offset;
2321 u32 crash_dump_fw_support;
2322 u32 crash_dump_drv_support;
2323 u32 crash_dump_app_support;
2324 u32 secure_jbod_support;
2325 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2326 bool use_seqnum_jbod_fp; /* Added for PD sequence */
2327 bool smp_affinity_enable;
2328 spinlock_t crashdump_lock;
2330 struct megasas_register_set __iomem *reg_set;
2331 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2332 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
2333 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
2334 u8 ld_ids[MEGASAS_MAX_LD_IDS];
2335 u8 ld_tgtid_status[MEGASAS_MAX_LD_IDS];
2336 u8 ld_ids_prev[MEGASAS_MAX_LD_IDS];
2337 u8 ld_ids_from_raidmap[MEGASAS_MAX_LD_IDS];
2347 u32 max_sectors_per_req;
2348 bool msix_load_balance;
2349 struct megasas_aen_event *ev;
2351 struct megasas_cmd **cmd_list;
2352 struct list_head cmd_pool;
2353 /* used to sync fire the cmd to fw */
2354 spinlock_t mfi_pool_lock;
2355 /* used to sync fire the cmd to fw */
2356 spinlock_t hba_lock;
2357 /* used to synch producer, consumer ptrs in dpc */
2358 spinlock_t stream_lock;
2359 spinlock_t completion_lock;
2360 struct dma_pool *frame_dma_pool;
2361 struct dma_pool *sense_dma_pool;
2363 struct megasas_evt_detail *evt_detail;
2364 dma_addr_t evt_detail_h;
2365 struct megasas_cmd *aen_cmd;
2366 struct semaphore ioctl_sem;
2368 struct Scsi_Host *host;
2370 wait_queue_head_t int_cmd_wait_q;
2371 wait_queue_head_t abort_cmd_wait_q;
2373 struct pci_dev *pdev;
2375 u32 fw_support_ieee;
2376 u32 threshold_reply_count;
2378 atomic_t fw_outstanding;
2379 atomic_t ldio_outstanding;
2380 atomic_t fw_reset_no_pci_access;
2381 atomic64_t total_io_count;
2382 atomic64_t high_iops_outstanding;
2384 struct megasas_instance_template *instancet;
2385 struct tasklet_struct isr_tasklet;
2386 struct work_struct work_init;
2387 struct delayed_work fw_fault_work;
2388 struct workqueue_struct *fw_fault_work_q;
2389 char fault_handler_work_q_name[48];
2395 u8 disableOnlineCtrlReset;
2396 u8 UnevenSpanSupport;
2399 u8 pd_list_not_supported;
2400 u16 fw_supported_vd_count;
2401 u16 fw_supported_pd_count;
2403 u16 drv_supported_vd_count;
2404 u16 drv_supported_pd_count;
2406 atomic_t adprecovery;
2407 unsigned long last_time;
2411 struct list_head internal_reset_pending_q;
2413 /* Ptr to hba specific information */
2415 unsigned int msix_vectors;
2416 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2419 struct megasas_cmd *map_update_cmd;
2420 struct megasas_cmd *jbod_seq_cmd;
2423 struct mutex reset_mutex;
2424 struct timer_list sriov_heartbeat_timer;
2425 char skip_heartbeat_timer_del;
2428 char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2431 u16 throttlequeuedepth;
2433 u16 max_chain_frame_sz;
2437 bool fw_sync_cache_support;
2440 u16 max_raid_mapsize;
2441 /* preffered count to send as LDIO irrspective of FP capable.*/
2442 u8 r1_ldio_hint_default;
2445 bool consistent_mask_64bit;
2446 bool support_nvme_passthru;
2447 bool enable_sdev_max_qd;
2450 u8 snapdump_wait_time;
2451 #ifdef CONFIG_DEBUG_FS
2452 struct dentry *debugfs_root;
2453 struct dentry *raidmap_dump;
2455 u8 enable_fw_dev_list;
2456 bool atomic_desc_support;
2457 bool support_seqnum_jbod_fp;
2458 bool support_pci_lane_margining;
2459 u8 low_latency_index_start;
2463 struct MR_LD_VF_MAP {
2465 union MR_LD_REF ref;
2471 struct MR_LD_VF_AFFILIATION {
2477 struct MR_LD_VF_MAP map[1];
2480 /* Plasma 1.11 FW backward compatibility structures */
2481 #define IOV_111_OFFSET 0x7CE
2482 #define MAX_VIRTUAL_FUNCTIONS 8
2483 #define MR_LD_ACCESS_HIDDEN 15
2492 struct MR_LD_VF_MAP_111 {
2495 u8 policy[MAX_VIRTUAL_FUNCTIONS];
2498 struct MR_LD_VF_AFFILIATION_111 {
2503 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2506 struct MR_CTRL_HB_HOST_MEM {
2508 u32 fwCounter; /* Firmware heart beat counter */
2510 u32 debugmode:1; /* 1=Firmware is in debug mode.
2511 Heart beat will not be updated. */
2515 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2516 u32 reserved_driver[7];
2522 MEGASAS_HBA_OPERATIONAL = 0,
2523 MEGASAS_ADPRESET_SM_INFAULT = 1,
2524 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
2525 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
2526 MEGASAS_HW_CRITICAL_ERROR = 4,
2527 MEGASAS_ADPRESET_SM_POLLING = 5,
2528 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
2531 struct megasas_instance_template {
2532 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2533 u32, struct megasas_register_set __iomem *);
2535 void (*enable_intr)(struct megasas_instance *);
2536 void (*disable_intr)(struct megasas_instance *);
2538 int (*clear_intr)(struct megasas_instance *);
2540 u32 (*read_fw_status_reg)(struct megasas_instance *);
2541 int (*adp_reset)(struct megasas_instance *, \
2542 struct megasas_register_set __iomem *);
2543 int (*check_reset)(struct megasas_instance *, \
2544 struct megasas_register_set __iomem *);
2545 irqreturn_t (*service_isr)(int irq, void *devp);
2546 void (*tasklet)(unsigned long);
2547 u32 (*init_adapter)(struct megasas_instance *);
2548 u32 (*build_and_issue_cmd) (struct megasas_instance *,
2549 struct scsi_cmnd *);
2550 void (*issue_dcmd)(struct megasas_instance *instance,
2551 struct megasas_cmd *cmd);
2554 #define MEGASAS_IS_LOGICAL(sdev) \
2555 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2557 #define MEGASAS_IS_LUN_VALID(sdev) \
2558 (((sdev)->lun == 0) ? 1 : 0)
2560 #define MEGASAS_DEV_INDEX(scp) \
2561 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2564 #define MEGASAS_PD_INDEX(scp) \
2565 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2568 struct megasas_cmd {
2570 union megasas_frame *frame;
2571 dma_addr_t frame_phys_addr;
2573 dma_addr_t sense_phys_addr;
2579 u8 retry_for_fw_reset;
2582 struct list_head list;
2583 struct scsi_cmnd *scmd;
2586 struct megasas_instance *instance;
2596 #define MAX_MGMT_ADAPTERS 1024
2597 #define MAX_IOCTL_SGE 16
2599 struct megasas_iocpacket {
2609 struct megasas_header hdr;
2612 struct iovec sgl[MAX_IOCTL_SGE];
2614 } __attribute__ ((packed));
2616 struct megasas_aen {
2620 u32 class_locale_word;
2621 } __attribute__ ((packed));
2623 #ifdef CONFIG_COMPAT
2624 struct compat_megasas_iocpacket {
2633 struct megasas_header hdr;
2635 struct compat_iovec sgl[MAX_IOCTL_SGE];
2636 } __attribute__ ((packed));
2638 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2641 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2642 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2644 struct megasas_mgmt_info {
2647 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2651 enum MEGASAS_OCR_CAUSE {
2653 SCSIIO_TIMEOUT_OCR = 1,
2654 MFI_IO_TIMEOUT_OCR = 2,
2657 enum DCMD_RETURN_STATUS {
2658 DCMD_SUCCESS = 0x00,
2659 DCMD_TIMEOUT = 0x01,
2666 MR_BuildRaidContext(struct megasas_instance *instance,
2667 struct IO_REQUEST_INFO *io_info,
2668 struct RAID_CONTEXT *pRAID_Context,
2669 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2670 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2671 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2672 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2673 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2674 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2675 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2677 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2678 struct LD_LOAD_BALANCE_INFO *lbInfo,
2679 struct IO_REQUEST_INFO *in_info,
2680 struct MR_DRV_RAID_MAP_ALL *drv_map);
2681 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2682 struct LD_LOAD_BALANCE_INFO *lbInfo);
2683 int megasas_get_ctrl_info(struct megasas_instance *instance);
2686 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2687 void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2688 bool is_target_prop);
2689 int megasas_get_target_prop(struct megasas_instance *instance,
2690 struct scsi_device *sdev);
2691 void megasas_get_snapdump_properties(struct megasas_instance *instance);
2693 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2694 u8 crash_buf_state);
2695 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2697 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2698 struct megasas_cmd_fusion *cmd);
2699 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2700 struct megasas_cmd *cmd, int timeout);
2701 void __megasas_return_cmd(struct megasas_instance *instance,
2702 struct megasas_cmd *cmd);
2704 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2705 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2706 int megasas_cmd_type(struct scsi_cmnd *cmd);
2707 void megasas_setup_jbod_map(struct megasas_instance *instance);
2709 void megasas_update_sdev_properties(struct scsi_device *sdev);
2710 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2711 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2712 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2713 u32 mega_mod64(u64 dividend, u32 divisor);
2714 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2715 void megasas_free_fusion_context(struct megasas_instance *instance);
2716 int megasas_fusion_start_watchdog(struct megasas_instance *instance);
2717 void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
2719 void megasas_set_dma_settings(struct megasas_instance *instance,
2720 struct megasas_dcmd_frame *dcmd,
2721 dma_addr_t dma_addr, u32 dma_len);
2722 int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance,
2725 int megasas_irqpoll(struct irq_poll *irqpoll, int budget);
2726 void megasas_dump_fusion_io(struct scsi_cmnd *scmd);
2727 u32 megasas_readl(struct megasas_instance *instance,
2728 const volatile void __iomem *addr);
2729 struct megasas_cmd *megasas_get_cmd(struct megasas_instance *instance);
2730 void megasas_return_cmd(struct megasas_instance *instance,
2731 struct megasas_cmd *cmd);
2732 int megasas_issue_polled(struct megasas_instance *instance,
2733 struct megasas_cmd *cmd);
2734 void megaraid_sas_kill_hba(struct megasas_instance *instance);
2735 void megasas_check_and_restore_queue_depth(struct megasas_instance *instance);
2736 void megasas_start_timer(struct megasas_instance *instance);
2737 int megasas_sriov_start_heartbeat(struct megasas_instance *instance,
2739 int megasas_alloc_cmds(struct megasas_instance *instance);
2740 void megasas_free_cmds(struct megasas_instance *instance);
2742 void megasas_init_debugfs(void);
2743 void megasas_exit_debugfs(void);
2744 void megasas_setup_debugfs(struct megasas_instance *instance);
2745 void megasas_destroy_debugfs(struct megasas_instance *instance);
2747 #endif /*LSI_MEGARAID_SAS_H */