drivers/scsi/megaraid/megaraid_sas.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Linux MegaRAID driver for SAS based RAID controllers
   4  *
   5  *  Copyright (c) 2003-2013  LSI Corporation
   6  *  Copyright (c) 2013-2016  Avago Technologies
   7  *  Copyright (c) 2016-2018  Broadcom Inc.
   8  *
   9  *  FILE: megaraid_sas.h
  10  *
  11  *  Authors: Broadcom Inc.
  12  *           Kashyap Desai <kashyap.desai@broadcom.com>
  13  *           Sumit Saxena <sumit.saxena@broadcom.com>
  14  *
  15  *  Send feedback to: megaraidlinux.pdl@broadcom.com
  16  */
  17
  18 #ifndef LSI_MEGARAID_SAS_H
  19 #define LSI_MEGARAID_SAS_H
  20
  21 #include <scsi/scsi_cmnd.h>
  22
  23 /*
  24  * MegaRAID SAS Driver meta data
  25  */
  26 #define MEGASAS_VERSION                         "07.727.03.00-rc1"
  27 #define MEGASAS_RELDATE                         "Oct 03, 2023"
  28
  29 #define MEGASAS_MSIX_NAME_LEN                   32
  30
  31 /*
  32  * Device IDs
  33  */
  34 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  35 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  36 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  37 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  38 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  39 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  40 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  41 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  42 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  43 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  44 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  45 #define PCI_DEVICE_ID_LSI_INTRUDER              0x00ce
  46 #define PCI_DEVICE_ID_LSI_INTRUDER_24           0x00cf
  47 #define PCI_DEVICE_ID_LSI_CUTLASS_52            0x0052
  48 #define PCI_DEVICE_ID_LSI_CUTLASS_53            0x0053
  49 #define PCI_DEVICE_ID_LSI_VENTURA                   0x0014
  50 #define PCI_DEVICE_ID_LSI_CRUSADER                  0x0015
  51 #define PCI_DEVICE_ID_LSI_HARPOON                   0x0016
  52 #define PCI_DEVICE_ID_LSI_TOMCAT                    0x0017
  53 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT         0x001B
  54 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT        0x001C
  55 #define PCI_DEVICE_ID_LSI_AERO_10E1             0x10e1
  56 #define PCI_DEVICE_ID_LSI_AERO_10E2             0x10e2
  57 #define PCI_DEVICE_ID_LSI_AERO_10E5             0x10e5
  58 #define PCI_DEVICE_ID_LSI_AERO_10E6             0x10e6
  59 #define PCI_DEVICE_ID_LSI_AERO_10E0             0x10e0
  60 #define PCI_DEVICE_ID_LSI_AERO_10E3             0x10e3
  61 #define PCI_DEVICE_ID_LSI_AERO_10E4             0x10e4
  62 #define PCI_DEVICE_ID_LSI_AERO_10E7             0x10e7
  63
  64 /*
  65  * Intel HBA SSDIDs
  66  */
  67 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  68 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  69 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  70 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  71 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  72 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  73 #define MEGARAID_INTEL_RMS3BC160_SSDID          0x352B
  74
  75 /*
  76  * Intruder HBA SSDIDs
  77  */
  78 #define MEGARAID_INTRUDER_SSDID1                0x9371
  79 #define MEGARAID_INTRUDER_SSDID2                0x9390
  80 #define MEGARAID_INTRUDER_SSDID3                0x9370
  81
  82 /*
  83  * Intel HBA branding
  84  */
  85 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  86         "Intel(R) RAID Controller RS3DC080"
  87 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  88         "Intel(R) RAID Controller RS3DC040"
  89 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  90         "Intel(R) RAID Controller RS3SC008"
  91 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  92         "Intel(R) RAID Controller RS3MC044"
  93 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  94         "Intel(R) RAID Controller RS3WC080"
  95 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
  96         "Intel(R) RAID Controller RS3WC040"
  97 #define MEGARAID_INTEL_RMS3BC160_BRANDING       \
  98         "Intel(R) Integrated RAID Module RMS3BC160"
  99
 100 /*
 101  * =====================================
 102  * MegaRAID SAS MFI firmware definitions
 103  * =====================================
 104  */
 105
 106 /*
 107  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
 108  * protocol between the software and firmware. Commands are issued using
 109  * "message frames"
 110  */
 111
 112 /*
 113  * FW posts its state in upper 4 bits of outbound_msg_0 register
 114  */
 115 #define MFI_STATE_MASK                          0xF0000000
 116 #define MFI_STATE_UNDEFINED                     0x00000000
 117 #define MFI_STATE_BB_INIT                       0x10000000
 118 #define MFI_STATE_FW_INIT                       0x40000000
 119 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 120 #define MFI_STATE_FW_INIT_2                     0x70000000
 121 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 122 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 123 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 124 #define MFI_STATE_READY                         0xB0000000
 125 #define MFI_STATE_OPERATIONAL                   0xC0000000
 126 #define MFI_STATE_FAULT                         0xF0000000
 127 #define MFI_STATE_FORCE_OCR                     0x00000080
 128 #define MFI_STATE_DMADONE                       0x00000008
 129 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 130 #define MFI_RESET_REQUIRED                      0x00000001
 131 #define MFI_RESET_ADAPTER                       0x00000002
 132 #define MEGAMFI_FRAME_SIZE                      64
 133
 134 #define MFI_STATE_FAULT_CODE                    0x0FFF0000
 135 #define MFI_STATE_FAULT_SUBCODE                 0x0000FF00
 136 /*
 137  * During FW init, clear pending cmds & reset state using inbound_msg_0
 138  *
 139  * ABORT        : Abort all pending cmds
 140  * READY        : Move from OPERATIONAL to READY state; discard queue info
 141  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 142  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 143  * HOTPLUG      : Resume from Hotplug
 144  * MFI_STOP_ADP : Send signal to FW to stop processing
 145  * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
 146  */
 147 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 148 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 149 #define DIAG_WRITE_ENABLE                       (0x00000080)
 150 #define DIAG_RESET_ADAPTER                      (0x00000004)
 151
 152 #define MFI_ADP_RESET                           0x00000040
 153 #define MFI_INIT_ABORT                          0x00000001
 154 #define MFI_INIT_READY                          0x00000002
 155 #define MFI_INIT_MFIMODE                        0x00000004
 156 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 157 #define MFI_INIT_HOTPLUG                        0x00000010
 158 #define MFI_STOP_ADP                            0x00000020
 159 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 160                                                 MFI_INIT_MFIMODE| \
 161                                                 MFI_INIT_ABORT
 162 #define MFI_ADP_TRIGGER_SNAP_DUMP               0x00000100
 163 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 164
 165 /*
 166  * MFI frame flags
 167  */
 168 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 169 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 170 #define MFI_FRAME_SGL32                         0x0000
 171 #define MFI_FRAME_SGL64                         0x0002
 172 #define MFI_FRAME_SENSE32                       0x0000
 173 #define MFI_FRAME_SENSE64                       0x0004
 174 #define MFI_FRAME_DIR_NONE                      0x0000
 175 #define MFI_FRAME_DIR_WRITE                     0x0008
 176 #define MFI_FRAME_DIR_READ                      0x0010
 177 #define MFI_FRAME_DIR_BOTH                      0x0018
 178 #define MFI_FRAME_IEEE                          0x0020
 179
 180 /* Driver internal */
 181 #define DRV_DCMD_POLLED_MODE            0x1
 182 #define DRV_DCMD_SKIP_REFIRE            0x2
 183
 184 /*
 185  * Definition for cmd_status
 186  */
 187 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 188
 189 /*
 190  * MFI command opcodes
 191  */
 192 enum MFI_CMD_OP {
 193         MFI_CMD_INIT            = 0x0,
 194         MFI_CMD_LD_READ         = 0x1,
 195         MFI_CMD_LD_WRITE        = 0x2,
 196         MFI_CMD_LD_SCSI_IO      = 0x3,
 197         MFI_CMD_PD_SCSI_IO      = 0x4,
 198         MFI_CMD_DCMD            = 0x5,
 199         MFI_CMD_ABORT           = 0x6,
 200         MFI_CMD_SMP             = 0x7,
 201         MFI_CMD_STP             = 0x8,
 202         MFI_CMD_NVME            = 0x9,
 203         MFI_CMD_TOOLBOX         = 0xa,
 204         MFI_CMD_OP_COUNT,
 205         MFI_CMD_INVALID         = 0xff
 206 };
 207
 208 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 209 #define MR_DCMD_LD_GET_LIST                     0x03010000
 210 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 211
 212 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 213 #define MR_FLUSH_CTRL_CACHE                     0x01
 214 #define MR_FLUSH_DISK_CACHE                     0x02
 215
 216 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 217 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 218 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 219
 220 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 221 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 222 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 223 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 224
 225 #define MR_DCMD_CLUSTER                         0x08000000
 226 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 227 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 228 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 229
 230 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 231 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 232 #define MR_DCMD_PD_GET_INFO                     0x02020000
 233
 234 /*
 235  * Global functions
 236  */
 237 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
 238
 239
 240 /*
 241  * MFI command completion codes
 242  */
 243 enum MFI_STAT {
 244         MFI_STAT_OK = 0x00,
 245         MFI_STAT_INVALID_CMD = 0x01,
 246         MFI_STAT_INVALID_DCMD = 0x02,
 247         MFI_STAT_INVALID_PARAMETER = 0x03,
 248         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 249         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 250         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 251         MFI_STAT_APP_IN_USE = 0x07,
 252         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 253         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 254         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 255         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 256         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 257         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 258         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 259         MFI_STAT_FLASH_BUSY = 0x0f,
 260         MFI_STAT_FLASH_ERROR = 0x10,
 261         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 262         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 263         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 264         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 265         MFI_STAT_FLUSH_FAILED = 0x15,
 266         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 267         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 268         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 269         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 270         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 271         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 272         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 273         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 274         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 275         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 276         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 277         MFI_STAT_MFC_HW_ERROR = 0x21,
 278         MFI_STAT_NO_HW_PRESENT = 0x22,
 279         MFI_STAT_NOT_FOUND = 0x23,
 280         MFI_STAT_NOT_IN_ENCL = 0x24,
 281         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 282         MFI_STAT_PD_TYPE_WRONG = 0x26,
 283         MFI_STAT_PR_DISABLED = 0x27,
 284         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 285         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 286         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 287         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 288         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 289         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 290         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 291         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 292         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 293         MFI_STAT_TIME_NOT_SET = 0x31,
 294         MFI_STAT_WRONG_STATE = 0x32,
 295         MFI_STAT_LD_OFFLINE = 0x33,
 296         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 297         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 298         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 299         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 300         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 301         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 302
 303         MFI_STAT_INVALID_STATUS = 0xFF
 304 };
 305
 306 enum mfi_evt_class {
 307         MFI_EVT_CLASS_DEBUG =           -2,
 308         MFI_EVT_CLASS_PROGRESS =        -1,
 309         MFI_EVT_CLASS_INFO =            0,
 310         MFI_EVT_CLASS_WARNING =         1,
 311         MFI_EVT_CLASS_CRITICAL =        2,
 312         MFI_EVT_CLASS_FATAL =           3,
 313         MFI_EVT_CLASS_DEAD =            4
 314 };
 315
 316 /*
 317  * Crash dump related defines
 318  */
 319 #define MAX_CRASH_DUMP_SIZE 512
 320 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 321
 322 enum MR_FW_CRASH_DUMP_STATE {
 323         UNAVAILABLE = 0,
 324         AVAILABLE = 1,
 325         COPYING = 2,
 326         COPIED = 3,
 327         COPY_ERROR = 4,
 328 };
 329
 330 enum _MR_CRASH_BUF_STATUS {
 331         MR_CRASH_BUF_TURN_OFF = 0,
 332         MR_CRASH_BUF_TURN_ON = 1,
 333 };
 334
 335 /*
 336  * Number of mailbox bytes in DCMD message frame
 337  */
 338 #define MFI_MBOX_SIZE                           12
 339
 340 enum MR_EVT_CLASS {
 341
 342         MR_EVT_CLASS_DEBUG = -2,
 343         MR_EVT_CLASS_PROGRESS = -1,
 344         MR_EVT_CLASS_INFO = 0,
 345         MR_EVT_CLASS_WARNING = 1,
 346         MR_EVT_CLASS_CRITICAL = 2,
 347         MR_EVT_CLASS_FATAL = 3,
 348         MR_EVT_CLASS_DEAD = 4,
 349
 350 };
 351
 352 enum MR_EVT_LOCALE {
 353
 354         MR_EVT_LOCALE_LD = 0x0001,
 355         MR_EVT_LOCALE_PD = 0x0002,
 356         MR_EVT_LOCALE_ENCL = 0x0004,
 357         MR_EVT_LOCALE_BBU = 0x0008,
 358         MR_EVT_LOCALE_SAS = 0x0010,
 359         MR_EVT_LOCALE_CTRL = 0x0020,
 360         MR_EVT_LOCALE_CONFIG = 0x0040,
 361         MR_EVT_LOCALE_CLUSTER = 0x0080,
 362         MR_EVT_LOCALE_ALL = 0xffff,
 363
 364 };
 365
 366 enum MR_EVT_ARGS {
 367
 368         MR_EVT_ARGS_NONE,
 369         MR_EVT_ARGS_CDB_SENSE,
 370         MR_EVT_ARGS_LD,
 371         MR_EVT_ARGS_LD_COUNT,
 372         MR_EVT_ARGS_LD_LBA,
 373         MR_EVT_ARGS_LD_OWNER,
 374         MR_EVT_ARGS_LD_LBA_PD_LBA,
 375         MR_EVT_ARGS_LD_PROG,
 376         MR_EVT_ARGS_LD_STATE,
 377         MR_EVT_ARGS_LD_STRIP,
 378         MR_EVT_ARGS_PD,
 379         MR_EVT_ARGS_PD_ERR,
 380         MR_EVT_ARGS_PD_LBA,
 381         MR_EVT_ARGS_PD_LBA_LD,
 382         MR_EVT_ARGS_PD_PROG,
 383         MR_EVT_ARGS_PD_STATE,
 384         MR_EVT_ARGS_PCI,
 385         MR_EVT_ARGS_RATE,
 386         MR_EVT_ARGS_STR,
 387         MR_EVT_ARGS_TIME,
 388         MR_EVT_ARGS_ECC,
 389         MR_EVT_ARGS_LD_PROP,
 390         MR_EVT_ARGS_PD_SPARE,
 391         MR_EVT_ARGS_PD_INDEX,
 392         MR_EVT_ARGS_DIAG_PASS,
 393         MR_EVT_ARGS_DIAG_FAIL,
 394         MR_EVT_ARGS_PD_LBA_LBA,
 395         MR_EVT_ARGS_PORT_PHY,
 396         MR_EVT_ARGS_PD_MISSING,
 397         MR_EVT_ARGS_PD_ADDRESS,
 398         MR_EVT_ARGS_BITMAP,
 399         MR_EVT_ARGS_CONNECTOR,
 400         MR_EVT_ARGS_PD_PD,
 401         MR_EVT_ARGS_PD_FRU,
 402         MR_EVT_ARGS_PD_PATHINFO,
 403         MR_EVT_ARGS_PD_POWER_STATE,
 404         MR_EVT_ARGS_GENERIC,
 405 };
 406
 407
 408 #define SGE_BUFFER_SIZE 4096
 409 #define MEGASAS_CLUSTER_ID_SIZE 16
 410 /*
 411  * define constants for device list query options
 412  */
 413 enum MR_PD_QUERY_TYPE {
 414         MR_PD_QUERY_TYPE_ALL                = 0,
 415         MR_PD_QUERY_TYPE_STATE              = 1,
 416         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 417         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 418         MR_PD_QUERY_TYPE_SPEED              = 4,
 419         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 420 };
 421
 422 enum MR_LD_QUERY_TYPE {
 423         MR_LD_QUERY_TYPE_ALL             = 0,
 424         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 425         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 426         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 427         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 428 };
 429
 430
 431 #define MR_EVT_CFG_CLEARED                              0x0004
 432 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 433 #define MR_EVT_PD_INSERTED                              0x005b
 434 #define MR_EVT_PD_REMOVED                               0x0070
 435 #define MR_EVT_LD_CREATED                               0x008a
 436 #define MR_EVT_LD_DELETED                               0x008b
 437 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 438 #define MR_EVT_LD_OFFLINE                               0x00fc
 439 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 440 #define MR_EVT_CTRL_PROP_CHANGED                        0x012f
 441
 442 enum MR_PD_STATE {
 443         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 444         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 445         MR_PD_STATE_HOT_SPARE           = 0x02,
 446         MR_PD_STATE_OFFLINE             = 0x10,
 447         MR_PD_STATE_FAILED              = 0x11,
 448         MR_PD_STATE_REBUILD             = 0x14,
 449         MR_PD_STATE_ONLINE              = 0x18,
 450         MR_PD_STATE_COPYBACK            = 0x20,
 451         MR_PD_STATE_SYSTEM              = 0x40,
 452  };
 453
 454 union MR_PD_REF {
 455         struct {
 456                 u16      deviceId;
 457                 u16      seqNum;
 458         } mrPdRef;
 459         u32      ref;
 460 };
 461
 462 /*
 463  * define the DDF Type bit structure
 464  */
 465 union MR_PD_DDF_TYPE {
 466          struct {
 467                 union {
 468                         struct {
 469 #ifndef __BIG_ENDIAN_BITFIELD
 470                                  u16     forcedPDGUID:1;
 471                                  u16     inVD:1;
 472                                  u16     isGlobalSpare:1;
 473                                  u16     isSpare:1;
 474                                  u16     isForeign:1;
 475                                  u16     reserved:7;
 476                                  u16     intf:4;
 477 #else
 478                                  u16     intf:4;
 479                                  u16     reserved:7;
 480                                  u16     isForeign:1;
 481                                  u16     isSpare:1;
 482                                  u16     isGlobalSpare:1;
 483                                  u16     inVD:1;
 484                                  u16     forcedPDGUID:1;
 485 #endif
 486                          } pdType;
 487                          u16     type;
 488                  };
 489                  u16     reserved;
 490          } ddf;
 491          struct {
 492                  u32    reserved;
 493          } nonDisk;
 494          u32     type;
 495 } __packed;
 496
 497 /*
 498  * defines the progress structure
 499  */
 500 union MR_PROGRESS {
 501         struct  {
 502                 u16 progress;
 503                 union {
 504                         u16 elapsedSecs;
 505                         u16 elapsedSecsForLastPercent;
 506                 };
 507         } mrProgress;
 508         u32 w;
 509 } __packed;
 510
 511 /*
 512  * defines the physical drive progress structure
 513  */
 514 struct MR_PD_PROGRESS {
 515         struct {
 516 #ifndef __BIG_ENDIAN_BITFIELD
 517                 u32     rbld:1;
 518                 u32     patrol:1;
 519                 u32     clear:1;
 520                 u32     copyBack:1;
 521                 u32     erase:1;
 522                 u32     locate:1;
 523                 u32     reserved:26;
 524 #else
 525                 u32     reserved:26;
 526                 u32     locate:1;
 527                 u32     erase:1;
 528                 u32     copyBack:1;
 529                 u32     clear:1;
 530                 u32     patrol:1;
 531                 u32     rbld:1;
 532 #endif
 533         } active;
 534         union MR_PROGRESS     rbld;
 535         union MR_PROGRESS     patrol;
 536         union {
 537                 union MR_PROGRESS     clear;
 538                 union MR_PROGRESS     erase;
 539         };
 540
 541         struct {
 542 #ifndef __BIG_ENDIAN_BITFIELD
 543                 u32     rbld:1;
 544                 u32     patrol:1;
 545                 u32     clear:1;
 546                 u32     copyBack:1;
 547                 u32     erase:1;
 548                 u32     reserved:27;
 549 #else
 550                 u32     reserved:27;
 551                 u32     erase:1;
 552                 u32     copyBack:1;
 553                 u32     clear:1;
 554                 u32     patrol:1;
 555                 u32     rbld:1;
 556 #endif
 557         } pause;
 558
 559         union MR_PROGRESS     reserved[3];
 560 } __packed;
 561
 562 struct  MR_PD_INFO {
 563         union MR_PD_REF ref;
 564         u8 inquiryData[96];
 565         u8 vpdPage83[64];
 566         u8 notSupported;
 567         u8 scsiDevType;
 568
 569         union {
 570                 u8 connectedPortBitmap;
 571                 u8 connectedPortNumbers;
 572         };
 573
 574         u8 deviceSpeed;
 575         u32 mediaErrCount;
 576         u32 otherErrCount;
 577         u32 predFailCount;
 578         u32 lastPredFailEventSeqNum;
 579
 580         u16 fwState;
 581         u8 disabledForRemoval;
 582         u8 linkSpeed;
 583         union MR_PD_DDF_TYPE state;
 584
 585         struct {
 586                 u8 count;
 587 #ifndef __BIG_ENDIAN_BITFIELD
 588                 u8 isPathBroken:4;
 589                 u8 reserved3:3;
 590                 u8 widePortCapable:1;
 591 #else
 592                 u8 widePortCapable:1;
 593                 u8 reserved3:3;
 594                 u8 isPathBroken:4;
 595 #endif
 596
 597                 u8 connectorIndex[2];
 598                 u8 reserved[4];
 599                 u64 sasAddr[2];
 600                 u8 reserved2[16];
 601         } pathInfo;
 602
 603         u64 rawSize;
 604         u64 nonCoercedSize;
 605         u64 coercedSize;
 606         u16 enclDeviceId;
 607         u8 enclIndex;
 608
 609         union {
 610                 u8 slotNumber;
 611                 u8 enclConnectorIndex;
 612         };
 613
 614         struct MR_PD_PROGRESS progInfo;
 615         u8 badBlockTableFull;
 616         u8 unusableInCurrentConfig;
 617         u8 vpdPage83Ext[64];
 618         u8 powerState;
 619         u8 enclPosition;
 620         u32 allowedOps;
 621         u16 copyBackPartnerId;
 622         u16 enclPartnerDeviceId;
 623         struct {
 624 #ifndef __BIG_ENDIAN_BITFIELD
 625                 u16 fdeCapable:1;
 626                 u16 fdeEnabled:1;
 627                 u16 secured:1;
 628                 u16 locked:1;
 629                 u16 foreign:1;
 630                 u16 needsEKM:1;
 631                 u16 reserved:10;
 632 #else
 633                 u16 reserved:10;
 634                 u16 needsEKM:1;
 635                 u16 foreign:1;
 636                 u16 locked:1;
 637                 u16 secured:1;
 638                 u16 fdeEnabled:1;
 639                 u16 fdeCapable:1;
 640 #endif
 641         } security;
 642         u8 mediaType;
 643         u8 notCertified;
 644         u8 bridgeVendor[8];
 645         u8 bridgeProductIdentification[16];
 646         u8 bridgeProductRevisionLevel[4];
 647         u8 satBridgeExists;
 648
 649         u8 interfaceType;
 650         u8 temperature;
 651         u8 emulatedBlockSize;
 652         u16 userDataBlockSize;
 653         u16 reserved2;
 654
 655         struct {
 656 #ifndef __BIG_ENDIAN_BITFIELD
 657                 u32 piType:3;
 658                 u32 piFormatted:1;
 659                 u32 piEligible:1;
 660                 u32 NCQ:1;
 661                 u32 WCE:1;
 662                 u32 commissionedSpare:1;
 663                 u32 emergencySpare:1;
 664                 u32 ineligibleForSSCD:1;
 665                 u32 ineligibleForLd:1;
 666                 u32 useSSEraseType:1;
 667                 u32 wceUnchanged:1;
 668                 u32 supportScsiUnmap:1;
 669                 u32 reserved:18;
 670 #else
 671                 u32 reserved:18;
 672                 u32 supportScsiUnmap:1;
 673                 u32 wceUnchanged:1;
 674                 u32 useSSEraseType:1;
 675                 u32 ineligibleForLd:1;
 676                 u32 ineligibleForSSCD:1;
 677                 u32 emergencySpare:1;
 678                 u32 commissionedSpare:1;
 679                 u32 WCE:1;
 680                 u32 NCQ:1;
 681                 u32 piEligible:1;
 682                 u32 piFormatted:1;
 683                 u32 piType:3;
 684 #endif
 685         } properties;
 686
 687         u64 shieldDiagCompletionTime;
 688         u8 shieldCounter;
 689
 690         u8 linkSpeedOther;
 691         u8 reserved4[2];
 692
 693         struct {
 694 #ifndef __BIG_ENDIAN_BITFIELD
 695                 u32 bbmErrCountSupported:1;
 696                 u32 bbmErrCount:31;
 697 #else
 698                 u32 bbmErrCount:31;
 699                 u32 bbmErrCountSupported:1;
 700 #endif
 701         } bbmErr;
 702
 703         u8 reserved1[512-428];
 704 } __packed;
 705
 706 /*
 707  * Definition of structure used to expose attributes of VD or JBOD
 708  * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
 709  * is fired by driver)
 710  */
 711 struct MR_TARGET_PROPERTIES {
 712         u32    max_io_size_kb;
 713         u32    device_qdepth;
 714         u32    sector_size;
 715         u8     reset_tmo;
 716         u8     reserved[499];
 717 } __packed;
 718
 719  /*
 720  * defines the physical drive address structure
 721  */
 722 struct MR_PD_ADDRESS {
 723         __le16  deviceId;
 724         u16     enclDeviceId;
 725
 726         union {
 727                 struct {
 728                         u8  enclIndex;
 729                         u8  slotNumber;
 730                 } mrPdAddress;
 731                 struct {
 732                         u8  enclPosition;
 733                         u8  enclConnectorIndex;
 734                 } mrEnclAddress;
 735         };
 736         u8      scsiDevType;
 737         union {
 738                 u8      connectedPortBitmap;
 739                 u8      connectedPortNumbers;
 740         };
 741         u64     sasAddr[2];
 742 } __packed;
 743
 744 /*
 745  * defines the physical drive list structure
 746  */
 747 struct MR_PD_LIST {
 748         __le32          size;
 749         __le32          count;
 750         struct MR_PD_ADDRESS   addr[1];
 751 } __packed;
 752
 753 struct megasas_pd_list {
 754         u16             tid;
 755         u8             driveType;
 756         u8             driveState;
 757 } __packed;
 758
 759  /*
 760  * defines the logical drive reference structure
 761  */
 762 union  MR_LD_REF {
 763         struct {
 764                 u8      targetId;
 765                 u8      reserved;
 766                 __le16     seqNum;
 767         };
 768         __le32     ref;
 769 } __packed;
 770
 771 /*
 772  * defines the logical drive list structure
 773  */
 774 struct MR_LD_LIST {
 775         __le32     ldCount;
 776         __le32     reserved;
 777         struct {
 778                 union MR_LD_REF   ref;
 779                 u8          state;
 780                 u8          reserved[3];
 781                 __le64          size;
 782         } ldList[MAX_LOGICAL_DRIVES_EXT];
 783 } __packed;
 784
 785 struct MR_LD_TARGETID_LIST {
 786         __le32  size;
 787         __le32  count;
 788         u8      pad[3];
 789         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 790 };
 791
 792 struct MR_HOST_DEVICE_LIST_ENTRY {
 793         struct {
 794                 union {
 795                         struct {
 796 #if defined(__BIG_ENDIAN_BITFIELD)
 797                                 u8 reserved:7;
 798                                 u8 is_sys_pd:1;
 799 #else
 800                                 u8 is_sys_pd:1;
 801                                 u8 reserved:7;
 802 #endif
 803                         } bits;
 804                         u8 byte;
 805                 } u;
 806         } flags;
 807         u8 scsi_type;
 808         __le16 target_id;
 809         u8 reserved[4];
 810         __le64 sas_addr[2];
 811 } __packed;
 812
 813 struct MR_HOST_DEVICE_LIST {
 814         __le32                  size;
 815         __le32                  count;
 816         __le32                  reserved[2];
 817         struct MR_HOST_DEVICE_LIST_ENTRY        host_device_list[1];
 818 } __packed;
 819
 820 #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) +              \
 821                               (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) *      \
 822                               (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
 823
 824
 825 /*
 826  * SAS controller properties
 827  */
 828 struct megasas_ctrl_prop {
 829
 830         u16 seq_num;
 831         u16 pred_fail_poll_interval;
 832         u16 intr_throttle_count;
 833         u16 intr_throttle_timeouts;
 834         u8 rebuild_rate;
 835         u8 patrol_read_rate;
 836         u8 bgi_rate;
 837         u8 cc_rate;
 838         u8 recon_rate;
 839         u8 cache_flush_interval;
 840         u8 spinup_drv_count;
 841         u8 spinup_delay;
 842         u8 cluster_enable;
 843         u8 coercion_mode;
 844         u8 alarm_enable;
 845         u8 disable_auto_rebuild;
 846         u8 disable_battery_warn;
 847         u8 ecc_bucket_size;
 848         u16 ecc_bucket_leak_rate;
 849         u8 restore_hotspare_on_insertion;
 850         u8 expose_encl_devices;
 851         u8 maintainPdFailHistory;
 852         u8 disallowHostRequestReordering;
 853         u8 abortCCOnError;
 854         u8 loadBalanceMode;
 855         u8 disableAutoDetectBackplane;
 856
 857         u8 snapVDSpace;
 858
 859         /*
 860         * Add properties that can be controlled by
 861         * a bit in the following structure.
 862         */
 863         struct {
 864 #if   defined(__BIG_ENDIAN_BITFIELD)
 865                 u32     reserved:18;
 866                 u32     enableJBOD:1;
 867                 u32     disableSpinDownHS:1;
 868                 u32     allowBootWithPinnedCache:1;
 869                 u32     disableOnlineCtrlReset:1;
 870                 u32     enableSecretKeyControl:1;
 871                 u32     autoEnhancedImport:1;
 872                 u32     enableSpinDownUnconfigured:1;
 873                 u32     SSDPatrolReadEnabled:1;
 874                 u32     SSDSMARTerEnabled:1;
 875                 u32     disableNCQ:1;
 876                 u32     useFdeOnly:1;
 877                 u32     prCorrectUnconfiguredAreas:1;
 878                 u32     SMARTerEnabled:1;
 879                 u32     copyBackDisabled:1;
 880 #else
 881                 u32     copyBackDisabled:1;
 882                 u32     SMARTerEnabled:1;
 883                 u32     prCorrectUnconfiguredAreas:1;
 884                 u32     useFdeOnly:1;
 885                 u32     disableNCQ:1;
 886                 u32     SSDSMARTerEnabled:1;
 887                 u32     SSDPatrolReadEnabled:1;
 888                 u32     enableSpinDownUnconfigured:1;
 889                 u32     autoEnhancedImport:1;
 890                 u32     enableSecretKeyControl:1;
 891                 u32     disableOnlineCtrlReset:1;
 892                 u32     allowBootWithPinnedCache:1;
 893                 u32     disableSpinDownHS:1;
 894                 u32     enableJBOD:1;
 895                 u32     reserved:18;
 896 #endif
 897         } OnOffProperties;
 898
 899         union {
 900                 u8 autoSnapVDSpace;
 901                 u8 viewSpace;
 902                 struct {
 903 #if   defined(__BIG_ENDIAN_BITFIELD)
 904                         u16 reserved3:9;
 905                         u16 enable_fw_dev_list:1;
 906                         u16 reserved2:1;
 907                         u16 enable_snap_dump:1;
 908                         u16 reserved1:4;
 909 #else
 910                         u16 reserved1:4;
 911                         u16 enable_snap_dump:1;
 912                         u16 reserved2:1;
 913                         u16 enable_fw_dev_list:1;
 914                         u16 reserved3:9;
 915 #endif
 916                 } on_off_properties2;
 917         };
 918         __le16 spinDownTime;
 919         u8  reserved[24];
 920 } __packed;
 921
 922 /*
 923  * SAS controller information
 924  */
 925 struct megasas_ctrl_info {
 926
 927         /*
 928          * PCI device information
 929          */
 930         struct {
 931
 932                 __le16 vendor_id;
 933                 __le16 device_id;
 934                 __le16 sub_vendor_id;
 935                 __le16 sub_device_id;
 936                 u8 reserved[24];
 937
 938         } __attribute__ ((packed)) pci;
 939
 940         /*
 941          * Host interface information
 942          */
 943         struct {
 944
 945                 u8 PCIX:1;
 946                 u8 PCIE:1;
 947                 u8 iSCSI:1;
 948                 u8 SAS_3G:1;
 949                 u8 SRIOV:1;
 950                 u8 reserved_0:3;
 951                 u8 reserved_1[6];
 952                 u8 port_count;
 953                 u64 port_addr[8];
 954
 955         } __attribute__ ((packed)) host_interface;
 956
 957         /*
 958          * Device (backend) interface information
 959          */
 960         struct {
 961
 962                 u8 SPI:1;
 963                 u8 SAS_3G:1;
 964                 u8 SATA_1_5G:1;
 965                 u8 SATA_3G:1;
 966                 u8 reserved_0:4;
 967                 u8 reserved_1[6];
 968                 u8 port_count;
 969                 u64 port_addr[8];
 970
 971         } __attribute__ ((packed)) device_interface;
 972
 973         /*
 974          * List of components residing in flash. All str are null terminated
 975          */
 976         __le32 image_check_word;
 977         __le32 image_component_count;
 978
 979         struct {
 980
 981                 char name[8];
 982                 char version[32];
 983                 char build_date[16];
 984                 char built_time[16];
 985
 986         } __attribute__ ((packed)) image_component[8];
 987
 988         /*
 989          * List of flash components that have been flashed on the card, but
 990          * are not in use, pending reset of the adapter. This list will be
 991          * empty if a flash operation has not occurred. All stings are null
 992          * terminated
 993          */
 994         __le32 pending_image_component_count;
 995
 996         struct {
 997
 998                 char name[8];
 999                 char version[32];
1000                 char build_date[16];
1001                 char build_time[16];
1002
1003         } __attribute__ ((packed)) pending_image_component[8];
1004
1005         u8 max_arms;
1006         u8 max_spans;
1007         u8 max_arrays;
1008         u8 max_lds;
1009
1010         char product_name[80];
1011         char serial_no[32];
1012
1013         /*
1014          * Other physical/controller/operation information. Indicates the
1015          * presence of the hardware
1016          */
1017         struct {
1018
1019                 u32 bbu:1;
1020                 u32 alarm:1;
1021                 u32 nvram:1;
1022                 u32 uart:1;
1023                 u32 reserved:28;
1024
1025         } __attribute__ ((packed)) hw_present;
1026
1027         __le32 current_fw_time;
1028
1029         /*
1030          * Maximum data transfer sizes
1031          */
1032         __le16 max_concurrent_cmds;
1033         __le16 max_sge_count;
1034         __le32 max_request_size;
1035
1036         /*
1037          * Logical and physical device counts
1038          */
1039         __le16 ld_present_count;
1040         __le16 ld_degraded_count;
1041         __le16 ld_offline_count;
1042
1043         __le16 pd_present_count;
1044         __le16 pd_disk_present_count;
1045         __le16 pd_disk_pred_failure_count;
1046         __le16 pd_disk_failed_count;
1047
1048         /*
1049          * Memory size information
1050          */
1051         __le16 nvram_size;
1052         __le16 memory_size;
1053         __le16 flash_size;
1054
1055         /*
1056          * Error counters
1057          */
1058         __le16 mem_correctable_error_count;
1059         __le16 mem_uncorrectable_error_count;
1060
1061         /*
1062          * Cluster information
1063          */
1064         u8 cluster_permitted;
1065         u8 cluster_active;
1066
1067         /*
1068          * Additional max data transfer sizes
1069          */
1070         __le16 max_strips_per_io;
1071
1072         /*
1073          * Controller capabilities structures
1074          */
1075         struct {
1076
1077                 u32 raid_level_0:1;
1078                 u32 raid_level_1:1;
1079                 u32 raid_level_5:1;
1080                 u32 raid_level_1E:1;
1081                 u32 raid_level_6:1;
1082                 u32 reserved:27;
1083
1084         } __attribute__ ((packed)) raid_levels;
1085
1086         struct {
1087
1088                 u32 rbld_rate:1;
1089                 u32 cc_rate:1;
1090                 u32 bgi_rate:1;
1091                 u32 recon_rate:1;
1092                 u32 patrol_rate:1;
1093                 u32 alarm_control:1;
1094                 u32 cluster_supported:1;
1095                 u32 bbu:1;
1096                 u32 spanning_allowed:1;
1097                 u32 dedicated_hotspares:1;
1098                 u32 revertible_hotspares:1;
1099                 u32 foreign_config_import:1;
1100                 u32 self_diagnostic:1;
1101                 u32 mixed_redundancy_arr:1;
1102                 u32 global_hot_spares:1;
1103                 u32 reserved:17;
1104
1105         } __attribute__ ((packed)) adapter_operations;
1106
1107         struct {
1108
1109                 u32 read_policy:1;
1110                 u32 write_policy:1;
1111                 u32 io_policy:1;
1112                 u32 access_policy:1;
1113                 u32 disk_cache_policy:1;
1114                 u32 reserved:27;
1115
1116         } __attribute__ ((packed)) ld_operations;
1117
1118         struct {
1119
1120                 u8 min;
1121                 u8 max;
1122                 u8 reserved[2];
1123
1124         } __attribute__ ((packed)) stripe_sz_ops;
1125
1126         struct {
1127
1128                 u32 force_online:1;
1129                 u32 force_offline:1;
1130                 u32 force_rebuild:1;
1131                 u32 reserved:29;
1132
1133         } __attribute__ ((packed)) pd_operations;
1134
1135         struct {
1136
1137                 u32 ctrl_supports_sas:1;
1138                 u32 ctrl_supports_sata:1;
1139                 u32 allow_mix_in_encl:1;
1140                 u32 allow_mix_in_ld:1;
1141                 u32 allow_sata_in_cluster:1;
1142                 u32 reserved:27;
1143
1144         } __attribute__ ((packed)) pd_mix_support;
1145
1146         /*
1147          * Define ECC single-bit-error bucket information
1148          */
1149         u8 ecc_bucket_count;
1150         u8 reserved_2[11];
1151
1152         /*
1153          * Include the controller properties (changeable items)
1154          */
1155         struct megasas_ctrl_prop properties;
1156
1157         /*
1158          * Define FW pkg version (set in envt v'bles on OEM basis)
1159          */
1160         char package_version[0x60];
1161
1162
1163         /*
1164         * If adapterOperations.supportMoreThan8Phys is set,
1165         * and deviceInterface.portCount is greater than 8,
1166         * SAS Addrs for first 8 ports shall be populated in
1167         * deviceInterface.portAddr, and the rest shall be
1168         * populated in deviceInterfacePortAddr2.
1169         */
1170         __le64      deviceInterfacePortAddr2[8]; /*6a0h */
1171         u8          reserved3[128];              /*6e0h */
1172
1173         struct {                                /*760h */
1174                 u16 minPdRaidLevel_0:4;
1175                 u16 maxPdRaidLevel_0:12;
1176
1177                 u16 minPdRaidLevel_1:4;
1178                 u16 maxPdRaidLevel_1:12;
1179
1180                 u16 minPdRaidLevel_5:4;
1181                 u16 maxPdRaidLevel_5:12;
1182
1183                 u16 minPdRaidLevel_1E:4;
1184                 u16 maxPdRaidLevel_1E:12;
1185
1186                 u16 minPdRaidLevel_6:4;
1187                 u16 maxPdRaidLevel_6:12;
1188
1189                 u16 minPdRaidLevel_10:4;
1190                 u16 maxPdRaidLevel_10:12;
1191
1192                 u16 minPdRaidLevel_50:4;
1193                 u16 maxPdRaidLevel_50:12;
1194
1195                 u16 minPdRaidLevel_60:4;
1196                 u16 maxPdRaidLevel_60:12;
1197
1198                 u16 minPdRaidLevel_1E_RLQ0:4;
1199                 u16 maxPdRaidLevel_1E_RLQ0:12;
1200
1201                 u16 minPdRaidLevel_1E0_RLQ0:4;
1202                 u16 maxPdRaidLevel_1E0_RLQ0:12;
1203
1204                 u16 reserved[6];
1205         } pdsForRaidLevels;
1206
1207         __le16 maxPds;                          /*780h */
1208         __le16 maxDedHSPs;                      /*782h */
1209         __le16 maxGlobalHSP;                    /*784h */
1210         __le16 ddfSize;                         /*786h */
1211         u8  maxLdsPerArray;                     /*788h */
1212         u8  partitionsInDDF;                    /*789h */
1213         u8  lockKeyBinding;                     /*78ah */
1214         u8  maxPITsPerLd;                       /*78bh */
1215         u8  maxViewsPerLd;                      /*78ch */
1216         u8  maxTargetId;                        /*78dh */
1217         __le16 maxBvlVdSize;                    /*78eh */
1218
1219         __le16 maxConfigurableSSCSize;          /*790h */
1220         __le16 currentSSCsize;                  /*792h */
1221
1222         char    expanderFwVersion[12];          /*794h */
1223
1224         __le16 PFKTrialTimeRemaining;           /*7A0h */
1225
1226         __le16 cacheMemorySize;                 /*7A2h */
1227
1228         struct {                                /*7A4h */
1229 #if   defined(__BIG_ENDIAN_BITFIELD)
1230                 u32     reserved:5;
1231                 u32     activePassive:2;
1232                 u32     supportConfigAutoBalance:1;
1233                 u32     mpio:1;
1234                 u32     supportDataLDonSSCArray:1;
1235                 u32     supportPointInTimeProgress:1;
1236                 u32     supportUnevenSpans:1;
1237                 u32     dedicatedHotSparesLimited:1;
1238                 u32     headlessMode:1;
1239                 u32     supportEmulatedDrives:1;
1240                 u32     supportResetNow:1;
1241                 u32     realTimeScheduler:1;
1242                 u32     supportSSDPatrolRead:1;
1243                 u32     supportPerfTuning:1;
1244                 u32     disableOnlinePFKChange:1;
1245                 u32     supportJBOD:1;
1246                 u32     supportBootTimePFKChange:1;
1247                 u32     supportSetLinkSpeed:1;
1248                 u32     supportEmergencySpares:1;
1249                 u32     supportSuspendResumeBGops:1;
1250                 u32     blockSSDWriteCacheChange:1;
1251                 u32     supportShieldState:1;
1252                 u32     supportLdBBMInfo:1;
1253                 u32     supportLdPIType3:1;
1254                 u32     supportLdPIType2:1;
1255                 u32     supportLdPIType1:1;
1256                 u32     supportPIcontroller:1;
1257 #else
1258                 u32     supportPIcontroller:1;
1259                 u32     supportLdPIType1:1;
1260                 u32     supportLdPIType2:1;
1261                 u32     supportLdPIType3:1;
1262                 u32     supportLdBBMInfo:1;
1263                 u32     supportShieldState:1;
1264                 u32     blockSSDWriteCacheChange:1;
1265                 u32     supportSuspendResumeBGops:1;
1266                 u32     supportEmergencySpares:1;
1267                 u32     supportSetLinkSpeed:1;
1268                 u32     supportBootTimePFKChange:1;
1269                 u32     supportJBOD:1;
1270                 u32     disableOnlinePFKChange:1;
1271                 u32     supportPerfTuning:1;
1272                 u32     supportSSDPatrolRead:1;
1273                 u32     realTimeScheduler:1;
1274
1275                 u32     supportResetNow:1;
1276                 u32     supportEmulatedDrives:1;
1277                 u32     headlessMode:1;
1278                 u32     dedicatedHotSparesLimited:1;
1279
1280
1281                 u32     supportUnevenSpans:1;
1282                 u32     supportPointInTimeProgress:1;
1283                 u32     supportDataLDonSSCArray:1;
1284                 u32     mpio:1;
1285                 u32     supportConfigAutoBalance:1;
1286                 u32     activePassive:2;
1287                 u32     reserved:5;
1288 #endif
1289         } adapterOperations2;
1290
1291         u8  driverVersion[32];                  /*7A8h */
1292         u8  maxDAPdCountSpinup60;               /*7C8h */
1293         u8  temperatureROC;                     /*7C9h */
1294         u8  temperatureCtrl;                    /*7CAh */
1295         u8  reserved4;                          /*7CBh */
1296         __le16 maxConfigurablePds;              /*7CCh */
1297
1298
1299         u8  reserved5[2];                       /*0x7CDh */
1300
1301         /*
1302         * HA cluster information
1303         */
1304         struct {
1305 #if defined(__BIG_ENDIAN_BITFIELD)
1306                 u32     reserved:25;
1307                 u32     passive:1;
1308                 u32     premiumFeatureMismatch:1;
1309                 u32     ctrlPropIncompatible:1;
1310                 u32     fwVersionMismatch:1;
1311                 u32     hwIncompatible:1;
1312                 u32     peerIsIncompatible:1;
1313                 u32     peerIsPresent:1;
1314 #else
1315                 u32     peerIsPresent:1;
1316                 u32     peerIsIncompatible:1;
1317                 u32     hwIncompatible:1;
1318                 u32     fwVersionMismatch:1;
1319                 u32     ctrlPropIncompatible:1;
1320                 u32     premiumFeatureMismatch:1;
1321                 u32     passive:1;
1322                 u32     reserved:25;
1323 #endif
1324         } cluster;
1325
1326         char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1327         struct {
1328                 u8  maxVFsSupported;            /*0x7E4*/
1329                 u8  numVFsEnabled;              /*0x7E5*/
1330                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1331                 u8  reserved;                   /*0x7E7*/
1332         } iov;
1333
1334         struct {
1335 #if defined(__BIG_ENDIAN_BITFIELD)
1336                 u32     reserved:7;
1337                 u32     useSeqNumJbodFP:1;
1338                 u32     supportExtendedSSCSize:1;
1339                 u32     supportDiskCacheSettingForSysPDs:1;
1340                 u32     supportCPLDUpdate:1;
1341                 u32     supportTTYLogCompression:1;
1342                 u32     discardCacheDuringLDDelete:1;
1343                 u32     supportSecurityonJBOD:1;
1344                 u32     supportCacheBypassModes:1;
1345                 u32     supportDisableSESMonitoring:1;
1346                 u32     supportForceFlash:1;
1347                 u32     supportNVDRAM:1;
1348                 u32     supportDrvActivityLEDSetting:1;
1349                 u32     supportAllowedOpsforDrvRemoval:1;
1350                 u32     supportHOQRebuild:1;
1351                 u32     supportForceTo512e:1;
1352                 u32     supportNVCacheErase:1;
1353                 u32     supportDebugQueue:1;
1354                 u32     supportSwZone:1;
1355                 u32     supportCrashDump:1;
1356                 u32     supportMaxExtLDs:1;
1357                 u32     supportT10RebuildAssist:1;
1358                 u32     supportDisableImmediateIO:1;
1359                 u32     supportThermalPollInterval:1;
1360                 u32     supportPersonalityChange:2;
1361 #else
1362                 u32     supportPersonalityChange:2;
1363                 u32     supportThermalPollInterval:1;
1364                 u32     supportDisableImmediateIO:1;
1365                 u32     supportT10RebuildAssist:1;
1366                 u32     supportMaxExtLDs:1;
1367                 u32     supportCrashDump:1;
1368                 u32     supportSwZone:1;
1369                 u32     supportDebugQueue:1;
1370                 u32     supportNVCacheErase:1;
1371                 u32     supportForceTo512e:1;
1372                 u32     supportHOQRebuild:1;
1373                 u32     supportAllowedOpsforDrvRemoval:1;
1374                 u32     supportDrvActivityLEDSetting:1;
1375                 u32     supportNVDRAM:1;
1376                 u32     supportForceFlash:1;
1377                 u32     supportDisableSESMonitoring:1;
1378                 u32     supportCacheBypassModes:1;
1379                 u32     supportSecurityonJBOD:1;
1380                 u32     discardCacheDuringLDDelete:1;
1381                 u32     supportTTYLogCompression:1;
1382                 u32     supportCPLDUpdate:1;
1383                 u32     supportDiskCacheSettingForSysPDs:1;
1384                 u32     supportExtendedSSCSize:1;
1385                 u32     useSeqNumJbodFP:1;
1386                 u32     reserved:7;
1387 #endif
1388         } adapterOperations3;
1389
1390         struct {
1391 #if defined(__BIG_ENDIAN_BITFIELD)
1392         u8 reserved:7;
1393         /* Indicates whether the CPLD image is part of
1394          *  the package and stored in flash
1395          */
1396         u8 cpld_in_flash:1;
1397 #else
1398         u8 cpld_in_flash:1;
1399         u8 reserved:7;
1400 #endif
1401         u8 reserved1[3];
1402         /* Null terminated string. Has the version
1403          *  information if cpld_in_flash = FALSE
1404          */
1405         u8 userCodeDefinition[12];
1406         } cpld;  /* Valid only if upgradableCPLD is TRUE */
1407
1408         struct {
1409         #if defined(__BIG_ENDIAN_BITFIELD)
1410                 u16 reserved:2;
1411                 u16 support_nvme_passthru:1;
1412                 u16 support_pl_debug_info:1;
1413                 u16 support_flash_comp_info:1;
1414                 u16 support_host_info:1;
1415                 u16 support_dual_fw_update:1;
1416                 u16 support_ssc_rev3:1;
1417                 u16 fw_swaps_bbu_vpd_info:1;
1418                 u16 support_pd_map_target_id:1;
1419                 u16 support_ses_ctrl_in_multipathcfg:1;
1420                 u16 image_upload_supported:1;
1421                 u16 support_encrypted_mfc:1;
1422                 u16 supported_enc_algo:1;
1423                 u16 support_ibutton_less:1;
1424                 u16 ctrl_info_ext_supported:1;
1425         #else
1426
1427                 u16 ctrl_info_ext_supported:1;
1428                 u16 support_ibutton_less:1;
1429                 u16 supported_enc_algo:1;
1430                 u16 support_encrypted_mfc:1;
1431                 u16 image_upload_supported:1;
1432                 /* FW supports LUN based association and target port based */
1433                 u16 support_ses_ctrl_in_multipathcfg:1;
1434                 /* association for the SES device connected in multipath mode */
1435                 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1436                 u16 support_pd_map_target_id:1;
1437                 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1438                  *  provide the data in little endian order
1439                  */
1440                 u16 fw_swaps_bbu_vpd_info:1;
1441                 u16 support_ssc_rev3:1;
1442                 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1443                 u16 support_dual_fw_update:1;
1444                 /* FW supports dual firmware update feature */
1445                 u16 support_host_info:1;
1446                 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1447                 u16 support_flash_comp_info:1;
1448                 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1449                 u16 support_pl_debug_info:1;
1450                 /* FW supports retrieval of PL debug information through apps */
1451                 u16 support_nvme_passthru:1;
1452                 /* FW supports NVMe passthru commands */
1453                 u16 reserved:2;
1454         #endif
1455                 } adapter_operations4;
1456         u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1457
1458         u32 size;
1459         u32 pad1;
1460
1461         u8 reserved6[64];
1462
1463         struct {
1464         #if defined(__BIG_ENDIAN_BITFIELD)
1465                 u32 reserved:19;
1466                 u32 support_pci_lane_margining: 1;
1467                 u32 support_psoc_update:1;
1468                 u32 support_force_personality_change:1;
1469                 u32 support_fde_type_mix:1;
1470                 u32 support_snap_dump:1;
1471                 u32 support_nvme_tm:1;
1472                 u32 support_oce_only:1;
1473                 u32 support_ext_mfg_vpd:1;
1474                 u32 support_pcie:1;
1475                 u32 support_cvhealth_info:1;
1476                 u32 support_profile_change:2;
1477                 u32 mr_config_ext2_supported:1;
1478         #else
1479                 u32 mr_config_ext2_supported:1;
1480                 u32 support_profile_change:2;
1481                 u32 support_cvhealth_info:1;
1482                 u32 support_pcie:1;
1483                 u32 support_ext_mfg_vpd:1;
1484                 u32 support_oce_only:1;
1485                 u32 support_nvme_tm:1;
1486                 u32 support_snap_dump:1;
1487                 u32 support_fde_type_mix:1;
1488                 u32 support_force_personality_change:1;
1489                 u32 support_psoc_update:1;
1490                 u32 support_pci_lane_margining: 1;
1491                 u32 reserved:19;
1492         #endif
1493         } adapter_operations5;
1494
1495         u32 rsvdForAdptOp[63];
1496
1497         u8 reserved7[3];
1498
1499         u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1500         u8 MaxResetTO;  /* Max Supported Reset timeout in seconds. */
1501         u8 reserved8[3];
1502 } __packed;
1503
1504 /*
1505  * ===============================
1506  * MegaRAID SAS driver definitions
1507  * ===============================
1508  */
1509 #define MEGASAS_MAX_PD_CHANNELS                 2
1510 #define MEGASAS_MAX_LD_CHANNELS                 2
1511 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1512                                                 MEGASAS_MAX_LD_CHANNELS)
1513 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1514 #define MEGASAS_DEFAULT_INIT_ID                 -1
1515 #define MEGASAS_MAX_LUN                         8
1516 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1517 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1518                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1519 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1520                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1521
1522 #define MEGASAS_MAX_SUPPORTED_LD_IDS            240
1523
1524 #define MEGASAS_MAX_SECTORS                    (2*1024)
1525 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1526 #define MEGASAS_DBG_LVL                         1
1527
1528 #define MEGASAS_FW_BUSY                         1
1529
1530 /* Driver's internal Logging levels*/
1531 #define OCR_DEBUG    (1 << 0)
1532 #define TM_DEBUG     (1 << 1)
1533 #define LD_PD_DEBUG    (1 << 2)
1534
1535 #define SCAN_PD_CHANNEL 0x1
1536 #define SCAN_VD_CHANNEL 0x2
1537
1538 #define MEGASAS_KDUMP_QUEUE_DEPTH               100
1539 #define MR_LARGE_IO_MIN_SIZE                    (32 * 1024)
1540 #define MR_R1_LDIO_PIGGYBACK_DEFAULT            4
1541
1542 enum MR_SCSI_CMD_TYPE {
1543         READ_WRITE_LDIO = 0,
1544         NON_READ_WRITE_LDIO = 1,
1545         READ_WRITE_SYSPDIO = 2,
1546         NON_READ_WRITE_SYSPDIO = 3,
1547 };
1548
1549 enum DCMD_TIMEOUT_ACTION {
1550         INITIATE_OCR = 0,
1551         KILL_ADAPTER = 1,
1552         IGNORE_TIMEOUT = 2,
1553 };
1554
1555 enum FW_BOOT_CONTEXT {
1556         PROBE_CONTEXT = 0,
1557         OCR_CONTEXT = 1,
1558 };
1559
1560 /* Frame Type */
1561 #define IO_FRAME                                0
1562 #define PTHRU_FRAME                             1
1563
1564 /*
1565  * When SCSI mid-layer calls driver's reset routine, driver waits for
1566  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1567  * that the driver cannot _actually_ abort or reset pending commands. While
1568  * it is waiting for the commands to complete, it prints a diagnostic message
1569  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1570  */
1571 #define MEGASAS_RESET_WAIT_TIME                 180
1572 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1573 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1574 #define MEGASAS_IOCTL_CMD                       0
1575 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1576 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1577 #define MEGASAS_DEFAULT_TM_TIMEOUT              50
1578 /*
1579  * FW reports the maximum of number of commands that it can accept (maximum
1580  * commands that can be outstanding) at any time. The driver must report a
1581  * lower number to the mid layer because it can issue a few internal commands
1582  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1583  * is shown below
1584  */
1585 #define MEGASAS_INT_CMDS                        32
1586 #define MEGASAS_SKINNY_INT_CMDS                 5
1587 #define MEGASAS_FUSION_INTERNAL_CMDS            8
1588 #define MEGASAS_FUSION_IOCTL_CMDS               3
1589 #define MEGASAS_MFI_IOCTL_CMDS                  27
1590
1591 #define MEGASAS_MAX_MSIX_QUEUES                 128
1592 /*
1593  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1594  * SGLs based on the size of dma_addr_t
1595  */
1596 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1597
1598 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1599
1600 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1601 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1602 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1603
1604 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1605 #define MFI_POLL_TIMEOUT_SECS                   60
1606 #define MFI_IO_TIMEOUT_SECS                     180
1607 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1608 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1609 #define MEGASAS_SRIOV_MAX_RESET_TRIES_VF        1
1610 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1611 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1612 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1613 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1614 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1615 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1616
1617 #define MFI_1068_PCSR_OFFSET                    0x84
1618 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1619 #define MFI_1068_FW_READY                       0xDDDD0000
1620
1621 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1622 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1623 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1624 #define MR_MAX_MSIX_REG_ARRAY                   16
1625 #define MR_RDPQ_MODE_OFFSET                     0X00800000
1626
1627 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT       16
1628 #define MR_MAX_RAID_MAP_SIZE_MASK               0x1FF
1629 #define MR_MIN_MAP_SIZE                         0x10000
1630 /* 64k */
1631
1632 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET         0X01000000
1633
1634 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET     (1 << 24)
1635
1636 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET         (1 << 25)
1637 #define MR_INTR_COALESCING_SUPPORT_OFFSET       (1 << 26)
1638
1639 #define MEGASAS_WATCHDOG_THREAD_INTERVAL        1000
1640 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS         20
1641 #define MEGASAS_WATCHDOG_WAIT_COUNT             50
1642
1643 enum MR_ADAPTER_TYPE {
1644         MFI_SERIES = 1,
1645         THUNDERBOLT_SERIES = 2,
1646         INVADER_SERIES = 3,
1647         VENTURA_SERIES = 4,
1648         AERO_SERIES = 5,
1649 };
1650
1651 /*
1652 * register set for both 1068 and 1078 controllers
1653 * structure extended for 1078 registers
1654 */
1655
1656 struct megasas_register_set {
1657         u32     doorbell;                       /*0000h*/
1658         u32     fusion_seq_offset;              /*0004h*/
1659         u32     fusion_host_diag;               /*0008h*/
1660         u32     reserved_01;                    /*000Ch*/
1661
1662         u32     inbound_msg_0;                  /*0010h*/
1663         u32     inbound_msg_1;                  /*0014h*/
1664         u32     outbound_msg_0;                 /*0018h*/
1665         u32     outbound_msg_1;                 /*001Ch*/
1666
1667         u32     inbound_doorbell;               /*0020h*/
1668         u32     inbound_intr_status;            /*0024h*/
1669         u32     inbound_intr_mask;              /*0028h*/
1670
1671         u32     outbound_doorbell;              /*002Ch*/
1672         u32     outbound_intr_status;           /*0030h*/
1673         u32     outbound_intr_mask;             /*0034h*/
1674
1675         u32     reserved_1[2];                  /*0038h*/
1676
1677         u32     inbound_queue_port;             /*0040h*/
1678         u32     outbound_queue_port;            /*0044h*/
1679
1680         u32     reserved_2[9];                  /*0048h*/
1681         u32     reply_post_host_index;          /*006Ch*/
1682         u32     reserved_2_2[12];               /*0070h*/
1683
1684         u32     outbound_doorbell_clear;        /*00A0h*/
1685
1686         u32     reserved_3[3];                  /*00A4h*/
1687
1688         u32     outbound_scratch_pad_0;         /*00B0h*/
1689         u32     outbound_scratch_pad_1;         /*00B4h*/
1690         u32     outbound_scratch_pad_2;         /*00B8h*/
1691         u32     outbound_scratch_pad_3;         /*00BCh*/
1692
1693         u32     inbound_low_queue_port ;        /*00C0h*/
1694
1695         u32     inbound_high_queue_port ;       /*00C4h*/
1696
1697         u32 inbound_single_queue_port;  /*00C8h*/
1698         u32     res_6[11];                      /*CCh*/
1699         u32     host_diag;
1700         u32     seq_offset;
1701         u32     index_registers[807];           /*00CCh*/
1702 } __attribute__ ((packed));
1703
1704 struct megasas_sge32 {
1705
1706         __le32 phys_addr;
1707         __le32 length;
1708
1709 } __attribute__ ((packed));
1710
1711 struct megasas_sge64 {
1712
1713         __le64 phys_addr;
1714         __le32 length;
1715
1716 } __attribute__ ((packed));
1717
1718 struct megasas_sge_skinny {
1719         __le64 phys_addr;
1720         __le32 length;
1721         __le32 flag;
1722 } __packed;
1723
1724 union megasas_sgl {
1725         DECLARE_FLEX_ARRAY(struct megasas_sge32, sge32);
1726         DECLARE_FLEX_ARRAY(struct megasas_sge64, sge64);
1727         DECLARE_FLEX_ARRAY(struct megasas_sge_skinny, sge_skinny);
1728 } __attribute__ ((packed));
1729
1730 struct megasas_header {
1731
1732         u8 cmd;                 /*00h */
1733         u8 sense_len;           /*01h */
1734         u8 cmd_status;          /*02h */
1735         u8 scsi_status;         /*03h */
1736
1737         u8 target_id;           /*04h */
1738         u8 lun;                 /*05h */
1739         u8 cdb_len;             /*06h */
1740         u8 sge_count;           /*07h */
1741
1742         __le32 context;         /*08h */
1743         __le32 pad_0;           /*0Ch */
1744
1745         __le16 flags;           /*10h */
1746         __le16 timeout;         /*12h */
1747         __le32 data_xferlen;    /*14h */
1748
1749 } __attribute__ ((packed));
1750
1751 union megasas_sgl_frame {
1752
1753         struct megasas_sge32 sge32[8];
1754         struct megasas_sge64 sge64[5];
1755
1756 } __attribute__ ((packed));
1757
1758 typedef union _MFI_CAPABILITIES {
1759         struct {
1760 #if   defined(__BIG_ENDIAN_BITFIELD)
1761         u32     reserved:15;
1762         u32     support_memdump:1;
1763         u32     support_fw_exposed_dev_list:1;
1764         u32     support_nvme_passthru:1;
1765         u32     support_64bit_mode:1;
1766         u32 support_pd_map_target_id:1;
1767         u32     support_qd_throttling:1;
1768         u32     support_fp_rlbypass:1;
1769         u32     support_vfid_in_ioframe:1;
1770         u32     support_ext_io_size:1;
1771         u32             support_ext_queue_depth:1;
1772         u32     security_protocol_cmds_fw:1;
1773         u32     support_core_affinity:1;
1774         u32     support_ndrive_r1_lb:1;
1775         u32             support_max_255lds:1;
1776         u32             support_fastpath_wb:1;
1777         u32     support_additional_msix:1;
1778         u32     support_fp_remote_lun:1;
1779 #else
1780         u32     support_fp_remote_lun:1;
1781         u32     support_additional_msix:1;
1782         u32             support_fastpath_wb:1;
1783         u32             support_max_255lds:1;
1784         u32     support_ndrive_r1_lb:1;
1785         u32     support_core_affinity:1;
1786         u32     security_protocol_cmds_fw:1;
1787         u32             support_ext_queue_depth:1;
1788         u32     support_ext_io_size:1;
1789         u32     support_vfid_in_ioframe:1;
1790         u32     support_fp_rlbypass:1;
1791         u32     support_qd_throttling:1;
1792         u32     support_pd_map_target_id:1;
1793         u32     support_64bit_mode:1;
1794         u32     support_nvme_passthru:1;
1795         u32     support_fw_exposed_dev_list:1;
1796         u32     support_memdump:1;
1797         u32     reserved:15;
1798 #endif
1799         } mfi_capabilities;
1800         __le32          reg;
1801 } MFI_CAPABILITIES;
1802
1803 struct megasas_init_frame {
1804
1805         u8 cmd;                 /*00h */
1806         u8 reserved_0;          /*01h */
1807         u8 cmd_status;          /*02h */
1808
1809         u8 reserved_1;          /*03h */
1810         MFI_CAPABILITIES driver_operations; /*04h*/
1811
1812         __le32 context;         /*08h */
1813         __le32 pad_0;           /*0Ch */
1814
1815         __le16 flags;           /*10h */
1816         __le16 replyqueue_mask;         /*12h */
1817         __le32 data_xfer_len;   /*14h */
1818
1819         __le32 queue_info_new_phys_addr_lo;     /*18h */
1820         __le32 queue_info_new_phys_addr_hi;     /*1Ch */
1821         __le32 queue_info_old_phys_addr_lo;     /*20h */
1822         __le32 queue_info_old_phys_addr_hi;     /*24h */
1823         __le32 reserved_4[2];   /*28h */
1824         __le32 system_info_lo;      /*30h */
1825         __le32 system_info_hi;      /*34h */
1826         __le32 reserved_5[2];   /*38h */
1827
1828 } __attribute__ ((packed));
1829
1830 struct megasas_init_queue_info {
1831
1832         __le32 init_flags;              /*00h */
1833         __le32 reply_queue_entries;     /*04h */
1834
1835         __le32 reply_queue_start_phys_addr_lo;  /*08h */
1836         __le32 reply_queue_start_phys_addr_hi;  /*0Ch */
1837         __le32 producer_index_phys_addr_lo;     /*10h */
1838         __le32 producer_index_phys_addr_hi;     /*14h */
1839         __le32 consumer_index_phys_addr_lo;     /*18h */
1840         __le32 consumer_index_phys_addr_hi;     /*1Ch */
1841
1842 } __attribute__ ((packed));
1843
1844 struct megasas_io_frame {
1845
1846         u8 cmd;                 /*00h */
1847         u8 sense_len;           /*01h */
1848         u8 cmd_status;          /*02h */
1849         u8 scsi_status;         /*03h */
1850
1851         u8 target_id;           /*04h */
1852         u8 access_byte;         /*05h */
1853         u8 reserved_0;          /*06h */
1854         u8 sge_count;           /*07h */
1855
1856         __le32 context;         /*08h */
1857         __le32 pad_0;           /*0Ch */
1858
1859         __le16 flags;           /*10h */
1860         __le16 timeout;         /*12h */
1861         __le32 lba_count;       /*14h */
1862
1863         __le32 sense_buf_phys_addr_lo;  /*18h */
1864         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1865
1866         __le32 start_lba_lo;    /*20h */
1867         __le32 start_lba_hi;    /*24h */
1868
1869         union megasas_sgl sgl;  /*28h */
1870
1871 } __attribute__ ((packed));
1872
1873 struct megasas_pthru_frame {
1874
1875         u8 cmd;                 /*00h */
1876         u8 sense_len;           /*01h */
1877         u8 cmd_status;          /*02h */
1878         u8 scsi_status;         /*03h */
1879
1880         u8 target_id;           /*04h */
1881         u8 lun;                 /*05h */
1882         u8 cdb_len;             /*06h */
1883         u8 sge_count;           /*07h */
1884
1885         __le32 context;         /*08h */
1886         __le32 pad_0;           /*0Ch */
1887
1888         __le16 flags;           /*10h */
1889         __le16 timeout;         /*12h */
1890         __le32 data_xfer_len;   /*14h */
1891
1892         __le32 sense_buf_phys_addr_lo;  /*18h */
1893         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1894
1895         u8 cdb[16];             /*20h */
1896         union megasas_sgl sgl;  /*30h */
1897
1898 } __attribute__ ((packed));
1899
1900 struct megasas_dcmd_frame {
1901
1902         u8 cmd;                 /*00h */
1903         u8 reserved_0;          /*01h */
1904         u8 cmd_status;          /*02h */
1905         u8 reserved_1[4];       /*03h */
1906         u8 sge_count;           /*07h */
1907
1908         __le32 context;         /*08h */
1909         __le32 pad_0;           /*0Ch */
1910
1911         __le16 flags;           /*10h */
1912         __le16 timeout;         /*12h */
1913
1914         __le32 data_xfer_len;   /*14h */
1915         __le32 opcode;          /*18h */
1916
1917         union {                 /*1Ch */
1918                 u8 b[12];
1919                 __le16 s[6];
1920                 __le32 w[3];
1921         } mbox;
1922
1923         union megasas_sgl sgl;  /*28h */
1924
1925 } __attribute__ ((packed));
1926
1927 struct megasas_abort_frame {
1928
1929         u8 cmd;                 /*00h */
1930         u8 reserved_0;          /*01h */
1931         u8 cmd_status;          /*02h */
1932
1933         u8 reserved_1;          /*03h */
1934         __le32 reserved_2;      /*04h */
1935
1936         __le32 context;         /*08h */
1937         __le32 pad_0;           /*0Ch */
1938
1939         __le16 flags;           /*10h */
1940         __le16 reserved_3;      /*12h */
1941         __le32 reserved_4;      /*14h */
1942
1943         __le32 abort_context;   /*18h */
1944         __le32 pad_1;           /*1Ch */
1945
1946         __le32 abort_mfi_phys_addr_lo;  /*20h */
1947         __le32 abort_mfi_phys_addr_hi;  /*24h */
1948
1949         __le32 reserved_5[6];   /*28h */
1950
1951 } __attribute__ ((packed));
1952
1953 struct megasas_smp_frame {
1954
1955         u8 cmd;                 /*00h */
1956         u8 reserved_1;          /*01h */
1957         u8 cmd_status;          /*02h */
1958         u8 connection_status;   /*03h */
1959
1960         u8 reserved_2[3];       /*04h */
1961         u8 sge_count;           /*07h */
1962
1963         __le32 context;         /*08h */
1964         __le32 pad_0;           /*0Ch */
1965
1966         __le16 flags;           /*10h */
1967         __le16 timeout;         /*12h */
1968
1969         __le32 data_xfer_len;   /*14h */
1970         __le64 sas_addr;        /*18h */
1971
1972         union {
1973                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1974                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1975         } sgl;
1976
1977 } __attribute__ ((packed));
1978
1979 struct megasas_stp_frame {
1980
1981         u8 cmd;                 /*00h */
1982         u8 reserved_1;          /*01h */
1983         u8 cmd_status;          /*02h */
1984         u8 reserved_2;          /*03h */
1985
1986         u8 target_id;           /*04h */
1987         u8 reserved_3[2];       /*05h */
1988         u8 sge_count;           /*07h */
1989
1990         __le32 context;         /*08h */
1991         __le32 pad_0;           /*0Ch */
1992
1993         __le16 flags;           /*10h */
1994         __le16 timeout;         /*12h */
1995
1996         __le32 data_xfer_len;   /*14h */
1997
1998         __le16 fis[10];         /*18h */
1999         __le32 stp_flags;
2000
2001         union {
2002                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
2003                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
2004         } sgl;
2005
2006 } __attribute__ ((packed));
2007
2008 union megasas_frame {
2009
2010         struct megasas_header hdr;
2011         struct megasas_init_frame init;
2012         struct megasas_io_frame io;
2013         struct megasas_pthru_frame pthru;
2014         struct megasas_dcmd_frame dcmd;
2015         struct megasas_abort_frame abort;
2016         struct megasas_smp_frame smp;
2017         struct megasas_stp_frame stp;
2018
2019         u8 raw_bytes[64];
2020 };
2021
2022 /**
2023  * struct MR_PRIV_DEVICE - sdev private hostdata
2024  * @is_tm_capable: firmware managed tm_capable flag
2025  * @tm_busy: TM request is in progress
2026  * @sdev_priv_busy: pending command per sdev
2027  */
2028 struct MR_PRIV_DEVICE {
2029         bool is_tm_capable;
2030         bool tm_busy;
2031         atomic_t sdev_priv_busy;
2032         atomic_t r1_ldio_hint;
2033         u8 interface_type;
2034         u8 task_abort_tmo;
2035         u8 target_reset_tmo;
2036 };
2037 struct megasas_cmd;
2038
2039 union megasas_evt_class_locale {
2040
2041         struct {
2042 #ifndef __BIG_ENDIAN_BITFIELD
2043                 u16 locale;
2044                 u8 reserved;
2045                 s8 class;
2046 #else
2047                 s8 class;
2048                 u8 reserved;
2049                 u16 locale;
2050 #endif
2051         } __attribute__ ((packed)) members;
2052
2053         u32 word;
2054
2055 } __attribute__ ((packed));
2056
2057 struct megasas_evt_log_info {
2058         __le32 newest_seq_num;
2059         __le32 oldest_seq_num;
2060         __le32 clear_seq_num;
2061         __le32 shutdown_seq_num;
2062         __le32 boot_seq_num;
2063
2064 } __attribute__ ((packed));
2065
2066 struct megasas_progress {
2067
2068         __le16 progress;
2069         __le16 elapsed_seconds;
2070
2071 } __attribute__ ((packed));
2072
2073 struct megasas_evtarg_ld {
2074
2075         u16 target_id;
2076         u8 ld_index;
2077         u8 reserved;
2078
2079 } __attribute__ ((packed));
2080
2081 struct megasas_evtarg_pd {
2082         u16 device_id;
2083         u8 encl_index;
2084         u8 slot_number;
2085
2086 } __attribute__ ((packed));
2087
2088 struct megasas_evt_detail {
2089
2090         __le32 seq_num;
2091         __le32 time_stamp;
2092         __le32 code;
2093         union megasas_evt_class_locale cl;
2094         u8 arg_type;
2095         u8 reserved1[15];
2096
2097         union {
2098                 struct {
2099                         struct megasas_evtarg_pd pd;
2100                         u8 cdb_length;
2101                         u8 sense_length;
2102                         u8 reserved[2];
2103                         u8 cdb[16];
2104                         u8 sense[64];
2105                 } __attribute__ ((packed)) cdbSense;
2106
2107                 struct megasas_evtarg_ld ld;
2108
2109                 struct {
2110                         struct megasas_evtarg_ld ld;
2111                         __le64 count;
2112                 } __attribute__ ((packed)) ld_count;
2113
2114                 struct {
2115                         __le64 lba;
2116                         struct megasas_evtarg_ld ld;
2117                 } __attribute__ ((packed)) ld_lba;
2118
2119                 struct {
2120                         struct megasas_evtarg_ld ld;
2121                         __le32 prevOwner;
2122                         __le32 newOwner;
2123                 } __attribute__ ((packed)) ld_owner;
2124
2125                 struct {
2126                         u64 ld_lba;
2127                         u64 pd_lba;
2128                         struct megasas_evtarg_ld ld;
2129                         struct megasas_evtarg_pd pd;
2130                 } __attribute__ ((packed)) ld_lba_pd_lba;
2131
2132                 struct {
2133                         struct megasas_evtarg_ld ld;
2134                         struct megasas_progress prog;
2135                 } __attribute__ ((packed)) ld_prog;
2136
2137                 struct {
2138                         struct megasas_evtarg_ld ld;
2139                         u32 prev_state;
2140                         u32 new_state;
2141                 } __attribute__ ((packed)) ld_state;
2142
2143                 struct {
2144                         u64 strip;
2145                         struct megasas_evtarg_ld ld;
2146                 } __attribute__ ((packed)) ld_strip;
2147
2148                 struct megasas_evtarg_pd pd;
2149
2150                 struct {
2151                         struct megasas_evtarg_pd pd;
2152                         u32 err;
2153                 } __attribute__ ((packed)) pd_err;
2154
2155                 struct {
2156                         u64 lba;
2157                         struct megasas_evtarg_pd pd;
2158                 } __attribute__ ((packed)) pd_lba;
2159
2160                 struct {
2161                         u64 lba;
2162                         struct megasas_evtarg_pd pd;
2163                         struct megasas_evtarg_ld ld;
2164                 } __attribute__ ((packed)) pd_lba_ld;
2165
2166                 struct {
2167                         struct megasas_evtarg_pd pd;
2168                         struct megasas_progress prog;
2169                 } __attribute__ ((packed)) pd_prog;
2170
2171                 struct {
2172                         struct megasas_evtarg_pd pd;
2173                         u32 prevState;
2174                         u32 newState;
2175                 } __attribute__ ((packed)) pd_state;
2176
2177                 struct {
2178                         u16 vendorId;
2179                         __le16 deviceId;
2180                         u16 subVendorId;
2181                         u16 subDeviceId;
2182                 } __attribute__ ((packed)) pci;
2183
2184                 u32 rate;
2185                 char str[96];
2186
2187                 struct {
2188                         u32 rtc;
2189                         u32 elapsedSeconds;
2190                 } __attribute__ ((packed)) time;
2191
2192                 struct {
2193                         u32 ecar;
2194                         u32 elog;
2195                         char str[64];
2196                 } __attribute__ ((packed)) ecc;
2197
2198                 u8 b[96];
2199                 __le16 s[48];
2200                 __le32 w[24];
2201                 __le64 d[12];
2202         } args;
2203
2204         char description[128];
2205
2206 } __attribute__ ((packed));
2207
2208 struct megasas_aen_event {
2209         struct delayed_work hotplug_work;
2210         struct megasas_instance *instance;
2211 };
2212
2213 struct megasas_irq_context {
2214         char name[MEGASAS_MSIX_NAME_LEN];
2215         struct megasas_instance *instance;
2216         u32 MSIxIndex;
2217         u32 os_irq;
2218         struct irq_poll irqpoll;
2219         bool irq_poll_scheduled;
2220         bool irq_line_enable;
2221         atomic_t   in_used;
2222 };
2223
2224 struct MR_DRV_SYSTEM_INFO {
2225         u8      infoVersion;
2226         u8      systemIdLength;
2227         u16     reserved0;
2228         u8      systemId[64];
2229         u8      reserved[1980];
2230 };
2231
2232 enum MR_PD_TYPE {
2233         UNKNOWN_DRIVE = 0,
2234         PARALLEL_SCSI = 1,
2235         SAS_PD = 2,
2236         SATA_PD = 3,
2237         FC_PD = 4,
2238         NVME_PD = 5,
2239 };
2240
2241 /* JBOD Queue depth definitions */
2242 #define MEGASAS_SATA_QD 32
2243 #define MEGASAS_SAS_QD 256
2244 #define MEGASAS_DEFAULT_PD_QD   64
2245 #define MEGASAS_NVME_QD        64
2246
2247 #define MR_DEFAULT_NVME_PAGE_SIZE       4096
2248 #define MR_DEFAULT_NVME_PAGE_SHIFT      12
2249 #define MR_DEFAULT_NVME_MDTS_KB         128
2250 #define MR_NVME_PAGE_SIZE_MASK          0x000000FF
2251
2252 /*Aero performance parameters*/
2253 #define MR_HIGH_IOPS_QUEUE_COUNT        8
2254 #define MR_DEVICE_HIGH_IOPS_DEPTH       8
2255 #define MR_HIGH_IOPS_BATCH_COUNT        16
2256
2257 enum MR_PERF_MODE {
2258         MR_BALANCED_PERF_MODE           = 0,
2259         MR_IOPS_PERF_MODE               = 1,
2260         MR_LATENCY_PERF_MODE            = 2,
2261 };
2262
2263 #define MEGASAS_PERF_MODE_2STR(mode) \
2264                 ((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
2265                  (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
2266                  (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
2267                  "Unknown")
2268
2269 enum MEGASAS_LD_TARGET_ID_STATUS {
2270         LD_TARGET_ID_INITIAL,
2271         LD_TARGET_ID_ACTIVE,
2272         LD_TARGET_ID_DELETED,
2273 };
2274
2275 #define MEGASAS_TARGET_ID(sdev)                                         \
2276         (((sdev->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id)
2277
2278 struct megasas_instance {
2279
2280         unsigned int *reply_map;
2281         __le32 *producer;
2282         dma_addr_t producer_h;
2283         __le32 *consumer;
2284         dma_addr_t consumer_h;
2285         struct MR_DRV_SYSTEM_INFO *system_info_buf;
2286         dma_addr_t system_info_h;
2287         struct MR_LD_VF_AFFILIATION *vf_affiliation;
2288         dma_addr_t vf_affiliation_h;
2289         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2290         dma_addr_t vf_affiliation_111_h;
2291         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2292         dma_addr_t hb_host_mem_h;
2293         struct MR_PD_INFO *pd_info;
2294         dma_addr_t pd_info_h;
2295         struct MR_TARGET_PROPERTIES *tgt_prop;
2296         dma_addr_t tgt_prop_h;
2297
2298         __le32 *reply_queue;
2299         dma_addr_t reply_queue_h;
2300
2301         u32 *crash_dump_buf;
2302         dma_addr_t crash_dump_h;
2303
2304         struct MR_PD_LIST *pd_list_buf;
2305         dma_addr_t pd_list_buf_h;
2306
2307         struct megasas_ctrl_info *ctrl_info_buf;
2308         dma_addr_t ctrl_info_buf_h;
2309
2310         struct MR_LD_LIST *ld_list_buf;
2311         dma_addr_t ld_list_buf_h;
2312
2313         struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2314         dma_addr_t ld_targetid_list_buf_h;
2315
2316         struct MR_HOST_DEVICE_LIST *host_device_list_buf;
2317         dma_addr_t host_device_list_buf_h;
2318
2319         struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2320         dma_addr_t snapdump_prop_h;
2321
2322         void *crash_buf[MAX_CRASH_DUMP_SIZE];
2323         unsigned int    fw_crash_buffer_size;
2324         unsigned int    fw_crash_state;
2325         unsigned int    fw_crash_buffer_offset;
2326         u32 drv_buf_index;
2327         u32 drv_buf_alloc;
2328         u32 crash_dump_fw_support;
2329         u32 crash_dump_drv_support;
2330         u32 crash_dump_app_support;
2331         u32 secure_jbod_support;
2332         u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2333         bool use_seqnum_jbod_fp;   /* Added for PD sequence */
2334         bool smp_affinity_enable;
2335         struct mutex crashdump_lock;
2336
2337         struct megasas_register_set __iomem *reg_set;
2338         u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2339         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
2340         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
2341         u8 ld_ids[MEGASAS_MAX_LD_IDS];
2342         u8 ld_tgtid_status[MEGASAS_MAX_LD_IDS];
2343         u8 ld_ids_prev[MEGASAS_MAX_LD_IDS];
2344         u8 ld_ids_from_raidmap[MEGASAS_MAX_LD_IDS];
2345         s8 init_id;
2346
2347         u16 max_num_sge;
2348         u16 max_fw_cmds;
2349         u16 max_mpt_cmds;
2350         u16 max_mfi_cmds;
2351         u16 max_scsi_cmds;
2352         u16 ldio_threshold;
2353         u16 cur_can_queue;
2354         u32 max_sectors_per_req;
2355         bool msix_load_balance;
2356         struct megasas_aen_event *ev;
2357
2358         struct megasas_cmd **cmd_list;
2359         struct list_head cmd_pool;
2360         /* used to sync fire the cmd to fw */
2361         spinlock_t mfi_pool_lock;
2362         /* used to sync fire the cmd to fw */
2363         spinlock_t hba_lock;
2364         /* used to synch producer, consumer ptrs in dpc */
2365         spinlock_t stream_lock;
2366         spinlock_t completion_lock;
2367         struct dma_pool *frame_dma_pool;
2368         struct dma_pool *sense_dma_pool;
2369
2370         struct megasas_evt_detail *evt_detail;
2371         dma_addr_t evt_detail_h;
2372         struct megasas_cmd *aen_cmd;
2373         struct semaphore ioctl_sem;
2374
2375         struct Scsi_Host *host;
2376
2377         wait_queue_head_t int_cmd_wait_q;
2378         wait_queue_head_t abort_cmd_wait_q;
2379
2380         struct pci_dev *pdev;
2381         u32 unique_id;
2382         u32 fw_support_ieee;
2383         u32 threshold_reply_count;
2384
2385         atomic_t fw_outstanding;
2386         atomic_t ldio_outstanding;
2387         atomic_t fw_reset_no_pci_access;
2388         atomic64_t total_io_count;
2389         atomic64_t high_iops_outstanding;
2390
2391         struct megasas_instance_template *instancet;
2392         struct tasklet_struct isr_tasklet;
2393         struct work_struct work_init;
2394         struct delayed_work fw_fault_work;
2395         struct workqueue_struct *fw_fault_work_q;
2396         char fault_handler_work_q_name[48];
2397
2398         u8 flag;
2399         u8 unload;
2400         u8 flag_ieee;
2401         u8 issuepend_done;
2402         u8 disableOnlineCtrlReset;
2403         u8 UnevenSpanSupport;
2404
2405         u8 supportmax256vd;
2406         u8 pd_list_not_supported;
2407         u16 fw_supported_vd_count;
2408         u16 fw_supported_pd_count;
2409
2410         u16 drv_supported_vd_count;
2411         u16 drv_supported_pd_count;
2412
2413         atomic_t adprecovery;
2414         unsigned long last_time;
2415         u32 mfiStatus;
2416         u32 last_seq_num;
2417
2418         struct list_head internal_reset_pending_q;
2419
2420         /* Ptr to hba specific information */
2421         void *ctrl_context;
2422         unsigned int msix_vectors;
2423         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2424         u64 map_id;
2425         u64 pd_seq_map_id;
2426         struct megasas_cmd *map_update_cmd;
2427         struct megasas_cmd *jbod_seq_cmd;
2428         unsigned long bar;
2429         long reset_flags;
2430         struct mutex reset_mutex;
2431         struct timer_list sriov_heartbeat_timer;
2432         char skip_heartbeat_timer_del;
2433         u8 requestorId;
2434         char PlasmaFW111;
2435         char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2436         u8 peerIsPresent;
2437         u8 passive;
2438         u16 throttlequeuedepth;
2439         u8 mask_interrupts;
2440         u16 max_chain_frame_sz;
2441         u8 is_imr;
2442         u8 is_rdpq;
2443         bool dev_handle;
2444         bool fw_sync_cache_support;
2445         u32 mfi_frame_size;
2446         bool msix_combined;
2447         u16 max_raid_mapsize;
2448         /* preffered count to send as LDIO irrspective of FP capable.*/
2449         u8  r1_ldio_hint_default;
2450         u32 nvme_page_size;
2451         u8 adapter_type;
2452         bool consistent_mask_64bit;
2453         bool support_nvme_passthru;
2454         bool enable_sdev_max_qd;
2455         u8 task_abort_tmo;
2456         u8 max_reset_tmo;
2457         u8 snapdump_wait_time;
2458 #ifdef CONFIG_DEBUG_FS
2459         struct dentry *debugfs_root;
2460         struct dentry *raidmap_dump;
2461 #endif
2462         u8 enable_fw_dev_list;
2463         bool atomic_desc_support;
2464         bool support_seqnum_jbod_fp;
2465         bool support_pci_lane_margining;
2466         u8  low_latency_index_start;
2467         int perf_mode;
2468         int iopoll_q_count;
2469 };
2470
2471 struct MR_LD_VF_MAP {
2472         u32 size;
2473         union MR_LD_REF ref;
2474         u8 ldVfCount;
2475         u8 reserved[6];
2476         u8 policy[1];
2477 };
2478
2479 struct MR_LD_VF_AFFILIATION {
2480         u32 size;
2481         u8 ldCount;
2482         u8 vfCount;
2483         u8 thisVf;
2484         u8 reserved[9];
2485         struct MR_LD_VF_MAP map[1];
2486 };
2487
2488 /* Plasma 1.11 FW backward compatibility structures */
2489 #define IOV_111_OFFSET 0x7CE
2490 #define MAX_VIRTUAL_FUNCTIONS 8
2491 #define MR_LD_ACCESS_HIDDEN 15
2492
2493 struct IOV_111 {
2494         u8 maxVFsSupported;
2495         u8 numVFsEnabled;
2496         u8 requestorId;
2497         u8 reserved[5];
2498 };
2499
2500 struct MR_LD_VF_MAP_111 {
2501         u8 targetId;
2502         u8 reserved[3];
2503         u8 policy[MAX_VIRTUAL_FUNCTIONS];
2504 };
2505
2506 struct MR_LD_VF_AFFILIATION_111 {
2507         u8 vdCount;
2508         u8 vfCount;
2509         u8 thisVf;
2510         u8 reserved[5];
2511         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2512 };
2513
2514 struct MR_CTRL_HB_HOST_MEM {
2515         struct {
2516                 u32 fwCounter;  /* Firmware heart beat counter */
2517                 struct {
2518                         u32 debugmode:1; /* 1=Firmware is in debug mode.
2519                                             Heart beat will not be updated. */
2520                         u32 reserved:31;
2521                 } debug;
2522                 u32 reserved_fw[6];
2523                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
2524                 u32 reserved_driver[7];
2525         } HB;
2526         u8 pad[0x400-0x40];
2527 };
2528
2529 enum {
2530         MEGASAS_HBA_OPERATIONAL                 = 0,
2531         MEGASAS_ADPRESET_SM_INFAULT             = 1,
2532         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
2533         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
2534         MEGASAS_HW_CRITICAL_ERROR               = 4,
2535         MEGASAS_ADPRESET_SM_POLLING             = 5,
2536         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
2537 };
2538
2539 struct megasas_instance_template {
2540         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2541                 u32, struct megasas_register_set __iomem *);
2542
2543         void (*enable_intr)(struct megasas_instance *);
2544         void (*disable_intr)(struct megasas_instance *);
2545
2546         int (*clear_intr)(struct megasas_instance *);
2547
2548         u32 (*read_fw_status_reg)(struct megasas_instance *);
2549         int (*adp_reset)(struct megasas_instance *, \
2550                 struct megasas_register_set __iomem *);
2551         int (*check_reset)(struct megasas_instance *, \
2552                 struct megasas_register_set __iomem *);
2553         irqreturn_t (*service_isr)(int irq, void *devp);
2554         void (*tasklet)(unsigned long);
2555         u32 (*init_adapter)(struct megasas_instance *);
2556         u32 (*build_and_issue_cmd) (struct megasas_instance *,
2557                                     struct scsi_cmnd *);
2558         void (*issue_dcmd)(struct megasas_instance *instance,
2559                             struct megasas_cmd *cmd);
2560 };
2561
2562 #define MEGASAS_IS_LOGICAL(sdev)                                        \
2563         ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2564
2565 #define MEGASAS_IS_LUN_VALID(sdev)                                      \
2566         (((sdev)->lun == 0) ? 1 : 0)
2567
2568 #define MEGASAS_DEV_INDEX(scp)                                          \
2569         (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +   \
2570         scp->device->id)
2571
2572 #define MEGASAS_PD_INDEX(scp)                                           \
2573         ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) +         \
2574         scp->device->id)
2575
2576 struct megasas_cmd {
2577
2578         union megasas_frame *frame;
2579         dma_addr_t frame_phys_addr;
2580         u8 *sense;
2581         dma_addr_t sense_phys_addr;
2582
2583         u32 index;
2584         u8 sync_cmd;
2585         u8 cmd_status_drv;
2586         u8 abort_aen;
2587         u8 retry_for_fw_reset;
2588
2589
2590         struct list_head list;
2591         struct scsi_cmnd *scmd;
2592         u8 flags;
2593
2594         struct megasas_instance *instance;
2595         union {
2596                 struct {
2597                         u16 smid;
2598                         u16 resvd;
2599                 } context;
2600                 u32 frame_count;
2601         };
2602 };
2603
2604 struct megasas_cmd_priv {
2605         void    *cmd_priv;
2606         u8      status;
2607 };
2608
2609 static inline struct megasas_cmd_priv *megasas_priv(struct scsi_cmnd *cmd)
2610 {
2611         return scsi_cmd_priv(cmd);
2612 }
2613
2614 #define MAX_MGMT_ADAPTERS               1024
2615 #define MAX_IOCTL_SGE                   16
2616
2617 struct megasas_iocpacket {
2618
2619         u16 host_no;
2620         u16 __pad1;
2621         u32 sgl_off;
2622         u32 sge_count;
2623         u32 sense_off;
2624         u32 sense_len;
2625         union {
2626                 u8 raw[128];
2627                 struct megasas_header hdr;
2628         } frame;
2629
2630         struct iovec sgl[MAX_IOCTL_SGE];
2631
2632 } __attribute__ ((packed));
2633
2634 struct megasas_aen {
2635         u16 host_no;
2636         u16 __pad1;
2637         u32 seq_num;
2638         u32 class_locale_word;
2639 } __attribute__ ((packed));
2640
2641 struct compat_megasas_iocpacket {
2642         u16 host_no;
2643         u16 __pad1;
2644         u32 sgl_off;
2645         u32 sge_count;
2646         u32 sense_off;
2647         u32 sense_len;
2648         union {
2649                 u8 raw[128];
2650                 struct megasas_header hdr;
2651         } frame;
2652         struct compat_iovec sgl[MAX_IOCTL_SGE];
2653 } __attribute__ ((packed));
2654
2655 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
2656
2657 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
2658 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
2659
2660 struct megasas_mgmt_info {
2661
2662         u16 count;
2663         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2664         int max_index;
2665 };
2666
2667 enum MEGASAS_OCR_CAUSE {
2668         FW_FAULT_OCR                    = 0,
2669         SCSIIO_TIMEOUT_OCR              = 1,
2670         MFI_IO_TIMEOUT_OCR              = 2,
2671 };
2672
2673 enum DCMD_RETURN_STATUS {
2674         DCMD_SUCCESS    = 0x00,
2675         DCMD_TIMEOUT    = 0x01,
2676         DCMD_FAILED     = 0x02,
2677         DCMD_BUSY       = 0x03,
2678         DCMD_INIT       = 0xff,
2679 };
2680
2681 u8
2682 MR_BuildRaidContext(struct megasas_instance *instance,
2683                     struct IO_REQUEST_INFO *io_info,
2684                     struct RAID_CONTEXT *pRAID_Context,
2685                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2686 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2687 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2688 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2689 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2690 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2691 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2692
2693 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2694                               struct LD_LOAD_BALANCE_INFO *lbInfo,
2695                               struct IO_REQUEST_INFO *in_info,
2696                               struct MR_DRV_RAID_MAP_ALL *drv_map);
2697 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2698         struct LD_LOAD_BALANCE_INFO *lbInfo);
2699 int megasas_get_ctrl_info(struct megasas_instance *instance);
2700 /* PD sequence */
2701 int
2702 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2703 void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2704                                            bool is_target_prop);
2705 int megasas_get_target_prop(struct megasas_instance *instance,
2706                             struct scsi_device *sdev);
2707 void megasas_get_snapdump_properties(struct megasas_instance *instance);
2708
2709 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2710         u8 crash_buf_state);
2711 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2712
2713 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2714         struct megasas_cmd_fusion *cmd);
2715 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2716         struct megasas_cmd *cmd, int timeout);
2717 void __megasas_return_cmd(struct megasas_instance *instance,
2718         struct megasas_cmd *cmd);
2719
2720 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2721         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2722 int megasas_cmd_type(struct scsi_cmnd *cmd);
2723 void megasas_setup_jbod_map(struct megasas_instance *instance);
2724
2725 void megasas_update_sdev_properties(struct scsi_device *sdev);
2726 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2727 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2728 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2729 u32 mega_mod64(u64 dividend, u32 divisor);
2730 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2731 void megasas_free_fusion_context(struct megasas_instance *instance);
2732 int megasas_fusion_start_watchdog(struct megasas_instance *instance);
2733 void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
2734
2735 void megasas_set_dma_settings(struct megasas_instance *instance,
2736                               struct megasas_dcmd_frame *dcmd,
2737                               dma_addr_t dma_addr, u32 dma_len);
2738 int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance,
2739                                      bool do_adp_reset,
2740                                      int ocr_context);
2741 int megasas_irqpoll(struct irq_poll *irqpoll, int budget);
2742 void megasas_dump_fusion_io(struct scsi_cmnd *scmd);
2743 u32 megasas_readl(struct megasas_instance *instance,
2744                   const volatile void __iomem *addr);
2745 struct megasas_cmd *megasas_get_cmd(struct megasas_instance *instance);
2746 void megasas_return_cmd(struct megasas_instance *instance,
2747                         struct megasas_cmd *cmd);
2748 int megasas_issue_polled(struct megasas_instance *instance,
2749                          struct megasas_cmd *cmd);
2750 void megaraid_sas_kill_hba(struct megasas_instance *instance);
2751 void megasas_check_and_restore_queue_depth(struct megasas_instance *instance);
2752 void megasas_start_timer(struct megasas_instance *instance);
2753 int megasas_sriov_start_heartbeat(struct megasas_instance *instance,
2754                                   int initial);
2755 int megasas_alloc_cmds(struct megasas_instance *instance);
2756 void megasas_free_cmds(struct megasas_instance *instance);
2757
2758 void megasas_init_debugfs(void);
2759 void megasas_exit_debugfs(void);
2760 void megasas_setup_debugfs(struct megasas_instance *instance);
2761 void megasas_destroy_debugfs(struct megasas_instance *instance);
2762 int megasas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
2763
2764 #endif                          /*LSI_MEGARAID_SAS_H */