1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
23 #include <uapi/scsi/fc/fc_els.h>
25 /* Macros to deal with bit fields. Each bit field must have 3 #defines
26 * associated with it (_SHIFT, _MASK, and _WORD).
27 * EG. For a bit field that is in the 7th bit of the "field4" field of a
28 * structure and is 2 bits in size the following #defines must exist:
34 * #define example_bit_field_SHIFT 7
35 * #define example_bit_field_MASK 0x03
36 * #define example_bit_field_WORD field4
39 * Then the macros below may be used to get or set the value of that field.
40 * EG. To get the value of the bit field from the above example:
42 * value = bf_get(example_bit_field, &t1);
43 * And then to set that bit field:
44 * bf_set(example_bit_field, &t1, 2);
45 * Or clear that bit field:
46 * bf_set(example_bit_field, &t1, 0);
48 #define bf_get_be32(name, ptr) \
49 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
50 #define bf_get_le32(name, ptr) \
51 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
52 #define bf_get(name, ptr) \
53 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
54 #define bf_set_le32(name, ptr, value) \
55 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
56 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
57 ~(name##_MASK << name##_SHIFT)))))
58 #define bf_set(name, ptr, value) \
59 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
60 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
67 struct lpfc_sli_intf {
69 #define lpfc_sli_intf_valid_SHIFT 29
70 #define lpfc_sli_intf_valid_MASK 0x00000007
71 #define lpfc_sli_intf_valid_WORD word0
72 #define LPFC_SLI_INTF_VALID 6
73 #define lpfc_sli_intf_sli_hint2_SHIFT 24
74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
75 #define lpfc_sli_intf_sli_hint2_WORD word0
76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
77 #define lpfc_sli_intf_sli_hint1_SHIFT 16
78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
79 #define lpfc_sli_intf_sli_hint1_WORD word0
80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
81 #define LPFC_SLI_INTF_SLI_HINT1_1 1
82 #define LPFC_SLI_INTF_SLI_HINT1_2 2
83 #define lpfc_sli_intf_if_type_SHIFT 12
84 #define lpfc_sli_intf_if_type_MASK 0x0000000F
85 #define lpfc_sli_intf_if_type_WORD word0
86 #define LPFC_SLI_INTF_IF_TYPE_0 0
87 #define LPFC_SLI_INTF_IF_TYPE_1 1
88 #define LPFC_SLI_INTF_IF_TYPE_2 2
89 #define LPFC_SLI_INTF_IF_TYPE_6 6
90 #define lpfc_sli_intf_sli_family_SHIFT 8
91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
92 #define lpfc_sli_intf_sli_family_WORD word0
93 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
94 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
95 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
96 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
97 #define lpfc_sli_intf_slirev_SHIFT 4
98 #define lpfc_sli_intf_slirev_MASK 0x0000000F
99 #define lpfc_sli_intf_slirev_WORD word0
100 #define LPFC_SLI_INTF_REV_SLI3 3
101 #define LPFC_SLI_INTF_REV_SLI4 4
102 #define lpfc_sli_intf_func_type_SHIFT 0
103 #define lpfc_sli_intf_func_type_MASK 0x00000001
104 #define lpfc_sli_intf_func_type_WORD word0
105 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
106 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1
109 #define LPFC_SLI4_MBX_EMBED true
110 #define LPFC_SLI4_MBX_NEMBED false
112 #define LPFC_SLI4_MB_WORD_COUNT 64
113 #define LPFC_MAX_MQ_PAGE 8
114 #define LPFC_MAX_WQ_PAGE_V0 4
115 #define LPFC_MAX_WQ_PAGE 8
116 #define LPFC_MAX_RQ_PAGE 8
117 #define LPFC_MAX_CQ_PAGE 4
118 #define LPFC_MAX_EQ_PAGE 8
120 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
121 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
122 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
124 /* Define SLI4 Alignment requirements. */
125 #define LPFC_ALIGN_16_BYTE 16
126 #define LPFC_ALIGN_64_BYTE 64
127 #define SLI4_PAGE_SIZE 4096
129 /* Define SLI4 specific definitions. */
130 #define LPFC_MQ_CQE_BYTE_OFFSET 256
131 #define LPFC_MBX_CMD_HDR_LENGTH 16
132 #define LPFC_MBX_ERROR_RANGE 0x4000
133 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
134 #define LPFC_BMBX_BIT1_ADDR_LO 0
135 #define LPFC_RPI_HDR_COUNT 64
136 #define LPFC_HDR_TEMPLATE_SIZE 4096
137 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
138 #define LPFC_FCF_RECORD_WD_CNT 132
139 #define LPFC_ENTIRE_FCF_DATABASE 0
140 #define LPFC_DFLT_FCF_INDEX 0
142 /* Virtual function numbers */
176 /* PCI function numbers */
177 #define LPFC_PCI_FUNC0 0
178 #define LPFC_PCI_FUNC1 1
179 #define LPFC_PCI_FUNC2 2
180 #define LPFC_PCI_FUNC3 3
181 #define LPFC_PCI_FUNC4 4
183 /* SLI4 interface type-2 PDEV_CTL register */
184 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
185 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
186 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
187 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
188 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
189 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
190 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
191 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
192 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000
194 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
196 /* Active interrupt test count */
197 #define LPFC_ACT_INTR_CNT 4
199 /* Algrithmns for scheduling FCP commands to WQs */
200 #define LPFC_FCP_SCHED_BY_HDWQ 0
201 #define LPFC_FCP_SCHED_BY_CPU 1
203 /* Algrithmns for NameServer Query after RSCN */
204 #define LPFC_NS_QUERY_GID_FT 0
205 #define LPFC_NS_QUERY_GID_PT 1
207 /* Delay Multiplier constant */
208 #define LPFC_DMULT_CONST 651042
209 #define LPFC_DMULT_MAX 1023
211 /* Configuration of Interrupts / sec for entire HBA port */
212 #define LPFC_MIN_IMAX 5000
213 #define LPFC_MAX_IMAX 5000000
214 #define LPFC_DEF_IMAX 0
216 #define LPFC_MAX_AUTO_EQ_DELAY 120
217 #define LPFC_EQ_DELAY_STEP 15
218 #define LPFC_EQD_ISR_TRIGGER 20000
220 #define LPFC_EQ_DELAY_MSECS 1000
222 #define LPFC_MIN_CPU_MAP 0
223 #define LPFC_MAX_CPU_MAP 1
224 #define LPFC_HBA_CPU_MAP 1
226 /* PORT_CAPABILITIES constants. */
227 #define LPFC_MAX_SUPPORTED_PAGES 8
233 #ifdef __BIG_ENDIAN_BITFIELD
234 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
236 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
237 #else /* __LITTLE_ENDIAN_BITFIELD */
238 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
239 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
242 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
243 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
244 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
245 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
246 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
247 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
248 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
255 /* Maximun size of immediate data that can fit into a 128 byte WQE */
256 #define LPFC_MAX_BDE_IMM_SIZE 64
258 struct lpfc_sli4_flags {
260 #define lpfc_idx_rsrc_rdy_SHIFT 0
261 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
262 #define lpfc_idx_rsrc_rdy_WORD word0
263 #define LPFC_IDX_RSRC_RDY 1
264 #define lpfc_rpi_rsrc_rdy_SHIFT 1
265 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
266 #define lpfc_rpi_rsrc_rdy_WORD word0
267 #define LPFC_RPI_RSRC_RDY 1
268 #define lpfc_vpi_rsrc_rdy_SHIFT 2
269 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
270 #define lpfc_vpi_rsrc_rdy_WORD word0
271 #define LPFC_VPI_RSRC_RDY 1
272 #define lpfc_vfi_rsrc_rdy_SHIFT 3
273 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
274 #define lpfc_vfi_rsrc_rdy_WORD word0
275 #define LPFC_VFI_RSRC_RDY 1
278 struct sli4_bls_rsp {
279 uint32_t word0_rsvd; /* Word0 must be reserved */
281 #define lpfc_abts_orig_SHIFT 0
282 #define lpfc_abts_orig_MASK 0x00000001
283 #define lpfc_abts_orig_WORD word1
284 #define LPFC_ABTS_UNSOL_RSP 1
285 #define LPFC_ABTS_UNSOL_INT 0
287 #define lpfc_abts_rxid_SHIFT 0
288 #define lpfc_abts_rxid_MASK 0x0000FFFF
289 #define lpfc_abts_rxid_WORD word2
290 #define lpfc_abts_oxid_SHIFT 16
291 #define lpfc_abts_oxid_MASK 0x0000FFFF
292 #define lpfc_abts_oxid_WORD word2
294 #define lpfc_vndr_code_SHIFT 0
295 #define lpfc_vndr_code_MASK 0x000000FF
296 #define lpfc_vndr_code_WORD word3
297 #define lpfc_rsn_expln_SHIFT 8
298 #define lpfc_rsn_expln_MASK 0x000000FF
299 #define lpfc_rsn_expln_WORD word3
300 #define lpfc_rsn_code_SHIFT 16
301 #define lpfc_rsn_code_MASK 0x000000FF
302 #define lpfc_rsn_code_WORD word3
305 uint32_t word5_rsvd; /* Word5 must be reserved */
308 /* event queue entry structure */
311 #define lpfc_eqe_resource_id_SHIFT 16
312 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
313 #define lpfc_eqe_resource_id_WORD word0
314 #define lpfc_eqe_minor_code_SHIFT 4
315 #define lpfc_eqe_minor_code_MASK 0x00000FFF
316 #define lpfc_eqe_minor_code_WORD word0
317 #define lpfc_eqe_major_code_SHIFT 1
318 #define lpfc_eqe_major_code_MASK 0x00000007
319 #define lpfc_eqe_major_code_WORD word0
320 #define lpfc_eqe_valid_SHIFT 0
321 #define lpfc_eqe_valid_MASK 0x00000001
322 #define lpfc_eqe_valid_WORD word0
325 /* completion queue entry structure (common fields for all cqe types) */
331 #define lpfc_cqe_valid_SHIFT 31
332 #define lpfc_cqe_valid_MASK 0x00000001
333 #define lpfc_cqe_valid_WORD word3
334 #define lpfc_cqe_code_SHIFT 16
335 #define lpfc_cqe_code_MASK 0x000000FF
336 #define lpfc_cqe_code_WORD word3
339 /* Completion Queue Entry Status Codes */
340 #define CQE_STATUS_SUCCESS 0x0
341 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
342 #define CQE_STATUS_REMOTE_STOP 0x2
343 #define CQE_STATUS_LOCAL_REJECT 0x3
344 #define CQE_STATUS_NPORT_RJT 0x4
345 #define CQE_STATUS_FABRIC_RJT 0x5
346 #define CQE_STATUS_NPORT_BSY 0x6
347 #define CQE_STATUS_FABRIC_BSY 0x7
348 #define CQE_STATUS_INTERMED_RSP 0x8
349 #define CQE_STATUS_LS_RJT 0x9
350 #define CQE_STATUS_CMD_REJECT 0xb
351 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
352 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
353 #define CQE_STATUS_DI_ERROR 0x16
355 /* Used when mapping CQE status to IOCB */
356 #define LPFC_IOCB_STATUS_MASK 0xf
358 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
359 #define CQE_HW_STATUS_NO_ERR 0x0
360 #define CQE_HW_STATUS_UNDERRUN 0x1
361 #define CQE_HW_STATUS_OVERRUN 0x2
363 /* Completion Queue Entry Codes */
364 #define CQE_CODE_COMPL_WQE 0x1
365 #define CQE_CODE_RELEASE_WQE 0x2
366 #define CQE_CODE_RECEIVE 0x4
367 #define CQE_CODE_XRI_ABORTED 0x5
368 #define CQE_CODE_RECEIVE_V1 0x9
369 #define CQE_CODE_NVME_ERSP 0xd
372 * Define mask value for xri_aborted and wcqe completed CQE extended status.
373 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
375 #define WCQE_PARAM_MASK 0x1FF
377 /* completion queue entry for wqe completions */
378 struct lpfc_wcqe_complete {
380 #define lpfc_wcqe_c_request_tag_SHIFT 16
381 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
382 #define lpfc_wcqe_c_request_tag_WORD word0
383 #define lpfc_wcqe_c_status_SHIFT 8
384 #define lpfc_wcqe_c_status_MASK 0x000000FF
385 #define lpfc_wcqe_c_status_WORD word0
386 #define lpfc_wcqe_c_hw_status_SHIFT 0
387 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
388 #define lpfc_wcqe_c_hw_status_WORD word0
389 #define lpfc_wcqe_c_ersp0_SHIFT 0
390 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
391 #define lpfc_wcqe_c_ersp0_WORD word0
392 uint32_t total_data_placed;
394 #define lpfc_wcqe_c_bg_edir_SHIFT 5
395 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
396 #define lpfc_wcqe_c_bg_edir_WORD parameter
397 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3
398 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
399 #define lpfc_wcqe_c_bg_tdpv_WORD parameter
400 #define lpfc_wcqe_c_bg_re_SHIFT 2
401 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
402 #define lpfc_wcqe_c_bg_re_WORD parameter
403 #define lpfc_wcqe_c_bg_ae_SHIFT 1
404 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
405 #define lpfc_wcqe_c_bg_ae_WORD parameter
406 #define lpfc_wcqe_c_bg_ge_SHIFT 0
407 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
408 #define lpfc_wcqe_c_bg_ge_WORD parameter
410 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
411 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
412 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
413 #define lpfc_wcqe_c_xb_SHIFT 28
414 #define lpfc_wcqe_c_xb_MASK 0x00000001
415 #define lpfc_wcqe_c_xb_WORD word3
416 #define lpfc_wcqe_c_pv_SHIFT 27
417 #define lpfc_wcqe_c_pv_MASK 0x00000001
418 #define lpfc_wcqe_c_pv_WORD word3
419 #define lpfc_wcqe_c_priority_SHIFT 24
420 #define lpfc_wcqe_c_priority_MASK 0x00000007
421 #define lpfc_wcqe_c_priority_WORD word3
422 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
423 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
424 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
425 #define lpfc_wcqe_c_sqhead_SHIFT 0
426 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
427 #define lpfc_wcqe_c_sqhead_WORD word3
430 /* completion queue entry for wqe release */
431 struct lpfc_wcqe_release {
435 #define lpfc_wcqe_r_wq_id_SHIFT 16
436 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
437 #define lpfc_wcqe_r_wq_id_WORD word2
438 #define lpfc_wcqe_r_wqe_index_SHIFT 0
439 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
440 #define lpfc_wcqe_r_wqe_index_WORD word2
442 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
443 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
444 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
445 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
446 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
447 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
450 struct sli4_wcqe_xri_aborted {
452 #define lpfc_wcqe_xa_status_SHIFT 8
453 #define lpfc_wcqe_xa_status_MASK 0x000000FF
454 #define lpfc_wcqe_xa_status_WORD word0
457 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
458 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
459 #define lpfc_wcqe_xa_remote_xid_WORD word2
460 #define lpfc_wcqe_xa_xri_SHIFT 0
461 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
462 #define lpfc_wcqe_xa_xri_WORD word2
464 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
465 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
466 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
467 #define lpfc_wcqe_xa_ia_SHIFT 30
468 #define lpfc_wcqe_xa_ia_MASK 0x00000001
469 #define lpfc_wcqe_xa_ia_WORD word3
470 #define CQE_XRI_ABORTED_IA_REMOTE 0
471 #define CQE_XRI_ABORTED_IA_LOCAL 1
472 #define lpfc_wcqe_xa_br_SHIFT 29
473 #define lpfc_wcqe_xa_br_MASK 0x00000001
474 #define lpfc_wcqe_xa_br_WORD word3
475 #define CQE_XRI_ABORTED_BR_BA_ACC 0
476 #define CQE_XRI_ABORTED_BR_BA_RJT 1
477 #define lpfc_wcqe_xa_eo_SHIFT 28
478 #define lpfc_wcqe_xa_eo_MASK 0x00000001
479 #define lpfc_wcqe_xa_eo_WORD word3
480 #define CQE_XRI_ABORTED_EO_REMOTE 0
481 #define CQE_XRI_ABORTED_EO_LOCAL 1
482 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
483 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
484 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
487 /* completion queue entry structure for rqe completion */
490 #define lpfc_rcqe_bindex_SHIFT 16
491 #define lpfc_rcqe_bindex_MASK 0x0000FFF
492 #define lpfc_rcqe_bindex_WORD word0
493 #define lpfc_rcqe_status_SHIFT 8
494 #define lpfc_rcqe_status_MASK 0x000000FF
495 #define lpfc_rcqe_status_WORD word0
496 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
497 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
498 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
499 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
501 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
502 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
503 #define lpfc_rcqe_fcf_id_v1_WORD word1
505 #define lpfc_rcqe_length_SHIFT 16
506 #define lpfc_rcqe_length_MASK 0x0000FFFF
507 #define lpfc_rcqe_length_WORD word2
508 #define lpfc_rcqe_rq_id_SHIFT 6
509 #define lpfc_rcqe_rq_id_MASK 0x000003FF
510 #define lpfc_rcqe_rq_id_WORD word2
511 #define lpfc_rcqe_fcf_id_SHIFT 0
512 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
513 #define lpfc_rcqe_fcf_id_WORD word2
514 #define lpfc_rcqe_rq_id_v1_SHIFT 0
515 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
516 #define lpfc_rcqe_rq_id_v1_WORD word2
518 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
519 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
520 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
521 #define lpfc_rcqe_port_SHIFT 30
522 #define lpfc_rcqe_port_MASK 0x00000001
523 #define lpfc_rcqe_port_WORD word3
524 #define lpfc_rcqe_hdr_length_SHIFT 24
525 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
526 #define lpfc_rcqe_hdr_length_WORD word3
527 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
528 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
529 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
530 #define lpfc_rcqe_eof_SHIFT 8
531 #define lpfc_rcqe_eof_MASK 0x000000FF
532 #define lpfc_rcqe_eof_WORD word3
533 #define FCOE_EOFn 0x41
534 #define FCOE_EOFt 0x42
535 #define FCOE_EOFni 0x49
536 #define FCOE_EOFa 0x50
537 #define lpfc_rcqe_sof_SHIFT 0
538 #define lpfc_rcqe_sof_MASK 0x000000FF
539 #define lpfc_rcqe_sof_WORD word3
540 #define FCOE_SOFi2 0x2d
541 #define FCOE_SOFi3 0x2e
542 #define FCOE_SOFn2 0x35
543 #define FCOE_SOFn3 0x36
551 /* buffer descriptors */
556 #define lpfc_bde4_last_SHIFT 31
557 #define lpfc_bde4_last_MASK 0x00000001
558 #define lpfc_bde4_last_WORD word2
559 #define lpfc_bde4_sge_offset_SHIFT 0
560 #define lpfc_bde4_sge_offset_MASK 0x000003FF
561 #define lpfc_bde4_sge_offset_WORD word2
563 #define lpfc_bde4_length_SHIFT 0
564 #define lpfc_bde4_length_MASK 0x000000FF
565 #define lpfc_bde4_length_WORD word3
568 struct lpfc_register {
572 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
573 #define LPFC_PORT_SEM_MASK 0xF000
574 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
575 #define LPFC_UERR_STATUS_HI 0x00A4
576 #define LPFC_UERR_STATUS_LO 0x00A0
577 #define LPFC_UE_MASK_HI 0x00AC
578 #define LPFC_UE_MASK_LO 0x00A8
580 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
581 #define LPFC_SLI_INTF 0x0058
582 #define LPFC_SLI_ASIC_VER 0x009C
584 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
585 #define lpfc_port_smphr_perr_SHIFT 31
586 #define lpfc_port_smphr_perr_MASK 0x1
587 #define lpfc_port_smphr_perr_WORD word0
588 #define lpfc_port_smphr_sfi_SHIFT 30
589 #define lpfc_port_smphr_sfi_MASK 0x1
590 #define lpfc_port_smphr_sfi_WORD word0
591 #define lpfc_port_smphr_nip_SHIFT 29
592 #define lpfc_port_smphr_nip_MASK 0x1
593 #define lpfc_port_smphr_nip_WORD word0
594 #define lpfc_port_smphr_ipc_SHIFT 28
595 #define lpfc_port_smphr_ipc_MASK 0x1
596 #define lpfc_port_smphr_ipc_WORD word0
597 #define lpfc_port_smphr_scr1_SHIFT 27
598 #define lpfc_port_smphr_scr1_MASK 0x1
599 #define lpfc_port_smphr_scr1_WORD word0
600 #define lpfc_port_smphr_scr2_SHIFT 26
601 #define lpfc_port_smphr_scr2_MASK 0x1
602 #define lpfc_port_smphr_scr2_WORD word0
603 #define lpfc_port_smphr_host_scratch_SHIFT 16
604 #define lpfc_port_smphr_host_scratch_MASK 0xFF
605 #define lpfc_port_smphr_host_scratch_WORD word0
606 #define lpfc_port_smphr_port_status_SHIFT 0
607 #define lpfc_port_smphr_port_status_MASK 0xFFFF
608 #define lpfc_port_smphr_port_status_WORD word0
610 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
611 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
612 #define LPFC_POST_STAGE_HOST_RDY 0x0002
613 #define LPFC_POST_STAGE_BE_RESET 0x0003
614 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
615 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
616 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
617 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
618 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
619 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
620 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
621 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
622 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
623 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
624 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
625 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
626 #define LPFC_POST_STAGE_ARMFW_START 0x0800
627 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
628 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
629 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
630 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
631 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
632 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
633 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
634 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
635 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
636 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
637 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
638 #define LPFC_POST_STAGE_RC_DONE 0x0B07
639 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
640 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
641 #define LPFC_POST_STAGE_PORT_READY 0xC000
642 #define LPFC_POST_STAGE_PORT_UE 0xF000
644 #define LPFC_CTL_PORT_STA_OFFSET 0x404
645 #define lpfc_sliport_status_err_SHIFT 31
646 #define lpfc_sliport_status_err_MASK 0x1
647 #define lpfc_sliport_status_err_WORD word0
648 #define lpfc_sliport_status_end_SHIFT 30
649 #define lpfc_sliport_status_end_MASK 0x1
650 #define lpfc_sliport_status_end_WORD word0
651 #define lpfc_sliport_status_oti_SHIFT 29
652 #define lpfc_sliport_status_oti_MASK 0x1
653 #define lpfc_sliport_status_oti_WORD word0
654 #define lpfc_sliport_status_dip_SHIFT 25
655 #define lpfc_sliport_status_dip_MASK 0x1
656 #define lpfc_sliport_status_dip_WORD word0
657 #define lpfc_sliport_status_rn_SHIFT 24
658 #define lpfc_sliport_status_rn_MASK 0x1
659 #define lpfc_sliport_status_rn_WORD word0
660 #define lpfc_sliport_status_rdy_SHIFT 23
661 #define lpfc_sliport_status_rdy_MASK 0x1
662 #define lpfc_sliport_status_rdy_WORD word0
663 #define MAX_IF_TYPE_2_RESETS 6
665 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
666 #define lpfc_sliport_ctrl_end_SHIFT 30
667 #define lpfc_sliport_ctrl_end_MASK 0x1
668 #define lpfc_sliport_ctrl_end_WORD word0
669 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
670 #define LPFC_SLIPORT_BIG_ENDIAN 1
671 #define lpfc_sliport_ctrl_ip_SHIFT 27
672 #define lpfc_sliport_ctrl_ip_MASK 0x1
673 #define lpfc_sliport_ctrl_ip_WORD word0
674 #define LPFC_SLIPORT_INIT_PORT 1
676 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
677 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
679 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
680 #define lpfc_sliport_eqdelay_delay_SHIFT 16
681 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
682 #define lpfc_sliport_eqdelay_delay_WORD word0
683 #define lpfc_sliport_eqdelay_id_SHIFT 0
684 #define lpfc_sliport_eqdelay_id_MASK 0xfff
685 #define lpfc_sliport_eqdelay_id_WORD word0
686 #define LPFC_SEC_TO_USEC 1000000
688 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
691 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
693 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
694 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
696 #define LPFC_HST_ISR0 0x0C18
697 #define LPFC_HST_ISR1 0x0C1C
698 #define LPFC_HST_ISR2 0x0C20
699 #define LPFC_HST_ISR3 0x0C24
700 #define LPFC_HST_ISR4 0x0C28
702 #define LPFC_HST_IMR0 0x0C48
703 #define LPFC_HST_IMR1 0x0C4C
704 #define LPFC_HST_IMR2 0x0C50
705 #define LPFC_HST_IMR3 0x0C54
706 #define LPFC_HST_IMR4 0x0C58
708 #define LPFC_HST_ISCR0 0x0C78
709 #define LPFC_HST_ISCR1 0x0C7C
710 #define LPFC_HST_ISCR2 0x0C80
711 #define LPFC_HST_ISCR3 0x0C84
712 #define LPFC_HST_ISCR4 0x0C88
714 #define LPFC_SLI4_INTR0 BIT0
715 #define LPFC_SLI4_INTR1 BIT1
716 #define LPFC_SLI4_INTR2 BIT2
717 #define LPFC_SLI4_INTR3 BIT3
718 #define LPFC_SLI4_INTR4 BIT4
719 #define LPFC_SLI4_INTR5 BIT5
720 #define LPFC_SLI4_INTR6 BIT6
721 #define LPFC_SLI4_INTR7 BIT7
722 #define LPFC_SLI4_INTR8 BIT8
723 #define LPFC_SLI4_INTR9 BIT9
724 #define LPFC_SLI4_INTR10 BIT10
725 #define LPFC_SLI4_INTR11 BIT11
726 #define LPFC_SLI4_INTR12 BIT12
727 #define LPFC_SLI4_INTR13 BIT13
728 #define LPFC_SLI4_INTR14 BIT14
729 #define LPFC_SLI4_INTR15 BIT15
730 #define LPFC_SLI4_INTR16 BIT16
731 #define LPFC_SLI4_INTR17 BIT17
732 #define LPFC_SLI4_INTR18 BIT18
733 #define LPFC_SLI4_INTR19 BIT19
734 #define LPFC_SLI4_INTR20 BIT20
735 #define LPFC_SLI4_INTR21 BIT21
736 #define LPFC_SLI4_INTR22 BIT22
737 #define LPFC_SLI4_INTR23 BIT23
738 #define LPFC_SLI4_INTR24 BIT24
739 #define LPFC_SLI4_INTR25 BIT25
740 #define LPFC_SLI4_INTR26 BIT26
741 #define LPFC_SLI4_INTR27 BIT27
742 #define LPFC_SLI4_INTR28 BIT28
743 #define LPFC_SLI4_INTR29 BIT29
744 #define LPFC_SLI4_INTR30 BIT30
745 #define LPFC_SLI4_INTR31 BIT31
748 * The Doorbell registers defined here exist in different BAR
749 * register sets depending on the UCNA Port's reported if_type
750 * value. For UCNA ports running SLI4 and if_type 0, they reside in
751 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
752 * BAR0. For FC ports running SLI4 and if_type 6, they reside in
753 * BAR2. The offsets and base address are different, so the driver
754 * has to compute the register addresses accordingly
756 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
757 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
758 #define LPFC_IF6_RQ_DOORBELL 0x0080
759 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24
760 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
761 #define lpfc_rq_db_list_fm_num_posted_WORD word0
762 #define lpfc_rq_db_list_fm_index_SHIFT 16
763 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
764 #define lpfc_rq_db_list_fm_index_WORD word0
765 #define lpfc_rq_db_list_fm_id_SHIFT 0
766 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
767 #define lpfc_rq_db_list_fm_id_WORD word0
768 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16
769 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
770 #define lpfc_rq_db_ring_fm_num_posted_WORD word0
771 #define lpfc_rq_db_ring_fm_id_SHIFT 0
772 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
773 #define lpfc_rq_db_ring_fm_id_WORD word0
775 #define LPFC_ULP0_WQ_DOORBELL 0x0040
776 #define LPFC_ULP1_WQ_DOORBELL 0x0060
777 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24
778 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
779 #define lpfc_wq_db_list_fm_num_posted_WORD word0
780 #define lpfc_wq_db_list_fm_index_SHIFT 16
781 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
782 #define lpfc_wq_db_list_fm_index_WORD word0
783 #define lpfc_wq_db_list_fm_id_SHIFT 0
784 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
785 #define lpfc_wq_db_list_fm_id_WORD word0
786 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16
787 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
788 #define lpfc_wq_db_ring_fm_num_posted_WORD word0
789 #define lpfc_wq_db_ring_fm_id_SHIFT 0
790 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
791 #define lpfc_wq_db_ring_fm_id_WORD word0
793 #define LPFC_IF6_WQ_DOORBELL 0x0040
794 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24
795 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
796 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0
797 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23
798 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
799 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0
800 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16
801 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
802 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0
803 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
804 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
805 #define lpfc_if6_wq_db_list_fm_id_WORD word0
807 #define LPFC_EQCQ_DOORBELL 0x0120
808 #define lpfc_eqcq_doorbell_se_SHIFT 31
809 #define lpfc_eqcq_doorbell_se_MASK 0x0001
810 #define lpfc_eqcq_doorbell_se_WORD word0
811 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
812 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
813 #define lpfc_eqcq_doorbell_arm_SHIFT 29
814 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
815 #define lpfc_eqcq_doorbell_arm_WORD word0
816 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
817 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
818 #define lpfc_eqcq_doorbell_num_released_WORD word0
819 #define lpfc_eqcq_doorbell_qt_SHIFT 10
820 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
821 #define lpfc_eqcq_doorbell_qt_WORD word0
822 #define LPFC_QUEUE_TYPE_COMPLETION 0
823 #define LPFC_QUEUE_TYPE_EVENT 1
824 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
825 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
826 #define lpfc_eqcq_doorbell_eqci_WORD word0
827 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
828 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
829 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0
830 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
831 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
832 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0
833 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
834 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
835 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0
836 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
837 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
838 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0
839 #define LPFC_CQID_HI_FIELD_SHIFT 10
840 #define LPFC_EQID_HI_FIELD_SHIFT 9
842 #define LPFC_IF6_CQ_DOORBELL 0x00C0
843 #define lpfc_if6_cq_doorbell_se_SHIFT 31
844 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
845 #define lpfc_if6_cq_doorbell_se_WORD word0
846 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
847 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1
848 #define lpfc_if6_cq_doorbell_arm_SHIFT 29
849 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
850 #define lpfc_if6_cq_doorbell_arm_WORD word0
851 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16
852 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
853 #define lpfc_if6_cq_doorbell_num_released_WORD word0
854 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
855 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
856 #define lpfc_if6_cq_doorbell_cqid_WORD word0
858 #define LPFC_IF6_EQ_DOORBELL 0x0120
859 #define lpfc_if6_eq_doorbell_io_SHIFT 31
860 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
861 #define lpfc_if6_eq_doorbell_io_WORD word0
862 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
863 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1
864 #define lpfc_if6_eq_doorbell_arm_SHIFT 29
865 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
866 #define lpfc_if6_eq_doorbell_arm_WORD word0
867 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16
868 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
869 #define lpfc_if6_eq_doorbell_num_released_WORD word0
870 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
871 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
872 #define lpfc_if6_eq_doorbell_eqid_WORD word0
874 #define LPFC_BMBX 0x0160
875 #define lpfc_bmbx_addr_SHIFT 2
876 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
877 #define lpfc_bmbx_addr_WORD word0
878 #define lpfc_bmbx_hi_SHIFT 1
879 #define lpfc_bmbx_hi_MASK 0x0001
880 #define lpfc_bmbx_hi_WORD word0
881 #define lpfc_bmbx_rdy_SHIFT 0
882 #define lpfc_bmbx_rdy_MASK 0x0001
883 #define lpfc_bmbx_rdy_WORD word0
885 #define LPFC_MQ_DOORBELL 0x0140
886 #define LPFC_IF6_MQ_DOORBELL 0x0160
887 #define lpfc_mq_doorbell_num_posted_SHIFT 16
888 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
889 #define lpfc_mq_doorbell_num_posted_WORD word0
890 #define lpfc_mq_doorbell_id_SHIFT 0
891 #define lpfc_mq_doorbell_id_MASK 0xFFFF
892 #define lpfc_mq_doorbell_id_WORD word0
894 struct lpfc_sli4_cfg_mhdr {
896 #define lpfc_mbox_hdr_emb_SHIFT 0
897 #define lpfc_mbox_hdr_emb_MASK 0x00000001
898 #define lpfc_mbox_hdr_emb_WORD word1
899 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
900 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
901 #define lpfc_mbox_hdr_sge_cnt_WORD word1
902 uint32_t payload_length;
908 union lpfc_sli4_cfg_shdr {
911 #define lpfc_mbox_hdr_opcode_SHIFT 0
912 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
913 #define lpfc_mbox_hdr_opcode_WORD word6
914 #define lpfc_mbox_hdr_subsystem_SHIFT 8
915 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
916 #define lpfc_mbox_hdr_subsystem_WORD word6
917 #define lpfc_mbox_hdr_port_number_SHIFT 16
918 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
919 #define lpfc_mbox_hdr_port_number_WORD word6
920 #define lpfc_mbox_hdr_domain_SHIFT 24
921 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
922 #define lpfc_mbox_hdr_domain_WORD word6
924 uint32_t request_length;
926 #define lpfc_mbox_hdr_version_SHIFT 0
927 #define lpfc_mbox_hdr_version_MASK 0x000000FF
928 #define lpfc_mbox_hdr_version_WORD word9
929 #define lpfc_mbox_hdr_pf_num_SHIFT 16
930 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
931 #define lpfc_mbox_hdr_pf_num_WORD word9
932 #define lpfc_mbox_hdr_vh_num_SHIFT 24
933 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
934 #define lpfc_mbox_hdr_vh_num_WORD word9
935 #define LPFC_Q_CREATE_VERSION_2 2
936 #define LPFC_Q_CREATE_VERSION_1 1
937 #define LPFC_Q_CREATE_VERSION_0 0
938 #define LPFC_OPCODE_VERSION_0 0
939 #define LPFC_OPCODE_VERSION_1 1
943 #define lpfc_mbox_hdr_opcode_SHIFT 0
944 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
945 #define lpfc_mbox_hdr_opcode_WORD word6
946 #define lpfc_mbox_hdr_subsystem_SHIFT 8
947 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
948 #define lpfc_mbox_hdr_subsystem_WORD word6
949 #define lpfc_mbox_hdr_domain_SHIFT 24
950 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
951 #define lpfc_mbox_hdr_domain_WORD word6
953 #define lpfc_mbox_hdr_status_SHIFT 0
954 #define lpfc_mbox_hdr_status_MASK 0x000000FF
955 #define lpfc_mbox_hdr_status_WORD word7
956 #define lpfc_mbox_hdr_add_status_SHIFT 8
957 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
958 #define lpfc_mbox_hdr_add_status_WORD word7
959 uint32_t response_length;
960 uint32_t actual_response_length;
964 /* Mailbox Header structures.
965 * struct mbox_header is defined for first generation SLI4_CFG mailbox
966 * calls deployed for BE-based ports.
968 * struct sli4_mbox_header is defined for second generation SLI4
969 * ports that don't deploy the SLI4_CFG mechanism.
972 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
973 union lpfc_sli4_cfg_shdr cfg_shdr;
976 #define LPFC_EXTENT_LOCAL 0
977 #define LPFC_TIMEOUT_DEFAULT 0
978 #define LPFC_EXTENT_VERSION_DEFAULT 0
980 /* Subsystem Definitions */
981 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
982 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
983 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB
984 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
986 /* Device Specific Definitions */
988 /* The HOST ENDIAN defines are in Big Endian format. */
989 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
990 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
993 #define LPFC_MBOX_OPCODE_NA 0x00
994 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
995 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
996 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
997 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
998 #define LPFC_MBOX_OPCODE_NOP 0x21
999 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
1000 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
1001 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1002 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
1003 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
1004 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
1005 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1006 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
1007 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
1008 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
1009 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
1010 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
1011 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
1012 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
1013 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
1014 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
1015 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1016 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1017 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1018 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1019 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1020 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1021 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1022 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1023 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1024 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1025 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1026 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1027 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1028 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1029 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1030 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1031 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1034 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1035 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1036 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1037 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1038 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1039 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1040 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1041 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1042 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1043 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1044 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1045 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1046 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1047 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1048 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1049 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42
1051 /* Low level Opcodes */
1052 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37
1054 /* Mailbox command structures */
1057 #define lpfc_eq_context_size_SHIFT 31
1058 #define lpfc_eq_context_size_MASK 0x00000001
1059 #define lpfc_eq_context_size_WORD word0
1060 #define LPFC_EQE_SIZE_4 0x0
1061 #define LPFC_EQE_SIZE_16 0x1
1062 #define lpfc_eq_context_valid_SHIFT 29
1063 #define lpfc_eq_context_valid_MASK 0x00000001
1064 #define lpfc_eq_context_valid_WORD word0
1065 #define lpfc_eq_context_autovalid_SHIFT 28
1066 #define lpfc_eq_context_autovalid_MASK 0x00000001
1067 #define lpfc_eq_context_autovalid_WORD word0
1069 #define lpfc_eq_context_count_SHIFT 26
1070 #define lpfc_eq_context_count_MASK 0x00000003
1071 #define lpfc_eq_context_count_WORD word1
1072 #define LPFC_EQ_CNT_256 0x0
1073 #define LPFC_EQ_CNT_512 0x1
1074 #define LPFC_EQ_CNT_1024 0x2
1075 #define LPFC_EQ_CNT_2048 0x3
1076 #define LPFC_EQ_CNT_4096 0x4
1078 #define lpfc_eq_context_delay_multi_SHIFT 13
1079 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1080 #define lpfc_eq_context_delay_multi_WORD word2
1084 struct eq_delay_info {
1087 uint32_t delay_multi;
1089 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8
1091 struct sgl_page_pairs {
1092 uint32_t sgl_pg0_addr_lo;
1093 uint32_t sgl_pg0_addr_hi;
1094 uint32_t sgl_pg1_addr_lo;
1095 uint32_t sgl_pg1_addr_hi;
1098 struct lpfc_mbx_post_sgl_pages {
1099 struct mbox_header header;
1101 #define lpfc_post_sgl_pages_xri_SHIFT 0
1102 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1103 #define lpfc_post_sgl_pages_xri_WORD word0
1104 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
1105 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1106 #define lpfc_post_sgl_pages_xricnt_WORD word0
1107 struct sgl_page_pairs sgl_pg_pairs[1];
1110 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1111 struct lpfc_mbx_post_uembed_sgl_page1 {
1112 union lpfc_sli4_cfg_shdr cfg_shdr;
1114 struct sgl_page_pairs sgl_pg_pairs;
1117 struct lpfc_mbx_sge {
1123 struct lpfc_mbx_nembed_cmd {
1124 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1125 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
1126 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1129 struct lpfc_mbx_nembed_sge_virt {
1130 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1133 struct lpfc_mbx_eq_create {
1134 struct mbox_header header;
1138 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1139 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1140 #define lpfc_mbx_eq_create_num_pages_WORD word0
1141 struct eq_context context;
1142 struct dma_address page[LPFC_MAX_EQ_PAGE];
1146 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1147 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1148 #define lpfc_mbx_eq_create_q_id_WORD word0
1153 struct lpfc_mbx_modify_eq_delay {
1154 struct mbox_header header;
1158 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1166 struct lpfc_mbx_eq_destroy {
1167 struct mbox_header header;
1171 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1172 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1173 #define lpfc_mbx_eq_destroy_q_id_WORD word0
1181 struct lpfc_mbx_nop {
1182 struct mbox_header header;
1183 uint32_t context[2];
1188 struct lpfc_mbx_set_ras_fwlog {
1189 struct mbox_header header;
1193 #define lpfc_fwlog_enable_SHIFT 0
1194 #define lpfc_fwlog_enable_MASK 0x00000001
1195 #define lpfc_fwlog_enable_WORD word4
1196 #define lpfc_fwlog_loglvl_SHIFT 8
1197 #define lpfc_fwlog_loglvl_MASK 0x0000000F
1198 #define lpfc_fwlog_loglvl_WORD word4
1199 #define lpfc_fwlog_ra_SHIFT 15
1200 #define lpfc_fwlog_ra_WORD 0x00000008
1201 #define lpfc_fwlog_buffcnt_SHIFT 16
1202 #define lpfc_fwlog_buffcnt_MASK 0x000000FF
1203 #define lpfc_fwlog_buffcnt_WORD word4
1204 #define lpfc_fwlog_buffsz_SHIFT 24
1205 #define lpfc_fwlog_buffsz_MASK 0x000000FF
1206 #define lpfc_fwlog_buffsz_WORD word4
1208 #define lpfc_fwlog_acqe_SHIFT 0
1209 #define lpfc_fwlog_acqe_MASK 0x0000FFFF
1210 #define lpfc_fwlog_acqe_WORD word5
1211 #define lpfc_fwlog_cqid_SHIFT 16
1212 #define lpfc_fwlog_cqid_MASK 0x0000FFFF
1213 #define lpfc_fwlog_cqid_WORD word5
1214 #define LPFC_MAX_FWLOG_PAGE 16
1215 struct dma_address lwpd;
1216 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE];
1227 #define lpfc_cq_context_event_SHIFT 31
1228 #define lpfc_cq_context_event_MASK 0x00000001
1229 #define lpfc_cq_context_event_WORD word0
1230 #define lpfc_cq_context_valid_SHIFT 29
1231 #define lpfc_cq_context_valid_MASK 0x00000001
1232 #define lpfc_cq_context_valid_WORD word0
1233 #define lpfc_cq_context_count_SHIFT 27
1234 #define lpfc_cq_context_count_MASK 0x00000003
1235 #define lpfc_cq_context_count_WORD word0
1236 #define LPFC_CQ_CNT_256 0x0
1237 #define LPFC_CQ_CNT_512 0x1
1238 #define LPFC_CQ_CNT_1024 0x2
1239 #define LPFC_CQ_CNT_WORD7 0x3
1240 #define lpfc_cq_context_autovalid_SHIFT 15
1241 #define lpfc_cq_context_autovalid_MASK 0x00000001
1242 #define lpfc_cq_context_autovalid_WORD word0
1244 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1245 #define lpfc_cq_eq_id_MASK 0x000000FF
1246 #define lpfc_cq_eq_id_WORD word1
1247 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1248 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1249 #define lpfc_cq_eq_id_2_WORD word1
1250 uint32_t lpfc_cq_context_count; /* Version 2 Only */
1254 struct lpfc_mbx_cq_create {
1255 struct mbox_header header;
1259 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1260 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1261 #define lpfc_mbx_cq_create_page_size_WORD word0
1262 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1263 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1264 #define lpfc_mbx_cq_create_num_pages_WORD word0
1265 struct cq_context context;
1266 struct dma_address page[LPFC_MAX_CQ_PAGE];
1270 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1271 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1272 #define lpfc_mbx_cq_create_q_id_WORD word0
1277 struct lpfc_mbx_cq_create_set {
1278 union lpfc_sli4_cfg_shdr cfg_shdr;
1282 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */
1283 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1284 #define lpfc_mbx_cq_create_set_page_size_WORD word0
1285 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1286 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1287 #define lpfc_mbx_cq_create_set_num_pages_WORD word0
1289 #define lpfc_mbx_cq_create_set_evt_SHIFT 31
1290 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1291 #define lpfc_mbx_cq_create_set_evt_WORD word1
1292 #define lpfc_mbx_cq_create_set_valid_SHIFT 29
1293 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1294 #define lpfc_mbx_cq_create_set_valid_WORD word1
1295 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27
1296 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1297 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1
1298 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25
1299 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1300 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1
1301 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15
1302 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1303 #define lpfc_mbx_cq_create_set_autovalid_WORD word1
1304 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14
1305 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1306 #define lpfc_mbx_cq_create_set_nodelay_WORD word1
1307 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12
1308 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1309 #define lpfc_mbx_cq_create_set_clswm_WORD word1
1311 #define lpfc_mbx_cq_create_set_arm_SHIFT 31
1312 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1313 #define lpfc_mbx_cq_create_set_arm_WORD word2
1314 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16
1315 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1316 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2
1317 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1318 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1319 #define lpfc_mbx_cq_create_set_num_cq_WORD word2
1321 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16
1322 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1323 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3
1324 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1325 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1326 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3
1328 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16
1329 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1330 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4
1331 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1332 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1333 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4
1335 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16
1336 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1337 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5
1338 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1339 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1340 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5
1342 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16
1343 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1344 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6
1345 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1346 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1347 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6
1349 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16
1350 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1351 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7
1352 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1353 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1354 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7
1356 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16
1357 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1358 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8
1359 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1360 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1361 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8
1363 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16
1364 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1365 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9
1366 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1367 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1368 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9
1370 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16
1371 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1372 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10
1373 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1374 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1375 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10
1376 struct dma_address page[1];
1380 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16
1381 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1382 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0
1383 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1384 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1385 #define lpfc_mbx_cq_create_set_base_id_WORD word0
1390 struct lpfc_mbx_cq_destroy {
1391 struct mbox_header header;
1395 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1396 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1397 #define lpfc_mbx_cq_destroy_q_id_WORD word0
1412 struct lpfc_mbx_wq_create {
1413 struct mbox_header header;
1415 struct { /* Version 0 Request */
1417 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1418 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1419 #define lpfc_mbx_wq_create_num_pages_WORD word0
1420 #define lpfc_mbx_wq_create_dua_SHIFT 8
1421 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1422 #define lpfc_mbx_wq_create_dua_WORD word0
1423 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
1424 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1425 #define lpfc_mbx_wq_create_cq_id_WORD word0
1426 struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1428 #define lpfc_mbx_wq_create_bua_SHIFT 0
1429 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1430 #define lpfc_mbx_wq_create_bua_WORD word9
1431 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8
1432 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1433 #define lpfc_mbx_wq_create_ulp_num_WORD word9
1435 struct { /* Version 1 Request */
1436 uint32_t word0; /* Word 0 is the same as in v0 */
1438 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1439 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1440 #define lpfc_mbx_wq_create_page_size_WORD word1
1441 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1442 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15
1443 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1444 #define lpfc_mbx_wq_create_dpp_req_WORD word1
1445 #define lpfc_mbx_wq_create_doe_SHIFT 14
1446 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1447 #define lpfc_mbx_wq_create_doe_WORD word1
1448 #define lpfc_mbx_wq_create_toe_SHIFT 13
1449 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1450 #define lpfc_mbx_wq_create_toe_WORD word1
1451 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1452 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1453 #define lpfc_mbx_wq_create_wqe_size_WORD word1
1454 #define LPFC_WQ_WQE_SIZE_64 0x5
1455 #define LPFC_WQ_WQE_SIZE_128 0x6
1456 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1457 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1458 #define lpfc_mbx_wq_create_wqe_count_WORD word1
1460 struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1464 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1465 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1466 #define lpfc_mbx_wq_create_q_id_WORD word0
1467 uint32_t doorbell_offset;
1469 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1470 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1471 #define lpfc_mbx_wq_create_bar_set_WORD word2
1472 #define WQ_PCI_BAR_0_AND_1 0x00
1473 #define WQ_PCI_BAR_2_AND_3 0x01
1474 #define WQ_PCI_BAR_4_AND_5 0x02
1475 #define lpfc_mbx_wq_create_db_format_SHIFT 16
1476 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1477 #define lpfc_mbx_wq_create_db_format_WORD word2
1481 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31
1482 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1483 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0
1484 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1485 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1486 #define lpfc_mbx_wq_create_v1_q_id_WORD word0
1488 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1489 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1490 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1
1491 uint32_t doorbell_offset;
1493 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16
1494 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1495 #define lpfc_mbx_wq_create_dpp_id_WORD word3
1496 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1497 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1498 #define lpfc_mbx_wq_create_dpp_bar_WORD word3
1499 uint32_t dpp_offset;
1504 struct lpfc_mbx_wq_destroy {
1505 struct mbox_header header;
1509 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1510 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1511 #define lpfc_mbx_wq_destroy_q_id_WORD word0
1519 #define LPFC_HDR_BUF_SIZE 128
1520 #define LPFC_DATA_BUF_SIZE 2048
1521 #define LPFC_NVMET_DATA_BUF_SIZE 128
1524 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1525 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1526 #define lpfc_rq_context_rqe_count_WORD word0
1527 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1528 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1529 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1530 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1531 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */
1532 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1533 #define lpfc_rq_context_rqe_count_1_WORD word0
1534 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */
1535 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1536 #define lpfc_rq_context_rqe_size_WORD word0
1537 #define LPFC_RQE_SIZE_8 2
1538 #define LPFC_RQE_SIZE_16 3
1539 #define LPFC_RQE_SIZE_32 4
1540 #define LPFC_RQE_SIZE_64 5
1541 #define LPFC_RQE_SIZE_128 6
1542 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1543 #define lpfc_rq_context_page_size_MASK 0x000000FF
1544 #define lpfc_rq_context_page_size_WORD word0
1545 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1547 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */
1548 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1549 #define lpfc_rq_context_data_size_WORD word1
1550 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1551 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1552 #define lpfc_rq_context_hdr_size_WORD word1
1554 #define lpfc_rq_context_cq_id_SHIFT 16
1555 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1556 #define lpfc_rq_context_cq_id_WORD word2
1557 #define lpfc_rq_context_buf_size_SHIFT 0
1558 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1559 #define lpfc_rq_context_buf_size_WORD word2
1560 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1561 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1562 #define lpfc_rq_context_base_cq_WORD word2
1563 uint32_t buffer_size; /* Version 1 Only */
1566 struct lpfc_mbx_rq_create {
1567 struct mbox_header header;
1571 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1572 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1573 #define lpfc_mbx_rq_create_num_pages_WORD word0
1574 #define lpfc_mbx_rq_create_dua_SHIFT 16
1575 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1576 #define lpfc_mbx_rq_create_dua_WORD word0
1577 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1578 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1579 #define lpfc_mbx_rq_create_bqu_WORD word0
1580 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1581 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1582 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1583 struct rq_context context;
1584 struct dma_address page[LPFC_MAX_RQ_PAGE];
1588 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1589 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1590 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1591 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1592 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1593 #define lpfc_mbx_rq_create_q_id_WORD word0
1594 uint32_t doorbell_offset;
1596 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1597 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1598 #define lpfc_mbx_rq_create_bar_set_WORD word2
1599 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1600 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1601 #define lpfc_mbx_rq_create_db_format_WORD word2
1606 struct lpfc_mbx_rq_create_v2 {
1607 union lpfc_sli4_cfg_shdr cfg_shdr;
1611 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1612 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1613 #define lpfc_mbx_rq_create_num_pages_WORD word0
1614 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16
1615 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1616 #define lpfc_mbx_rq_create_rq_cnt_WORD word0
1617 #define lpfc_mbx_rq_create_dua_SHIFT 16
1618 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1619 #define lpfc_mbx_rq_create_dua_WORD word0
1620 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1621 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1622 #define lpfc_mbx_rq_create_bqu_WORD word0
1623 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1624 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1625 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1626 #define lpfc_mbx_rq_create_dim_SHIFT 29
1627 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1628 #define lpfc_mbx_rq_create_dim_WORD word0
1629 #define lpfc_mbx_rq_create_dfd_SHIFT 30
1630 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1631 #define lpfc_mbx_rq_create_dfd_WORD word0
1632 #define lpfc_mbx_rq_create_dnb_SHIFT 31
1633 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1634 #define lpfc_mbx_rq_create_dnb_WORD word0
1635 struct rq_context context;
1636 struct dma_address page[1];
1640 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1641 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1642 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1643 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1644 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1645 #define lpfc_mbx_rq_create_q_id_WORD word0
1646 uint32_t doorbell_offset;
1648 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1649 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1650 #define lpfc_mbx_rq_create_bar_set_WORD word2
1651 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1652 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1653 #define lpfc_mbx_rq_create_db_format_WORD word2
1658 struct lpfc_mbx_rq_destroy {
1659 struct mbox_header header;
1663 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1664 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1665 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1675 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1676 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1677 #define lpfc_mq_context_cq_id_WORD word0
1678 #define lpfc_mq_context_ring_size_SHIFT 16
1679 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1680 #define lpfc_mq_context_ring_size_WORD word0
1681 #define LPFC_MQ_RING_SIZE_16 0x5
1682 #define LPFC_MQ_RING_SIZE_32 0x6
1683 #define LPFC_MQ_RING_SIZE_64 0x7
1684 #define LPFC_MQ_RING_SIZE_128 0x8
1686 #define lpfc_mq_context_valid_SHIFT 31
1687 #define lpfc_mq_context_valid_MASK 0x00000001
1688 #define lpfc_mq_context_valid_WORD word1
1693 struct lpfc_mbx_mq_create {
1694 struct mbox_header header;
1698 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1699 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1700 #define lpfc_mbx_mq_create_num_pages_WORD word0
1701 struct mq_context context;
1702 struct dma_address page[LPFC_MAX_MQ_PAGE];
1706 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1707 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1708 #define lpfc_mbx_mq_create_q_id_WORD word0
1713 struct lpfc_mbx_mq_create_ext {
1714 struct mbox_header header;
1718 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1719 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1720 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1721 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1722 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1723 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1724 uint32_t async_evt_bmap;
1725 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1726 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1727 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1728 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1729 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1730 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1731 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1732 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1733 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1734 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1735 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1736 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1737 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1738 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1739 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1740 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1741 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1742 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1743 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1744 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1745 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1746 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1747 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1748 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1749 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1750 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1751 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1752 struct mq_context context;
1753 struct dma_address page[LPFC_MAX_MQ_PAGE];
1757 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1758 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1759 #define lpfc_mbx_mq_create_q_id_WORD word0
1762 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1763 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1764 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1767 struct lpfc_mbx_mq_destroy {
1768 struct mbox_header header;
1772 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1773 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1774 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1782 /* Start Gen 2 SLI4 Mailbox definitions: */
1784 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1785 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1786 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1787 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1788 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1790 struct lpfc_mbx_get_rsrc_extent_info {
1791 struct mbox_header header;
1795 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1796 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1797 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1801 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1802 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1803 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1804 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1805 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1806 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1811 struct lpfc_mbx_query_fw_config {
1812 struct mbox_header header;
1814 uint32_t config_number;
1815 #define LPFC_FC_FCOE 0x00000007
1816 uint32_t asic_revision;
1817 uint32_t physical_port;
1818 uint32_t function_mode;
1819 #define LPFC_FCOE_INI_MODE 0x00000040
1820 #define LPFC_FCOE_TGT_MODE 0x00000080
1821 #define LPFC_DUA_MODE 0x00000800
1823 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1824 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1825 uint32_t ulp0_nap_words[12];
1827 uint32_t ulp1_nap_words[12];
1828 uint32_t function_capabilities;
1833 uint32_t ulp0_nap2_words[2];
1834 uint32_t ulp1_nap2_words[2];
1838 struct lpfc_mbx_set_beacon_config {
1839 struct mbox_header header;
1841 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1842 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1843 #define lpfc_mbx_set_beacon_port_num_WORD word4
1844 #define lpfc_mbx_set_beacon_port_type_SHIFT 6
1845 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1846 #define lpfc_mbx_set_beacon_port_type_WORD word4
1847 #define lpfc_mbx_set_beacon_state_SHIFT 8
1848 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1849 #define lpfc_mbx_set_beacon_state_WORD word4
1850 #define lpfc_mbx_set_beacon_duration_SHIFT 16
1851 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1852 #define lpfc_mbx_set_beacon_duration_WORD word4
1854 /* COMMON_SET_BEACON_CONFIG_V1 */
1855 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16
1856 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1857 #define lpfc_mbx_set_beacon_duration_v1_WORD word4
1858 uint32_t word5; /* RESERVED */
1861 struct lpfc_id_range {
1863 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1864 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1865 #define lpfc_mbx_rsrc_id_word4_0_WORD word5
1866 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1867 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1868 #define lpfc_mbx_rsrc_id_word4_1_WORD word5
1871 struct lpfc_mbx_set_link_diag_state {
1872 struct mbox_header header;
1876 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1877 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1878 #define lpfc_mbx_set_diag_state_diag_WORD word0
1879 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2
1880 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1881 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0
1882 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1883 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1
1884 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1885 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1886 #define lpfc_mbx_set_diag_state_link_num_WORD word0
1887 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1888 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1889 #define lpfc_mbx_set_diag_state_link_type_WORD word0
1897 struct lpfc_mbx_set_link_diag_loopback {
1898 struct mbox_header header;
1902 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1903 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1904 #define lpfc_mbx_set_diag_lpbk_type_WORD word0
1905 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1906 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1907 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1908 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3
1909 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1910 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1911 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1912 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1913 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1914 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1922 struct lpfc_mbx_run_link_diag_test {
1923 struct mbox_header header;
1927 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1928 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1929 #define lpfc_mbx_run_diag_test_link_num_WORD word0
1930 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1931 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1932 #define lpfc_mbx_run_diag_test_link_type_WORD word0
1934 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1935 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1936 #define lpfc_mbx_run_diag_test_test_id_WORD word1
1937 #define lpfc_mbx_run_diag_test_loops_SHIFT 16
1938 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1939 #define lpfc_mbx_run_diag_test_loops_WORD word1
1941 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1942 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1943 #define lpfc_mbx_run_diag_test_test_ver_WORD word2
1944 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1945 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1946 #define lpfc_mbx_run_diag_test_err_act_WORD word2
1955 * struct lpfc_mbx_alloc_rsrc_extents:
1956 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1957 * 6 words of header + 4 words of shared subcommand header +
1958 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1960 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1961 * for extents payload.
1963 * 212/2 (bytes per extent) = 106 extents.
1964 * 106/2 (extents per word) = 53 words.
1965 * lpfc_id_range id is statically size to 53.
1967 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1968 * extent ranges. For ALLOC, the type and cnt are required.
1969 * For GET_ALLOCATED, only the type is required.
1971 struct lpfc_mbx_alloc_rsrc_extents {
1972 struct mbox_header header;
1976 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1977 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1978 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1979 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1980 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1981 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1985 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1986 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1987 #define lpfc_mbx_rsrc_cnt_WORD word4
1988 struct lpfc_id_range id[53];
1994 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1995 * structure shares the same SHIFT/MASK/WORD defines provided in the
1996 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1997 * the structures defined above. This non-embedded structure provides for the
1998 * maximum number of extents supported by the port.
2000 struct lpfc_mbx_nembed_rsrc_extent {
2001 union lpfc_sli4_cfg_shdr cfg_shdr;
2003 struct lpfc_id_range id;
2006 struct lpfc_mbx_dealloc_rsrc_extents {
2007 struct mbox_header header;
2010 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
2011 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
2012 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
2017 /* Start SLI4 FCoE specific mbox structures. */
2019 struct lpfc_mbx_post_hdr_tmpl {
2020 struct mbox_header header;
2022 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
2023 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
2024 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
2025 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
2026 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
2027 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
2028 uint32_t rpi_paddr_lo;
2029 uint32_t rpi_paddr_hi;
2032 struct sli4_sge { /* SLI-4 */
2037 #define lpfc_sli4_sge_offset_SHIFT 0
2038 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
2039 #define lpfc_sli4_sge_offset_WORD word2
2040 #define lpfc_sli4_sge_type_SHIFT 27
2041 #define lpfc_sli4_sge_type_MASK 0x0000000F
2042 #define lpfc_sli4_sge_type_WORD word2
2043 #define LPFC_SGE_TYPE_DATA 0x0
2044 #define LPFC_SGE_TYPE_DIF 0x4
2045 #define LPFC_SGE_TYPE_LSP 0x5
2046 #define LPFC_SGE_TYPE_PEDIF 0x6
2047 #define LPFC_SGE_TYPE_PESEED 0x7
2048 #define LPFC_SGE_TYPE_DISEED 0x8
2049 #define LPFC_SGE_TYPE_ENC 0x9
2050 #define LPFC_SGE_TYPE_ATM 0xA
2051 #define LPFC_SGE_TYPE_SKIP 0xC
2052 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
2053 #define lpfc_sli4_sge_last_MASK 0x00000001
2054 #define lpfc_sli4_sge_last_WORD word2
2058 struct sli4_hybrid_sgl {
2059 struct list_head list_node;
2060 struct sli4_sge *dma_sgl;
2061 dma_addr_t dma_phys_sgl;
2064 struct fcp_cmd_rsp_buf {
2065 struct list_head list_node;
2067 /* for storing cmd/rsp dma alloc'ed virt_addr */
2068 struct fcp_cmnd *fcp_cmnd;
2069 struct fcp_rsp *fcp_rsp;
2071 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */
2072 dma_addr_t fcp_cmd_rsp_dma_handle;
2075 struct sli4_sge_diseed { /* SLI-4 */
2077 uint32_t ref_tag_tran;
2080 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2081 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2082 #define lpfc_sli4_sge_dif_apptran_WORD word2
2083 #define lpfc_sli4_sge_dif_af_SHIFT 24
2084 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2085 #define lpfc_sli4_sge_dif_af_WORD word2
2086 #define lpfc_sli4_sge_dif_na_SHIFT 25
2087 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2088 #define lpfc_sli4_sge_dif_na_WORD word2
2089 #define lpfc_sli4_sge_dif_hi_SHIFT 26
2090 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2091 #define lpfc_sli4_sge_dif_hi_WORD word2
2092 #define lpfc_sli4_sge_dif_type_SHIFT 27
2093 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2094 #define lpfc_sli4_sge_dif_type_WORD word2
2095 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
2096 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2097 #define lpfc_sli4_sge_dif_last_WORD word2
2099 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2100 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2101 #define lpfc_sli4_sge_dif_apptag_WORD word3
2102 #define lpfc_sli4_sge_dif_bs_SHIFT 16
2103 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2104 #define lpfc_sli4_sge_dif_bs_WORD word3
2105 #define lpfc_sli4_sge_dif_ai_SHIFT 19
2106 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2107 #define lpfc_sli4_sge_dif_ai_WORD word3
2108 #define lpfc_sli4_sge_dif_me_SHIFT 20
2109 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2110 #define lpfc_sli4_sge_dif_me_WORD word3
2111 #define lpfc_sli4_sge_dif_re_SHIFT 21
2112 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2113 #define lpfc_sli4_sge_dif_re_WORD word3
2114 #define lpfc_sli4_sge_dif_ce_SHIFT 22
2115 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2116 #define lpfc_sli4_sge_dif_ce_WORD word3
2117 #define lpfc_sli4_sge_dif_nr_SHIFT 23
2118 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2119 #define lpfc_sli4_sge_dif_nr_WORD word3
2120 #define lpfc_sli4_sge_dif_oprx_SHIFT 24
2121 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2122 #define lpfc_sli4_sge_dif_oprx_WORD word3
2123 #define lpfc_sli4_sge_dif_optx_SHIFT 28
2124 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2125 #define lpfc_sli4_sge_dif_optx_WORD word3
2126 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2130 uint32_t max_rcv_size;
2131 uint32_t fka_adv_period;
2132 uint32_t fip_priority;
2134 #define lpfc_fcf_record_mac_0_SHIFT 0
2135 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2136 #define lpfc_fcf_record_mac_0_WORD word3
2137 #define lpfc_fcf_record_mac_1_SHIFT 8
2138 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2139 #define lpfc_fcf_record_mac_1_WORD word3
2140 #define lpfc_fcf_record_mac_2_SHIFT 16
2141 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2142 #define lpfc_fcf_record_mac_2_WORD word3
2143 #define lpfc_fcf_record_mac_3_SHIFT 24
2144 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2145 #define lpfc_fcf_record_mac_3_WORD word3
2147 #define lpfc_fcf_record_mac_4_SHIFT 0
2148 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2149 #define lpfc_fcf_record_mac_4_WORD word4
2150 #define lpfc_fcf_record_mac_5_SHIFT 8
2151 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2152 #define lpfc_fcf_record_mac_5_WORD word4
2153 #define lpfc_fcf_record_fcf_avail_SHIFT 16
2154 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2155 #define lpfc_fcf_record_fcf_avail_WORD word4
2156 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
2157 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2158 #define lpfc_fcf_record_mac_addr_prov_WORD word4
2159 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
2160 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
2162 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2163 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2164 #define lpfc_fcf_record_fab_name_0_WORD word5
2165 #define lpfc_fcf_record_fab_name_1_SHIFT 8
2166 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2167 #define lpfc_fcf_record_fab_name_1_WORD word5
2168 #define lpfc_fcf_record_fab_name_2_SHIFT 16
2169 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2170 #define lpfc_fcf_record_fab_name_2_WORD word5
2171 #define lpfc_fcf_record_fab_name_3_SHIFT 24
2172 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2173 #define lpfc_fcf_record_fab_name_3_WORD word5
2175 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2176 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2177 #define lpfc_fcf_record_fab_name_4_WORD word6
2178 #define lpfc_fcf_record_fab_name_5_SHIFT 8
2179 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2180 #define lpfc_fcf_record_fab_name_5_WORD word6
2181 #define lpfc_fcf_record_fab_name_6_SHIFT 16
2182 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2183 #define lpfc_fcf_record_fab_name_6_WORD word6
2184 #define lpfc_fcf_record_fab_name_7_SHIFT 24
2185 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2186 #define lpfc_fcf_record_fab_name_7_WORD word6
2188 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2189 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2190 #define lpfc_fcf_record_fc_map_0_WORD word7
2191 #define lpfc_fcf_record_fc_map_1_SHIFT 8
2192 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2193 #define lpfc_fcf_record_fc_map_1_WORD word7
2194 #define lpfc_fcf_record_fc_map_2_SHIFT 16
2195 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2196 #define lpfc_fcf_record_fc_map_2_WORD word7
2197 #define lpfc_fcf_record_fcf_valid_SHIFT 24
2198 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2199 #define lpfc_fcf_record_fcf_valid_WORD word7
2200 #define lpfc_fcf_record_fcf_fc_SHIFT 25
2201 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2202 #define lpfc_fcf_record_fcf_fc_WORD word7
2203 #define lpfc_fcf_record_fcf_sol_SHIFT 31
2204 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2205 #define lpfc_fcf_record_fcf_sol_WORD word7
2207 #define lpfc_fcf_record_fcf_index_SHIFT 0
2208 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2209 #define lpfc_fcf_record_fcf_index_WORD word8
2210 #define lpfc_fcf_record_fcf_state_SHIFT 16
2211 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2212 #define lpfc_fcf_record_fcf_state_WORD word8
2213 uint8_t vlan_bitmap[512];
2215 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2216 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2217 #define lpfc_fcf_record_switch_name_0_WORD word137
2218 #define lpfc_fcf_record_switch_name_1_SHIFT 8
2219 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2220 #define lpfc_fcf_record_switch_name_1_WORD word137
2221 #define lpfc_fcf_record_switch_name_2_SHIFT 16
2222 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2223 #define lpfc_fcf_record_switch_name_2_WORD word137
2224 #define lpfc_fcf_record_switch_name_3_SHIFT 24
2225 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2226 #define lpfc_fcf_record_switch_name_3_WORD word137
2228 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2229 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2230 #define lpfc_fcf_record_switch_name_4_WORD word138
2231 #define lpfc_fcf_record_switch_name_5_SHIFT 8
2232 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2233 #define lpfc_fcf_record_switch_name_5_WORD word138
2234 #define lpfc_fcf_record_switch_name_6_SHIFT 16
2235 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2236 #define lpfc_fcf_record_switch_name_6_WORD word138
2237 #define lpfc_fcf_record_switch_name_7_SHIFT 24
2238 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2239 #define lpfc_fcf_record_switch_name_7_WORD word138
2242 struct lpfc_mbx_read_fcf_tbl {
2243 union lpfc_sli4_cfg_shdr cfg_shdr;
2247 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2248 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2249 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
2256 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2257 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2258 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
2261 struct lpfc_mbx_add_fcf_tbl_entry {
2262 union lpfc_sli4_cfg_shdr cfg_shdr;
2264 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2265 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2266 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
2267 struct lpfc_mbx_sge fcf_sge;
2270 struct lpfc_mbx_del_fcf_tbl_entry {
2271 struct mbox_header header;
2273 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2274 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2275 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
2276 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
2277 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2278 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
2281 struct lpfc_mbx_redisc_fcf_tbl {
2282 struct mbox_header header;
2284 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2285 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2286 #define lpfc_mbx_redisc_fcf_count_WORD word10
2289 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2290 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2291 #define lpfc_mbx_redisc_fcf_index_WORD word12
2294 /* Status field for embedded SLI_CONFIG mailbox command */
2295 #define STATUS_SUCCESS 0x0
2296 #define STATUS_FAILED 0x1
2297 #define STATUS_ILLEGAL_REQUEST 0x2
2298 #define STATUS_ILLEGAL_FIELD 0x3
2299 #define STATUS_INSUFFICIENT_BUFFER 0x4
2300 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2301 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2302 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2303 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2304 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2305 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2306 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2307 #define STATUS_ASSERT_FAILED 0x1e
2308 #define STATUS_INVALID_SESSION 0x1f
2309 #define STATUS_INVALID_CONNECTION 0x20
2310 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2311 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2312 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2313 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2314 #define STATUS_FLASHROM_READ_FAILED 0x27
2315 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2316 #define STATUS_ERROR_ACITMAIN 0x2a
2317 #define STATUS_REBOOT_REQUIRED 0x2c
2318 #define STATUS_FCF_IN_USE 0x3a
2319 #define STATUS_FCF_TABLE_EMPTY 0x43
2322 * Additional status field for embedded SLI_CONFIG mailbox
2325 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2326 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2327 #define ADD_STATUS_INVALID_REQUEST 0x4B
2328 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58
2330 struct lpfc_mbx_sli4_config {
2331 struct mbox_header header;
2334 struct lpfc_mbx_init_vfi {
2336 #define lpfc_init_vfi_vr_SHIFT 31
2337 #define lpfc_init_vfi_vr_MASK 0x00000001
2338 #define lpfc_init_vfi_vr_WORD word1
2339 #define lpfc_init_vfi_vt_SHIFT 30
2340 #define lpfc_init_vfi_vt_MASK 0x00000001
2341 #define lpfc_init_vfi_vt_WORD word1
2342 #define lpfc_init_vfi_vf_SHIFT 29
2343 #define lpfc_init_vfi_vf_MASK 0x00000001
2344 #define lpfc_init_vfi_vf_WORD word1
2345 #define lpfc_init_vfi_vp_SHIFT 28
2346 #define lpfc_init_vfi_vp_MASK 0x00000001
2347 #define lpfc_init_vfi_vp_WORD word1
2348 #define lpfc_init_vfi_vfi_SHIFT 0
2349 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2350 #define lpfc_init_vfi_vfi_WORD word1
2352 #define lpfc_init_vfi_vpi_SHIFT 16
2353 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2354 #define lpfc_init_vfi_vpi_WORD word2
2355 #define lpfc_init_vfi_fcfi_SHIFT 0
2356 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2357 #define lpfc_init_vfi_fcfi_WORD word2
2359 #define lpfc_init_vfi_pri_SHIFT 13
2360 #define lpfc_init_vfi_pri_MASK 0x00000007
2361 #define lpfc_init_vfi_pri_WORD word3
2362 #define lpfc_init_vfi_vf_id_SHIFT 1
2363 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2364 #define lpfc_init_vfi_vf_id_WORD word3
2366 #define lpfc_init_vfi_hop_count_SHIFT 24
2367 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2368 #define lpfc_init_vfi_hop_count_WORD word4
2370 #define MBX_VFI_IN_USE 0x9F02
2373 struct lpfc_mbx_reg_vfi {
2375 #define lpfc_reg_vfi_upd_SHIFT 29
2376 #define lpfc_reg_vfi_upd_MASK 0x00000001
2377 #define lpfc_reg_vfi_upd_WORD word1
2378 #define lpfc_reg_vfi_vp_SHIFT 28
2379 #define lpfc_reg_vfi_vp_MASK 0x00000001
2380 #define lpfc_reg_vfi_vp_WORD word1
2381 #define lpfc_reg_vfi_vfi_SHIFT 0
2382 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2383 #define lpfc_reg_vfi_vfi_WORD word1
2385 #define lpfc_reg_vfi_vpi_SHIFT 16
2386 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2387 #define lpfc_reg_vfi_vpi_WORD word2
2388 #define lpfc_reg_vfi_fcfi_SHIFT 0
2389 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2390 #define lpfc_reg_vfi_fcfi_WORD word2
2392 struct ulp_bde64 bde;
2396 #define lpfc_reg_vfi_nport_id_SHIFT 0
2397 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2398 #define lpfc_reg_vfi_nport_id_WORD word10
2399 #define lpfc_reg_vfi_bbcr_SHIFT 27
2400 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2401 #define lpfc_reg_vfi_bbcr_WORD word10
2402 #define lpfc_reg_vfi_bbscn_SHIFT 28
2403 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2404 #define lpfc_reg_vfi_bbscn_WORD word10
2407 struct lpfc_mbx_init_vpi {
2409 #define lpfc_init_vpi_vfi_SHIFT 16
2410 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2411 #define lpfc_init_vpi_vfi_WORD word1
2412 #define lpfc_init_vpi_vpi_SHIFT 0
2413 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2414 #define lpfc_init_vpi_vpi_WORD word1
2417 struct lpfc_mbx_read_vpi {
2418 uint32_t word1_rsvd;
2420 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2421 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2422 #define lpfc_mbx_read_vpi_vnportid_WORD word2
2423 uint32_t word3_rsvd;
2425 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2426 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2427 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
2428 #define lpfc_mbx_read_vpi_pb_SHIFT 15
2429 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2430 #define lpfc_mbx_read_vpi_pb_WORD word4
2431 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
2432 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2433 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
2434 #define lpfc_mbx_read_vpi_ns_SHIFT 30
2435 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2436 #define lpfc_mbx_read_vpi_ns_WORD word4
2437 #define lpfc_mbx_read_vpi_hl_SHIFT 31
2438 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2439 #define lpfc_mbx_read_vpi_hl_WORD word4
2440 uint32_t word5_rsvd;
2442 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2443 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2444 #define lpfc_mbx_read_vpi_vpi_WORD word6
2446 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2447 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2448 #define lpfc_mbx_read_vpi_mac_0_WORD word7
2449 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
2450 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2451 #define lpfc_mbx_read_vpi_mac_1_WORD word7
2452 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
2453 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2454 #define lpfc_mbx_read_vpi_mac_2_WORD word7
2455 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
2456 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2457 #define lpfc_mbx_read_vpi_mac_3_WORD word7
2459 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2460 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2461 #define lpfc_mbx_read_vpi_mac_4_WORD word8
2462 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
2463 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2464 #define lpfc_mbx_read_vpi_mac_5_WORD word8
2465 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
2466 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2467 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
2468 #define lpfc_mbx_read_vpi_vv_SHIFT 28
2469 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2470 #define lpfc_mbx_read_vpi_vv_WORD word8
2473 struct lpfc_mbx_unreg_vfi {
2474 uint32_t word1_rsvd;
2476 #define lpfc_unreg_vfi_vfi_SHIFT 0
2477 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2478 #define lpfc_unreg_vfi_vfi_WORD word2
2481 struct lpfc_mbx_resume_rpi {
2483 #define lpfc_resume_rpi_index_SHIFT 0
2484 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2485 #define lpfc_resume_rpi_index_WORD word1
2486 #define lpfc_resume_rpi_ii_SHIFT 30
2487 #define lpfc_resume_rpi_ii_MASK 0x00000003
2488 #define lpfc_resume_rpi_ii_WORD word1
2489 #define RESUME_INDEX_RPI 0
2490 #define RESUME_INDEX_VPI 1
2491 #define RESUME_INDEX_VFI 2
2492 #define RESUME_INDEX_FCFI 3
2496 #define REG_FCF_INVALID_QID 0xFFFF
2497 struct lpfc_mbx_reg_fcfi {
2499 #define lpfc_reg_fcfi_info_index_SHIFT 0
2500 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2501 #define lpfc_reg_fcfi_info_index_WORD word1
2502 #define lpfc_reg_fcfi_fcfi_SHIFT 16
2503 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2504 #define lpfc_reg_fcfi_fcfi_WORD word1
2506 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2507 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2508 #define lpfc_reg_fcfi_rq_id1_WORD word2
2509 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
2510 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2511 #define lpfc_reg_fcfi_rq_id0_WORD word2
2513 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2514 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2515 #define lpfc_reg_fcfi_rq_id3_WORD word3
2516 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
2517 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2518 #define lpfc_reg_fcfi_rq_id2_WORD word3
2520 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2521 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2522 #define lpfc_reg_fcfi_type_match0_WORD word4
2523 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
2524 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2525 #define lpfc_reg_fcfi_type_mask0_WORD word4
2526 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2527 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2528 #define lpfc_reg_fcfi_rctl_match0_WORD word4
2529 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2530 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2531 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
2533 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2534 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2535 #define lpfc_reg_fcfi_type_match1_WORD word5
2536 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
2537 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2538 #define lpfc_reg_fcfi_type_mask1_WORD word5
2539 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2540 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2541 #define lpfc_reg_fcfi_rctl_match1_WORD word5
2542 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2543 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2544 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
2546 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2547 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2548 #define lpfc_reg_fcfi_type_match2_WORD word6
2549 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
2550 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2551 #define lpfc_reg_fcfi_type_mask2_WORD word6
2552 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2553 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2554 #define lpfc_reg_fcfi_rctl_match2_WORD word6
2555 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2556 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2557 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
2559 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2560 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2561 #define lpfc_reg_fcfi_type_match3_WORD word7
2562 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
2563 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2564 #define lpfc_reg_fcfi_type_mask3_WORD word7
2565 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2566 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2567 #define lpfc_reg_fcfi_rctl_match3_WORD word7
2568 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2569 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2570 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
2572 #define lpfc_reg_fcfi_mam_SHIFT 13
2573 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2574 #define lpfc_reg_fcfi_mam_WORD word8
2575 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2576 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2577 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2578 #define lpfc_reg_fcfi_vv_SHIFT 12
2579 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2580 #define lpfc_reg_fcfi_vv_WORD word8
2581 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2582 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2583 #define lpfc_reg_fcfi_vlan_tag_WORD word8
2586 struct lpfc_mbx_reg_fcfi_mrq {
2588 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2589 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2590 #define lpfc_reg_fcfi_mrq_info_index_WORD word1
2591 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16
2592 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2593 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1
2595 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2596 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2597 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2
2598 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16
2599 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2600 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2
2602 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2603 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2604 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3
2605 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16
2606 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2607 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3
2609 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24
2610 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2611 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4
2612 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16
2613 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2614 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4
2615 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8
2616 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2617 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4
2618 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2619 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2620 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4
2622 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24
2623 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2624 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5
2625 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16
2626 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2627 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5
2628 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8
2629 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2630 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5
2631 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2632 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2633 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5
2635 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24
2636 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2637 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6
2638 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16
2639 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2640 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6
2641 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8
2642 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2643 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6
2644 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2645 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2646 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6
2648 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24
2649 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2650 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7
2651 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16
2652 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2653 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7
2654 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8
2655 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2656 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7
2657 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2658 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2659 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7
2661 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31
2662 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2663 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8
2664 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30
2665 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2666 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8
2667 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29
2668 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2669 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8
2670 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28
2671 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2672 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8
2673 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27
2674 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2675 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8
2676 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26
2677 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2678 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8
2679 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25
2680 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2681 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8
2682 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24
2683 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2684 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8
2685 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23
2686 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2687 #define lpfc_reg_fcfi_mrq_pt7_WORD word8
2688 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22
2689 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2690 #define lpfc_reg_fcfi_mrq_pt6_WORD word8
2691 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21
2692 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2693 #define lpfc_reg_fcfi_mrq_pt5_WORD word8
2694 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20
2695 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2696 #define lpfc_reg_fcfi_mrq_pt4_WORD word8
2697 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19
2698 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2699 #define lpfc_reg_fcfi_mrq_pt3_WORD word8
2700 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18
2701 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2702 #define lpfc_reg_fcfi_mrq_pt2_WORD word8
2703 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17
2704 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2705 #define lpfc_reg_fcfi_mrq_pt1_WORD word8
2706 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16
2707 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2708 #define lpfc_reg_fcfi_mrq_pt0_WORD word8
2709 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15
2710 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2711 #define lpfc_reg_fcfi_mrq_xmv_WORD word8
2712 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13
2713 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2714 #define lpfc_reg_fcfi_mrq_mode_WORD word8
2715 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12
2716 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2717 #define lpfc_reg_fcfi_mrq_vv_WORD word8
2718 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2719 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2720 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8
2722 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12
2723 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2724 #define lpfc_reg_fcfi_mrq_policy_WORD word9
2725 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8
2726 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2727 #define lpfc_reg_fcfi_mrq_filter_WORD word9
2728 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2729 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2730 #define lpfc_reg_fcfi_mrq_npairs_WORD word9
2740 struct lpfc_mbx_unreg_fcfi {
2743 #define lpfc_unreg_fcfi_SHIFT 0
2744 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2745 #define lpfc_unreg_fcfi_WORD word2
2748 struct lpfc_mbx_read_rev {
2750 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2751 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2752 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2753 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2754 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2755 #define lpfc_mbx_rd_rev_fcoe_WORD word1
2756 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2757 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2758 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
2759 #define LPFC_PREDCBX_CEE_MODE 0
2760 #define LPFC_DCBX_CEE_MODE 1
2761 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
2762 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2763 #define lpfc_mbx_rd_rev_vpd_WORD word1
2764 uint32_t first_hw_rev;
2765 #define LPFC_G7_ASIC_1 0xd
2766 uint32_t second_hw_rev;
2767 uint32_t word4_rsvd;
2768 uint32_t third_hw_rev;
2770 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2771 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2772 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
2773 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2774 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2775 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
2776 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2777 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2778 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2779 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2780 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2781 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2782 uint32_t word7_rsvd;
2784 uint8_t fw_name[16];
2785 uint32_t ulp_fw_id_rev;
2786 uint8_t ulp_fw_name[16];
2787 uint32_t word18_47_rsvd[30];
2789 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2790 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2791 #define lpfc_mbx_rd_rev_avail_len_WORD word48
2792 uint32_t vpd_paddr_low;
2793 uint32_t vpd_paddr_high;
2794 uint32_t avail_vpd_len;
2795 uint32_t rsvd_52_63[12];
2798 struct lpfc_mbx_read_config {
2800 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2801 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2802 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2804 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2805 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2806 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2807 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2808 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2809 #define lpfc_mbx_rd_conf_lnk_type_WORD word2
2810 #define LPFC_LNK_TYPE_GE 0
2811 #define LPFC_LNK_TYPE_FC 1
2812 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2813 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2814 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2815 #define lpfc_mbx_rd_conf_trunk_SHIFT 12
2816 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F
2817 #define lpfc_mbx_rd_conf_trunk_WORD word2
2818 #define lpfc_mbx_rd_conf_pt_SHIFT 20
2819 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003
2820 #define lpfc_mbx_rd_conf_pt_WORD word2
2821 #define lpfc_mbx_rd_conf_tf_SHIFT 22
2822 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001
2823 #define lpfc_mbx_rd_conf_tf_WORD word2
2824 #define lpfc_mbx_rd_conf_ptv_SHIFT 23
2825 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001
2826 #define lpfc_mbx_rd_conf_ptv_WORD word2
2827 #define lpfc_mbx_rd_conf_topology_SHIFT 24
2828 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2829 #define lpfc_mbx_rd_conf_topology_WORD word2
2832 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2833 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2834 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2837 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2838 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2839 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2840 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16
2841 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2842 #define lpfc_mbx_rd_conf_link_speed_WORD word6
2845 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2846 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2847 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8
2848 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4
2849 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2850 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8
2851 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8
2852 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2853 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8
2855 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2856 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2857 #define lpfc_mbx_rd_conf_lmt_WORD word9
2861 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2862 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2863 #define lpfc_mbx_rd_conf_xri_base_WORD word12
2864 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2865 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2866 #define lpfc_mbx_rd_conf_xri_count_WORD word12
2868 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2869 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2870 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
2871 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2872 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2873 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
2875 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2876 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2877 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
2878 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2879 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2880 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
2882 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2883 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2884 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
2885 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2886 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2887 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
2889 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2890 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2891 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2893 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2894 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2895 #define lpfc_mbx_rd_conf_rq_count_WORD word17
2896 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2897 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2898 #define lpfc_mbx_rd_conf_eq_count_WORD word17
2900 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2901 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2902 #define lpfc_mbx_rd_conf_wq_count_WORD word18
2903 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2904 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2905 #define lpfc_mbx_rd_conf_cq_count_WORD word18
2908 struct lpfc_mbx_request_features {
2910 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2911 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2912 #define lpfc_mbx_rq_ftr_qry_WORD word1
2914 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2915 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2916 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2917 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2918 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2919 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2920 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2921 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2922 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2923 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2924 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2925 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2926 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2927 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2928 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2929 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2930 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2931 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2932 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2933 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2934 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2935 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2936 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2937 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2938 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9
2939 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2940 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2
2941 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2942 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2943 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2944 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16
2945 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2946 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2
2948 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2949 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2950 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2951 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2952 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2953 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2954 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2955 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2956 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2957 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2958 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2959 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2960 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2961 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2962 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2963 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2964 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2965 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2966 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2967 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2968 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2969 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2970 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2971 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2972 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2973 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2974 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2975 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16
2976 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2977 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3
2980 struct lpfc_mbx_memory_dump_type3 {
2982 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
2983 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
2984 #define lpfc_mbx_memory_dump_type3_type_WORD word1
2985 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24
2986 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
2987 #define lpfc_mbx_memory_dump_type3_link_WORD word1
2989 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
2990 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
2991 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2
2992 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16
2993 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
2994 #define lpfc_mbx_memory_dump_type3_offset_WORD word2
2996 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
2997 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
2998 #define lpfc_mbx_memory_dump_type3_length_WORD word3
3001 uint32_t return_len;
3004 #define DMP_PAGE_A0 0xa0
3005 #define DMP_PAGE_A2 0xa2
3006 #define DMP_SFF_PAGE_A0_SIZE 256
3007 #define DMP_SFF_PAGE_A2_SIZE 256
3009 #define SFP_WAVELENGTH_LC1310 1310
3010 #define SFP_WAVELENGTH_LL1550 1550
3014 * * SFF-8472 TABLE 3.4
3016 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
3017 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
3018 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
3019 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
3020 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
3021 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
3022 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
3023 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
3024 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
3025 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
3026 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
3027 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3028 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3029 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
3030 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3031 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3033 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
3035 #define SSF_IDENTIFIER 0
3036 #define SSF_EXT_IDENTIFIER 1
3037 #define SSF_CONNECTOR 2
3038 #define SSF_TRANSCEIVER_CODE_B0 3
3039 #define SSF_TRANSCEIVER_CODE_B1 4
3040 #define SSF_TRANSCEIVER_CODE_B2 5
3041 #define SSF_TRANSCEIVER_CODE_B3 6
3042 #define SSF_TRANSCEIVER_CODE_B4 7
3043 #define SSF_TRANSCEIVER_CODE_B5 8
3044 #define SSF_TRANSCEIVER_CODE_B6 9
3045 #define SSF_TRANSCEIVER_CODE_B7 10
3046 #define SSF_ENCODING 11
3047 #define SSF_BR_NOMINAL 12
3048 #define SSF_RATE_IDENTIFIER 13
3049 #define SSF_LENGTH_9UM_KM 14
3050 #define SSF_LENGTH_9UM 15
3051 #define SSF_LENGTH_50UM_OM2 16
3052 #define SSF_LENGTH_62UM_OM1 17
3053 #define SFF_LENGTH_COPPER 18
3054 #define SSF_LENGTH_50UM_OM3 19
3055 #define SSF_VENDOR_NAME 20
3056 #define SSF_VENDOR_OUI 36
3057 #define SSF_VENDOR_PN 40
3058 #define SSF_VENDOR_REV 56
3059 #define SSF_WAVELENGTH_B1 60
3060 #define SSF_WAVELENGTH_B0 61
3061 #define SSF_CC_BASE 63
3062 #define SSF_OPTIONS_B1 64
3063 #define SSF_OPTIONS_B0 65
3064 #define SSF_BR_MAX 66
3065 #define SSF_BR_MIN 67
3066 #define SSF_VENDOR_SN 68
3067 #define SSF_DATE_CODE 84
3068 #define SSF_MONITORING_TYPEDIAGNOSTIC 92
3069 #define SSF_ENHANCED_OPTIONS 93
3070 #define SFF_8472_COMPLIANCE 94
3071 #define SSF_CC_EXT 95
3072 #define SSF_A0_VENDOR_SPECIFIC 96
3074 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
3076 #define SSF_TEMP_HIGH_ALARM 0
3077 #define SSF_TEMP_LOW_ALARM 2
3078 #define SSF_TEMP_HIGH_WARNING 4
3079 #define SSF_TEMP_LOW_WARNING 6
3080 #define SSF_VOLTAGE_HIGH_ALARM 8
3081 #define SSF_VOLTAGE_LOW_ALARM 10
3082 #define SSF_VOLTAGE_HIGH_WARNING 12
3083 #define SSF_VOLTAGE_LOW_WARNING 14
3084 #define SSF_BIAS_HIGH_ALARM 16
3085 #define SSF_BIAS_LOW_ALARM 18
3086 #define SSF_BIAS_HIGH_WARNING 20
3087 #define SSF_BIAS_LOW_WARNING 22
3088 #define SSF_TXPOWER_HIGH_ALARM 24
3089 #define SSF_TXPOWER_LOW_ALARM 26
3090 #define SSF_TXPOWER_HIGH_WARNING 28
3091 #define SSF_TXPOWER_LOW_WARNING 30
3092 #define SSF_RXPOWER_HIGH_ALARM 32
3093 #define SSF_RXPOWER_LOW_ALARM 34
3094 #define SSF_RXPOWER_HIGH_WARNING 36
3095 #define SSF_RXPOWER_LOW_WARNING 38
3096 #define SSF_EXT_CAL_CONSTANTS 56
3097 #define SSF_CC_DMI 95
3098 #define SFF_TEMPERATURE_B1 96
3099 #define SFF_TEMPERATURE_B0 97
3100 #define SFF_VCC_B1 98
3101 #define SFF_VCC_B0 99
3102 #define SFF_TX_BIAS_CURRENT_B1 100
3103 #define SFF_TX_BIAS_CURRENT_B0 101
3104 #define SFF_TXPOWER_B1 102
3105 #define SFF_TXPOWER_B0 103
3106 #define SFF_RXPOWER_B1 104
3107 #define SFF_RXPOWER_B0 105
3108 #define SSF_STATUS_CONTROL 110
3109 #define SSF_ALARM_FLAGS 112
3110 #define SSF_WARNING_FLAGS 116
3111 #define SSF_EXT_TATUS_CONTROL_B1 118
3112 #define SSF_EXT_TATUS_CONTROL_B0 119
3113 #define SSF_A2_VENDOR_SPECIFIC 120
3114 #define SSF_USER_EEPROM 128
3115 #define SSF_VENDOR_CONTROL 148
3119 * Tranceiver codes Fibre Channel SFF-8472
3123 struct sff_trasnceiver_codes_byte0 {
3124 uint8_t inifiband:4;
3125 uint8_t teng_ethernet:4;
3128 struct sff_trasnceiver_codes_byte1 {
3133 struct sff_trasnceiver_codes_byte2 {
3137 struct sff_trasnceiver_codes_byte3 {
3141 struct sff_trasnceiver_codes_byte4 {
3143 uint8_t fc_lw_laser:1;
3144 uint8_t fc_sw_laser:1;
3145 uint8_t fc_md_distance:1;
3146 uint8_t fc_lg_distance:1;
3147 uint8_t fc_int_distance:1;
3148 uint8_t fc_short_distance:1;
3149 uint8_t fc_vld_distance:1;
3152 struct sff_trasnceiver_codes_byte5 {
3153 uint8_t reserved1:1;
3154 uint8_t reserved2:1;
3155 uint8_t fc_sfp_active:1; /* Active cable */
3156 uint8_t fc_sfp_passive:1; /* Passive cable */
3157 uint8_t fc_lw_laser:1; /* Longwave laser */
3158 uint8_t fc_sw_laser_sl:1;
3159 uint8_t fc_sw_laser_sn:1;
3160 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */
3163 struct sff_trasnceiver_codes_byte6 {
3164 uint8_t fc_tm_sm:1; /* Single Mode */
3166 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */
3167 uint8_t fc_tm_tv:1; /* Video Coax (TV) */
3168 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */
3169 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */
3170 uint8_t fc_tm_tw:1; /* Twin Axial Pair */
3173 struct sff_trasnceiver_codes_byte7 {
3174 uint8_t fc_sp_100MB:1; /* 100 MB/sec */
3176 uint8_t fc_sp_200mb:1; /* 200 MB/sec */
3177 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */
3178 uint8_t fc_sp_400MB:1; /* 400 MB/sec */
3179 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */
3180 uint8_t fc_sp_800MB:1; /* 800 MB/sec */
3181 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */
3184 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3185 struct user_eeprom {
3186 uint8_t vendor_name[16];
3187 uint8_t vendor_oui[3];
3188 uint8_t vendor_pn[816];
3189 uint8_t vendor_rev[4];
3190 uint8_t vendor_sn[16];
3191 uint8_t datecode[6];
3192 uint8_t lot_code[2];
3193 uint8_t reserved191[57];
3196 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3197 &(~((SLI4_PAGE_SIZE)-1)))
3199 struct lpfc_sli4_parameters {
3201 #define cfg_prot_type_SHIFT 0
3202 #define cfg_prot_type_MASK 0x000000FF
3203 #define cfg_prot_type_WORD word0
3205 #define cfg_ft_SHIFT 0
3206 #define cfg_ft_MASK 0x00000001
3207 #define cfg_ft_WORD word1
3208 #define cfg_sli_rev_SHIFT 4
3209 #define cfg_sli_rev_MASK 0x0000000f
3210 #define cfg_sli_rev_WORD word1
3211 #define cfg_sli_family_SHIFT 8
3212 #define cfg_sli_family_MASK 0x0000000f
3213 #define cfg_sli_family_WORD word1
3214 #define cfg_if_type_SHIFT 12
3215 #define cfg_if_type_MASK 0x0000000f
3216 #define cfg_if_type_WORD word1
3217 #define cfg_sli_hint_1_SHIFT 16
3218 #define cfg_sli_hint_1_MASK 0x000000ff
3219 #define cfg_sli_hint_1_WORD word1
3220 #define cfg_sli_hint_2_SHIFT 24
3221 #define cfg_sli_hint_2_MASK 0x0000001f
3222 #define cfg_sli_hint_2_WORD word1
3224 #define cfg_eqav_SHIFT 31
3225 #define cfg_eqav_MASK 0x00000001
3226 #define cfg_eqav_WORD word2
3229 #define cfg_cqv_SHIFT 14
3230 #define cfg_cqv_MASK 0x00000003
3231 #define cfg_cqv_WORD word4
3232 #define cfg_cqpsize_SHIFT 16
3233 #define cfg_cqpsize_MASK 0x000000ff
3234 #define cfg_cqpsize_WORD word4
3235 #define cfg_cqav_SHIFT 31
3236 #define cfg_cqav_MASK 0x00000001
3237 #define cfg_cqav_WORD word4
3240 #define cfg_mqv_SHIFT 14
3241 #define cfg_mqv_MASK 0x00000003
3242 #define cfg_mqv_WORD word6
3245 #define cfg_wqpcnt_SHIFT 0
3246 #define cfg_wqpcnt_MASK 0x0000000f
3247 #define cfg_wqpcnt_WORD word8
3248 #define cfg_wqsize_SHIFT 8
3249 #define cfg_wqsize_MASK 0x0000000f
3250 #define cfg_wqsize_WORD word8
3251 #define cfg_wqv_SHIFT 14
3252 #define cfg_wqv_MASK 0x00000003
3253 #define cfg_wqv_WORD word8
3254 #define cfg_wqpsize_SHIFT 16
3255 #define cfg_wqpsize_MASK 0x000000ff
3256 #define cfg_wqpsize_WORD word8
3259 #define cfg_rqv_SHIFT 14
3260 #define cfg_rqv_MASK 0x00000003
3261 #define cfg_rqv_WORD word10
3263 #define cfg_rq_db_window_SHIFT 28
3264 #define cfg_rq_db_window_MASK 0x0000000f
3265 #define cfg_rq_db_window_WORD word11
3267 #define cfg_fcoe_SHIFT 0
3268 #define cfg_fcoe_MASK 0x00000001
3269 #define cfg_fcoe_WORD word12
3270 #define cfg_ext_SHIFT 1
3271 #define cfg_ext_MASK 0x00000001
3272 #define cfg_ext_WORD word12
3273 #define cfg_hdrr_SHIFT 2
3274 #define cfg_hdrr_MASK 0x00000001
3275 #define cfg_hdrr_WORD word12
3276 #define cfg_phwq_SHIFT 15
3277 #define cfg_phwq_MASK 0x00000001
3278 #define cfg_phwq_WORD word12
3279 #define cfg_oas_SHIFT 25
3280 #define cfg_oas_MASK 0x00000001
3281 #define cfg_oas_WORD word12
3282 #define cfg_loopbk_scope_SHIFT 28
3283 #define cfg_loopbk_scope_MASK 0x0000000f
3284 #define cfg_loopbk_scope_WORD word12
3285 uint32_t sge_supp_len;
3287 #define cfg_sgl_page_cnt_SHIFT 0
3288 #define cfg_sgl_page_cnt_MASK 0x0000000f
3289 #define cfg_sgl_page_cnt_WORD word14
3290 #define cfg_sgl_page_size_SHIFT 8
3291 #define cfg_sgl_page_size_MASK 0x000000ff
3292 #define cfg_sgl_page_size_WORD word14
3293 #define cfg_sgl_pp_align_SHIFT 16
3294 #define cfg_sgl_pp_align_MASK 0x000000ff
3295 #define cfg_sgl_pp_align_WORD word14
3301 #define cfg_ext_embed_cb_SHIFT 0
3302 #define cfg_ext_embed_cb_MASK 0x00000001
3303 #define cfg_ext_embed_cb_WORD word19
3304 #define cfg_mds_diags_SHIFT 1
3305 #define cfg_mds_diags_MASK 0x00000001
3306 #define cfg_mds_diags_WORD word19
3307 #define cfg_nvme_SHIFT 3
3308 #define cfg_nvme_MASK 0x00000001
3309 #define cfg_nvme_WORD word19
3310 #define cfg_xib_SHIFT 4
3311 #define cfg_xib_MASK 0x00000001
3312 #define cfg_xib_WORD word19
3313 #define cfg_xpsgl_SHIFT 6
3314 #define cfg_xpsgl_MASK 0x00000001
3315 #define cfg_xpsgl_WORD word19
3316 #define cfg_eqdr_SHIFT 8
3317 #define cfg_eqdr_MASK 0x00000001
3318 #define cfg_eqdr_WORD word19
3319 #define cfg_nosr_SHIFT 9
3320 #define cfg_nosr_MASK 0x00000001
3321 #define cfg_nosr_WORD word19
3323 #define cfg_bv1s_SHIFT 10
3324 #define cfg_bv1s_MASK 0x00000001
3325 #define cfg_bv1s_WORD word19
3326 #define cfg_pvl_SHIFT 13
3327 #define cfg_pvl_MASK 0x00000001
3328 #define cfg_pvl_WORD word19
3330 #define cfg_nsler_SHIFT 12
3331 #define cfg_nsler_MASK 0x00000001
3332 #define cfg_nsler_WORD word19
3335 #define cfg_max_tow_xri_SHIFT 0
3336 #define cfg_max_tow_xri_MASK 0x0000ffff
3337 #define cfg_max_tow_xri_WORD word20
3339 uint32_t word21; /* RESERVED */
3340 uint32_t word22; /* RESERVED */
3341 uint32_t word23; /* RESERVED */
3344 #define cfg_frag_field_offset_SHIFT 0
3345 #define cfg_frag_field_offset_MASK 0x0000ffff
3346 #define cfg_frag_field_offset_WORD word24
3348 #define cfg_frag_field_size_SHIFT 16
3349 #define cfg_frag_field_size_MASK 0x0000ffff
3350 #define cfg_frag_field_size_WORD word24
3353 #define cfg_sgl_field_offset_SHIFT 0
3354 #define cfg_sgl_field_offset_MASK 0x0000ffff
3355 #define cfg_sgl_field_offset_WORD word25
3357 #define cfg_sgl_field_size_SHIFT 16
3358 #define cfg_sgl_field_size_MASK 0x0000ffff
3359 #define cfg_sgl_field_size_WORD word25
3361 uint32_t word26; /* Chain SGE initial value LOW */
3362 uint32_t word27; /* Chain SGE initial value HIGH */
3363 #define LPFC_NODELAY_MAX_IO 32
3366 #define LPFC_SET_UE_RECOVERY 0x10
3367 #define LPFC_SET_MDS_DIAGS 0x12
3368 #define LPFC_SET_DUAL_DUMP 0x1e
3369 struct lpfc_mbx_set_feature {
3370 struct mbox_header header;
3374 #define lpfc_mbx_set_feature_UER_SHIFT 0
3375 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3376 #define lpfc_mbx_set_feature_UER_WORD word6
3377 #define lpfc_mbx_set_feature_mds_SHIFT 2
3378 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3379 #define lpfc_mbx_set_feature_mds_WORD word6
3380 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1
3381 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3382 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6
3383 #define lpfc_mbx_set_feature_dd_SHIFT 0
3384 #define lpfc_mbx_set_feature_dd_MASK 0x00000001
3385 #define lpfc_mbx_set_feature_dd_WORD word6
3386 #define lpfc_mbx_set_feature_ddquery_SHIFT 1
3387 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001
3388 #define lpfc_mbx_set_feature_ddquery_WORD word6
3389 #define LPFC_DISABLE_DUAL_DUMP 0
3390 #define LPFC_ENABLE_DUAL_DUMP 1
3391 #define LPFC_QUERY_OP_DUAL_DUMP 2
3393 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3394 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3395 #define lpfc_mbx_set_feature_UERP_WORD word7
3396 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3397 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3398 #define lpfc_mbx_set_feature_UESR_WORD word7
3402 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3403 struct lpfc_mbx_set_host_data {
3404 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48
3405 struct mbox_header header;
3408 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3411 struct lpfc_mbx_set_trunk_mode {
3412 struct mbox_header header;
3414 #define lpfc_mbx_set_trunk_mode_WORD word0
3415 #define lpfc_mbx_set_trunk_mode_SHIFT 0
3416 #define lpfc_mbx_set_trunk_mode_MASK 0xFF
3421 struct lpfc_mbx_get_sli4_parameters {
3422 struct mbox_header header;
3423 struct lpfc_sli4_parameters sli4_parameters;
3426 struct lpfc_rscr_desc_generic {
3427 #define LPFC_RSRC_DESC_WSIZE 22
3428 uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3431 struct lpfc_rsrc_desc_pcie {
3433 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3434 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3435 #define lpfc_rsrc_desc_pcie_type_WORD word0
3436 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3437 #define lpfc_rsrc_desc_pcie_length_SHIFT 8
3438 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3439 #define lpfc_rsrc_desc_pcie_length_WORD word0
3441 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3442 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3443 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1
3446 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3447 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3448 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
3449 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
3450 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3451 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
3452 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
3453 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3454 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3
3456 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3457 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3458 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
3461 struct lpfc_rsrc_desc_fcfcoe {
3463 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3464 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3465 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0
3466 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3467 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8
3468 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3469 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0
3470 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3471 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72
3472 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88
3474 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3475 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3476 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
3477 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
3478 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3479 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
3481 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3482 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3483 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
3484 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
3485 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3486 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
3488 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3489 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3490 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
3491 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
3492 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3493 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
3495 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3496 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3497 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
3498 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
3499 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3500 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
3502 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3503 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3504 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
3505 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
3506 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3507 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
3516 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3517 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3518 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
3519 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
3520 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3521 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
3522 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
3523 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3524 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
3525 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
3526 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3527 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
3528 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
3529 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3530 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
3531 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3536 uint32_t reserved[4];
3539 struct lpfc_func_cfg {
3540 #define LPFC_RSRC_DESC_MAX_NUM 2
3541 uint32_t rsrc_desc_count;
3542 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3545 struct lpfc_mbx_get_func_cfg {
3546 struct mbox_header header;
3547 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3548 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3549 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3550 struct lpfc_func_cfg func_cfg;
3553 struct lpfc_prof_cfg {
3554 #define LPFC_RSRC_DESC_MAX_NUM 2
3555 uint32_t rsrc_desc_count;
3556 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3559 struct lpfc_mbx_get_prof_cfg {
3560 struct mbox_header header;
3561 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3562 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3563 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3567 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3568 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3569 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
3570 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
3571 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3572 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
3575 struct lpfc_prof_cfg prof_cfg;
3580 struct lpfc_controller_attribute {
3581 uint32_t version_string[8];
3582 uint32_t manufacturer_name[8];
3583 uint32_t supported_modes;
3585 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3586 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3587 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17
3588 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
3589 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3590 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17
3591 uint32_t mbx_da_struct_ver;
3592 uint32_t ep_fw_da_struct_ver;
3593 uint32_t ncsi_ver_str[3];
3594 uint32_t dflt_ext_timeout;
3595 uint32_t model_number[8];
3596 uint32_t description[16];
3597 uint32_t serial_number[8];
3598 uint32_t ip_ver_str[8];
3599 uint32_t fw_ver_str[8];
3600 uint32_t bios_ver_str[8];
3601 uint32_t redboot_ver_str[8];
3602 uint32_t driver_ver_str[8];
3603 uint32_t flash_fw_ver_str[8];
3604 uint32_t functionality;
3606 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3607 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3608 #define lpfc_cntl_attr_max_cbd_len_WORD word105
3609 #define lpfc_cntl_attr_asic_rev_SHIFT 16
3610 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3611 #define lpfc_cntl_attr_asic_rev_WORD word105
3612 #define lpfc_cntl_attr_gen_guid0_SHIFT 24
3613 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3614 #define lpfc_cntl_attr_gen_guid0_WORD word105
3615 uint32_t gen_guid1_12[3];
3617 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3618 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3619 #define lpfc_cntl_attr_gen_guid13_14_WORD word109
3620 #define lpfc_cntl_attr_gen_guid15_SHIFT 16
3621 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3622 #define lpfc_cntl_attr_gen_guid15_WORD word109
3623 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
3624 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3625 #define lpfc_cntl_attr_hba_port_cnt_WORD word109
3627 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3628 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3629 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
3630 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24
3631 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3632 #define lpfc_cntl_attr_multi_func_dev_WORD word110
3634 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3635 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3636 #define lpfc_cntl_attr_cache_valid_WORD word111
3637 #define lpfc_cntl_attr_hba_status_SHIFT 8
3638 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3639 #define lpfc_cntl_attr_hba_status_WORD word111
3640 #define lpfc_cntl_attr_max_domain_SHIFT 16
3641 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3642 #define lpfc_cntl_attr_max_domain_WORD word111
3643 #define lpfc_cntl_attr_lnk_numb_SHIFT 24
3644 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3645 #define lpfc_cntl_attr_lnk_numb_WORD word111
3646 #define lpfc_cntl_attr_lnk_type_SHIFT 30
3647 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3648 #define lpfc_cntl_attr_lnk_type_WORD word111
3649 uint32_t fw_post_status;
3650 uint32_t hba_mtu[8];
3652 uint32_t reserved1[3];
3654 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3655 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3656 #define lpfc_cntl_attr_pci_vendor_id_WORD word125
3657 #define lpfc_cntl_attr_pci_device_id_SHIFT 16
3658 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3659 #define lpfc_cntl_attr_pci_device_id_WORD word125
3661 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3662 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3663 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126
3664 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
3665 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3666 #define lpfc_cntl_attr_pci_subsys_id_WORD word126
3668 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3669 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3670 #define lpfc_cntl_attr_pci_bus_num_WORD word127
3671 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8
3672 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3673 #define lpfc_cntl_attr_pci_dev_num_WORD word127
3674 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
3675 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3676 #define lpfc_cntl_attr_pci_fnc_num_WORD word127
3677 #define lpfc_cntl_attr_inf_type_SHIFT 24
3678 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3679 #define lpfc_cntl_attr_inf_type_WORD word127
3680 uint32_t unique_id[2];
3682 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3683 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3684 #define lpfc_cntl_attr_num_netfil_WORD word130
3685 uint32_t reserved2[4];
3688 struct lpfc_mbx_get_cntl_attributes {
3689 union lpfc_sli4_cfg_shdr cfg_shdr;
3690 struct lpfc_controller_attribute cntl_attr;
3693 struct lpfc_mbx_get_port_name {
3694 struct mbox_header header;
3698 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3699 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3700 #define lpfc_mbx_get_port_name_lnk_type_WORD word4
3704 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3705 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3706 #define lpfc_mbx_get_port_name_name0_WORD word4
3707 #define lpfc_mbx_get_port_name_name1_SHIFT 8
3708 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3709 #define lpfc_mbx_get_port_name_name1_WORD word4
3710 #define lpfc_mbx_get_port_name_name2_SHIFT 16
3711 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3712 #define lpfc_mbx_get_port_name_name2_WORD word4
3713 #define lpfc_mbx_get_port_name_name3_SHIFT 24
3714 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3715 #define lpfc_mbx_get_port_name_name3_WORD word4
3716 #define LPFC_LINK_NUMBER_0 0
3717 #define LPFC_LINK_NUMBER_1 1
3718 #define LPFC_LINK_NUMBER_2 2
3719 #define LPFC_LINK_NUMBER_3 3
3724 /* Mailbox Completion Queue Error Messages */
3725 #define MB_CQE_STATUS_SUCCESS 0x0
3726 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3727 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3728 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3729 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3730 #define MB_CQE_STATUS_DMA_FAILED 0x5
3732 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1
3733 struct lpfc_mbx_wr_object {
3734 struct mbox_header header;
3738 #define lpfc_wr_object_eof_SHIFT 31
3739 #define lpfc_wr_object_eof_MASK 0x00000001
3740 #define lpfc_wr_object_eof_WORD word4
3741 #define lpfc_wr_object_eas_SHIFT 29
3742 #define lpfc_wr_object_eas_MASK 0x00000001
3743 #define lpfc_wr_object_eas_WORD word4
3744 #define lpfc_wr_object_write_length_SHIFT 0
3745 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3746 #define lpfc_wr_object_write_length_WORD word4
3747 uint32_t write_offset;
3748 uint32_t object_name[26];
3750 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3753 uint32_t actual_write_length;
3755 #define lpfc_wr_object_change_status_SHIFT 0
3756 #define lpfc_wr_object_change_status_MASK 0x000000FF
3757 #define lpfc_wr_object_change_status_WORD word5
3758 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00
3759 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01
3760 #define LPFC_CHANGE_STATUS_FW_RESET 0x02
3761 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04
3762 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05
3763 #define lpfc_wr_object_csf_SHIFT 8
3764 #define lpfc_wr_object_csf_MASK 0x00000001
3765 #define lpfc_wr_object_csf_WORD word5
3770 /* mailbox queue entry structure */
3773 #define lpfc_mqe_status_SHIFT 16
3774 #define lpfc_mqe_status_MASK 0x0000FFFF
3775 #define lpfc_mqe_status_WORD word0
3776 #define lpfc_mqe_command_SHIFT 8
3777 #define lpfc_mqe_command_MASK 0x000000FF
3778 #define lpfc_mqe_command_WORD word0
3780 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3781 /* sli4 mailbox commands */
3782 struct lpfc_mbx_sli4_config sli4_config;
3783 struct lpfc_mbx_init_vfi init_vfi;
3784 struct lpfc_mbx_reg_vfi reg_vfi;
3785 struct lpfc_mbx_reg_vfi unreg_vfi;
3786 struct lpfc_mbx_init_vpi init_vpi;
3787 struct lpfc_mbx_resume_rpi resume_rpi;
3788 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3789 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3790 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3791 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3792 struct lpfc_mbx_reg_fcfi reg_fcfi;
3793 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3794 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3795 struct lpfc_mbx_mq_create mq_create;
3796 struct lpfc_mbx_mq_create_ext mq_create_ext;
3797 struct lpfc_mbx_eq_create eq_create;
3798 struct lpfc_mbx_modify_eq_delay eq_delay;
3799 struct lpfc_mbx_cq_create cq_create;
3800 struct lpfc_mbx_cq_create_set cq_create_set;
3801 struct lpfc_mbx_wq_create wq_create;
3802 struct lpfc_mbx_rq_create rq_create;
3803 struct lpfc_mbx_rq_create_v2 rq_create_v2;
3804 struct lpfc_mbx_mq_destroy mq_destroy;
3805 struct lpfc_mbx_eq_destroy eq_destroy;
3806 struct lpfc_mbx_cq_destroy cq_destroy;
3807 struct lpfc_mbx_wq_destroy wq_destroy;
3808 struct lpfc_mbx_rq_destroy rq_destroy;
3809 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3810 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3811 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3812 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3813 struct lpfc_mbx_nembed_cmd nembed_cmd;
3814 struct lpfc_mbx_read_rev read_rev;
3815 struct lpfc_mbx_read_vpi read_vpi;
3816 struct lpfc_mbx_read_config rd_config;
3817 struct lpfc_mbx_request_features req_ftrs;
3818 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3819 struct lpfc_mbx_query_fw_config query_fw_cfg;
3820 struct lpfc_mbx_set_beacon_config beacon_config;
3821 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3822 struct lpfc_mbx_set_link_diag_state link_diag_state;
3823 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3824 struct lpfc_mbx_run_link_diag_test link_diag_test;
3825 struct lpfc_mbx_get_func_cfg get_func_cfg;
3826 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3827 struct lpfc_mbx_wr_object wr_object;
3828 struct lpfc_mbx_get_port_name get_port_name;
3829 struct lpfc_mbx_set_feature set_feature;
3830 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3831 struct lpfc_mbx_set_host_data set_host_data;
3832 struct lpfc_mbx_set_trunk_mode set_trunk_mode;
3833 struct lpfc_mbx_nop nop;
3834 struct lpfc_mbx_set_ras_fwlog ras_fwlog;
3840 #define lpfc_mcqe_status_SHIFT 0
3841 #define lpfc_mcqe_status_MASK 0x0000FFFF
3842 #define lpfc_mcqe_status_WORD word0
3843 #define lpfc_mcqe_ext_status_SHIFT 16
3844 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3845 #define lpfc_mcqe_ext_status_WORD word0
3849 #define lpfc_trailer_valid_SHIFT 31
3850 #define lpfc_trailer_valid_MASK 0x00000001
3851 #define lpfc_trailer_valid_WORD trailer
3852 #define lpfc_trailer_async_SHIFT 30
3853 #define lpfc_trailer_async_MASK 0x00000001
3854 #define lpfc_trailer_async_WORD trailer
3855 #define lpfc_trailer_hpi_SHIFT 29
3856 #define lpfc_trailer_hpi_MASK 0x00000001
3857 #define lpfc_trailer_hpi_WORD trailer
3858 #define lpfc_trailer_completed_SHIFT 28
3859 #define lpfc_trailer_completed_MASK 0x00000001
3860 #define lpfc_trailer_completed_WORD trailer
3861 #define lpfc_trailer_consumed_SHIFT 27
3862 #define lpfc_trailer_consumed_MASK 0x00000001
3863 #define lpfc_trailer_consumed_WORD trailer
3864 #define lpfc_trailer_type_SHIFT 16
3865 #define lpfc_trailer_type_MASK 0x000000FF
3866 #define lpfc_trailer_type_WORD trailer
3867 #define lpfc_trailer_code_SHIFT 8
3868 #define lpfc_trailer_code_MASK 0x000000FF
3869 #define lpfc_trailer_code_WORD trailer
3870 #define LPFC_TRAILER_CODE_LINK 0x1
3871 #define LPFC_TRAILER_CODE_FCOE 0x2
3872 #define LPFC_TRAILER_CODE_DCBX 0x3
3873 #define LPFC_TRAILER_CODE_GRP5 0x5
3874 #define LPFC_TRAILER_CODE_FC 0x10
3875 #define LPFC_TRAILER_CODE_SLI 0x11
3878 struct lpfc_acqe_link {
3880 #define lpfc_acqe_link_speed_SHIFT 24
3881 #define lpfc_acqe_link_speed_MASK 0x000000FF
3882 #define lpfc_acqe_link_speed_WORD word0
3883 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
3884 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
3885 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
3886 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
3887 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
3888 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
3889 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
3890 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
3891 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
3892 #define lpfc_acqe_link_duplex_SHIFT 16
3893 #define lpfc_acqe_link_duplex_MASK 0x000000FF
3894 #define lpfc_acqe_link_duplex_WORD word0
3895 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
3896 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
3897 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
3898 #define lpfc_acqe_link_status_SHIFT 8
3899 #define lpfc_acqe_link_status_MASK 0x000000FF
3900 #define lpfc_acqe_link_status_WORD word0
3901 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3902 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3903 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3904 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3905 #define lpfc_acqe_link_type_SHIFT 6
3906 #define lpfc_acqe_link_type_MASK 0x00000003
3907 #define lpfc_acqe_link_type_WORD word0
3908 #define lpfc_acqe_link_number_SHIFT 0
3909 #define lpfc_acqe_link_number_MASK 0x0000003F
3910 #define lpfc_acqe_link_number_WORD word0
3912 #define lpfc_acqe_link_fault_SHIFT 0
3913 #define lpfc_acqe_link_fault_MASK 0x000000FF
3914 #define lpfc_acqe_link_fault_WORD word1
3915 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3916 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3917 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3918 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
3919 #define lpfc_acqe_logical_link_speed_SHIFT 16
3920 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3921 #define lpfc_acqe_logical_link_speed_WORD word1
3924 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3925 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3928 struct lpfc_acqe_fip {
3931 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3932 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3933 #define lpfc_acqe_fip_fcf_count_WORD word1
3934 #define lpfc_acqe_fip_event_type_SHIFT 16
3935 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3936 #define lpfc_acqe_fip_event_type_WORD word1
3939 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3940 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3941 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3942 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3943 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3946 struct lpfc_acqe_dcbx {
3953 struct lpfc_acqe_grp5 {
3955 #define lpfc_acqe_grp5_type_SHIFT 6
3956 #define lpfc_acqe_grp5_type_MASK 0x00000003
3957 #define lpfc_acqe_grp5_type_WORD word0
3958 #define lpfc_acqe_grp5_number_SHIFT 0
3959 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3960 #define lpfc_acqe_grp5_number_WORD word0
3962 #define lpfc_acqe_grp5_llink_spd_SHIFT 16
3963 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3964 #define lpfc_acqe_grp5_llink_spd_WORD word1
3969 extern const char *const trunk_errmsg[];
3971 struct lpfc_acqe_fc_la {
3973 #define lpfc_acqe_fc_la_speed_SHIFT 24
3974 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3975 #define lpfc_acqe_fc_la_speed_WORD word0
3976 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
3977 #define LPFC_FC_LA_SPEED_1G 0x1
3978 #define LPFC_FC_LA_SPEED_2G 0x2
3979 #define LPFC_FC_LA_SPEED_4G 0x4
3980 #define LPFC_FC_LA_SPEED_8G 0x8
3981 #define LPFC_FC_LA_SPEED_10G 0xA
3982 #define LPFC_FC_LA_SPEED_16G 0x10
3983 #define LPFC_FC_LA_SPEED_32G 0x20
3984 #define LPFC_FC_LA_SPEED_64G 0x21
3985 #define LPFC_FC_LA_SPEED_128G 0x22
3986 #define LPFC_FC_LA_SPEED_256G 0x23
3987 #define lpfc_acqe_fc_la_topology_SHIFT 16
3988 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3989 #define lpfc_acqe_fc_la_topology_WORD word0
3990 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3991 #define LPFC_FC_LA_TOP_P2P 0x1
3992 #define LPFC_FC_LA_TOP_FCAL 0x2
3993 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3994 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3995 #define lpfc_acqe_fc_la_att_type_SHIFT 8
3996 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3997 #define lpfc_acqe_fc_la_att_type_WORD word0
3998 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3999 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4000 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4001 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4002 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4003 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4004 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7
4005 #define lpfc_acqe_fc_la_port_type_SHIFT 6
4006 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4007 #define lpfc_acqe_fc_la_port_type_WORD word0
4008 #define LPFC_LINK_TYPE_ETHERNET 0x0
4009 #define LPFC_LINK_TYPE_FC 0x1
4010 #define lpfc_acqe_fc_la_port_number_SHIFT 0
4011 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4012 #define lpfc_acqe_fc_la_port_number_WORD word0
4014 /* Attention Type is 0x07 (Trunking Event) word0 */
4015 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16
4016 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001
4017 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0
4018 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17
4019 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001
4020 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0
4021 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18
4022 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001
4023 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0
4024 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19
4025 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001
4026 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0
4027 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20
4028 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001
4029 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0
4030 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21
4031 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001
4032 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0
4033 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22
4034 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001
4035 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0
4036 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23
4037 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001
4038 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0
4040 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16
4041 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4042 #define lpfc_acqe_fc_la_llink_spd_WORD word1
4043 #define lpfc_acqe_fc_la_fault_SHIFT 0
4044 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4045 #define lpfc_acqe_fc_la_fault_WORD word1
4046 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0
4047 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F
4048 #define lpfc_acqe_fc_la_trunk_fault_WORD word1
4049 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4
4050 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F
4051 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1
4052 #define LPFC_FC_LA_FAULT_NONE 0x0
4053 #define LPFC_FC_LA_FAULT_LOCAL 0x1
4054 #define LPFC_FC_LA_FAULT_REMOTE 0x2
4057 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4058 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4061 struct lpfc_acqe_misconfigured_event {
4064 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
4065 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4066 #define lpfc_sli_misconfigured_port0_state_WORD word0
4067 #define lpfc_sli_misconfigured_port1_state_SHIFT 8
4068 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4069 #define lpfc_sli_misconfigured_port1_state_WORD word0
4070 #define lpfc_sli_misconfigured_port2_state_SHIFT 16
4071 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4072 #define lpfc_sli_misconfigured_port2_state_WORD word0
4073 #define lpfc_sli_misconfigured_port3_state_SHIFT 24
4074 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4075 #define lpfc_sli_misconfigured_port3_state_WORD word0
4077 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
4078 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4079 #define lpfc_sli_misconfigured_port0_op_WORD word1
4080 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1
4081 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4082 #define lpfc_sli_misconfigured_port0_severity_WORD word1
4083 #define lpfc_sli_misconfigured_port1_op_SHIFT 8
4084 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4085 #define lpfc_sli_misconfigured_port1_op_WORD word1
4086 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9
4087 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4088 #define lpfc_sli_misconfigured_port1_severity_WORD word1
4089 #define lpfc_sli_misconfigured_port2_op_SHIFT 16
4090 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4091 #define lpfc_sli_misconfigured_port2_op_WORD word1
4092 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17
4093 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4094 #define lpfc_sli_misconfigured_port2_severity_WORD word1
4095 #define lpfc_sli_misconfigured_port3_op_SHIFT 24
4096 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4097 #define lpfc_sli_misconfigured_port3_op_WORD word1
4098 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25
4099 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4100 #define lpfc_sli_misconfigured_port3_severity_WORD word1
4102 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
4103 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4104 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4105 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4106 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4107 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4110 struct lpfc_acqe_sli {
4111 uint32_t event_data1;
4112 uint32_t event_data2;
4115 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4116 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4117 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4118 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4119 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4120 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4121 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4122 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF
4123 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10
4127 * Define the bootstrap mailbox (bmbx) region used to communicate
4128 * mailbox command between the host and port. The mailbox consists
4129 * of a payload area of 256 bytes and a completion queue of length
4132 struct lpfc_bmbx_create {
4133 struct lpfc_mqe mqe;
4134 struct lpfc_mcqe mcqe;
4137 #define SGL_ALIGN_SZ 64
4138 #define SGL_PAGE_SIZE 4096
4139 /* align SGL addr on a size boundary - adjust address up */
4140 #define NO_XRI 0xffff
4144 #define wqe_xri_tag_SHIFT 0
4145 #define wqe_xri_tag_MASK 0x0000FFFF
4146 #define wqe_xri_tag_WORD word6
4147 #define wqe_ctxt_tag_SHIFT 16
4148 #define wqe_ctxt_tag_MASK 0x0000FFFF
4149 #define wqe_ctxt_tag_WORD word6
4151 #define wqe_dif_SHIFT 0
4152 #define wqe_dif_MASK 0x00000003
4153 #define wqe_dif_WORD word7
4154 #define LPFC_WQE_DIF_PASSTHRU 1
4155 #define LPFC_WQE_DIF_STRIP 2
4156 #define LPFC_WQE_DIF_INSERT 3
4157 #define wqe_ct_SHIFT 2
4158 #define wqe_ct_MASK 0x00000003
4159 #define wqe_ct_WORD word7
4160 #define wqe_status_SHIFT 4
4161 #define wqe_status_MASK 0x0000000f
4162 #define wqe_status_WORD word7
4163 #define wqe_cmnd_SHIFT 8
4164 #define wqe_cmnd_MASK 0x000000ff
4165 #define wqe_cmnd_WORD word7
4166 #define wqe_class_SHIFT 16
4167 #define wqe_class_MASK 0x00000007
4168 #define wqe_class_WORD word7
4169 #define wqe_ar_SHIFT 19
4170 #define wqe_ar_MASK 0x00000001
4171 #define wqe_ar_WORD word7
4172 #define wqe_ag_SHIFT wqe_ar_SHIFT
4173 #define wqe_ag_MASK wqe_ar_MASK
4174 #define wqe_ag_WORD wqe_ar_WORD
4175 #define wqe_pu_SHIFT 20
4176 #define wqe_pu_MASK 0x00000003
4177 #define wqe_pu_WORD word7
4178 #define wqe_erp_SHIFT 22
4179 #define wqe_erp_MASK 0x00000001
4180 #define wqe_erp_WORD word7
4181 #define wqe_conf_SHIFT wqe_erp_SHIFT
4182 #define wqe_conf_MASK wqe_erp_MASK
4183 #define wqe_conf_WORD wqe_erp_WORD
4184 #define wqe_lnk_SHIFT 23
4185 #define wqe_lnk_MASK 0x00000001
4186 #define wqe_lnk_WORD word7
4187 #define wqe_tmo_SHIFT 24
4188 #define wqe_tmo_MASK 0x000000ff
4189 #define wqe_tmo_WORD word7
4190 uint32_t abort_tag; /* word 8 in WQE */
4192 #define wqe_reqtag_SHIFT 0
4193 #define wqe_reqtag_MASK 0x0000FFFF
4194 #define wqe_reqtag_WORD word9
4195 #define wqe_temp_rpi_SHIFT 16
4196 #define wqe_temp_rpi_MASK 0x0000FFFF
4197 #define wqe_temp_rpi_WORD word9
4198 #define wqe_rcvoxid_SHIFT 16
4199 #define wqe_rcvoxid_MASK 0x0000FFFF
4200 #define wqe_rcvoxid_WORD word9
4201 #define wqe_sof_SHIFT 24
4202 #define wqe_sof_MASK 0x000000FF
4203 #define wqe_sof_WORD word9
4204 #define wqe_eof_SHIFT 16
4205 #define wqe_eof_MASK 0x000000FF
4206 #define wqe_eof_WORD word9
4208 #define wqe_ebde_cnt_SHIFT 0
4209 #define wqe_ebde_cnt_MASK 0x0000000f
4210 #define wqe_ebde_cnt_WORD word10
4211 #define wqe_nvme_SHIFT 4
4212 #define wqe_nvme_MASK 0x00000001
4213 #define wqe_nvme_WORD word10
4214 #define wqe_oas_SHIFT 6
4215 #define wqe_oas_MASK 0x00000001
4216 #define wqe_oas_WORD word10
4217 #define wqe_lenloc_SHIFT 7
4218 #define wqe_lenloc_MASK 0x00000003
4219 #define wqe_lenloc_WORD word10
4220 #define LPFC_WQE_LENLOC_NONE 0
4221 #define LPFC_WQE_LENLOC_WORD3 1
4222 #define LPFC_WQE_LENLOC_WORD12 2
4223 #define LPFC_WQE_LENLOC_WORD4 3
4224 #define wqe_qosd_SHIFT 9
4225 #define wqe_qosd_MASK 0x00000001
4226 #define wqe_qosd_WORD word10
4227 #define wqe_xbl_SHIFT 11
4228 #define wqe_xbl_MASK 0x00000001
4229 #define wqe_xbl_WORD word10
4230 #define wqe_iod_SHIFT 13
4231 #define wqe_iod_MASK 0x00000001
4232 #define wqe_iod_WORD word10
4233 #define LPFC_WQE_IOD_NONE 0
4234 #define LPFC_WQE_IOD_WRITE 0
4235 #define LPFC_WQE_IOD_READ 1
4236 #define wqe_dbde_SHIFT 14
4237 #define wqe_dbde_MASK 0x00000001
4238 #define wqe_dbde_WORD word10
4239 #define wqe_wqes_SHIFT 15
4240 #define wqe_wqes_MASK 0x00000001
4241 #define wqe_wqes_WORD word10
4242 /* Note that this field overlaps above fields */
4243 #define wqe_wqid_SHIFT 1
4244 #define wqe_wqid_MASK 0x00007fff
4245 #define wqe_wqid_WORD word10
4246 #define wqe_pri_SHIFT 16
4247 #define wqe_pri_MASK 0x00000007
4248 #define wqe_pri_WORD word10
4249 #define wqe_pv_SHIFT 19
4250 #define wqe_pv_MASK 0x00000001
4251 #define wqe_pv_WORD word10
4252 #define wqe_xc_SHIFT 21
4253 #define wqe_xc_MASK 0x00000001
4254 #define wqe_xc_WORD word10
4255 #define wqe_sr_SHIFT 22
4256 #define wqe_sr_MASK 0x00000001
4257 #define wqe_sr_WORD word10
4258 #define wqe_ccpe_SHIFT 23
4259 #define wqe_ccpe_MASK 0x00000001
4260 #define wqe_ccpe_WORD word10
4261 #define wqe_ccp_SHIFT 24
4262 #define wqe_ccp_MASK 0x000000ff
4263 #define wqe_ccp_WORD word10
4265 #define wqe_cmd_type_SHIFT 0
4266 #define wqe_cmd_type_MASK 0x0000000f
4267 #define wqe_cmd_type_WORD word11
4268 #define wqe_els_id_SHIFT 4
4269 #define wqe_els_id_MASK 0x00000003
4270 #define wqe_els_id_WORD word11
4271 #define LPFC_ELS_ID_FLOGI 3
4272 #define LPFC_ELS_ID_FDISC 2
4273 #define LPFC_ELS_ID_LOGO 1
4274 #define LPFC_ELS_ID_DEFAULT 0
4275 #define wqe_irsp_SHIFT 4
4276 #define wqe_irsp_MASK 0x00000001
4277 #define wqe_irsp_WORD word11
4278 #define wqe_pbde_SHIFT 5
4279 #define wqe_pbde_MASK 0x00000001
4280 #define wqe_pbde_WORD word11
4281 #define wqe_sup_SHIFT 6
4282 #define wqe_sup_MASK 0x00000001
4283 #define wqe_sup_WORD word11
4284 #define wqe_ffrq_SHIFT 6
4285 #define wqe_ffrq_MASK 0x00000001
4286 #define wqe_ffrq_WORD word11
4287 #define wqe_wqec_SHIFT 7
4288 #define wqe_wqec_MASK 0x00000001
4289 #define wqe_wqec_WORD word11
4290 #define wqe_irsplen_SHIFT 8
4291 #define wqe_irsplen_MASK 0x0000000f
4292 #define wqe_irsplen_WORD word11
4293 #define wqe_cqid_SHIFT 16
4294 #define wqe_cqid_MASK 0x0000ffff
4295 #define wqe_cqid_WORD word11
4296 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4301 #define wqe_els_did_SHIFT 0
4302 #define wqe_els_did_MASK 0x00FFFFFF
4303 #define wqe_els_did_WORD word5
4304 #define wqe_xmit_bls_pt_SHIFT 28
4305 #define wqe_xmit_bls_pt_MASK 0x00000003
4306 #define wqe_xmit_bls_pt_WORD word5
4307 #define wqe_xmit_bls_ar_SHIFT 30
4308 #define wqe_xmit_bls_ar_MASK 0x00000001
4309 #define wqe_xmit_bls_ar_WORD word5
4310 #define wqe_xmit_bls_xo_SHIFT 31
4311 #define wqe_xmit_bls_xo_MASK 0x00000001
4312 #define wqe_xmit_bls_xo_WORD word5
4315 struct lpfc_wqe_generic{
4316 struct ulp_bde64 bde;
4320 struct wqe_common wqe_com;
4321 uint32_t payload[4];
4324 struct els_request64_wqe {
4325 struct ulp_bde64 bde;
4326 uint32_t payload_len;
4328 #define els_req64_sid_SHIFT 0
4329 #define els_req64_sid_MASK 0x00FFFFFF
4330 #define els_req64_sid_WORD word4
4331 #define els_req64_sp_SHIFT 24
4332 #define els_req64_sp_MASK 0x00000001
4333 #define els_req64_sp_WORD word4
4334 #define els_req64_vf_SHIFT 25
4335 #define els_req64_vf_MASK 0x00000001
4336 #define els_req64_vf_WORD word4
4337 struct wqe_did wqe_dest;
4338 struct wqe_common wqe_com; /* words 6-11 */
4340 #define els_req64_vfid_SHIFT 1
4341 #define els_req64_vfid_MASK 0x00000FFF
4342 #define els_req64_vfid_WORD word12
4343 #define els_req64_pri_SHIFT 13
4344 #define els_req64_pri_MASK 0x00000007
4345 #define els_req64_pri_WORD word12
4347 #define els_req64_hopcnt_SHIFT 24
4348 #define els_req64_hopcnt_MASK 0x000000ff
4349 #define els_req64_hopcnt_WORD word13
4351 uint32_t max_response_payload_len;
4354 struct xmit_els_rsp64_wqe {
4355 struct ulp_bde64 bde;
4356 uint32_t response_payload_len;
4358 #define els_rsp64_sid_SHIFT 0
4359 #define els_rsp64_sid_MASK 0x00FFFFFF
4360 #define els_rsp64_sid_WORD word4
4361 #define els_rsp64_sp_SHIFT 24
4362 #define els_rsp64_sp_MASK 0x00000001
4363 #define els_rsp64_sp_WORD word4
4364 struct wqe_did wqe_dest;
4365 struct wqe_common wqe_com; /* words 6-11 */
4367 #define wqe_rsp_temp_rpi_SHIFT 0
4368 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4369 #define wqe_rsp_temp_rpi_WORD word12
4370 uint32_t rsvd_13_15[3];
4373 struct xmit_bls_rsp64_wqe {
4375 /* Payload0 for BA_ACC */
4376 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
4377 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4378 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
4379 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
4380 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4381 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
4382 /* Payload0 for BA_RJT */
4383 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4384 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4385 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
4386 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
4387 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4388 #define xmit_bls_rsp64_rjt_expc_WORD payload0
4389 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
4390 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4391 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
4393 #define xmit_bls_rsp64_rxid_SHIFT 0
4394 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4395 #define xmit_bls_rsp64_rxid_WORD word1
4396 #define xmit_bls_rsp64_oxid_SHIFT 16
4397 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4398 #define xmit_bls_rsp64_oxid_WORD word1
4400 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4401 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4402 #define xmit_bls_rsp64_seqcnthi_WORD word2
4403 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
4404 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4405 #define xmit_bls_rsp64_seqcntlo_WORD word2
4408 struct wqe_did wqe_dest;
4409 struct wqe_common wqe_com; /* words 6-11 */
4411 #define xmit_bls_rsp64_temprpi_SHIFT 0
4412 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4413 #define xmit_bls_rsp64_temprpi_WORD word12
4414 uint32_t rsvd_13_15[3];
4417 struct wqe_rctl_dfctl {
4419 #define wqe_si_SHIFT 2
4420 #define wqe_si_MASK 0x000000001
4421 #define wqe_si_WORD word5
4422 #define wqe_la_SHIFT 3
4423 #define wqe_la_MASK 0x000000001
4424 #define wqe_la_WORD word5
4425 #define wqe_xo_SHIFT 6
4426 #define wqe_xo_MASK 0x000000001
4427 #define wqe_xo_WORD word5
4428 #define wqe_ls_SHIFT 7
4429 #define wqe_ls_MASK 0x000000001
4430 #define wqe_ls_WORD word5
4431 #define wqe_dfctl_SHIFT 8
4432 #define wqe_dfctl_MASK 0x0000000ff
4433 #define wqe_dfctl_WORD word5
4434 #define wqe_type_SHIFT 16
4435 #define wqe_type_MASK 0x0000000ff
4436 #define wqe_type_WORD word5
4437 #define wqe_rctl_SHIFT 24
4438 #define wqe_rctl_MASK 0x0000000ff
4439 #define wqe_rctl_WORD word5
4442 struct xmit_seq64_wqe {
4443 struct ulp_bde64 bde;
4445 uint32_t relative_offset;
4446 struct wqe_rctl_dfctl wge_ctl;
4447 struct wqe_common wqe_com; /* words 6-11 */
4449 uint32_t rsvd_12_15[3];
4451 struct xmit_bcast64_wqe {
4452 struct ulp_bde64 bde;
4453 uint32_t seq_payload_len;
4455 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4456 struct wqe_common wqe_com; /* words 6-11 */
4457 uint32_t rsvd_12_15[4];
4460 struct gen_req64_wqe {
4461 struct ulp_bde64 bde;
4462 uint32_t request_payload_len;
4463 uint32_t relative_offset;
4464 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4465 struct wqe_common wqe_com; /* words 6-11 */
4466 uint32_t rsvd_12_14[3];
4467 uint32_t max_response_payload_len;
4470 /* Define NVME PRLI request to fabric. NVME is a
4471 * fabric-only protocol.
4472 * Updated to red-lined v1.08 on Sept 16, 2016
4474 struct lpfc_nvme_prli {
4476 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4477 #define prli_acc_rsp_code_SHIFT 8
4478 #define prli_acc_rsp_code_MASK 0x0000000f
4479 #define prli_acc_rsp_code_WORD word1
4480 #define prli_estabImagePair_SHIFT 13
4481 #define prli_estabImagePair_MASK 0x00000001
4482 #define prli_estabImagePair_WORD word1
4483 #define prli_type_code_ext_SHIFT 16
4484 #define prli_type_code_ext_MASK 0x000000ff
4485 #define prli_type_code_ext_WORD word1
4486 #define prli_type_code_SHIFT 24
4487 #define prli_type_code_MASK 0x000000ff
4488 #define prli_type_code_WORD word1
4489 uint32_t word_rsvd2;
4490 uint32_t word_rsvd3;
4493 #define prli_fba_SHIFT 0
4494 #define prli_fba_MASK 0x00000001
4495 #define prli_fba_WORD word4
4496 #define prli_disc_SHIFT 3
4497 #define prli_disc_MASK 0x00000001
4498 #define prli_disc_WORD word4
4499 #define prli_tgt_SHIFT 4
4500 #define prli_tgt_MASK 0x00000001
4501 #define prli_tgt_WORD word4
4502 #define prli_init_SHIFT 5
4503 #define prli_init_MASK 0x00000001
4504 #define prli_init_WORD word4
4505 #define prli_conf_SHIFT 7
4506 #define prli_conf_MASK 0x00000001
4507 #define prli_conf_WORD word4
4508 #define prli_nsler_SHIFT 8
4509 #define prli_nsler_MASK 0x00000001
4510 #define prli_nsler_WORD word4
4512 #define prli_fb_sz_SHIFT 0
4513 #define prli_fb_sz_MASK 0x0000ffff
4514 #define prli_fb_sz_WORD word5
4515 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */
4518 struct create_xri_wqe {
4519 uint32_t rsrvd[5]; /* words 0-4 */
4520 struct wqe_did wqe_dest; /* word 5 */
4521 struct wqe_common wqe_com; /* words 6-11 */
4522 uint32_t rsvd_12_15[4]; /* word 12-15 */
4525 #define INHIBIT_ABORT 1
4526 #define T_REQUEST_TAG 3
4529 struct abort_cmd_wqe {
4532 #define abort_cmd_ia_SHIFT 0
4533 #define abort_cmd_ia_MASK 0x000000001
4534 #define abort_cmd_ia_WORD word3
4535 #define abort_cmd_criteria_SHIFT 8
4536 #define abort_cmd_criteria_MASK 0x0000000ff
4537 #define abort_cmd_criteria_WORD word3
4540 struct wqe_common wqe_com; /* words 6-11 */
4541 uint32_t rsvd_12_15[4]; /* word 12-15 */
4544 struct fcp_iwrite64_wqe {
4545 struct ulp_bde64 bde;
4547 #define cmd_buff_len_SHIFT 16
4548 #define cmd_buff_len_MASK 0x00000ffff
4549 #define cmd_buff_len_WORD word3
4550 #define payload_offset_len_SHIFT 0
4551 #define payload_offset_len_MASK 0x0000ffff
4552 #define payload_offset_len_WORD word3
4553 uint32_t total_xfer_len;
4554 uint32_t initial_xfer_len;
4555 struct wqe_common wqe_com; /* words 6-11 */
4557 struct ulp_bde64 ph_bde; /* words 13-15 */
4560 struct fcp_iread64_wqe {
4561 struct ulp_bde64 bde;
4563 #define cmd_buff_len_SHIFT 16
4564 #define cmd_buff_len_MASK 0x00000ffff
4565 #define cmd_buff_len_WORD word3
4566 #define payload_offset_len_SHIFT 0
4567 #define payload_offset_len_MASK 0x0000ffff
4568 #define payload_offset_len_WORD word3
4569 uint32_t total_xfer_len; /* word 4 */
4570 uint32_t rsrvd5; /* word 5 */
4571 struct wqe_common wqe_com; /* words 6-11 */
4573 struct ulp_bde64 ph_bde; /* words 13-15 */
4576 struct fcp_icmnd64_wqe {
4577 struct ulp_bde64 bde; /* words 0-2 */
4579 #define cmd_buff_len_SHIFT 16
4580 #define cmd_buff_len_MASK 0x00000ffff
4581 #define cmd_buff_len_WORD word3
4582 #define payload_offset_len_SHIFT 0
4583 #define payload_offset_len_MASK 0x0000ffff
4584 #define payload_offset_len_WORD word3
4585 uint32_t rsrvd4; /* word 4 */
4586 uint32_t rsrvd5; /* word 5 */
4587 struct wqe_common wqe_com; /* words 6-11 */
4588 uint32_t rsvd_12_15[4]; /* word 12-15 */
4591 struct fcp_trsp64_wqe {
4592 struct ulp_bde64 bde;
4593 uint32_t response_len;
4594 uint32_t rsvd_4_5[2];
4595 struct wqe_common wqe_com; /* words 6-11 */
4596 uint32_t rsvd_12_15[4]; /* word 12-15 */
4599 struct fcp_tsend64_wqe {
4600 struct ulp_bde64 bde;
4601 uint32_t payload_offset_len;
4602 uint32_t relative_offset;
4604 struct wqe_common wqe_com; /* words 6-11 */
4605 uint32_t fcp_data_len; /* word 12 */
4606 uint32_t rsvd_13_15[3]; /* word 13-15 */
4609 struct fcp_treceive64_wqe {
4610 struct ulp_bde64 bde;
4611 uint32_t payload_offset_len;
4612 uint32_t relative_offset;
4614 struct wqe_common wqe_com; /* words 6-11 */
4615 uint32_t fcp_data_len; /* word 12 */
4616 uint32_t rsvd_13_15[3]; /* word 13-15 */
4618 #define TXRDY_PAYLOAD_LEN 12
4620 #define CMD_SEND_FRAME 0xE1
4622 struct send_frame_wqe {
4623 struct ulp_bde64 bde; /* words 0-2 */
4624 uint32_t frame_len; /* word 3 */
4625 uint32_t fc_hdr_wd0; /* word 4 */
4626 uint32_t fc_hdr_wd1; /* word 5 */
4627 struct wqe_common wqe_com; /* words 6-11 */
4628 uint32_t fc_hdr_wd2; /* word 12 */
4629 uint32_t fc_hdr_wd3; /* word 13 */
4630 uint32_t fc_hdr_wd4; /* word 14 */
4631 uint32_t fc_hdr_wd5; /* word 15 */
4634 #define ELS_RDF_REG_TAG_CNT 4
4635 struct lpfc_els_rdf_reg_desc {
4636 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */
4637 __be32 desc_tags[ELS_RDF_REG_TAG_CNT];
4638 /* tags in reg_desc */
4641 struct lpfc_els_rdf_req {
4642 struct fc_els_rdf rdf; /* hdr up to descriptors */
4643 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */
4646 struct lpfc_els_rdf_rsp {
4647 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */
4648 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */
4653 struct lpfc_wqe_generic generic;
4654 struct fcp_icmnd64_wqe fcp_icmd;
4655 struct fcp_iread64_wqe fcp_iread;
4656 struct fcp_iwrite64_wqe fcp_iwrite;
4657 struct abort_cmd_wqe abort_cmd;
4658 struct create_xri_wqe create_xri;
4659 struct xmit_bcast64_wqe xmit_bcast64;
4660 struct xmit_seq64_wqe xmit_sequence;
4661 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4662 struct xmit_els_rsp64_wqe xmit_els_rsp;
4663 struct els_request64_wqe els_req;
4664 struct gen_req64_wqe gen_req;
4665 struct fcp_trsp64_wqe fcp_trsp;
4666 struct fcp_tsend64_wqe fcp_tsend;
4667 struct fcp_treceive64_wqe fcp_treceive;
4668 struct send_frame_wqe send_frame;
4673 struct lpfc_wqe_generic generic;
4674 struct fcp_icmnd64_wqe fcp_icmd;
4675 struct fcp_iread64_wqe fcp_iread;
4676 struct fcp_iwrite64_wqe fcp_iwrite;
4677 struct abort_cmd_wqe abort_cmd;
4678 struct create_xri_wqe create_xri;
4679 struct xmit_bcast64_wqe xmit_bcast64;
4680 struct xmit_seq64_wqe xmit_sequence;
4681 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4682 struct xmit_els_rsp64_wqe xmit_els_rsp;
4683 struct els_request64_wqe els_req;
4684 struct gen_req64_wqe gen_req;
4685 struct fcp_trsp64_wqe fcp_trsp;
4686 struct fcp_tsend64_wqe fcp_tsend;
4687 struct fcp_treceive64_wqe fcp_treceive;
4688 struct send_frame_wqe send_frame;
4691 #define MAGIC_NUMBER_G6 0xFEAA0003
4692 #define MAGIC_NUMBER_G7 0xFEAA0005
4694 struct lpfc_grp_hdr {
4696 uint32_t magic_number;
4698 #define lpfc_grp_hdr_file_type_SHIFT 24
4699 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4700 #define lpfc_grp_hdr_file_type_WORD word2
4701 #define lpfc_grp_hdr_id_SHIFT 16
4702 #define lpfc_grp_hdr_id_MASK 0x000000FF
4703 #define lpfc_grp_hdr_id_WORD word2
4704 uint8_t rev_name[128];
4706 uint8_t revision[32];
4709 /* Defines for WQE command type */
4710 #define FCP_COMMAND 0x0
4711 #define NVME_READ_CMD 0x0
4712 #define FCP_COMMAND_DATA_OUT 0x1
4713 #define NVME_WRITE_CMD 0x1
4714 #define FCP_COMMAND_TRECEIVE 0x2
4715 #define FCP_COMMAND_TRSP 0x3
4716 #define FCP_COMMAND_TSEND 0x7
4717 #define OTHER_COMMAND 0x8
4718 #define ELS_COMMAND_NON_FIP 0xC
4719 #define ELS_COMMAND_FIP 0xD
4721 #define LPFC_NVME_EMBED_CMD 0x0
4722 #define LPFC_NVME_EMBED_WRITE 0x1
4723 #define LPFC_NVME_EMBED_READ 0x2
4726 #define CMD_ABORT_XRI_WQE 0x0F
4727 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4728 #define CMD_XMIT_BCAST64_WQE 0x84
4729 #define CMD_ELS_REQUEST64_WQE 0x8A
4730 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4731 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4732 #define CMD_FCP_IWRITE64_WQE 0x98
4733 #define CMD_FCP_IREAD64_WQE 0x9A
4734 #define CMD_FCP_ICMND64_WQE 0x9C
4735 #define CMD_FCP_TSEND64_WQE 0x9F
4736 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4737 #define CMD_FCP_TRSP64_WQE 0xA3
4738 #define CMD_GEN_REQUEST64_WQE 0xC2
4740 #define CMD_WQE_MASK 0xff
4743 #define LPFC_FW_DUMP 1
4744 #define LPFC_FW_RESET 2
4745 #define LPFC_DV_RESET 3