1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
23 /* Macros to deal with bit fields. Each bit field must have 3 #defines
24 * associated with it (_SHIFT, _MASK, and _WORD).
25 * EG. For a bit field that is in the 7th bit of the "field4" field of a
26 * structure and is 2 bits in size the following #defines must exist:
32 * #define example_bit_field_SHIFT 7
33 * #define example_bit_field_MASK 0x03
34 * #define example_bit_field_WORD field4
37 * Then the macros below may be used to get or set the value of that field.
38 * EG. To get the value of the bit field from the above example:
40 * value = bf_get(example_bit_field, &t1);
41 * And then to set that bit field:
42 * bf_set(example_bit_field, &t1, 2);
43 * Or clear that bit field:
44 * bf_set(example_bit_field, &t1, 0);
46 #define bf_get_be32(name, ptr) \
47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48 #define bf_get_le32(name, ptr) \
49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
50 #define bf_get(name, ptr) \
51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
52 #define bf_set_le32(name, ptr, value) \
53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
55 ~(name##_MASK << name##_SHIFT)))))
56 #define bf_set(name, ptr, value) \
57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
65 struct lpfc_sli_intf {
67 #define lpfc_sli_intf_valid_SHIFT 29
68 #define lpfc_sli_intf_valid_MASK 0x00000007
69 #define lpfc_sli_intf_valid_WORD word0
70 #define LPFC_SLI_INTF_VALID 6
71 #define lpfc_sli_intf_sli_hint2_SHIFT 24
72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
73 #define lpfc_sli_intf_sli_hint2_WORD word0
74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
75 #define lpfc_sli_intf_sli_hint1_SHIFT 16
76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
77 #define lpfc_sli_intf_sli_hint1_WORD word0
78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
79 #define LPFC_SLI_INTF_SLI_HINT1_1 1
80 #define LPFC_SLI_INTF_SLI_HINT1_2 2
81 #define lpfc_sli_intf_if_type_SHIFT 12
82 #define lpfc_sli_intf_if_type_MASK 0x0000000F
83 #define lpfc_sli_intf_if_type_WORD word0
84 #define LPFC_SLI_INTF_IF_TYPE_0 0
85 #define LPFC_SLI_INTF_IF_TYPE_1 1
86 #define LPFC_SLI_INTF_IF_TYPE_2 2
87 #define lpfc_sli_intf_sli_family_SHIFT 8
88 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
89 #define lpfc_sli_intf_sli_family_WORD word0
90 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
91 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
92 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
93 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
94 #define lpfc_sli_intf_slirev_SHIFT 4
95 #define lpfc_sli_intf_slirev_MASK 0x0000000F
96 #define lpfc_sli_intf_slirev_WORD word0
97 #define LPFC_SLI_INTF_REV_SLI3 3
98 #define LPFC_SLI_INTF_REV_SLI4 4
99 #define lpfc_sli_intf_func_type_SHIFT 0
100 #define lpfc_sli_intf_func_type_MASK 0x00000001
101 #define lpfc_sli_intf_func_type_WORD word0
102 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
103 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1
106 #define LPFC_SLI4_MBX_EMBED true
107 #define LPFC_SLI4_MBX_NEMBED false
109 #define LPFC_SLI4_MB_WORD_COUNT 64
110 #define LPFC_MAX_MQ_PAGE 8
111 #define LPFC_MAX_WQ_PAGE_V0 4
112 #define LPFC_MAX_WQ_PAGE 8
113 #define LPFC_MAX_RQ_PAGE 8
114 #define LPFC_MAX_CQ_PAGE 4
115 #define LPFC_MAX_EQ_PAGE 8
117 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
118 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
119 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
121 /* Define SLI4 Alignment requirements. */
122 #define LPFC_ALIGN_16_BYTE 16
123 #define LPFC_ALIGN_64_BYTE 64
124 #define SLI4_PAGE_SIZE 4096
126 /* Define SLI4 specific definitions. */
127 #define LPFC_MQ_CQE_BYTE_OFFSET 256
128 #define LPFC_MBX_CMD_HDR_LENGTH 16
129 #define LPFC_MBX_ERROR_RANGE 0x4000
130 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
131 #define LPFC_BMBX_BIT1_ADDR_LO 0
132 #define LPFC_RPI_HDR_COUNT 64
133 #define LPFC_HDR_TEMPLATE_SIZE 4096
134 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
135 #define LPFC_FCF_RECORD_WD_CNT 132
136 #define LPFC_ENTIRE_FCF_DATABASE 0
137 #define LPFC_DFLT_FCF_INDEX 0
139 /* Virtual function numbers */
173 /* PCI function numbers */
174 #define LPFC_PCI_FUNC0 0
175 #define LPFC_PCI_FUNC1 1
176 #define LPFC_PCI_FUNC2 2
177 #define LPFC_PCI_FUNC3 3
178 #define LPFC_PCI_FUNC4 4
180 /* SLI4 interface type-2 PDEV_CTL register */
181 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
182 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
183 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
184 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
185 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
186 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
188 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
190 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
192 /* Active interrupt test count */
193 #define LPFC_ACT_INTR_CNT 4
195 /* Algrithmns for scheduling FCP commands to WQs */
196 #define LPFC_FCP_SCHED_ROUND_ROBIN 0
197 #define LPFC_FCP_SCHED_BY_CPU 1
199 /* Delay Multiplier constant */
200 #define LPFC_DMULT_CONST 651042
201 #define LPFC_DMULT_MAX 1023
203 /* Configuration of Interrupts / sec for entire HBA port */
204 #define LPFC_MIN_IMAX 5000
205 #define LPFC_MAX_IMAX 5000000
206 #define LPFC_DEF_IMAX 150000
208 #define LPFC_MIN_CPU_MAP 0
209 #define LPFC_MAX_CPU_MAP 2
210 #define LPFC_HBA_CPU_MAP 1
211 #define LPFC_DRIVER_CPU_MAP 2 /* Default */
213 /* PORT_CAPABILITIES constants. */
214 #define LPFC_MAX_SUPPORTED_PAGES 8
220 #ifdef __BIG_ENDIAN_BITFIELD
221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
223 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
224 #else /* __LITTLE_ENDIAN_BITFIELD */
225 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
226 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
229 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
230 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
231 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
232 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
233 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
234 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
235 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
242 /* Maximun size of immediate data that can fit into a 128 byte WQE */
243 #define LPFC_MAX_BDE_IMM_SIZE 64
245 struct lpfc_sli4_flags {
247 #define lpfc_idx_rsrc_rdy_SHIFT 0
248 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
249 #define lpfc_idx_rsrc_rdy_WORD word0
250 #define LPFC_IDX_RSRC_RDY 1
251 #define lpfc_rpi_rsrc_rdy_SHIFT 1
252 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
253 #define lpfc_rpi_rsrc_rdy_WORD word0
254 #define LPFC_RPI_RSRC_RDY 1
255 #define lpfc_vpi_rsrc_rdy_SHIFT 2
256 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
257 #define lpfc_vpi_rsrc_rdy_WORD word0
258 #define LPFC_VPI_RSRC_RDY 1
259 #define lpfc_vfi_rsrc_rdy_SHIFT 3
260 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
261 #define lpfc_vfi_rsrc_rdy_WORD word0
262 #define LPFC_VFI_RSRC_RDY 1
265 struct sli4_bls_rsp {
266 uint32_t word0_rsvd; /* Word0 must be reserved */
268 #define lpfc_abts_orig_SHIFT 0
269 #define lpfc_abts_orig_MASK 0x00000001
270 #define lpfc_abts_orig_WORD word1
271 #define LPFC_ABTS_UNSOL_RSP 1
272 #define LPFC_ABTS_UNSOL_INT 0
274 #define lpfc_abts_rxid_SHIFT 0
275 #define lpfc_abts_rxid_MASK 0x0000FFFF
276 #define lpfc_abts_rxid_WORD word2
277 #define lpfc_abts_oxid_SHIFT 16
278 #define lpfc_abts_oxid_MASK 0x0000FFFF
279 #define lpfc_abts_oxid_WORD word2
281 #define lpfc_vndr_code_SHIFT 0
282 #define lpfc_vndr_code_MASK 0x000000FF
283 #define lpfc_vndr_code_WORD word3
284 #define lpfc_rsn_expln_SHIFT 8
285 #define lpfc_rsn_expln_MASK 0x000000FF
286 #define lpfc_rsn_expln_WORD word3
287 #define lpfc_rsn_code_SHIFT 16
288 #define lpfc_rsn_code_MASK 0x000000FF
289 #define lpfc_rsn_code_WORD word3
292 uint32_t word5_rsvd; /* Word5 must be reserved */
295 /* event queue entry structure */
298 #define lpfc_eqe_resource_id_SHIFT 16
299 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
300 #define lpfc_eqe_resource_id_WORD word0
301 #define lpfc_eqe_minor_code_SHIFT 4
302 #define lpfc_eqe_minor_code_MASK 0x00000FFF
303 #define lpfc_eqe_minor_code_WORD word0
304 #define lpfc_eqe_major_code_SHIFT 1
305 #define lpfc_eqe_major_code_MASK 0x00000007
306 #define lpfc_eqe_major_code_WORD word0
307 #define lpfc_eqe_valid_SHIFT 0
308 #define lpfc_eqe_valid_MASK 0x00000001
309 #define lpfc_eqe_valid_WORD word0
312 /* completion queue entry structure (common fields for all cqe types) */
318 #define lpfc_cqe_valid_SHIFT 31
319 #define lpfc_cqe_valid_MASK 0x00000001
320 #define lpfc_cqe_valid_WORD word3
321 #define lpfc_cqe_code_SHIFT 16
322 #define lpfc_cqe_code_MASK 0x000000FF
323 #define lpfc_cqe_code_WORD word3
326 /* Completion Queue Entry Status Codes */
327 #define CQE_STATUS_SUCCESS 0x0
328 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
329 #define CQE_STATUS_REMOTE_STOP 0x2
330 #define CQE_STATUS_LOCAL_REJECT 0x3
331 #define CQE_STATUS_NPORT_RJT 0x4
332 #define CQE_STATUS_FABRIC_RJT 0x5
333 #define CQE_STATUS_NPORT_BSY 0x6
334 #define CQE_STATUS_FABRIC_BSY 0x7
335 #define CQE_STATUS_INTERMED_RSP 0x8
336 #define CQE_STATUS_LS_RJT 0x9
337 #define CQE_STATUS_CMD_REJECT 0xb
338 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
339 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
340 #define CQE_STATUS_DI_ERROR 0x16
342 /* Used when mapping CQE status to IOCB */
343 #define LPFC_IOCB_STATUS_MASK 0xf
345 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
346 #define CQE_HW_STATUS_NO_ERR 0x0
347 #define CQE_HW_STATUS_UNDERRUN 0x1
348 #define CQE_HW_STATUS_OVERRUN 0x2
350 /* Completion Queue Entry Codes */
351 #define CQE_CODE_COMPL_WQE 0x1
352 #define CQE_CODE_RELEASE_WQE 0x2
353 #define CQE_CODE_RECEIVE 0x4
354 #define CQE_CODE_XRI_ABORTED 0x5
355 #define CQE_CODE_RECEIVE_V1 0x9
356 #define CQE_CODE_NVME_ERSP 0xd
359 * Define mask value for xri_aborted and wcqe completed CQE extended status.
360 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
362 #define WCQE_PARAM_MASK 0x1FF
364 /* completion queue entry for wqe completions */
365 struct lpfc_wcqe_complete {
367 #define lpfc_wcqe_c_request_tag_SHIFT 16
368 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
369 #define lpfc_wcqe_c_request_tag_WORD word0
370 #define lpfc_wcqe_c_status_SHIFT 8
371 #define lpfc_wcqe_c_status_MASK 0x000000FF
372 #define lpfc_wcqe_c_status_WORD word0
373 #define lpfc_wcqe_c_hw_status_SHIFT 0
374 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
375 #define lpfc_wcqe_c_hw_status_WORD word0
376 #define lpfc_wcqe_c_ersp0_SHIFT 0
377 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
378 #define lpfc_wcqe_c_ersp0_WORD word0
379 uint32_t total_data_placed;
381 #define lpfc_wcqe_c_bg_edir_SHIFT 5
382 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
383 #define lpfc_wcqe_c_bg_edir_WORD parameter
384 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3
385 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
386 #define lpfc_wcqe_c_bg_tdpv_WORD parameter
387 #define lpfc_wcqe_c_bg_re_SHIFT 2
388 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
389 #define lpfc_wcqe_c_bg_re_WORD parameter
390 #define lpfc_wcqe_c_bg_ae_SHIFT 1
391 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
392 #define lpfc_wcqe_c_bg_ae_WORD parameter
393 #define lpfc_wcqe_c_bg_ge_SHIFT 0
394 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
395 #define lpfc_wcqe_c_bg_ge_WORD parameter
397 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
398 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
399 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
400 #define lpfc_wcqe_c_xb_SHIFT 28
401 #define lpfc_wcqe_c_xb_MASK 0x00000001
402 #define lpfc_wcqe_c_xb_WORD word3
403 #define lpfc_wcqe_c_pv_SHIFT 27
404 #define lpfc_wcqe_c_pv_MASK 0x00000001
405 #define lpfc_wcqe_c_pv_WORD word3
406 #define lpfc_wcqe_c_priority_SHIFT 24
407 #define lpfc_wcqe_c_priority_MASK 0x00000007
408 #define lpfc_wcqe_c_priority_WORD word3
409 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
410 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
411 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
412 #define lpfc_wcqe_c_sqhead_SHIFT 0
413 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
414 #define lpfc_wcqe_c_sqhead_WORD word3
417 /* completion queue entry for wqe release */
418 struct lpfc_wcqe_release {
422 #define lpfc_wcqe_r_wq_id_SHIFT 16
423 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
424 #define lpfc_wcqe_r_wq_id_WORD word2
425 #define lpfc_wcqe_r_wqe_index_SHIFT 0
426 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
427 #define lpfc_wcqe_r_wqe_index_WORD word2
429 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
430 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
431 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
432 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
433 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
434 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
437 struct sli4_wcqe_xri_aborted {
439 #define lpfc_wcqe_xa_status_SHIFT 8
440 #define lpfc_wcqe_xa_status_MASK 0x000000FF
441 #define lpfc_wcqe_xa_status_WORD word0
444 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
445 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
446 #define lpfc_wcqe_xa_remote_xid_WORD word2
447 #define lpfc_wcqe_xa_xri_SHIFT 0
448 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
449 #define lpfc_wcqe_xa_xri_WORD word2
451 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
452 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
453 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
454 #define lpfc_wcqe_xa_ia_SHIFT 30
455 #define lpfc_wcqe_xa_ia_MASK 0x00000001
456 #define lpfc_wcqe_xa_ia_WORD word3
457 #define CQE_XRI_ABORTED_IA_REMOTE 0
458 #define CQE_XRI_ABORTED_IA_LOCAL 1
459 #define lpfc_wcqe_xa_br_SHIFT 29
460 #define lpfc_wcqe_xa_br_MASK 0x00000001
461 #define lpfc_wcqe_xa_br_WORD word3
462 #define CQE_XRI_ABORTED_BR_BA_ACC 0
463 #define CQE_XRI_ABORTED_BR_BA_RJT 1
464 #define lpfc_wcqe_xa_eo_SHIFT 28
465 #define lpfc_wcqe_xa_eo_MASK 0x00000001
466 #define lpfc_wcqe_xa_eo_WORD word3
467 #define CQE_XRI_ABORTED_EO_REMOTE 0
468 #define CQE_XRI_ABORTED_EO_LOCAL 1
469 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
470 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
471 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
474 /* completion queue entry structure for rqe completion */
477 #define lpfc_rcqe_bindex_SHIFT 16
478 #define lpfc_rcqe_bindex_MASK 0x0000FFF
479 #define lpfc_rcqe_bindex_WORD word0
480 #define lpfc_rcqe_status_SHIFT 8
481 #define lpfc_rcqe_status_MASK 0x000000FF
482 #define lpfc_rcqe_status_WORD word0
483 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
484 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
485 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
486 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
488 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
489 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
490 #define lpfc_rcqe_fcf_id_v1_WORD word1
492 #define lpfc_rcqe_length_SHIFT 16
493 #define lpfc_rcqe_length_MASK 0x0000FFFF
494 #define lpfc_rcqe_length_WORD word2
495 #define lpfc_rcqe_rq_id_SHIFT 6
496 #define lpfc_rcqe_rq_id_MASK 0x000003FF
497 #define lpfc_rcqe_rq_id_WORD word2
498 #define lpfc_rcqe_fcf_id_SHIFT 0
499 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
500 #define lpfc_rcqe_fcf_id_WORD word2
501 #define lpfc_rcqe_rq_id_v1_SHIFT 0
502 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
503 #define lpfc_rcqe_rq_id_v1_WORD word2
505 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
506 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
507 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
508 #define lpfc_rcqe_port_SHIFT 30
509 #define lpfc_rcqe_port_MASK 0x00000001
510 #define lpfc_rcqe_port_WORD word3
511 #define lpfc_rcqe_hdr_length_SHIFT 24
512 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
513 #define lpfc_rcqe_hdr_length_WORD word3
514 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
515 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
516 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
517 #define lpfc_rcqe_eof_SHIFT 8
518 #define lpfc_rcqe_eof_MASK 0x000000FF
519 #define lpfc_rcqe_eof_WORD word3
520 #define FCOE_EOFn 0x41
521 #define FCOE_EOFt 0x42
522 #define FCOE_EOFni 0x49
523 #define FCOE_EOFa 0x50
524 #define lpfc_rcqe_sof_SHIFT 0
525 #define lpfc_rcqe_sof_MASK 0x000000FF
526 #define lpfc_rcqe_sof_WORD word3
527 #define FCOE_SOFi2 0x2d
528 #define FCOE_SOFi3 0x2e
529 #define FCOE_SOFn2 0x35
530 #define FCOE_SOFn3 0x36
538 /* buffer descriptors */
543 #define lpfc_bde4_last_SHIFT 31
544 #define lpfc_bde4_last_MASK 0x00000001
545 #define lpfc_bde4_last_WORD word2
546 #define lpfc_bde4_sge_offset_SHIFT 0
547 #define lpfc_bde4_sge_offset_MASK 0x000003FF
548 #define lpfc_bde4_sge_offset_WORD word2
550 #define lpfc_bde4_length_SHIFT 0
551 #define lpfc_bde4_length_MASK 0x000000FF
552 #define lpfc_bde4_length_WORD word3
555 struct lpfc_register {
559 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
560 #define LPFC_PORT_SEM_MASK 0xF000
561 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
562 #define LPFC_UERR_STATUS_HI 0x00A4
563 #define LPFC_UERR_STATUS_LO 0x00A0
564 #define LPFC_UE_MASK_HI 0x00AC
565 #define LPFC_UE_MASK_LO 0x00A8
567 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
568 #define LPFC_SLI_INTF 0x0058
570 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
571 #define lpfc_port_smphr_perr_SHIFT 31
572 #define lpfc_port_smphr_perr_MASK 0x1
573 #define lpfc_port_smphr_perr_WORD word0
574 #define lpfc_port_smphr_sfi_SHIFT 30
575 #define lpfc_port_smphr_sfi_MASK 0x1
576 #define lpfc_port_smphr_sfi_WORD word0
577 #define lpfc_port_smphr_nip_SHIFT 29
578 #define lpfc_port_smphr_nip_MASK 0x1
579 #define lpfc_port_smphr_nip_WORD word0
580 #define lpfc_port_smphr_ipc_SHIFT 28
581 #define lpfc_port_smphr_ipc_MASK 0x1
582 #define lpfc_port_smphr_ipc_WORD word0
583 #define lpfc_port_smphr_scr1_SHIFT 27
584 #define lpfc_port_smphr_scr1_MASK 0x1
585 #define lpfc_port_smphr_scr1_WORD word0
586 #define lpfc_port_smphr_scr2_SHIFT 26
587 #define lpfc_port_smphr_scr2_MASK 0x1
588 #define lpfc_port_smphr_scr2_WORD word0
589 #define lpfc_port_smphr_host_scratch_SHIFT 16
590 #define lpfc_port_smphr_host_scratch_MASK 0xFF
591 #define lpfc_port_smphr_host_scratch_WORD word0
592 #define lpfc_port_smphr_port_status_SHIFT 0
593 #define lpfc_port_smphr_port_status_MASK 0xFFFF
594 #define lpfc_port_smphr_port_status_WORD word0
596 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
597 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
598 #define LPFC_POST_STAGE_HOST_RDY 0x0002
599 #define LPFC_POST_STAGE_BE_RESET 0x0003
600 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
601 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
602 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
603 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
604 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
605 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
606 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
607 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
608 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
609 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
610 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
611 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
612 #define LPFC_POST_STAGE_ARMFW_START 0x0800
613 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
614 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
615 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
616 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
617 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
618 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
619 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
620 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
621 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
622 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
623 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
624 #define LPFC_POST_STAGE_RC_DONE 0x0B07
625 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
626 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
627 #define LPFC_POST_STAGE_PORT_READY 0xC000
628 #define LPFC_POST_STAGE_PORT_UE 0xF000
630 #define LPFC_CTL_PORT_STA_OFFSET 0x404
631 #define lpfc_sliport_status_err_SHIFT 31
632 #define lpfc_sliport_status_err_MASK 0x1
633 #define lpfc_sliport_status_err_WORD word0
634 #define lpfc_sliport_status_end_SHIFT 30
635 #define lpfc_sliport_status_end_MASK 0x1
636 #define lpfc_sliport_status_end_WORD word0
637 #define lpfc_sliport_status_oti_SHIFT 29
638 #define lpfc_sliport_status_oti_MASK 0x1
639 #define lpfc_sliport_status_oti_WORD word0
640 #define lpfc_sliport_status_rn_SHIFT 24
641 #define lpfc_sliport_status_rn_MASK 0x1
642 #define lpfc_sliport_status_rn_WORD word0
643 #define lpfc_sliport_status_rdy_SHIFT 23
644 #define lpfc_sliport_status_rdy_MASK 0x1
645 #define lpfc_sliport_status_rdy_WORD word0
646 #define MAX_IF_TYPE_2_RESETS 6
648 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
649 #define lpfc_sliport_ctrl_end_SHIFT 30
650 #define lpfc_sliport_ctrl_end_MASK 0x1
651 #define lpfc_sliport_ctrl_end_WORD word0
652 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
653 #define LPFC_SLIPORT_BIG_ENDIAN 1
654 #define lpfc_sliport_ctrl_ip_SHIFT 27
655 #define lpfc_sliport_ctrl_ip_MASK 0x1
656 #define lpfc_sliport_ctrl_ip_WORD word0
657 #define LPFC_SLIPORT_INIT_PORT 1
659 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
660 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
662 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
663 #define lpfc_sliport_eqdelay_delay_SHIFT 16
664 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
665 #define lpfc_sliport_eqdelay_delay_WORD word0
666 #define lpfc_sliport_eqdelay_id_SHIFT 0
667 #define lpfc_sliport_eqdelay_id_MASK 0xfff
668 #define lpfc_sliport_eqdelay_id_WORD word0
669 #define LPFC_SEC_TO_USEC 1000000
671 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
674 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
676 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
677 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
679 #define LPFC_HST_ISR0 0x0C18
680 #define LPFC_HST_ISR1 0x0C1C
681 #define LPFC_HST_ISR2 0x0C20
682 #define LPFC_HST_ISR3 0x0C24
683 #define LPFC_HST_ISR4 0x0C28
685 #define LPFC_HST_IMR0 0x0C48
686 #define LPFC_HST_IMR1 0x0C4C
687 #define LPFC_HST_IMR2 0x0C50
688 #define LPFC_HST_IMR3 0x0C54
689 #define LPFC_HST_IMR4 0x0C58
691 #define LPFC_HST_ISCR0 0x0C78
692 #define LPFC_HST_ISCR1 0x0C7C
693 #define LPFC_HST_ISCR2 0x0C80
694 #define LPFC_HST_ISCR3 0x0C84
695 #define LPFC_HST_ISCR4 0x0C88
697 #define LPFC_SLI4_INTR0 BIT0
698 #define LPFC_SLI4_INTR1 BIT1
699 #define LPFC_SLI4_INTR2 BIT2
700 #define LPFC_SLI4_INTR3 BIT3
701 #define LPFC_SLI4_INTR4 BIT4
702 #define LPFC_SLI4_INTR5 BIT5
703 #define LPFC_SLI4_INTR6 BIT6
704 #define LPFC_SLI4_INTR7 BIT7
705 #define LPFC_SLI4_INTR8 BIT8
706 #define LPFC_SLI4_INTR9 BIT9
707 #define LPFC_SLI4_INTR10 BIT10
708 #define LPFC_SLI4_INTR11 BIT11
709 #define LPFC_SLI4_INTR12 BIT12
710 #define LPFC_SLI4_INTR13 BIT13
711 #define LPFC_SLI4_INTR14 BIT14
712 #define LPFC_SLI4_INTR15 BIT15
713 #define LPFC_SLI4_INTR16 BIT16
714 #define LPFC_SLI4_INTR17 BIT17
715 #define LPFC_SLI4_INTR18 BIT18
716 #define LPFC_SLI4_INTR19 BIT19
717 #define LPFC_SLI4_INTR20 BIT20
718 #define LPFC_SLI4_INTR21 BIT21
719 #define LPFC_SLI4_INTR22 BIT22
720 #define LPFC_SLI4_INTR23 BIT23
721 #define LPFC_SLI4_INTR24 BIT24
722 #define LPFC_SLI4_INTR25 BIT25
723 #define LPFC_SLI4_INTR26 BIT26
724 #define LPFC_SLI4_INTR27 BIT27
725 #define LPFC_SLI4_INTR28 BIT28
726 #define LPFC_SLI4_INTR29 BIT29
727 #define LPFC_SLI4_INTR30 BIT30
728 #define LPFC_SLI4_INTR31 BIT31
731 * The Doorbell registers defined here exist in different BAR
732 * register sets depending on the UCNA Port's reported if_type
733 * value. For UCNA ports running SLI4 and if_type 0, they reside in
734 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
735 * BAR0. The offsets are the same so the driver must account for
736 * any base address difference.
738 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
739 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
740 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24
741 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
742 #define lpfc_rq_db_list_fm_num_posted_WORD word0
743 #define lpfc_rq_db_list_fm_index_SHIFT 16
744 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
745 #define lpfc_rq_db_list_fm_index_WORD word0
746 #define lpfc_rq_db_list_fm_id_SHIFT 0
747 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
748 #define lpfc_rq_db_list_fm_id_WORD word0
749 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16
750 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
751 #define lpfc_rq_db_ring_fm_num_posted_WORD word0
752 #define lpfc_rq_db_ring_fm_id_SHIFT 0
753 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
754 #define lpfc_rq_db_ring_fm_id_WORD word0
756 #define LPFC_ULP0_WQ_DOORBELL 0x0040
757 #define LPFC_ULP1_WQ_DOORBELL 0x0060
758 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24
759 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
760 #define lpfc_wq_db_list_fm_num_posted_WORD word0
761 #define lpfc_wq_db_list_fm_index_SHIFT 16
762 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
763 #define lpfc_wq_db_list_fm_index_WORD word0
764 #define lpfc_wq_db_list_fm_id_SHIFT 0
765 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
766 #define lpfc_wq_db_list_fm_id_WORD word0
767 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16
768 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
769 #define lpfc_wq_db_ring_fm_num_posted_WORD word0
770 #define lpfc_wq_db_ring_fm_id_SHIFT 0
771 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
772 #define lpfc_wq_db_ring_fm_id_WORD word0
774 #define LPFC_EQCQ_DOORBELL 0x0120
775 #define lpfc_eqcq_doorbell_se_SHIFT 31
776 #define lpfc_eqcq_doorbell_se_MASK 0x0001
777 #define lpfc_eqcq_doorbell_se_WORD word0
778 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
779 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
780 #define lpfc_eqcq_doorbell_arm_SHIFT 29
781 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
782 #define lpfc_eqcq_doorbell_arm_WORD word0
783 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
784 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
785 #define lpfc_eqcq_doorbell_num_released_WORD word0
786 #define lpfc_eqcq_doorbell_qt_SHIFT 10
787 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
788 #define lpfc_eqcq_doorbell_qt_WORD word0
789 #define LPFC_QUEUE_TYPE_COMPLETION 0
790 #define LPFC_QUEUE_TYPE_EVENT 1
791 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
792 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
793 #define lpfc_eqcq_doorbell_eqci_WORD word0
794 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
795 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
796 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0
797 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
798 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
799 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0
800 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
801 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
802 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0
803 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
804 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
805 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0
806 #define LPFC_CQID_HI_FIELD_SHIFT 10
807 #define LPFC_EQID_HI_FIELD_SHIFT 9
809 #define LPFC_BMBX 0x0160
810 #define lpfc_bmbx_addr_SHIFT 2
811 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
812 #define lpfc_bmbx_addr_WORD word0
813 #define lpfc_bmbx_hi_SHIFT 1
814 #define lpfc_bmbx_hi_MASK 0x0001
815 #define lpfc_bmbx_hi_WORD word0
816 #define lpfc_bmbx_rdy_SHIFT 0
817 #define lpfc_bmbx_rdy_MASK 0x0001
818 #define lpfc_bmbx_rdy_WORD word0
820 #define LPFC_MQ_DOORBELL 0x0140
821 #define lpfc_mq_doorbell_num_posted_SHIFT 16
822 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
823 #define lpfc_mq_doorbell_num_posted_WORD word0
824 #define lpfc_mq_doorbell_id_SHIFT 0
825 #define lpfc_mq_doorbell_id_MASK 0xFFFF
826 #define lpfc_mq_doorbell_id_WORD word0
828 struct lpfc_sli4_cfg_mhdr {
830 #define lpfc_mbox_hdr_emb_SHIFT 0
831 #define lpfc_mbox_hdr_emb_MASK 0x00000001
832 #define lpfc_mbox_hdr_emb_WORD word1
833 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
834 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
835 #define lpfc_mbox_hdr_sge_cnt_WORD word1
836 uint32_t payload_length;
842 union lpfc_sli4_cfg_shdr {
845 #define lpfc_mbox_hdr_opcode_SHIFT 0
846 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
847 #define lpfc_mbox_hdr_opcode_WORD word6
848 #define lpfc_mbox_hdr_subsystem_SHIFT 8
849 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
850 #define lpfc_mbox_hdr_subsystem_WORD word6
851 #define lpfc_mbox_hdr_port_number_SHIFT 16
852 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
853 #define lpfc_mbox_hdr_port_number_WORD word6
854 #define lpfc_mbox_hdr_domain_SHIFT 24
855 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
856 #define lpfc_mbox_hdr_domain_WORD word6
858 uint32_t request_length;
860 #define lpfc_mbox_hdr_version_SHIFT 0
861 #define lpfc_mbox_hdr_version_MASK 0x000000FF
862 #define lpfc_mbox_hdr_version_WORD word9
863 #define lpfc_mbox_hdr_pf_num_SHIFT 16
864 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
865 #define lpfc_mbox_hdr_pf_num_WORD word9
866 #define lpfc_mbox_hdr_vh_num_SHIFT 24
867 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
868 #define lpfc_mbox_hdr_vh_num_WORD word9
869 #define LPFC_Q_CREATE_VERSION_2 2
870 #define LPFC_Q_CREATE_VERSION_1 1
871 #define LPFC_Q_CREATE_VERSION_0 0
872 #define LPFC_OPCODE_VERSION_0 0
873 #define LPFC_OPCODE_VERSION_1 1
877 #define lpfc_mbox_hdr_opcode_SHIFT 0
878 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
879 #define lpfc_mbox_hdr_opcode_WORD word6
880 #define lpfc_mbox_hdr_subsystem_SHIFT 8
881 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
882 #define lpfc_mbox_hdr_subsystem_WORD word6
883 #define lpfc_mbox_hdr_domain_SHIFT 24
884 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
885 #define lpfc_mbox_hdr_domain_WORD word6
887 #define lpfc_mbox_hdr_status_SHIFT 0
888 #define lpfc_mbox_hdr_status_MASK 0x000000FF
889 #define lpfc_mbox_hdr_status_WORD word7
890 #define lpfc_mbox_hdr_add_status_SHIFT 8
891 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
892 #define lpfc_mbox_hdr_add_status_WORD word7
893 uint32_t response_length;
894 uint32_t actual_response_length;
898 /* Mailbox Header structures.
899 * struct mbox_header is defined for first generation SLI4_CFG mailbox
900 * calls deployed for BE-based ports.
902 * struct sli4_mbox_header is defined for second generation SLI4
903 * ports that don't deploy the SLI4_CFG mechanism.
906 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
907 union lpfc_sli4_cfg_shdr cfg_shdr;
910 #define LPFC_EXTENT_LOCAL 0
911 #define LPFC_TIMEOUT_DEFAULT 0
912 #define LPFC_EXTENT_VERSION_DEFAULT 0
914 /* Subsystem Definitions */
915 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
916 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
917 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
919 /* Device Specific Definitions */
921 /* The HOST ENDIAN defines are in Big Endian format. */
922 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
923 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
926 #define LPFC_MBOX_OPCODE_NA 0x00
927 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
928 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
929 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
930 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
931 #define LPFC_MBOX_OPCODE_NOP 0x21
932 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
933 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
934 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
935 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
936 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
937 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
938 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
939 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
940 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
941 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
942 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
943 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
944 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
945 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
946 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
947 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
948 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
949 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
950 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
951 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
952 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
953 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
954 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
955 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
956 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
957 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
958 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
959 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
960 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
961 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
962 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
963 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
964 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
967 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
968 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
969 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
970 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
971 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
972 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
973 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
974 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
975 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
976 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
977 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
978 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
979 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
980 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
981 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
983 /* Mailbox command structures */
986 #define lpfc_eq_context_size_SHIFT 31
987 #define lpfc_eq_context_size_MASK 0x00000001
988 #define lpfc_eq_context_size_WORD word0
989 #define LPFC_EQE_SIZE_4 0x0
990 #define LPFC_EQE_SIZE_16 0x1
991 #define lpfc_eq_context_valid_SHIFT 29
992 #define lpfc_eq_context_valid_MASK 0x00000001
993 #define lpfc_eq_context_valid_WORD word0
995 #define lpfc_eq_context_count_SHIFT 26
996 #define lpfc_eq_context_count_MASK 0x00000003
997 #define lpfc_eq_context_count_WORD word1
998 #define LPFC_EQ_CNT_256 0x0
999 #define LPFC_EQ_CNT_512 0x1
1000 #define LPFC_EQ_CNT_1024 0x2
1001 #define LPFC_EQ_CNT_2048 0x3
1002 #define LPFC_EQ_CNT_4096 0x4
1004 #define lpfc_eq_context_delay_multi_SHIFT 13
1005 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1006 #define lpfc_eq_context_delay_multi_WORD word2
1010 struct eq_delay_info {
1013 uint32_t delay_multi;
1015 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8
1017 struct sgl_page_pairs {
1018 uint32_t sgl_pg0_addr_lo;
1019 uint32_t sgl_pg0_addr_hi;
1020 uint32_t sgl_pg1_addr_lo;
1021 uint32_t sgl_pg1_addr_hi;
1024 struct lpfc_mbx_post_sgl_pages {
1025 struct mbox_header header;
1027 #define lpfc_post_sgl_pages_xri_SHIFT 0
1028 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1029 #define lpfc_post_sgl_pages_xri_WORD word0
1030 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
1031 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1032 #define lpfc_post_sgl_pages_xricnt_WORD word0
1033 struct sgl_page_pairs sgl_pg_pairs[1];
1036 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1037 struct lpfc_mbx_post_uembed_sgl_page1 {
1038 union lpfc_sli4_cfg_shdr cfg_shdr;
1040 struct sgl_page_pairs sgl_pg_pairs;
1043 struct lpfc_mbx_sge {
1049 struct lpfc_mbx_nembed_cmd {
1050 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1051 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
1052 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1055 struct lpfc_mbx_nembed_sge_virt {
1056 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1059 struct lpfc_mbx_eq_create {
1060 struct mbox_header header;
1064 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1065 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1066 #define lpfc_mbx_eq_create_num_pages_WORD word0
1067 struct eq_context context;
1068 struct dma_address page[LPFC_MAX_EQ_PAGE];
1072 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1073 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1074 #define lpfc_mbx_eq_create_q_id_WORD word0
1079 struct lpfc_mbx_modify_eq_delay {
1080 struct mbox_header header;
1084 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1092 struct lpfc_mbx_eq_destroy {
1093 struct mbox_header header;
1097 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1098 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1099 #define lpfc_mbx_eq_destroy_q_id_WORD word0
1107 struct lpfc_mbx_nop {
1108 struct mbox_header header;
1109 uint32_t context[2];
1114 #define lpfc_cq_context_event_SHIFT 31
1115 #define lpfc_cq_context_event_MASK 0x00000001
1116 #define lpfc_cq_context_event_WORD word0
1117 #define lpfc_cq_context_valid_SHIFT 29
1118 #define lpfc_cq_context_valid_MASK 0x00000001
1119 #define lpfc_cq_context_valid_WORD word0
1120 #define lpfc_cq_context_count_SHIFT 27
1121 #define lpfc_cq_context_count_MASK 0x00000003
1122 #define lpfc_cq_context_count_WORD word0
1123 #define LPFC_CQ_CNT_256 0x0
1124 #define LPFC_CQ_CNT_512 0x1
1125 #define LPFC_CQ_CNT_1024 0x2
1127 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1128 #define lpfc_cq_eq_id_MASK 0x000000FF
1129 #define lpfc_cq_eq_id_WORD word1
1130 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1131 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1132 #define lpfc_cq_eq_id_2_WORD word1
1137 struct lpfc_mbx_cq_create {
1138 struct mbox_header header;
1142 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1143 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1144 #define lpfc_mbx_cq_create_page_size_WORD word0
1145 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1146 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1147 #define lpfc_mbx_cq_create_num_pages_WORD word0
1148 struct cq_context context;
1149 struct dma_address page[LPFC_MAX_CQ_PAGE];
1153 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1154 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1155 #define lpfc_mbx_cq_create_q_id_WORD word0
1160 struct lpfc_mbx_cq_create_set {
1161 union lpfc_sli4_cfg_shdr cfg_shdr;
1165 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */
1166 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1167 #define lpfc_mbx_cq_create_set_page_size_WORD word0
1168 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1169 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1170 #define lpfc_mbx_cq_create_set_num_pages_WORD word0
1172 #define lpfc_mbx_cq_create_set_evt_SHIFT 31
1173 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1174 #define lpfc_mbx_cq_create_set_evt_WORD word1
1175 #define lpfc_mbx_cq_create_set_valid_SHIFT 29
1176 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1177 #define lpfc_mbx_cq_create_set_valid_WORD word1
1178 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27
1179 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1180 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1
1181 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25
1182 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1183 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1
1184 #define lpfc_mbx_cq_create_set_auto_SHIFT 15
1185 #define lpfc_mbx_cq_create_set_auto_MASK 0x0000001
1186 #define lpfc_mbx_cq_create_set_auto_WORD word1
1187 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14
1188 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1189 #define lpfc_mbx_cq_create_set_nodelay_WORD word1
1190 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12
1191 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1192 #define lpfc_mbx_cq_create_set_clswm_WORD word1
1194 #define lpfc_mbx_cq_create_set_arm_SHIFT 31
1195 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1196 #define lpfc_mbx_cq_create_set_arm_WORD word2
1197 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1198 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1199 #define lpfc_mbx_cq_create_set_num_cq_WORD word2
1201 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16
1202 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1203 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3
1204 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1205 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1206 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3
1208 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16
1209 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1210 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4
1211 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1212 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1213 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4
1215 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16
1216 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1217 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5
1218 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1219 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1220 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5
1222 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16
1223 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1224 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6
1225 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1226 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1227 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6
1229 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16
1230 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1231 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7
1232 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1233 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1234 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7
1236 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16
1237 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1238 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8
1239 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1240 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1241 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8
1243 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16
1244 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1245 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9
1246 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1247 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1248 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9
1250 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16
1251 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1252 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10
1253 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1254 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1255 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10
1256 struct dma_address page[1];
1260 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16
1261 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1262 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0
1263 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1264 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1265 #define lpfc_mbx_cq_create_set_base_id_WORD word0
1270 struct lpfc_mbx_cq_destroy {
1271 struct mbox_header header;
1275 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1276 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1277 #define lpfc_mbx_cq_destroy_q_id_WORD word0
1292 struct lpfc_mbx_wq_create {
1293 struct mbox_header header;
1295 struct { /* Version 0 Request */
1297 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1298 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1299 #define lpfc_mbx_wq_create_num_pages_WORD word0
1300 #define lpfc_mbx_wq_create_dua_SHIFT 8
1301 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1302 #define lpfc_mbx_wq_create_dua_WORD word0
1303 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
1304 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1305 #define lpfc_mbx_wq_create_cq_id_WORD word0
1306 struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1308 #define lpfc_mbx_wq_create_bua_SHIFT 0
1309 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1310 #define lpfc_mbx_wq_create_bua_WORD word9
1311 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8
1312 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1313 #define lpfc_mbx_wq_create_ulp_num_WORD word9
1315 struct { /* Version 1 Request */
1316 uint32_t word0; /* Word 0 is the same as in v0 */
1318 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1319 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1320 #define lpfc_mbx_wq_create_page_size_WORD word1
1321 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1322 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1323 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1324 #define lpfc_mbx_wq_create_wqe_size_WORD word1
1325 #define LPFC_WQ_WQE_SIZE_64 0x5
1326 #define LPFC_WQ_WQE_SIZE_128 0x6
1327 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1328 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1329 #define lpfc_mbx_wq_create_wqe_count_WORD word1
1331 struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1335 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1336 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1337 #define lpfc_mbx_wq_create_q_id_WORD word0
1338 uint32_t doorbell_offset;
1340 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1341 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1342 #define lpfc_mbx_wq_create_bar_set_WORD word2
1343 #define WQ_PCI_BAR_0_AND_1 0x00
1344 #define WQ_PCI_BAR_2_AND_3 0x01
1345 #define WQ_PCI_BAR_4_AND_5 0x02
1346 #define lpfc_mbx_wq_create_db_format_SHIFT 16
1347 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1348 #define lpfc_mbx_wq_create_db_format_WORD word2
1353 struct lpfc_mbx_wq_destroy {
1354 struct mbox_header header;
1358 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1359 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1360 #define lpfc_mbx_wq_destroy_q_id_WORD word0
1368 #define LPFC_HDR_BUF_SIZE 128
1369 #define LPFC_DATA_BUF_SIZE 2048
1370 #define LPFC_NVMET_DATA_BUF_SIZE 128
1373 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1374 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1375 #define lpfc_rq_context_rqe_count_WORD word0
1376 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1377 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1378 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1379 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1380 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */
1381 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1382 #define lpfc_rq_context_rqe_count_1_WORD word0
1383 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */
1384 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1385 #define lpfc_rq_context_rqe_size_WORD word0
1386 #define LPFC_RQE_SIZE_8 2
1387 #define LPFC_RQE_SIZE_16 3
1388 #define LPFC_RQE_SIZE_32 4
1389 #define LPFC_RQE_SIZE_64 5
1390 #define LPFC_RQE_SIZE_128 6
1391 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1392 #define lpfc_rq_context_page_size_MASK 0x000000FF
1393 #define lpfc_rq_context_page_size_WORD word0
1394 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1396 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */
1397 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1398 #define lpfc_rq_context_data_size_WORD word1
1399 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1400 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1401 #define lpfc_rq_context_hdr_size_WORD word1
1403 #define lpfc_rq_context_cq_id_SHIFT 16
1404 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1405 #define lpfc_rq_context_cq_id_WORD word2
1406 #define lpfc_rq_context_buf_size_SHIFT 0
1407 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1408 #define lpfc_rq_context_buf_size_WORD word2
1409 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1410 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1411 #define lpfc_rq_context_base_cq_WORD word2
1412 uint32_t buffer_size; /* Version 1 Only */
1415 struct lpfc_mbx_rq_create {
1416 struct mbox_header header;
1420 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1421 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1422 #define lpfc_mbx_rq_create_num_pages_WORD word0
1423 #define lpfc_mbx_rq_create_dua_SHIFT 16
1424 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1425 #define lpfc_mbx_rq_create_dua_WORD word0
1426 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1427 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1428 #define lpfc_mbx_rq_create_bqu_WORD word0
1429 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1430 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1431 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1432 struct rq_context context;
1433 struct dma_address page[LPFC_MAX_RQ_PAGE];
1437 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1438 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1439 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1440 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1441 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1442 #define lpfc_mbx_rq_create_q_id_WORD word0
1443 uint32_t doorbell_offset;
1445 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1446 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1447 #define lpfc_mbx_rq_create_bar_set_WORD word2
1448 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1449 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1450 #define lpfc_mbx_rq_create_db_format_WORD word2
1455 struct lpfc_mbx_rq_create_v2 {
1456 union lpfc_sli4_cfg_shdr cfg_shdr;
1460 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1461 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1462 #define lpfc_mbx_rq_create_num_pages_WORD word0
1463 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16
1464 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1465 #define lpfc_mbx_rq_create_rq_cnt_WORD word0
1466 #define lpfc_mbx_rq_create_dua_SHIFT 16
1467 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1468 #define lpfc_mbx_rq_create_dua_WORD word0
1469 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1470 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1471 #define lpfc_mbx_rq_create_bqu_WORD word0
1472 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1473 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1474 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1475 #define lpfc_mbx_rq_create_dim_SHIFT 29
1476 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1477 #define lpfc_mbx_rq_create_dim_WORD word0
1478 #define lpfc_mbx_rq_create_dfd_SHIFT 30
1479 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1480 #define lpfc_mbx_rq_create_dfd_WORD word0
1481 #define lpfc_mbx_rq_create_dnb_SHIFT 31
1482 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1483 #define lpfc_mbx_rq_create_dnb_WORD word0
1484 struct rq_context context;
1485 struct dma_address page[1];
1489 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1490 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1491 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1492 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1493 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1494 #define lpfc_mbx_rq_create_q_id_WORD word0
1495 uint32_t doorbell_offset;
1497 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1498 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1499 #define lpfc_mbx_rq_create_bar_set_WORD word2
1500 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1501 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1502 #define lpfc_mbx_rq_create_db_format_WORD word2
1507 struct lpfc_mbx_rq_destroy {
1508 struct mbox_header header;
1512 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1513 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1514 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1524 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1525 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1526 #define lpfc_mq_context_cq_id_WORD word0
1527 #define lpfc_mq_context_ring_size_SHIFT 16
1528 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1529 #define lpfc_mq_context_ring_size_WORD word0
1530 #define LPFC_MQ_RING_SIZE_16 0x5
1531 #define LPFC_MQ_RING_SIZE_32 0x6
1532 #define LPFC_MQ_RING_SIZE_64 0x7
1533 #define LPFC_MQ_RING_SIZE_128 0x8
1535 #define lpfc_mq_context_valid_SHIFT 31
1536 #define lpfc_mq_context_valid_MASK 0x00000001
1537 #define lpfc_mq_context_valid_WORD word1
1542 struct lpfc_mbx_mq_create {
1543 struct mbox_header header;
1547 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1548 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1549 #define lpfc_mbx_mq_create_num_pages_WORD word0
1550 struct mq_context context;
1551 struct dma_address page[LPFC_MAX_MQ_PAGE];
1555 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1556 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1557 #define lpfc_mbx_mq_create_q_id_WORD word0
1562 struct lpfc_mbx_mq_create_ext {
1563 struct mbox_header header;
1567 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1568 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1569 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1570 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1571 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1572 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1573 uint32_t async_evt_bmap;
1574 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1575 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1576 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1577 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1578 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1579 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1580 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1581 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1582 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1583 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1584 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1585 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1586 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1587 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1588 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1589 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1590 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1591 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1592 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1593 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1594 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1595 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1596 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1597 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1598 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1599 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1600 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1601 struct mq_context context;
1602 struct dma_address page[LPFC_MAX_MQ_PAGE];
1606 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1607 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1608 #define lpfc_mbx_mq_create_q_id_WORD word0
1611 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1612 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1613 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1616 struct lpfc_mbx_mq_destroy {
1617 struct mbox_header header;
1621 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1622 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1623 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1631 /* Start Gen 2 SLI4 Mailbox definitions: */
1633 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1634 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1635 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1636 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1637 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1639 struct lpfc_mbx_get_rsrc_extent_info {
1640 struct mbox_header header;
1644 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1645 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1646 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1650 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1651 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1652 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1653 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1654 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1655 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1660 struct lpfc_mbx_query_fw_config {
1661 struct mbox_header header;
1663 uint32_t config_number;
1664 #define LPFC_FC_FCOE 0x00000007
1665 uint32_t asic_revision;
1666 uint32_t physical_port;
1667 uint32_t function_mode;
1668 #define LPFC_FCOE_INI_MODE 0x00000040
1669 #define LPFC_FCOE_TGT_MODE 0x00000080
1670 #define LPFC_DUA_MODE 0x00000800
1672 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1673 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1674 uint32_t ulp0_nap_words[12];
1676 uint32_t ulp1_nap_words[12];
1677 uint32_t function_capabilities;
1682 uint32_t ulp0_nap2_words[2];
1683 uint32_t ulp1_nap2_words[2];
1687 struct lpfc_mbx_set_beacon_config {
1688 struct mbox_header header;
1690 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1691 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1692 #define lpfc_mbx_set_beacon_port_num_WORD word4
1693 #define lpfc_mbx_set_beacon_port_type_SHIFT 6
1694 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1695 #define lpfc_mbx_set_beacon_port_type_WORD word4
1696 #define lpfc_mbx_set_beacon_state_SHIFT 8
1697 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1698 #define lpfc_mbx_set_beacon_state_WORD word4
1699 #define lpfc_mbx_set_beacon_duration_SHIFT 16
1700 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1701 #define lpfc_mbx_set_beacon_duration_WORD word4
1702 #define lpfc_mbx_set_beacon_status_duration_SHIFT 24
1703 #define lpfc_mbx_set_beacon_status_duration_MASK 0x000000FF
1704 #define lpfc_mbx_set_beacon_status_duration_WORD word4
1707 struct lpfc_id_range {
1709 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1710 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1711 #define lpfc_mbx_rsrc_id_word4_0_WORD word5
1712 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1713 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1714 #define lpfc_mbx_rsrc_id_word4_1_WORD word5
1717 struct lpfc_mbx_set_link_diag_state {
1718 struct mbox_header header;
1722 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1723 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1724 #define lpfc_mbx_set_diag_state_diag_WORD word0
1725 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2
1726 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1727 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0
1728 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1729 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1
1730 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1731 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1732 #define lpfc_mbx_set_diag_state_link_num_WORD word0
1733 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1734 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1735 #define lpfc_mbx_set_diag_state_link_type_WORD word0
1743 struct lpfc_mbx_set_link_diag_loopback {
1744 struct mbox_header header;
1748 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1749 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1750 #define lpfc_mbx_set_diag_lpbk_type_WORD word0
1751 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1752 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1753 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1754 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1755 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1756 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1757 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1758 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1759 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1767 struct lpfc_mbx_run_link_diag_test {
1768 struct mbox_header header;
1772 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1773 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1774 #define lpfc_mbx_run_diag_test_link_num_WORD word0
1775 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1776 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1777 #define lpfc_mbx_run_diag_test_link_type_WORD word0
1779 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1780 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1781 #define lpfc_mbx_run_diag_test_test_id_WORD word1
1782 #define lpfc_mbx_run_diag_test_loops_SHIFT 16
1783 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1784 #define lpfc_mbx_run_diag_test_loops_WORD word1
1786 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1787 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1788 #define lpfc_mbx_run_diag_test_test_ver_WORD word2
1789 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1790 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1791 #define lpfc_mbx_run_diag_test_err_act_WORD word2
1800 * struct lpfc_mbx_alloc_rsrc_extents:
1801 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1802 * 6 words of header + 4 words of shared subcommand header +
1803 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1805 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1806 * for extents payload.
1808 * 212/2 (bytes per extent) = 106 extents.
1809 * 106/2 (extents per word) = 53 words.
1810 * lpfc_id_range id is statically size to 53.
1812 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1813 * extent ranges. For ALLOC, the type and cnt are required.
1814 * For GET_ALLOCATED, only the type is required.
1816 struct lpfc_mbx_alloc_rsrc_extents {
1817 struct mbox_header header;
1821 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1822 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1823 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1824 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1825 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1826 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1830 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1831 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1832 #define lpfc_mbx_rsrc_cnt_WORD word4
1833 struct lpfc_id_range id[53];
1839 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1840 * structure shares the same SHIFT/MASK/WORD defines provided in the
1841 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1842 * the structures defined above. This non-embedded structure provides for the
1843 * maximum number of extents supported by the port.
1845 struct lpfc_mbx_nembed_rsrc_extent {
1846 union lpfc_sli4_cfg_shdr cfg_shdr;
1848 struct lpfc_id_range id;
1851 struct lpfc_mbx_dealloc_rsrc_extents {
1852 struct mbox_header header;
1855 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1856 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1857 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
1862 /* Start SLI4 FCoE specific mbox structures. */
1864 struct lpfc_mbx_post_hdr_tmpl {
1865 struct mbox_header header;
1867 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1868 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1869 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1870 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1871 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1872 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1873 uint32_t rpi_paddr_lo;
1874 uint32_t rpi_paddr_hi;
1877 struct sli4_sge { /* SLI-4 */
1882 #define lpfc_sli4_sge_offset_SHIFT 0
1883 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1884 #define lpfc_sli4_sge_offset_WORD word2
1885 #define lpfc_sli4_sge_type_SHIFT 27
1886 #define lpfc_sli4_sge_type_MASK 0x0000000F
1887 #define lpfc_sli4_sge_type_WORD word2
1888 #define LPFC_SGE_TYPE_DATA 0x0
1889 #define LPFC_SGE_TYPE_DIF 0x4
1890 #define LPFC_SGE_TYPE_LSP 0x5
1891 #define LPFC_SGE_TYPE_PEDIF 0x6
1892 #define LPFC_SGE_TYPE_PESEED 0x7
1893 #define LPFC_SGE_TYPE_DISEED 0x8
1894 #define LPFC_SGE_TYPE_ENC 0x9
1895 #define LPFC_SGE_TYPE_ATM 0xA
1896 #define LPFC_SGE_TYPE_SKIP 0xC
1897 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
1898 #define lpfc_sli4_sge_last_MASK 0x00000001
1899 #define lpfc_sli4_sge_last_WORD word2
1903 struct sli4_sge_diseed { /* SLI-4 */
1905 uint32_t ref_tag_tran;
1908 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
1909 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
1910 #define lpfc_sli4_sge_dif_apptran_WORD word2
1911 #define lpfc_sli4_sge_dif_af_SHIFT 24
1912 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
1913 #define lpfc_sli4_sge_dif_af_WORD word2
1914 #define lpfc_sli4_sge_dif_na_SHIFT 25
1915 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
1916 #define lpfc_sli4_sge_dif_na_WORD word2
1917 #define lpfc_sli4_sge_dif_hi_SHIFT 26
1918 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
1919 #define lpfc_sli4_sge_dif_hi_WORD word2
1920 #define lpfc_sli4_sge_dif_type_SHIFT 27
1921 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
1922 #define lpfc_sli4_sge_dif_type_WORD word2
1923 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
1924 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
1925 #define lpfc_sli4_sge_dif_last_WORD word2
1927 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
1928 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
1929 #define lpfc_sli4_sge_dif_apptag_WORD word3
1930 #define lpfc_sli4_sge_dif_bs_SHIFT 16
1931 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
1932 #define lpfc_sli4_sge_dif_bs_WORD word3
1933 #define lpfc_sli4_sge_dif_ai_SHIFT 19
1934 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
1935 #define lpfc_sli4_sge_dif_ai_WORD word3
1936 #define lpfc_sli4_sge_dif_me_SHIFT 20
1937 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
1938 #define lpfc_sli4_sge_dif_me_WORD word3
1939 #define lpfc_sli4_sge_dif_re_SHIFT 21
1940 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
1941 #define lpfc_sli4_sge_dif_re_WORD word3
1942 #define lpfc_sli4_sge_dif_ce_SHIFT 22
1943 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
1944 #define lpfc_sli4_sge_dif_ce_WORD word3
1945 #define lpfc_sli4_sge_dif_nr_SHIFT 23
1946 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
1947 #define lpfc_sli4_sge_dif_nr_WORD word3
1948 #define lpfc_sli4_sge_dif_oprx_SHIFT 24
1949 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
1950 #define lpfc_sli4_sge_dif_oprx_WORD word3
1951 #define lpfc_sli4_sge_dif_optx_SHIFT 28
1952 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
1953 #define lpfc_sli4_sge_dif_optx_WORD word3
1954 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1958 uint32_t max_rcv_size;
1959 uint32_t fka_adv_period;
1960 uint32_t fip_priority;
1962 #define lpfc_fcf_record_mac_0_SHIFT 0
1963 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
1964 #define lpfc_fcf_record_mac_0_WORD word3
1965 #define lpfc_fcf_record_mac_1_SHIFT 8
1966 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
1967 #define lpfc_fcf_record_mac_1_WORD word3
1968 #define lpfc_fcf_record_mac_2_SHIFT 16
1969 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
1970 #define lpfc_fcf_record_mac_2_WORD word3
1971 #define lpfc_fcf_record_mac_3_SHIFT 24
1972 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
1973 #define lpfc_fcf_record_mac_3_WORD word3
1975 #define lpfc_fcf_record_mac_4_SHIFT 0
1976 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
1977 #define lpfc_fcf_record_mac_4_WORD word4
1978 #define lpfc_fcf_record_mac_5_SHIFT 8
1979 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
1980 #define lpfc_fcf_record_mac_5_WORD word4
1981 #define lpfc_fcf_record_fcf_avail_SHIFT 16
1982 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
1983 #define lpfc_fcf_record_fcf_avail_WORD word4
1984 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1985 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1986 #define lpfc_fcf_record_mac_addr_prov_WORD word4
1987 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1988 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1990 #define lpfc_fcf_record_fab_name_0_SHIFT 0
1991 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1992 #define lpfc_fcf_record_fab_name_0_WORD word5
1993 #define lpfc_fcf_record_fab_name_1_SHIFT 8
1994 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1995 #define lpfc_fcf_record_fab_name_1_WORD word5
1996 #define lpfc_fcf_record_fab_name_2_SHIFT 16
1997 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
1998 #define lpfc_fcf_record_fab_name_2_WORD word5
1999 #define lpfc_fcf_record_fab_name_3_SHIFT 24
2000 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2001 #define lpfc_fcf_record_fab_name_3_WORD word5
2003 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2004 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2005 #define lpfc_fcf_record_fab_name_4_WORD word6
2006 #define lpfc_fcf_record_fab_name_5_SHIFT 8
2007 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2008 #define lpfc_fcf_record_fab_name_5_WORD word6
2009 #define lpfc_fcf_record_fab_name_6_SHIFT 16
2010 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2011 #define lpfc_fcf_record_fab_name_6_WORD word6
2012 #define lpfc_fcf_record_fab_name_7_SHIFT 24
2013 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2014 #define lpfc_fcf_record_fab_name_7_WORD word6
2016 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2017 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2018 #define lpfc_fcf_record_fc_map_0_WORD word7
2019 #define lpfc_fcf_record_fc_map_1_SHIFT 8
2020 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2021 #define lpfc_fcf_record_fc_map_1_WORD word7
2022 #define lpfc_fcf_record_fc_map_2_SHIFT 16
2023 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2024 #define lpfc_fcf_record_fc_map_2_WORD word7
2025 #define lpfc_fcf_record_fcf_valid_SHIFT 24
2026 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2027 #define lpfc_fcf_record_fcf_valid_WORD word7
2028 #define lpfc_fcf_record_fcf_fc_SHIFT 25
2029 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2030 #define lpfc_fcf_record_fcf_fc_WORD word7
2031 #define lpfc_fcf_record_fcf_sol_SHIFT 31
2032 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2033 #define lpfc_fcf_record_fcf_sol_WORD word7
2035 #define lpfc_fcf_record_fcf_index_SHIFT 0
2036 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2037 #define lpfc_fcf_record_fcf_index_WORD word8
2038 #define lpfc_fcf_record_fcf_state_SHIFT 16
2039 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2040 #define lpfc_fcf_record_fcf_state_WORD word8
2041 uint8_t vlan_bitmap[512];
2043 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2044 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2045 #define lpfc_fcf_record_switch_name_0_WORD word137
2046 #define lpfc_fcf_record_switch_name_1_SHIFT 8
2047 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2048 #define lpfc_fcf_record_switch_name_1_WORD word137
2049 #define lpfc_fcf_record_switch_name_2_SHIFT 16
2050 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2051 #define lpfc_fcf_record_switch_name_2_WORD word137
2052 #define lpfc_fcf_record_switch_name_3_SHIFT 24
2053 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2054 #define lpfc_fcf_record_switch_name_3_WORD word137
2056 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2057 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2058 #define lpfc_fcf_record_switch_name_4_WORD word138
2059 #define lpfc_fcf_record_switch_name_5_SHIFT 8
2060 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2061 #define lpfc_fcf_record_switch_name_5_WORD word138
2062 #define lpfc_fcf_record_switch_name_6_SHIFT 16
2063 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2064 #define lpfc_fcf_record_switch_name_6_WORD word138
2065 #define lpfc_fcf_record_switch_name_7_SHIFT 24
2066 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2067 #define lpfc_fcf_record_switch_name_7_WORD word138
2070 struct lpfc_mbx_read_fcf_tbl {
2071 union lpfc_sli4_cfg_shdr cfg_shdr;
2075 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2076 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2077 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
2084 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2085 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2086 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
2089 struct lpfc_mbx_add_fcf_tbl_entry {
2090 union lpfc_sli4_cfg_shdr cfg_shdr;
2092 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2093 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2094 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
2095 struct lpfc_mbx_sge fcf_sge;
2098 struct lpfc_mbx_del_fcf_tbl_entry {
2099 struct mbox_header header;
2101 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2102 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2103 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
2104 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
2105 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2106 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
2109 struct lpfc_mbx_redisc_fcf_tbl {
2110 struct mbox_header header;
2112 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2113 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2114 #define lpfc_mbx_redisc_fcf_count_WORD word10
2117 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2118 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2119 #define lpfc_mbx_redisc_fcf_index_WORD word12
2122 /* Status field for embedded SLI_CONFIG mailbox command */
2123 #define STATUS_SUCCESS 0x0
2124 #define STATUS_FAILED 0x1
2125 #define STATUS_ILLEGAL_REQUEST 0x2
2126 #define STATUS_ILLEGAL_FIELD 0x3
2127 #define STATUS_INSUFFICIENT_BUFFER 0x4
2128 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2129 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2130 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2131 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2132 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2133 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2134 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2135 #define STATUS_ASSERT_FAILED 0x1e
2136 #define STATUS_INVALID_SESSION 0x1f
2137 #define STATUS_INVALID_CONNECTION 0x20
2138 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2139 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2140 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2141 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2142 #define STATUS_FLASHROM_READ_FAILED 0x27
2143 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2144 #define STATUS_ERROR_ACITMAIN 0x2a
2145 #define STATUS_REBOOT_REQUIRED 0x2c
2146 #define STATUS_FCF_IN_USE 0x3a
2147 #define STATUS_FCF_TABLE_EMPTY 0x43
2150 * Additional status field for embedded SLI_CONFIG mailbox
2153 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2155 struct lpfc_mbx_sli4_config {
2156 struct mbox_header header;
2159 struct lpfc_mbx_init_vfi {
2161 #define lpfc_init_vfi_vr_SHIFT 31
2162 #define lpfc_init_vfi_vr_MASK 0x00000001
2163 #define lpfc_init_vfi_vr_WORD word1
2164 #define lpfc_init_vfi_vt_SHIFT 30
2165 #define lpfc_init_vfi_vt_MASK 0x00000001
2166 #define lpfc_init_vfi_vt_WORD word1
2167 #define lpfc_init_vfi_vf_SHIFT 29
2168 #define lpfc_init_vfi_vf_MASK 0x00000001
2169 #define lpfc_init_vfi_vf_WORD word1
2170 #define lpfc_init_vfi_vp_SHIFT 28
2171 #define lpfc_init_vfi_vp_MASK 0x00000001
2172 #define lpfc_init_vfi_vp_WORD word1
2173 #define lpfc_init_vfi_vfi_SHIFT 0
2174 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2175 #define lpfc_init_vfi_vfi_WORD word1
2177 #define lpfc_init_vfi_vpi_SHIFT 16
2178 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2179 #define lpfc_init_vfi_vpi_WORD word2
2180 #define lpfc_init_vfi_fcfi_SHIFT 0
2181 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2182 #define lpfc_init_vfi_fcfi_WORD word2
2184 #define lpfc_init_vfi_pri_SHIFT 13
2185 #define lpfc_init_vfi_pri_MASK 0x00000007
2186 #define lpfc_init_vfi_pri_WORD word3
2187 #define lpfc_init_vfi_vf_id_SHIFT 1
2188 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2189 #define lpfc_init_vfi_vf_id_WORD word3
2191 #define lpfc_init_vfi_hop_count_SHIFT 24
2192 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2193 #define lpfc_init_vfi_hop_count_WORD word4
2195 #define MBX_VFI_IN_USE 0x9F02
2198 struct lpfc_mbx_reg_vfi {
2200 #define lpfc_reg_vfi_upd_SHIFT 29
2201 #define lpfc_reg_vfi_upd_MASK 0x00000001
2202 #define lpfc_reg_vfi_upd_WORD word1
2203 #define lpfc_reg_vfi_vp_SHIFT 28
2204 #define lpfc_reg_vfi_vp_MASK 0x00000001
2205 #define lpfc_reg_vfi_vp_WORD word1
2206 #define lpfc_reg_vfi_vfi_SHIFT 0
2207 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2208 #define lpfc_reg_vfi_vfi_WORD word1
2210 #define lpfc_reg_vfi_vpi_SHIFT 16
2211 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2212 #define lpfc_reg_vfi_vpi_WORD word2
2213 #define lpfc_reg_vfi_fcfi_SHIFT 0
2214 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2215 #define lpfc_reg_vfi_fcfi_WORD word2
2217 struct ulp_bde64 bde;
2221 #define lpfc_reg_vfi_nport_id_SHIFT 0
2222 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2223 #define lpfc_reg_vfi_nport_id_WORD word10
2224 #define lpfc_reg_vfi_bbcr_SHIFT 27
2225 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2226 #define lpfc_reg_vfi_bbcr_WORD word10
2227 #define lpfc_reg_vfi_bbscn_SHIFT 28
2228 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2229 #define lpfc_reg_vfi_bbscn_WORD word10
2232 struct lpfc_mbx_init_vpi {
2234 #define lpfc_init_vpi_vfi_SHIFT 16
2235 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2236 #define lpfc_init_vpi_vfi_WORD word1
2237 #define lpfc_init_vpi_vpi_SHIFT 0
2238 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2239 #define lpfc_init_vpi_vpi_WORD word1
2242 struct lpfc_mbx_read_vpi {
2243 uint32_t word1_rsvd;
2245 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2246 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2247 #define lpfc_mbx_read_vpi_vnportid_WORD word2
2248 uint32_t word3_rsvd;
2250 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2251 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2252 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
2253 #define lpfc_mbx_read_vpi_pb_SHIFT 15
2254 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2255 #define lpfc_mbx_read_vpi_pb_WORD word4
2256 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
2257 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2258 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
2259 #define lpfc_mbx_read_vpi_ns_SHIFT 30
2260 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2261 #define lpfc_mbx_read_vpi_ns_WORD word4
2262 #define lpfc_mbx_read_vpi_hl_SHIFT 31
2263 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2264 #define lpfc_mbx_read_vpi_hl_WORD word4
2265 uint32_t word5_rsvd;
2267 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2268 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2269 #define lpfc_mbx_read_vpi_vpi_WORD word6
2271 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2272 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2273 #define lpfc_mbx_read_vpi_mac_0_WORD word7
2274 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
2275 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2276 #define lpfc_mbx_read_vpi_mac_1_WORD word7
2277 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
2278 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2279 #define lpfc_mbx_read_vpi_mac_2_WORD word7
2280 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
2281 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2282 #define lpfc_mbx_read_vpi_mac_3_WORD word7
2284 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2285 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2286 #define lpfc_mbx_read_vpi_mac_4_WORD word8
2287 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
2288 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2289 #define lpfc_mbx_read_vpi_mac_5_WORD word8
2290 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
2291 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2292 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
2293 #define lpfc_mbx_read_vpi_vv_SHIFT 28
2294 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2295 #define lpfc_mbx_read_vpi_vv_WORD word8
2298 struct lpfc_mbx_unreg_vfi {
2299 uint32_t word1_rsvd;
2301 #define lpfc_unreg_vfi_vfi_SHIFT 0
2302 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2303 #define lpfc_unreg_vfi_vfi_WORD word2
2306 struct lpfc_mbx_resume_rpi {
2308 #define lpfc_resume_rpi_index_SHIFT 0
2309 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2310 #define lpfc_resume_rpi_index_WORD word1
2311 #define lpfc_resume_rpi_ii_SHIFT 30
2312 #define lpfc_resume_rpi_ii_MASK 0x00000003
2313 #define lpfc_resume_rpi_ii_WORD word1
2314 #define RESUME_INDEX_RPI 0
2315 #define RESUME_INDEX_VPI 1
2316 #define RESUME_INDEX_VFI 2
2317 #define RESUME_INDEX_FCFI 3
2321 #define REG_FCF_INVALID_QID 0xFFFF
2322 struct lpfc_mbx_reg_fcfi {
2324 #define lpfc_reg_fcfi_info_index_SHIFT 0
2325 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2326 #define lpfc_reg_fcfi_info_index_WORD word1
2327 #define lpfc_reg_fcfi_fcfi_SHIFT 16
2328 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2329 #define lpfc_reg_fcfi_fcfi_WORD word1
2331 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2332 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2333 #define lpfc_reg_fcfi_rq_id1_WORD word2
2334 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
2335 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2336 #define lpfc_reg_fcfi_rq_id0_WORD word2
2338 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2339 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2340 #define lpfc_reg_fcfi_rq_id3_WORD word3
2341 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
2342 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2343 #define lpfc_reg_fcfi_rq_id2_WORD word3
2345 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2346 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2347 #define lpfc_reg_fcfi_type_match0_WORD word4
2348 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
2349 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2350 #define lpfc_reg_fcfi_type_mask0_WORD word4
2351 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2352 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2353 #define lpfc_reg_fcfi_rctl_match0_WORD word4
2354 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2355 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2356 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
2358 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2359 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2360 #define lpfc_reg_fcfi_type_match1_WORD word5
2361 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
2362 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2363 #define lpfc_reg_fcfi_type_mask1_WORD word5
2364 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2365 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2366 #define lpfc_reg_fcfi_rctl_match1_WORD word5
2367 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2368 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2369 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
2371 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2372 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2373 #define lpfc_reg_fcfi_type_match2_WORD word6
2374 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
2375 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2376 #define lpfc_reg_fcfi_type_mask2_WORD word6
2377 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2378 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2379 #define lpfc_reg_fcfi_rctl_match2_WORD word6
2380 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2381 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2382 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
2384 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2385 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2386 #define lpfc_reg_fcfi_type_match3_WORD word7
2387 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
2388 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2389 #define lpfc_reg_fcfi_type_mask3_WORD word7
2390 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2391 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2392 #define lpfc_reg_fcfi_rctl_match3_WORD word7
2393 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2394 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2395 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
2397 #define lpfc_reg_fcfi_mam_SHIFT 13
2398 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2399 #define lpfc_reg_fcfi_mam_WORD word8
2400 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2401 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2402 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2403 #define lpfc_reg_fcfi_vv_SHIFT 12
2404 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2405 #define lpfc_reg_fcfi_vv_WORD word8
2406 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2407 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2408 #define lpfc_reg_fcfi_vlan_tag_WORD word8
2411 struct lpfc_mbx_reg_fcfi_mrq {
2413 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2414 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2415 #define lpfc_reg_fcfi_mrq_info_index_WORD word1
2416 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16
2417 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2418 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1
2420 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2421 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2422 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2
2423 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16
2424 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2425 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2
2427 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2428 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2429 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3
2430 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16
2431 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2432 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3
2434 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24
2435 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2436 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4
2437 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16
2438 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2439 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4
2440 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8
2441 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2442 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4
2443 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2444 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2445 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4
2447 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24
2448 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2449 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5
2450 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16
2451 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2452 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5
2453 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8
2454 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2455 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5
2456 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2457 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2458 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5
2460 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24
2461 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2462 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6
2463 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16
2464 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2465 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6
2466 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8
2467 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2468 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6
2469 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2470 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2471 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6
2473 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24
2474 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2475 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7
2476 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16
2477 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2478 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7
2479 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8
2480 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2481 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7
2482 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2483 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2484 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7
2486 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31
2487 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2488 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8
2489 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30
2490 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2491 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8
2492 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29
2493 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2494 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8
2495 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28
2496 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2497 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8
2498 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27
2499 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2500 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8
2501 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26
2502 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2503 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8
2504 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25
2505 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2506 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8
2507 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24
2508 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2509 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8
2510 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23
2511 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2512 #define lpfc_reg_fcfi_mrq_pt7_WORD word8
2513 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22
2514 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2515 #define lpfc_reg_fcfi_mrq_pt6_WORD word8
2516 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21
2517 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2518 #define lpfc_reg_fcfi_mrq_pt5_WORD word8
2519 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20
2520 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2521 #define lpfc_reg_fcfi_mrq_pt4_WORD word8
2522 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19
2523 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2524 #define lpfc_reg_fcfi_mrq_pt3_WORD word8
2525 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18
2526 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2527 #define lpfc_reg_fcfi_mrq_pt2_WORD word8
2528 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17
2529 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2530 #define lpfc_reg_fcfi_mrq_pt1_WORD word8
2531 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16
2532 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2533 #define lpfc_reg_fcfi_mrq_pt0_WORD word8
2534 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15
2535 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2536 #define lpfc_reg_fcfi_mrq_xmv_WORD word8
2537 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13
2538 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2539 #define lpfc_reg_fcfi_mrq_mode_WORD word8
2540 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12
2541 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2542 #define lpfc_reg_fcfi_mrq_vv_WORD word8
2543 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2544 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2545 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8
2547 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12
2548 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2549 #define lpfc_reg_fcfi_mrq_policy_WORD word9
2550 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8
2551 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2552 #define lpfc_reg_fcfi_mrq_filter_WORD word9
2553 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2554 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2555 #define lpfc_reg_fcfi_mrq_npairs_WORD word9
2565 struct lpfc_mbx_unreg_fcfi {
2568 #define lpfc_unreg_fcfi_SHIFT 0
2569 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2570 #define lpfc_unreg_fcfi_WORD word2
2573 struct lpfc_mbx_read_rev {
2575 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2576 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2577 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2578 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2579 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2580 #define lpfc_mbx_rd_rev_fcoe_WORD word1
2581 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2582 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2583 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
2584 #define LPFC_PREDCBX_CEE_MODE 0
2585 #define LPFC_DCBX_CEE_MODE 1
2586 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
2587 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2588 #define lpfc_mbx_rd_rev_vpd_WORD word1
2589 uint32_t first_hw_rev;
2590 uint32_t second_hw_rev;
2591 uint32_t word4_rsvd;
2592 uint32_t third_hw_rev;
2594 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2595 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2596 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
2597 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2598 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2599 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
2600 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2601 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2602 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2603 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2604 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2605 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2606 uint32_t word7_rsvd;
2608 uint8_t fw_name[16];
2609 uint32_t ulp_fw_id_rev;
2610 uint8_t ulp_fw_name[16];
2611 uint32_t word18_47_rsvd[30];
2613 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2614 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2615 #define lpfc_mbx_rd_rev_avail_len_WORD word48
2616 uint32_t vpd_paddr_low;
2617 uint32_t vpd_paddr_high;
2618 uint32_t avail_vpd_len;
2619 uint32_t rsvd_52_63[12];
2622 struct lpfc_mbx_read_config {
2624 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2625 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2626 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2628 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2629 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2630 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2631 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2632 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2633 #define lpfc_mbx_rd_conf_lnk_type_WORD word2
2634 #define LPFC_LNK_TYPE_GE 0
2635 #define LPFC_LNK_TYPE_FC 1
2636 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2637 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2638 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2639 #define lpfc_mbx_rd_conf_topology_SHIFT 24
2640 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2641 #define lpfc_mbx_rd_conf_topology_WORD word2
2644 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2645 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2646 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2649 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2650 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2651 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2652 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16
2653 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2654 #define lpfc_mbx_rd_conf_link_speed_WORD word6
2657 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2658 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2659 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8
2660 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4
2661 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2662 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8
2663 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8
2664 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2665 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8
2667 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2668 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2669 #define lpfc_mbx_rd_conf_lmt_WORD word9
2673 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2674 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2675 #define lpfc_mbx_rd_conf_xri_base_WORD word12
2676 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2677 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2678 #define lpfc_mbx_rd_conf_xri_count_WORD word12
2680 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2681 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2682 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
2683 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2684 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2685 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
2687 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2688 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2689 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
2690 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2691 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2692 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
2694 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2695 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2696 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
2697 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2698 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2699 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
2701 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2702 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2703 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2705 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2706 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2707 #define lpfc_mbx_rd_conf_rq_count_WORD word17
2708 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2709 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2710 #define lpfc_mbx_rd_conf_eq_count_WORD word17
2712 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2713 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2714 #define lpfc_mbx_rd_conf_wq_count_WORD word18
2715 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2716 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2717 #define lpfc_mbx_rd_conf_cq_count_WORD word18
2720 struct lpfc_mbx_request_features {
2722 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2723 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2724 #define lpfc_mbx_rq_ftr_qry_WORD word1
2726 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2727 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2728 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2729 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2730 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2731 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2732 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2733 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2734 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2735 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2736 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2737 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2738 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2739 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2740 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2741 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2742 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2743 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2744 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2745 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2746 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2747 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2748 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2749 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2750 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9
2751 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2752 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2
2753 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2754 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2755 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2756 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16
2757 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2758 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2
2760 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2761 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2762 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2763 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2764 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2765 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2766 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2767 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2768 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2769 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2770 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2771 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2772 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2773 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2774 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2775 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2776 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2777 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2778 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2779 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2780 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2781 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2782 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2783 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2784 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2785 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2786 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2787 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16
2788 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2789 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3
2792 struct lpfc_mbx_memory_dump_type3 {
2794 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
2795 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
2796 #define lpfc_mbx_memory_dump_type3_type_WORD word1
2797 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24
2798 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
2799 #define lpfc_mbx_memory_dump_type3_link_WORD word1
2801 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
2802 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
2803 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2
2804 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16
2805 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
2806 #define lpfc_mbx_memory_dump_type3_offset_WORD word2
2808 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
2809 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
2810 #define lpfc_mbx_memory_dump_type3_length_WORD word3
2813 uint32_t return_len;
2816 #define DMP_PAGE_A0 0xa0
2817 #define DMP_PAGE_A2 0xa2
2818 #define DMP_SFF_PAGE_A0_SIZE 256
2819 #define DMP_SFF_PAGE_A2_SIZE 256
2821 #define SFP_WAVELENGTH_LC1310 1310
2822 #define SFP_WAVELENGTH_LL1550 1550
2826 * * SFF-8472 TABLE 3.4
2828 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
2829 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
2830 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
2831 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
2832 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
2833 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
2834 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
2835 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
2836 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
2837 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
2838 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
2839 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
2840 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
2841 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
2842 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
2843 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
2845 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
2847 #define SSF_IDENTIFIER 0
2848 #define SSF_EXT_IDENTIFIER 1
2849 #define SSF_CONNECTOR 2
2850 #define SSF_TRANSCEIVER_CODE_B0 3
2851 #define SSF_TRANSCEIVER_CODE_B1 4
2852 #define SSF_TRANSCEIVER_CODE_B2 5
2853 #define SSF_TRANSCEIVER_CODE_B3 6
2854 #define SSF_TRANSCEIVER_CODE_B4 7
2855 #define SSF_TRANSCEIVER_CODE_B5 8
2856 #define SSF_TRANSCEIVER_CODE_B6 9
2857 #define SSF_TRANSCEIVER_CODE_B7 10
2858 #define SSF_ENCODING 11
2859 #define SSF_BR_NOMINAL 12
2860 #define SSF_RATE_IDENTIFIER 13
2861 #define SSF_LENGTH_9UM_KM 14
2862 #define SSF_LENGTH_9UM 15
2863 #define SSF_LENGTH_50UM_OM2 16
2864 #define SSF_LENGTH_62UM_OM1 17
2865 #define SFF_LENGTH_COPPER 18
2866 #define SSF_LENGTH_50UM_OM3 19
2867 #define SSF_VENDOR_NAME 20
2868 #define SSF_VENDOR_OUI 36
2869 #define SSF_VENDOR_PN 40
2870 #define SSF_VENDOR_REV 56
2871 #define SSF_WAVELENGTH_B1 60
2872 #define SSF_WAVELENGTH_B0 61
2873 #define SSF_CC_BASE 63
2874 #define SSF_OPTIONS_B1 64
2875 #define SSF_OPTIONS_B0 65
2876 #define SSF_BR_MAX 66
2877 #define SSF_BR_MIN 67
2878 #define SSF_VENDOR_SN 68
2879 #define SSF_DATE_CODE 84
2880 #define SSF_MONITORING_TYPEDIAGNOSTIC 92
2881 #define SSF_ENHANCED_OPTIONS 93
2882 #define SFF_8472_COMPLIANCE 94
2883 #define SSF_CC_EXT 95
2884 #define SSF_A0_VENDOR_SPECIFIC 96
2886 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
2888 #define SSF_TEMP_HIGH_ALARM 0
2889 #define SSF_TEMP_LOW_ALARM 2
2890 #define SSF_TEMP_HIGH_WARNING 4
2891 #define SSF_TEMP_LOW_WARNING 6
2892 #define SSF_VOLTAGE_HIGH_ALARM 8
2893 #define SSF_VOLTAGE_LOW_ALARM 10
2894 #define SSF_VOLTAGE_HIGH_WARNING 12
2895 #define SSF_VOLTAGE_LOW_WARNING 14
2896 #define SSF_BIAS_HIGH_ALARM 16
2897 #define SSF_BIAS_LOW_ALARM 18
2898 #define SSF_BIAS_HIGH_WARNING 20
2899 #define SSF_BIAS_LOW_WARNING 22
2900 #define SSF_TXPOWER_HIGH_ALARM 24
2901 #define SSF_TXPOWER_LOW_ALARM 26
2902 #define SSF_TXPOWER_HIGH_WARNING 28
2903 #define SSF_TXPOWER_LOW_WARNING 30
2904 #define SSF_RXPOWER_HIGH_ALARM 32
2905 #define SSF_RXPOWER_LOW_ALARM 34
2906 #define SSF_RXPOWER_HIGH_WARNING 36
2907 #define SSF_RXPOWER_LOW_WARNING 38
2908 #define SSF_EXT_CAL_CONSTANTS 56
2909 #define SSF_CC_DMI 95
2910 #define SFF_TEMPERATURE_B1 96
2911 #define SFF_TEMPERATURE_B0 97
2912 #define SFF_VCC_B1 98
2913 #define SFF_VCC_B0 99
2914 #define SFF_TX_BIAS_CURRENT_B1 100
2915 #define SFF_TX_BIAS_CURRENT_B0 101
2916 #define SFF_TXPOWER_B1 102
2917 #define SFF_TXPOWER_B0 103
2918 #define SFF_RXPOWER_B1 104
2919 #define SFF_RXPOWER_B0 105
2920 #define SSF_STATUS_CONTROL 110
2921 #define SSF_ALARM_FLAGS 112
2922 #define SSF_WARNING_FLAGS 116
2923 #define SSF_EXT_TATUS_CONTROL_B1 118
2924 #define SSF_EXT_TATUS_CONTROL_B0 119
2925 #define SSF_A2_VENDOR_SPECIFIC 120
2926 #define SSF_USER_EEPROM 128
2927 #define SSF_VENDOR_CONTROL 148
2931 * Tranceiver codes Fibre Channel SFF-8472
2935 struct sff_trasnceiver_codes_byte0 {
2936 uint8_t inifiband:4;
2937 uint8_t teng_ethernet:4;
2940 struct sff_trasnceiver_codes_byte1 {
2945 struct sff_trasnceiver_codes_byte2 {
2949 struct sff_trasnceiver_codes_byte3 {
2953 struct sff_trasnceiver_codes_byte4 {
2955 uint8_t fc_lw_laser:1;
2956 uint8_t fc_sw_laser:1;
2957 uint8_t fc_md_distance:1;
2958 uint8_t fc_lg_distance:1;
2959 uint8_t fc_int_distance:1;
2960 uint8_t fc_short_distance:1;
2961 uint8_t fc_vld_distance:1;
2964 struct sff_trasnceiver_codes_byte5 {
2965 uint8_t reserved1:1;
2966 uint8_t reserved2:1;
2967 uint8_t fc_sfp_active:1; /* Active cable */
2968 uint8_t fc_sfp_passive:1; /* Passive cable */
2969 uint8_t fc_lw_laser:1; /* Longwave laser */
2970 uint8_t fc_sw_laser_sl:1;
2971 uint8_t fc_sw_laser_sn:1;
2972 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */
2975 struct sff_trasnceiver_codes_byte6 {
2976 uint8_t fc_tm_sm:1; /* Single Mode */
2978 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */
2979 uint8_t fc_tm_tv:1; /* Video Coax (TV) */
2980 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */
2981 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */
2982 uint8_t fc_tm_tw:1; /* Twin Axial Pair */
2985 struct sff_trasnceiver_codes_byte7 {
2986 uint8_t fc_sp_100MB:1; /* 100 MB/sec */
2988 uint8_t fc_sp_200mb:1; /* 200 MB/sec */
2989 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */
2990 uint8_t fc_sp_400MB:1; /* 400 MB/sec */
2991 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */
2992 uint8_t fc_sp_800MB:1; /* 800 MB/sec */
2993 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */
2996 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
2997 struct user_eeprom {
2998 uint8_t vendor_name[16];
2999 uint8_t vendor_oui[3];
3000 uint8_t vendor_pn[816];
3001 uint8_t vendor_rev[4];
3002 uint8_t vendor_sn[16];
3003 uint8_t datecode[6];
3004 uint8_t lot_code[2];
3005 uint8_t reserved191[57];
3008 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3009 &(~((SLI4_PAGE_SIZE)-1)))
3011 struct lpfc_sli4_parameters {
3013 #define cfg_prot_type_SHIFT 0
3014 #define cfg_prot_type_MASK 0x000000FF
3015 #define cfg_prot_type_WORD word0
3017 #define cfg_ft_SHIFT 0
3018 #define cfg_ft_MASK 0x00000001
3019 #define cfg_ft_WORD word1
3020 #define cfg_sli_rev_SHIFT 4
3021 #define cfg_sli_rev_MASK 0x0000000f
3022 #define cfg_sli_rev_WORD word1
3023 #define cfg_sli_family_SHIFT 8
3024 #define cfg_sli_family_MASK 0x0000000f
3025 #define cfg_sli_family_WORD word1
3026 #define cfg_if_type_SHIFT 12
3027 #define cfg_if_type_MASK 0x0000000f
3028 #define cfg_if_type_WORD word1
3029 #define cfg_sli_hint_1_SHIFT 16
3030 #define cfg_sli_hint_1_MASK 0x000000ff
3031 #define cfg_sli_hint_1_WORD word1
3032 #define cfg_sli_hint_2_SHIFT 24
3033 #define cfg_sli_hint_2_MASK 0x0000001f
3034 #define cfg_sli_hint_2_WORD word1
3038 #define cfg_cqv_SHIFT 14
3039 #define cfg_cqv_MASK 0x00000003
3040 #define cfg_cqv_WORD word4
3043 #define cfg_mqv_SHIFT 14
3044 #define cfg_mqv_MASK 0x00000003
3045 #define cfg_mqv_WORD word6
3048 #define cfg_wqpcnt_SHIFT 0
3049 #define cfg_wqpcnt_MASK 0x0000000f
3050 #define cfg_wqpcnt_WORD word8
3051 #define cfg_wqsize_SHIFT 8
3052 #define cfg_wqsize_MASK 0x0000000f
3053 #define cfg_wqsize_WORD word8
3054 #define cfg_wqv_SHIFT 14
3055 #define cfg_wqv_MASK 0x00000003
3056 #define cfg_wqv_WORD word8
3057 #define cfg_wqpsize_SHIFT 16
3058 #define cfg_wqpsize_MASK 0x000000ff
3059 #define cfg_wqpsize_WORD word8
3062 #define cfg_rqv_SHIFT 14
3063 #define cfg_rqv_MASK 0x00000003
3064 #define cfg_rqv_WORD word10
3066 #define cfg_rq_db_window_SHIFT 28
3067 #define cfg_rq_db_window_MASK 0x0000000f
3068 #define cfg_rq_db_window_WORD word11
3070 #define cfg_fcoe_SHIFT 0
3071 #define cfg_fcoe_MASK 0x00000001
3072 #define cfg_fcoe_WORD word12
3073 #define cfg_ext_SHIFT 1
3074 #define cfg_ext_MASK 0x00000001
3075 #define cfg_ext_WORD word12
3076 #define cfg_hdrr_SHIFT 2
3077 #define cfg_hdrr_MASK 0x00000001
3078 #define cfg_hdrr_WORD word12
3079 #define cfg_phwq_SHIFT 15
3080 #define cfg_phwq_MASK 0x00000001
3081 #define cfg_phwq_WORD word12
3082 #define cfg_oas_SHIFT 25
3083 #define cfg_oas_MASK 0x00000001
3084 #define cfg_oas_WORD word12
3085 #define cfg_loopbk_scope_SHIFT 28
3086 #define cfg_loopbk_scope_MASK 0x0000000f
3087 #define cfg_loopbk_scope_WORD word12
3088 uint32_t sge_supp_len;
3090 #define cfg_sgl_page_cnt_SHIFT 0
3091 #define cfg_sgl_page_cnt_MASK 0x0000000f
3092 #define cfg_sgl_page_cnt_WORD word14
3093 #define cfg_sgl_page_size_SHIFT 8
3094 #define cfg_sgl_page_size_MASK 0x000000ff
3095 #define cfg_sgl_page_size_WORD word14
3096 #define cfg_sgl_pp_align_SHIFT 16
3097 #define cfg_sgl_pp_align_MASK 0x000000ff
3098 #define cfg_sgl_pp_align_WORD word14
3104 #define cfg_ext_embed_cb_SHIFT 0
3105 #define cfg_ext_embed_cb_MASK 0x00000001
3106 #define cfg_ext_embed_cb_WORD word19
3107 #define cfg_mds_diags_SHIFT 1
3108 #define cfg_mds_diags_MASK 0x00000001
3109 #define cfg_mds_diags_WORD word19
3110 #define cfg_nvme_SHIFT 3
3111 #define cfg_nvme_MASK 0x00000001
3112 #define cfg_nvme_WORD word19
3113 #define cfg_xib_SHIFT 4
3114 #define cfg_xib_MASK 0x00000001
3115 #define cfg_xib_WORD word19
3116 #define cfg_eqdr_SHIFT 8
3117 #define cfg_eqdr_MASK 0x00000001
3118 #define cfg_eqdr_WORD word19
3119 #define LPFC_NODELAY_MAX_IO 32
3122 #define LPFC_SET_UE_RECOVERY 0x10
3123 #define LPFC_SET_MDS_DIAGS 0x11
3124 struct lpfc_mbx_set_feature {
3125 struct mbox_header header;
3129 #define lpfc_mbx_set_feature_UER_SHIFT 0
3130 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3131 #define lpfc_mbx_set_feature_UER_WORD word6
3132 #define lpfc_mbx_set_feature_mds_SHIFT 0
3133 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3134 #define lpfc_mbx_set_feature_mds_WORD word6
3135 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1
3136 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3137 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6
3139 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3140 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3141 #define lpfc_mbx_set_feature_UERP_WORD word7
3142 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3143 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3144 #define lpfc_mbx_set_feature_UESR_WORD word7
3148 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3149 struct lpfc_mbx_set_host_data {
3150 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48
3151 struct mbox_header header;
3154 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3158 struct lpfc_mbx_get_sli4_parameters {
3159 struct mbox_header header;
3160 struct lpfc_sli4_parameters sli4_parameters;
3163 struct lpfc_rscr_desc_generic {
3164 #define LPFC_RSRC_DESC_WSIZE 22
3165 uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3168 struct lpfc_rsrc_desc_pcie {
3170 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3171 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3172 #define lpfc_rsrc_desc_pcie_type_WORD word0
3173 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3174 #define lpfc_rsrc_desc_pcie_length_SHIFT 8
3175 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3176 #define lpfc_rsrc_desc_pcie_length_WORD word0
3178 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3179 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3180 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1
3183 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3184 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3185 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
3186 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
3187 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3188 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
3189 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
3190 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3191 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3
3193 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3194 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3195 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
3198 struct lpfc_rsrc_desc_fcfcoe {
3200 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3201 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3202 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0
3203 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3204 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8
3205 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3206 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0
3207 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3208 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72
3209 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88
3211 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3212 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3213 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
3214 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
3215 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3216 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
3218 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3219 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3220 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
3221 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
3222 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3223 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
3225 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3226 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3227 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
3228 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
3229 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3230 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
3232 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3233 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3234 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
3235 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
3236 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3237 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
3239 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3240 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3241 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
3242 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
3243 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3244 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
3253 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3254 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3255 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
3256 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
3257 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3258 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
3259 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
3260 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3261 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
3262 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
3263 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3264 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
3265 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
3266 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3267 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
3268 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3273 uint32_t reserved[4];
3276 struct lpfc_func_cfg {
3277 #define LPFC_RSRC_DESC_MAX_NUM 2
3278 uint32_t rsrc_desc_count;
3279 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3282 struct lpfc_mbx_get_func_cfg {
3283 struct mbox_header header;
3284 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3285 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3286 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3287 struct lpfc_func_cfg func_cfg;
3290 struct lpfc_prof_cfg {
3291 #define LPFC_RSRC_DESC_MAX_NUM 2
3292 uint32_t rsrc_desc_count;
3293 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3296 struct lpfc_mbx_get_prof_cfg {
3297 struct mbox_header header;
3298 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3299 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3300 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3304 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3305 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3306 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
3307 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
3308 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3309 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
3312 struct lpfc_prof_cfg prof_cfg;
3317 struct lpfc_controller_attribute {
3318 uint32_t version_string[8];
3319 uint32_t manufacturer_name[8];
3320 uint32_t supported_modes;
3322 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3323 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3324 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17
3325 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
3326 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3327 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17
3328 uint32_t mbx_da_struct_ver;
3329 uint32_t ep_fw_da_struct_ver;
3330 uint32_t ncsi_ver_str[3];
3331 uint32_t dflt_ext_timeout;
3332 uint32_t model_number[8];
3333 uint32_t description[16];
3334 uint32_t serial_number[8];
3335 uint32_t ip_ver_str[8];
3336 uint32_t fw_ver_str[8];
3337 uint32_t bios_ver_str[8];
3338 uint32_t redboot_ver_str[8];
3339 uint32_t driver_ver_str[8];
3340 uint32_t flash_fw_ver_str[8];
3341 uint32_t functionality;
3343 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3344 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3345 #define lpfc_cntl_attr_max_cbd_len_WORD word105
3346 #define lpfc_cntl_attr_asic_rev_SHIFT 16
3347 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3348 #define lpfc_cntl_attr_asic_rev_WORD word105
3349 #define lpfc_cntl_attr_gen_guid0_SHIFT 24
3350 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3351 #define lpfc_cntl_attr_gen_guid0_WORD word105
3352 uint32_t gen_guid1_12[3];
3354 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3355 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3356 #define lpfc_cntl_attr_gen_guid13_14_WORD word109
3357 #define lpfc_cntl_attr_gen_guid15_SHIFT 16
3358 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3359 #define lpfc_cntl_attr_gen_guid15_WORD word109
3360 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
3361 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3362 #define lpfc_cntl_attr_hba_port_cnt_WORD word109
3364 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3365 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3366 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
3367 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24
3368 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3369 #define lpfc_cntl_attr_multi_func_dev_WORD word110
3371 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3372 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3373 #define lpfc_cntl_attr_cache_valid_WORD word111
3374 #define lpfc_cntl_attr_hba_status_SHIFT 8
3375 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3376 #define lpfc_cntl_attr_hba_status_WORD word111
3377 #define lpfc_cntl_attr_max_domain_SHIFT 16
3378 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3379 #define lpfc_cntl_attr_max_domain_WORD word111
3380 #define lpfc_cntl_attr_lnk_numb_SHIFT 24
3381 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3382 #define lpfc_cntl_attr_lnk_numb_WORD word111
3383 #define lpfc_cntl_attr_lnk_type_SHIFT 30
3384 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3385 #define lpfc_cntl_attr_lnk_type_WORD word111
3386 uint32_t fw_post_status;
3387 uint32_t hba_mtu[8];
3389 uint32_t reserved1[3];
3391 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3392 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3393 #define lpfc_cntl_attr_pci_vendor_id_WORD word125
3394 #define lpfc_cntl_attr_pci_device_id_SHIFT 16
3395 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3396 #define lpfc_cntl_attr_pci_device_id_WORD word125
3398 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3399 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3400 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126
3401 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
3402 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3403 #define lpfc_cntl_attr_pci_subsys_id_WORD word126
3405 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3406 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3407 #define lpfc_cntl_attr_pci_bus_num_WORD word127
3408 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8
3409 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3410 #define lpfc_cntl_attr_pci_dev_num_WORD word127
3411 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
3412 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3413 #define lpfc_cntl_attr_pci_fnc_num_WORD word127
3414 #define lpfc_cntl_attr_inf_type_SHIFT 24
3415 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3416 #define lpfc_cntl_attr_inf_type_WORD word127
3417 uint32_t unique_id[2];
3419 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3420 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3421 #define lpfc_cntl_attr_num_netfil_WORD word130
3422 uint32_t reserved2[4];
3425 struct lpfc_mbx_get_cntl_attributes {
3426 union lpfc_sli4_cfg_shdr cfg_shdr;
3427 struct lpfc_controller_attribute cntl_attr;
3430 struct lpfc_mbx_get_port_name {
3431 struct mbox_header header;
3435 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3436 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3437 #define lpfc_mbx_get_port_name_lnk_type_WORD word4
3441 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3442 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3443 #define lpfc_mbx_get_port_name_name0_WORD word4
3444 #define lpfc_mbx_get_port_name_name1_SHIFT 8
3445 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3446 #define lpfc_mbx_get_port_name_name1_WORD word4
3447 #define lpfc_mbx_get_port_name_name2_SHIFT 16
3448 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3449 #define lpfc_mbx_get_port_name_name2_WORD word4
3450 #define lpfc_mbx_get_port_name_name3_SHIFT 24
3451 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3452 #define lpfc_mbx_get_port_name_name3_WORD word4
3453 #define LPFC_LINK_NUMBER_0 0
3454 #define LPFC_LINK_NUMBER_1 1
3455 #define LPFC_LINK_NUMBER_2 2
3456 #define LPFC_LINK_NUMBER_3 3
3461 /* Mailbox Completion Queue Error Messages */
3462 #define MB_CQE_STATUS_SUCCESS 0x0
3463 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3464 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3465 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3466 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3467 #define MB_CQE_STATUS_DMA_FAILED 0x5
3469 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1
3470 struct lpfc_mbx_wr_object {
3471 struct mbox_header header;
3475 #define lpfc_wr_object_eof_SHIFT 31
3476 #define lpfc_wr_object_eof_MASK 0x00000001
3477 #define lpfc_wr_object_eof_WORD word4
3478 #define lpfc_wr_object_write_length_SHIFT 0
3479 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3480 #define lpfc_wr_object_write_length_WORD word4
3481 uint32_t write_offset;
3482 uint32_t object_name[26];
3484 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3487 uint32_t actual_write_length;
3492 /* mailbox queue entry structure */
3495 #define lpfc_mqe_status_SHIFT 16
3496 #define lpfc_mqe_status_MASK 0x0000FFFF
3497 #define lpfc_mqe_status_WORD word0
3498 #define lpfc_mqe_command_SHIFT 8
3499 #define lpfc_mqe_command_MASK 0x000000FF
3500 #define lpfc_mqe_command_WORD word0
3502 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3503 /* sli4 mailbox commands */
3504 struct lpfc_mbx_sli4_config sli4_config;
3505 struct lpfc_mbx_init_vfi init_vfi;
3506 struct lpfc_mbx_reg_vfi reg_vfi;
3507 struct lpfc_mbx_reg_vfi unreg_vfi;
3508 struct lpfc_mbx_init_vpi init_vpi;
3509 struct lpfc_mbx_resume_rpi resume_rpi;
3510 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3511 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3512 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3513 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3514 struct lpfc_mbx_reg_fcfi reg_fcfi;
3515 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3516 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3517 struct lpfc_mbx_mq_create mq_create;
3518 struct lpfc_mbx_mq_create_ext mq_create_ext;
3519 struct lpfc_mbx_eq_create eq_create;
3520 struct lpfc_mbx_modify_eq_delay eq_delay;
3521 struct lpfc_mbx_cq_create cq_create;
3522 struct lpfc_mbx_cq_create_set cq_create_set;
3523 struct lpfc_mbx_wq_create wq_create;
3524 struct lpfc_mbx_rq_create rq_create;
3525 struct lpfc_mbx_rq_create_v2 rq_create_v2;
3526 struct lpfc_mbx_mq_destroy mq_destroy;
3527 struct lpfc_mbx_eq_destroy eq_destroy;
3528 struct lpfc_mbx_cq_destroy cq_destroy;
3529 struct lpfc_mbx_wq_destroy wq_destroy;
3530 struct lpfc_mbx_rq_destroy rq_destroy;
3531 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3532 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3533 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3534 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3535 struct lpfc_mbx_nembed_cmd nembed_cmd;
3536 struct lpfc_mbx_read_rev read_rev;
3537 struct lpfc_mbx_read_vpi read_vpi;
3538 struct lpfc_mbx_read_config rd_config;
3539 struct lpfc_mbx_request_features req_ftrs;
3540 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3541 struct lpfc_mbx_query_fw_config query_fw_cfg;
3542 struct lpfc_mbx_set_beacon_config beacon_config;
3543 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3544 struct lpfc_mbx_set_link_diag_state link_diag_state;
3545 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3546 struct lpfc_mbx_run_link_diag_test link_diag_test;
3547 struct lpfc_mbx_get_func_cfg get_func_cfg;
3548 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3549 struct lpfc_mbx_wr_object wr_object;
3550 struct lpfc_mbx_get_port_name get_port_name;
3551 struct lpfc_mbx_set_feature set_feature;
3552 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3553 struct lpfc_mbx_set_host_data set_host_data;
3554 struct lpfc_mbx_nop nop;
3560 #define lpfc_mcqe_status_SHIFT 0
3561 #define lpfc_mcqe_status_MASK 0x0000FFFF
3562 #define lpfc_mcqe_status_WORD word0
3563 #define lpfc_mcqe_ext_status_SHIFT 16
3564 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3565 #define lpfc_mcqe_ext_status_WORD word0
3569 #define lpfc_trailer_valid_SHIFT 31
3570 #define lpfc_trailer_valid_MASK 0x00000001
3571 #define lpfc_trailer_valid_WORD trailer
3572 #define lpfc_trailer_async_SHIFT 30
3573 #define lpfc_trailer_async_MASK 0x00000001
3574 #define lpfc_trailer_async_WORD trailer
3575 #define lpfc_trailer_hpi_SHIFT 29
3576 #define lpfc_trailer_hpi_MASK 0x00000001
3577 #define lpfc_trailer_hpi_WORD trailer
3578 #define lpfc_trailer_completed_SHIFT 28
3579 #define lpfc_trailer_completed_MASK 0x00000001
3580 #define lpfc_trailer_completed_WORD trailer
3581 #define lpfc_trailer_consumed_SHIFT 27
3582 #define lpfc_trailer_consumed_MASK 0x00000001
3583 #define lpfc_trailer_consumed_WORD trailer
3584 #define lpfc_trailer_type_SHIFT 16
3585 #define lpfc_trailer_type_MASK 0x000000FF
3586 #define lpfc_trailer_type_WORD trailer
3587 #define lpfc_trailer_code_SHIFT 8
3588 #define lpfc_trailer_code_MASK 0x000000FF
3589 #define lpfc_trailer_code_WORD trailer
3590 #define LPFC_TRAILER_CODE_LINK 0x1
3591 #define LPFC_TRAILER_CODE_FCOE 0x2
3592 #define LPFC_TRAILER_CODE_DCBX 0x3
3593 #define LPFC_TRAILER_CODE_GRP5 0x5
3594 #define LPFC_TRAILER_CODE_FC 0x10
3595 #define LPFC_TRAILER_CODE_SLI 0x11
3598 struct lpfc_acqe_link {
3600 #define lpfc_acqe_link_speed_SHIFT 24
3601 #define lpfc_acqe_link_speed_MASK 0x000000FF
3602 #define lpfc_acqe_link_speed_WORD word0
3603 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
3604 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
3605 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
3606 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
3607 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
3608 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
3609 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
3610 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
3611 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
3612 #define lpfc_acqe_link_duplex_SHIFT 16
3613 #define lpfc_acqe_link_duplex_MASK 0x000000FF
3614 #define lpfc_acqe_link_duplex_WORD word0
3615 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
3616 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
3617 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
3618 #define lpfc_acqe_link_status_SHIFT 8
3619 #define lpfc_acqe_link_status_MASK 0x000000FF
3620 #define lpfc_acqe_link_status_WORD word0
3621 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3622 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3623 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3624 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3625 #define lpfc_acqe_link_type_SHIFT 6
3626 #define lpfc_acqe_link_type_MASK 0x00000003
3627 #define lpfc_acqe_link_type_WORD word0
3628 #define lpfc_acqe_link_number_SHIFT 0
3629 #define lpfc_acqe_link_number_MASK 0x0000003F
3630 #define lpfc_acqe_link_number_WORD word0
3632 #define lpfc_acqe_link_fault_SHIFT 0
3633 #define lpfc_acqe_link_fault_MASK 0x000000FF
3634 #define lpfc_acqe_link_fault_WORD word1
3635 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3636 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3637 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3638 #define lpfc_acqe_logical_link_speed_SHIFT 16
3639 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3640 #define lpfc_acqe_logical_link_speed_WORD word1
3643 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3644 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3647 struct lpfc_acqe_fip {
3650 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3651 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3652 #define lpfc_acqe_fip_fcf_count_WORD word1
3653 #define lpfc_acqe_fip_event_type_SHIFT 16
3654 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3655 #define lpfc_acqe_fip_event_type_WORD word1
3658 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3659 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3660 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3661 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3662 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3665 struct lpfc_acqe_dcbx {
3672 struct lpfc_acqe_grp5 {
3674 #define lpfc_acqe_grp5_type_SHIFT 6
3675 #define lpfc_acqe_grp5_type_MASK 0x00000003
3676 #define lpfc_acqe_grp5_type_WORD word0
3677 #define lpfc_acqe_grp5_number_SHIFT 0
3678 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3679 #define lpfc_acqe_grp5_number_WORD word0
3681 #define lpfc_acqe_grp5_llink_spd_SHIFT 16
3682 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3683 #define lpfc_acqe_grp5_llink_spd_WORD word1
3688 struct lpfc_acqe_fc_la {
3690 #define lpfc_acqe_fc_la_speed_SHIFT 24
3691 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3692 #define lpfc_acqe_fc_la_speed_WORD word0
3693 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
3694 #define LPFC_FC_LA_SPEED_1G 0x1
3695 #define LPFC_FC_LA_SPEED_2G 0x2
3696 #define LPFC_FC_LA_SPEED_4G 0x4
3697 #define LPFC_FC_LA_SPEED_8G 0x8
3698 #define LPFC_FC_LA_SPEED_10G 0xA
3699 #define LPFC_FC_LA_SPEED_16G 0x10
3700 #define LPFC_FC_LA_SPEED_32G 0x20
3701 #define lpfc_acqe_fc_la_topology_SHIFT 16
3702 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3703 #define lpfc_acqe_fc_la_topology_WORD word0
3704 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3705 #define LPFC_FC_LA_TOP_P2P 0x1
3706 #define LPFC_FC_LA_TOP_FCAL 0x2
3707 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3708 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3709 #define lpfc_acqe_fc_la_att_type_SHIFT 8
3710 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3711 #define lpfc_acqe_fc_la_att_type_WORD word0
3712 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3713 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
3714 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
3715 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
3716 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
3717 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
3718 #define lpfc_acqe_fc_la_port_type_SHIFT 6
3719 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
3720 #define lpfc_acqe_fc_la_port_type_WORD word0
3721 #define LPFC_LINK_TYPE_ETHERNET 0x0
3722 #define LPFC_LINK_TYPE_FC 0x1
3723 #define lpfc_acqe_fc_la_port_number_SHIFT 0
3724 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
3725 #define lpfc_acqe_fc_la_port_number_WORD word0
3727 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16
3728 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
3729 #define lpfc_acqe_fc_la_llink_spd_WORD word1
3730 #define lpfc_acqe_fc_la_fault_SHIFT 0
3731 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
3732 #define lpfc_acqe_fc_la_fault_WORD word1
3733 #define LPFC_FC_LA_FAULT_NONE 0x0
3734 #define LPFC_FC_LA_FAULT_LOCAL 0x1
3735 #define LPFC_FC_LA_FAULT_REMOTE 0x2
3738 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
3739 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
3742 struct lpfc_acqe_misconfigured_event {
3745 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
3746 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
3747 #define lpfc_sli_misconfigured_port0_state_WORD word0
3748 #define lpfc_sli_misconfigured_port1_state_SHIFT 8
3749 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
3750 #define lpfc_sli_misconfigured_port1_state_WORD word0
3751 #define lpfc_sli_misconfigured_port2_state_SHIFT 16
3752 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
3753 #define lpfc_sli_misconfigured_port2_state_WORD word0
3754 #define lpfc_sli_misconfigured_port3_state_SHIFT 24
3755 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
3756 #define lpfc_sli_misconfigured_port3_state_WORD word0
3758 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
3759 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
3760 #define lpfc_sli_misconfigured_port0_op_WORD word1
3761 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1
3762 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
3763 #define lpfc_sli_misconfigured_port0_severity_WORD word1
3764 #define lpfc_sli_misconfigured_port1_op_SHIFT 8
3765 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
3766 #define lpfc_sli_misconfigured_port1_op_WORD word1
3767 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9
3768 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
3769 #define lpfc_sli_misconfigured_port1_severity_WORD word1
3770 #define lpfc_sli_misconfigured_port2_op_SHIFT 16
3771 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
3772 #define lpfc_sli_misconfigured_port2_op_WORD word1
3773 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17
3774 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
3775 #define lpfc_sli_misconfigured_port2_severity_WORD word1
3776 #define lpfc_sli_misconfigured_port3_op_SHIFT 24
3777 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
3778 #define lpfc_sli_misconfigured_port3_op_WORD word1
3779 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25
3780 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
3781 #define lpfc_sli_misconfigured_port3_severity_WORD word1
3783 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
3784 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
3785 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
3786 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
3787 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
3788 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
3791 struct lpfc_acqe_sli {
3792 uint32_t event_data1;
3793 uint32_t event_data2;
3796 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
3797 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
3798 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
3799 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
3800 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
3801 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
3802 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
3806 * Define the bootstrap mailbox (bmbx) region used to communicate
3807 * mailbox command between the host and port. The mailbox consists
3808 * of a payload area of 256 bytes and a completion queue of length
3811 struct lpfc_bmbx_create {
3812 struct lpfc_mqe mqe;
3813 struct lpfc_mcqe mcqe;
3816 #define SGL_ALIGN_SZ 64
3817 #define SGL_PAGE_SIZE 4096
3818 /* align SGL addr on a size boundary - adjust address up */
3819 #define NO_XRI 0xffff
3823 #define wqe_xri_tag_SHIFT 0
3824 #define wqe_xri_tag_MASK 0x0000FFFF
3825 #define wqe_xri_tag_WORD word6
3826 #define wqe_ctxt_tag_SHIFT 16
3827 #define wqe_ctxt_tag_MASK 0x0000FFFF
3828 #define wqe_ctxt_tag_WORD word6
3830 #define wqe_dif_SHIFT 0
3831 #define wqe_dif_MASK 0x00000003
3832 #define wqe_dif_WORD word7
3833 #define LPFC_WQE_DIF_PASSTHRU 1
3834 #define LPFC_WQE_DIF_STRIP 2
3835 #define LPFC_WQE_DIF_INSERT 3
3836 #define wqe_ct_SHIFT 2
3837 #define wqe_ct_MASK 0x00000003
3838 #define wqe_ct_WORD word7
3839 #define wqe_status_SHIFT 4
3840 #define wqe_status_MASK 0x0000000f
3841 #define wqe_status_WORD word7
3842 #define wqe_cmnd_SHIFT 8
3843 #define wqe_cmnd_MASK 0x000000ff
3844 #define wqe_cmnd_WORD word7
3845 #define wqe_class_SHIFT 16
3846 #define wqe_class_MASK 0x00000007
3847 #define wqe_class_WORD word7
3848 #define wqe_ar_SHIFT 19
3849 #define wqe_ar_MASK 0x00000001
3850 #define wqe_ar_WORD word7
3851 #define wqe_ag_SHIFT wqe_ar_SHIFT
3852 #define wqe_ag_MASK wqe_ar_MASK
3853 #define wqe_ag_WORD wqe_ar_WORD
3854 #define wqe_pu_SHIFT 20
3855 #define wqe_pu_MASK 0x00000003
3856 #define wqe_pu_WORD word7
3857 #define wqe_erp_SHIFT 22
3858 #define wqe_erp_MASK 0x00000001
3859 #define wqe_erp_WORD word7
3860 #define wqe_conf_SHIFT wqe_erp_SHIFT
3861 #define wqe_conf_MASK wqe_erp_MASK
3862 #define wqe_conf_WORD wqe_erp_WORD
3863 #define wqe_lnk_SHIFT 23
3864 #define wqe_lnk_MASK 0x00000001
3865 #define wqe_lnk_WORD word7
3866 #define wqe_tmo_SHIFT 24
3867 #define wqe_tmo_MASK 0x000000ff
3868 #define wqe_tmo_WORD word7
3869 uint32_t abort_tag; /* word 8 in WQE */
3871 #define wqe_reqtag_SHIFT 0
3872 #define wqe_reqtag_MASK 0x0000FFFF
3873 #define wqe_reqtag_WORD word9
3874 #define wqe_temp_rpi_SHIFT 16
3875 #define wqe_temp_rpi_MASK 0x0000FFFF
3876 #define wqe_temp_rpi_WORD word9
3877 #define wqe_rcvoxid_SHIFT 16
3878 #define wqe_rcvoxid_MASK 0x0000FFFF
3879 #define wqe_rcvoxid_WORD word9
3881 #define wqe_ebde_cnt_SHIFT 0
3882 #define wqe_ebde_cnt_MASK 0x0000000f
3883 #define wqe_ebde_cnt_WORD word10
3884 #define wqe_nvme_SHIFT 4
3885 #define wqe_nvme_MASK 0x00000001
3886 #define wqe_nvme_WORD word10
3887 #define wqe_oas_SHIFT 6
3888 #define wqe_oas_MASK 0x00000001
3889 #define wqe_oas_WORD word10
3890 #define wqe_lenloc_SHIFT 7
3891 #define wqe_lenloc_MASK 0x00000003
3892 #define wqe_lenloc_WORD word10
3893 #define LPFC_WQE_LENLOC_NONE 0
3894 #define LPFC_WQE_LENLOC_WORD3 1
3895 #define LPFC_WQE_LENLOC_WORD12 2
3896 #define LPFC_WQE_LENLOC_WORD4 3
3897 #define wqe_qosd_SHIFT 9
3898 #define wqe_qosd_MASK 0x00000001
3899 #define wqe_qosd_WORD word10
3900 #define wqe_xbl_SHIFT 11
3901 #define wqe_xbl_MASK 0x00000001
3902 #define wqe_xbl_WORD word10
3903 #define wqe_iod_SHIFT 13
3904 #define wqe_iod_MASK 0x00000001
3905 #define wqe_iod_WORD word10
3906 #define LPFC_WQE_IOD_WRITE 0
3907 #define LPFC_WQE_IOD_READ 1
3908 #define wqe_dbde_SHIFT 14
3909 #define wqe_dbde_MASK 0x00000001
3910 #define wqe_dbde_WORD word10
3911 #define wqe_wqes_SHIFT 15
3912 #define wqe_wqes_MASK 0x00000001
3913 #define wqe_wqes_WORD word10
3914 /* Note that this field overlaps above fields */
3915 #define wqe_wqid_SHIFT 1
3916 #define wqe_wqid_MASK 0x00007fff
3917 #define wqe_wqid_WORD word10
3918 #define wqe_pri_SHIFT 16
3919 #define wqe_pri_MASK 0x00000007
3920 #define wqe_pri_WORD word10
3921 #define wqe_pv_SHIFT 19
3922 #define wqe_pv_MASK 0x00000001
3923 #define wqe_pv_WORD word10
3924 #define wqe_xc_SHIFT 21
3925 #define wqe_xc_MASK 0x00000001
3926 #define wqe_xc_WORD word10
3927 #define wqe_sr_SHIFT 22
3928 #define wqe_sr_MASK 0x00000001
3929 #define wqe_sr_WORD word10
3930 #define wqe_ccpe_SHIFT 23
3931 #define wqe_ccpe_MASK 0x00000001
3932 #define wqe_ccpe_WORD word10
3933 #define wqe_ccp_SHIFT 24
3934 #define wqe_ccp_MASK 0x000000ff
3935 #define wqe_ccp_WORD word10
3937 #define wqe_cmd_type_SHIFT 0
3938 #define wqe_cmd_type_MASK 0x0000000f
3939 #define wqe_cmd_type_WORD word11
3940 #define wqe_els_id_SHIFT 4
3941 #define wqe_els_id_MASK 0x00000003
3942 #define wqe_els_id_WORD word11
3943 #define LPFC_ELS_ID_FLOGI 3
3944 #define LPFC_ELS_ID_FDISC 2
3945 #define LPFC_ELS_ID_LOGO 1
3946 #define LPFC_ELS_ID_DEFAULT 0
3947 #define wqe_irsp_SHIFT 4
3948 #define wqe_irsp_MASK 0x00000001
3949 #define wqe_irsp_WORD word11
3950 #define wqe_sup_SHIFT 6
3951 #define wqe_sup_MASK 0x00000001
3952 #define wqe_sup_WORD word11
3953 #define wqe_wqec_SHIFT 7
3954 #define wqe_wqec_MASK 0x00000001
3955 #define wqe_wqec_WORD word11
3956 #define wqe_irsplen_SHIFT 8
3957 #define wqe_irsplen_MASK 0x0000000f
3958 #define wqe_irsplen_WORD word11
3959 #define wqe_cqid_SHIFT 16
3960 #define wqe_cqid_MASK 0x0000ffff
3961 #define wqe_cqid_WORD word11
3962 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
3967 #define wqe_els_did_SHIFT 0
3968 #define wqe_els_did_MASK 0x00FFFFFF
3969 #define wqe_els_did_WORD word5
3970 #define wqe_xmit_bls_pt_SHIFT 28
3971 #define wqe_xmit_bls_pt_MASK 0x00000003
3972 #define wqe_xmit_bls_pt_WORD word5
3973 #define wqe_xmit_bls_ar_SHIFT 30
3974 #define wqe_xmit_bls_ar_MASK 0x00000001
3975 #define wqe_xmit_bls_ar_WORD word5
3976 #define wqe_xmit_bls_xo_SHIFT 31
3977 #define wqe_xmit_bls_xo_MASK 0x00000001
3978 #define wqe_xmit_bls_xo_WORD word5
3981 struct lpfc_wqe_generic{
3982 struct ulp_bde64 bde;
3986 struct wqe_common wqe_com;
3987 uint32_t payload[4];
3990 struct els_request64_wqe {
3991 struct ulp_bde64 bde;
3992 uint32_t payload_len;
3994 #define els_req64_sid_SHIFT 0
3995 #define els_req64_sid_MASK 0x00FFFFFF
3996 #define els_req64_sid_WORD word4
3997 #define els_req64_sp_SHIFT 24
3998 #define els_req64_sp_MASK 0x00000001
3999 #define els_req64_sp_WORD word4
4000 #define els_req64_vf_SHIFT 25
4001 #define els_req64_vf_MASK 0x00000001
4002 #define els_req64_vf_WORD word4
4003 struct wqe_did wqe_dest;
4004 struct wqe_common wqe_com; /* words 6-11 */
4006 #define els_req64_vfid_SHIFT 1
4007 #define els_req64_vfid_MASK 0x00000FFF
4008 #define els_req64_vfid_WORD word12
4009 #define els_req64_pri_SHIFT 13
4010 #define els_req64_pri_MASK 0x00000007
4011 #define els_req64_pri_WORD word12
4013 #define els_req64_hopcnt_SHIFT 24
4014 #define els_req64_hopcnt_MASK 0x000000ff
4015 #define els_req64_hopcnt_WORD word13
4017 uint32_t max_response_payload_len;
4020 struct xmit_els_rsp64_wqe {
4021 struct ulp_bde64 bde;
4022 uint32_t response_payload_len;
4024 #define els_rsp64_sid_SHIFT 0
4025 #define els_rsp64_sid_MASK 0x00FFFFFF
4026 #define els_rsp64_sid_WORD word4
4027 #define els_rsp64_sp_SHIFT 24
4028 #define els_rsp64_sp_MASK 0x00000001
4029 #define els_rsp64_sp_WORD word4
4030 struct wqe_did wqe_dest;
4031 struct wqe_common wqe_com; /* words 6-11 */
4033 #define wqe_rsp_temp_rpi_SHIFT 0
4034 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4035 #define wqe_rsp_temp_rpi_WORD word12
4036 uint32_t rsvd_13_15[3];
4039 struct xmit_bls_rsp64_wqe {
4041 /* Payload0 for BA_ACC */
4042 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
4043 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4044 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
4045 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
4046 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4047 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
4048 /* Payload0 for BA_RJT */
4049 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4050 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4051 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
4052 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
4053 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4054 #define xmit_bls_rsp64_rjt_expc_WORD payload0
4055 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
4056 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4057 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
4059 #define xmit_bls_rsp64_rxid_SHIFT 0
4060 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4061 #define xmit_bls_rsp64_rxid_WORD word1
4062 #define xmit_bls_rsp64_oxid_SHIFT 16
4063 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4064 #define xmit_bls_rsp64_oxid_WORD word1
4066 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4067 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4068 #define xmit_bls_rsp64_seqcnthi_WORD word2
4069 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
4070 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4071 #define xmit_bls_rsp64_seqcntlo_WORD word2
4074 struct wqe_did wqe_dest;
4075 struct wqe_common wqe_com; /* words 6-11 */
4077 #define xmit_bls_rsp64_temprpi_SHIFT 0
4078 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4079 #define xmit_bls_rsp64_temprpi_WORD word12
4080 uint32_t rsvd_13_15[3];
4083 struct wqe_rctl_dfctl {
4085 #define wqe_si_SHIFT 2
4086 #define wqe_si_MASK 0x000000001
4087 #define wqe_si_WORD word5
4088 #define wqe_la_SHIFT 3
4089 #define wqe_la_MASK 0x000000001
4090 #define wqe_la_WORD word5
4091 #define wqe_xo_SHIFT 6
4092 #define wqe_xo_MASK 0x000000001
4093 #define wqe_xo_WORD word5
4094 #define wqe_ls_SHIFT 7
4095 #define wqe_ls_MASK 0x000000001
4096 #define wqe_ls_WORD word5
4097 #define wqe_dfctl_SHIFT 8
4098 #define wqe_dfctl_MASK 0x0000000ff
4099 #define wqe_dfctl_WORD word5
4100 #define wqe_type_SHIFT 16
4101 #define wqe_type_MASK 0x0000000ff
4102 #define wqe_type_WORD word5
4103 #define wqe_rctl_SHIFT 24
4104 #define wqe_rctl_MASK 0x0000000ff
4105 #define wqe_rctl_WORD word5
4108 struct xmit_seq64_wqe {
4109 struct ulp_bde64 bde;
4111 uint32_t relative_offset;
4112 struct wqe_rctl_dfctl wge_ctl;
4113 struct wqe_common wqe_com; /* words 6-11 */
4115 uint32_t rsvd_12_15[3];
4117 struct xmit_bcast64_wqe {
4118 struct ulp_bde64 bde;
4119 uint32_t seq_payload_len;
4121 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4122 struct wqe_common wqe_com; /* words 6-11 */
4123 uint32_t rsvd_12_15[4];
4126 struct gen_req64_wqe {
4127 struct ulp_bde64 bde;
4128 uint32_t request_payload_len;
4129 uint32_t relative_offset;
4130 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4131 struct wqe_common wqe_com; /* words 6-11 */
4132 uint32_t rsvd_12_14[3];
4133 uint32_t max_response_payload_len;
4136 /* Define NVME PRLI request to fabric. NVME is a
4137 * fabric-only protocol.
4138 * Updated to red-lined v1.08 on Sept 16, 2016
4140 struct lpfc_nvme_prli {
4142 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4143 #define prli_acc_rsp_code_SHIFT 8
4144 #define prli_acc_rsp_code_MASK 0x0000000f
4145 #define prli_acc_rsp_code_WORD word1
4146 #define prli_estabImagePair_SHIFT 13
4147 #define prli_estabImagePair_MASK 0x00000001
4148 #define prli_estabImagePair_WORD word1
4149 #define prli_type_code_ext_SHIFT 16
4150 #define prli_type_code_ext_MASK 0x000000ff
4151 #define prli_type_code_ext_WORD word1
4152 #define prli_type_code_SHIFT 24
4153 #define prli_type_code_MASK 0x000000ff
4154 #define prli_type_code_WORD word1
4155 uint32_t word_rsvd2;
4156 uint32_t word_rsvd3;
4158 #define prli_fba_SHIFT 0
4159 #define prli_fba_MASK 0x00000001
4160 #define prli_fba_WORD word4
4161 #define prli_disc_SHIFT 3
4162 #define prli_disc_MASK 0x00000001
4163 #define prli_disc_WORD word4
4164 #define prli_tgt_SHIFT 4
4165 #define prli_tgt_MASK 0x00000001
4166 #define prli_tgt_WORD word4
4167 #define prli_init_SHIFT 5
4168 #define prli_init_MASK 0x00000001
4169 #define prli_init_WORD word4
4170 #define prli_recov_SHIFT 8
4171 #define prli_recov_MASK 0x00000001
4172 #define prli_recov_WORD word4
4174 #define prli_fb_sz_SHIFT 0
4175 #define prli_fb_sz_MASK 0x0000ffff
4176 #define prli_fb_sz_WORD word5
4177 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */
4180 struct create_xri_wqe {
4181 uint32_t rsrvd[5]; /* words 0-4 */
4182 struct wqe_did wqe_dest; /* word 5 */
4183 struct wqe_common wqe_com; /* words 6-11 */
4184 uint32_t rsvd_12_15[4]; /* word 12-15 */
4187 #define T_REQUEST_TAG 3
4190 struct abort_cmd_wqe {
4193 #define abort_cmd_ia_SHIFT 0
4194 #define abort_cmd_ia_MASK 0x000000001
4195 #define abort_cmd_ia_WORD word3
4196 #define abort_cmd_criteria_SHIFT 8
4197 #define abort_cmd_criteria_MASK 0x0000000ff
4198 #define abort_cmd_criteria_WORD word3
4201 struct wqe_common wqe_com; /* words 6-11 */
4202 uint32_t rsvd_12_15[4]; /* word 12-15 */
4205 struct fcp_iwrite64_wqe {
4206 struct ulp_bde64 bde;
4208 #define cmd_buff_len_SHIFT 16
4209 #define cmd_buff_len_MASK 0x00000ffff
4210 #define cmd_buff_len_WORD word3
4211 #define payload_offset_len_SHIFT 0
4212 #define payload_offset_len_MASK 0x0000ffff
4213 #define payload_offset_len_WORD word3
4214 uint32_t total_xfer_len;
4215 uint32_t initial_xfer_len;
4216 struct wqe_common wqe_com; /* words 6-11 */
4218 struct ulp_bde64 ph_bde; /* words 13-15 */
4221 struct fcp_iread64_wqe {
4222 struct ulp_bde64 bde;
4224 #define cmd_buff_len_SHIFT 16
4225 #define cmd_buff_len_MASK 0x00000ffff
4226 #define cmd_buff_len_WORD word3
4227 #define payload_offset_len_SHIFT 0
4228 #define payload_offset_len_MASK 0x0000ffff
4229 #define payload_offset_len_WORD word3
4230 uint32_t total_xfer_len; /* word 4 */
4231 uint32_t rsrvd5; /* word 5 */
4232 struct wqe_common wqe_com; /* words 6-11 */
4234 struct ulp_bde64 ph_bde; /* words 13-15 */
4237 struct fcp_icmnd64_wqe {
4238 struct ulp_bde64 bde; /* words 0-2 */
4240 #define cmd_buff_len_SHIFT 16
4241 #define cmd_buff_len_MASK 0x00000ffff
4242 #define cmd_buff_len_WORD word3
4243 #define payload_offset_len_SHIFT 0
4244 #define payload_offset_len_MASK 0x0000ffff
4245 #define payload_offset_len_WORD word3
4246 uint32_t rsrvd4; /* word 4 */
4247 uint32_t rsrvd5; /* word 5 */
4248 struct wqe_common wqe_com; /* words 6-11 */
4249 uint32_t rsvd_12_15[4]; /* word 12-15 */
4252 struct fcp_trsp64_wqe {
4253 struct ulp_bde64 bde;
4254 uint32_t response_len;
4255 uint32_t rsvd_4_5[2];
4256 struct wqe_common wqe_com; /* words 6-11 */
4257 uint32_t rsvd_12_15[4]; /* word 12-15 */
4260 struct fcp_tsend64_wqe {
4261 struct ulp_bde64 bde;
4262 uint32_t payload_offset_len;
4263 uint32_t relative_offset;
4265 struct wqe_common wqe_com; /* words 6-11 */
4266 uint32_t fcp_data_len; /* word 12 */
4267 uint32_t rsvd_13_15[3]; /* word 13-15 */
4270 struct fcp_treceive64_wqe {
4271 struct ulp_bde64 bde;
4272 uint32_t payload_offset_len;
4273 uint32_t relative_offset;
4275 struct wqe_common wqe_com; /* words 6-11 */
4276 uint32_t fcp_data_len; /* word 12 */
4277 uint32_t rsvd_13_15[3]; /* word 13-15 */
4279 #define TXRDY_PAYLOAD_LEN 12
4281 #define CMD_SEND_FRAME 0xE1
4283 struct send_frame_wqe {
4284 struct ulp_bde64 bde; /* words 0-2 */
4285 uint32_t frame_len; /* word 3 */
4286 uint32_t fc_hdr_wd0; /* word 4 */
4287 uint32_t fc_hdr_wd1; /* word 5 */
4288 struct wqe_common wqe_com; /* words 6-11 */
4289 uint32_t fc_hdr_wd2; /* word 12 */
4290 uint32_t fc_hdr_wd3; /* word 13 */
4291 uint32_t fc_hdr_wd4; /* word 14 */
4292 uint32_t fc_hdr_wd5; /* word 15 */
4297 struct lpfc_wqe_generic generic;
4298 struct fcp_icmnd64_wqe fcp_icmd;
4299 struct fcp_iread64_wqe fcp_iread;
4300 struct fcp_iwrite64_wqe fcp_iwrite;
4301 struct abort_cmd_wqe abort_cmd;
4302 struct create_xri_wqe create_xri;
4303 struct xmit_bcast64_wqe xmit_bcast64;
4304 struct xmit_seq64_wqe xmit_sequence;
4305 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4306 struct xmit_els_rsp64_wqe xmit_els_rsp;
4307 struct els_request64_wqe els_req;
4308 struct gen_req64_wqe gen_req;
4309 struct fcp_trsp64_wqe fcp_trsp;
4310 struct fcp_tsend64_wqe fcp_tsend;
4311 struct fcp_treceive64_wqe fcp_treceive;
4312 struct send_frame_wqe send_frame;
4317 struct lpfc_wqe_generic generic;
4318 struct fcp_icmnd64_wqe fcp_icmd;
4319 struct fcp_iread64_wqe fcp_iread;
4320 struct fcp_iwrite64_wqe fcp_iwrite;
4321 struct fcp_trsp64_wqe fcp_trsp;
4322 struct fcp_tsend64_wqe fcp_tsend;
4323 struct fcp_treceive64_wqe fcp_treceive;
4324 struct xmit_seq64_wqe xmit_sequence;
4325 struct gen_req64_wqe gen_req;
4328 #define LPFC_GROUP_OJECT_MAGIC_G5 0xfeaa0001
4329 #define LPFC_GROUP_OJECT_MAGIC_G6 0xfeaa0003
4330 #define LPFC_FILE_TYPE_GROUP 0xf7
4331 #define LPFC_FILE_ID_GROUP 0xa2
4332 struct lpfc_grp_hdr {
4334 uint32_t magic_number;
4336 #define lpfc_grp_hdr_file_type_SHIFT 24
4337 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4338 #define lpfc_grp_hdr_file_type_WORD word2
4339 #define lpfc_grp_hdr_id_SHIFT 16
4340 #define lpfc_grp_hdr_id_MASK 0x000000FF
4341 #define lpfc_grp_hdr_id_WORD word2
4342 uint8_t rev_name[128];
4344 uint8_t revision[32];
4347 /* Defines for WQE command type */
4348 #define FCP_COMMAND 0x0
4349 #define NVME_READ_CMD 0x0
4350 #define FCP_COMMAND_DATA_OUT 0x1
4351 #define NVME_WRITE_CMD 0x1
4352 #define FCP_COMMAND_TRECEIVE 0x2
4353 #define FCP_COMMAND_TRSP 0x3
4354 #define FCP_COMMAND_TSEND 0x7
4355 #define OTHER_COMMAND 0x8
4356 #define ELS_COMMAND_NON_FIP 0xC
4357 #define ELS_COMMAND_FIP 0xD
4359 #define LPFC_NVME_EMBED_CMD 0x0
4360 #define LPFC_NVME_EMBED_WRITE 0x1
4361 #define LPFC_NVME_EMBED_READ 0x2
4364 #define CMD_ABORT_XRI_WQE 0x0F
4365 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4366 #define CMD_XMIT_BCAST64_WQE 0x84
4367 #define CMD_ELS_REQUEST64_WQE 0x8A
4368 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4369 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4370 #define CMD_FCP_IWRITE64_WQE 0x98
4371 #define CMD_FCP_IREAD64_WQE 0x9A
4372 #define CMD_FCP_ICMND64_WQE 0x9C
4373 #define CMD_FCP_TSEND64_WQE 0x9F
4374 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4375 #define CMD_FCP_TRSP64_WQE 0xA3
4376 #define CMD_GEN_REQUEST64_WQE 0xC2
4378 #define CMD_WQE_MASK 0xff
4381 #define LPFC_FW_DUMP 1
4382 #define LPFC_FW_RESET 2
4383 #define LPFC_DV_RESET 3