1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
23 /* Macros to deal with bit fields. Each bit field must have 3 #defines
24 * associated with it (_SHIFT, _MASK, and _WORD).
25 * EG. For a bit field that is in the 7th bit of the "field4" field of a
26 * structure and is 2 bits in size the following #defines must exist:
32 * #define example_bit_field_SHIFT 7
33 * #define example_bit_field_MASK 0x03
34 * #define example_bit_field_WORD field4
37 * Then the macros below may be used to get or set the value of that field.
38 * EG. To get the value of the bit field from the above example:
40 * value = bf_get(example_bit_field, &t1);
41 * And then to set that bit field:
42 * bf_set(example_bit_field, &t1, 2);
43 * Or clear that bit field:
44 * bf_set(example_bit_field, &t1, 0);
46 #define bf_get_be32(name, ptr) \
47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48 #define bf_get_le32(name, ptr) \
49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
50 #define bf_get(name, ptr) \
51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
52 #define bf_set_le32(name, ptr, value) \
53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
55 ~(name##_MASK << name##_SHIFT)))))
56 #define bf_set(name, ptr, value) \
57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
65 struct lpfc_sli_intf {
67 #define lpfc_sli_intf_valid_SHIFT 29
68 #define lpfc_sli_intf_valid_MASK 0x00000007
69 #define lpfc_sli_intf_valid_WORD word0
70 #define LPFC_SLI_INTF_VALID 6
71 #define lpfc_sli_intf_sli_hint2_SHIFT 24
72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
73 #define lpfc_sli_intf_sli_hint2_WORD word0
74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
75 #define lpfc_sli_intf_sli_hint1_SHIFT 16
76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
77 #define lpfc_sli_intf_sli_hint1_WORD word0
78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
79 #define LPFC_SLI_INTF_SLI_HINT1_1 1
80 #define LPFC_SLI_INTF_SLI_HINT1_2 2
81 #define lpfc_sli_intf_if_type_SHIFT 12
82 #define lpfc_sli_intf_if_type_MASK 0x0000000F
83 #define lpfc_sli_intf_if_type_WORD word0
84 #define LPFC_SLI_INTF_IF_TYPE_0 0
85 #define LPFC_SLI_INTF_IF_TYPE_1 1
86 #define LPFC_SLI_INTF_IF_TYPE_2 2
87 #define LPFC_SLI_INTF_IF_TYPE_6 6
88 #define lpfc_sli_intf_sli_family_SHIFT 8
89 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
90 #define lpfc_sli_intf_sli_family_WORD word0
91 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
92 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
95 #define lpfc_sli_intf_slirev_SHIFT 4
96 #define lpfc_sli_intf_slirev_MASK 0x0000000F
97 #define lpfc_sli_intf_slirev_WORD word0
98 #define LPFC_SLI_INTF_REV_SLI3 3
99 #define LPFC_SLI_INTF_REV_SLI4 4
100 #define lpfc_sli_intf_func_type_SHIFT 0
101 #define lpfc_sli_intf_func_type_MASK 0x00000001
102 #define lpfc_sli_intf_func_type_WORD word0
103 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
104 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1
107 #define LPFC_SLI4_MBX_EMBED true
108 #define LPFC_SLI4_MBX_NEMBED false
110 #define LPFC_SLI4_MB_WORD_COUNT 64
111 #define LPFC_MAX_MQ_PAGE 8
112 #define LPFC_MAX_WQ_PAGE_V0 4
113 #define LPFC_MAX_WQ_PAGE 8
114 #define LPFC_MAX_RQ_PAGE 8
115 #define LPFC_MAX_CQ_PAGE 4
116 #define LPFC_MAX_EQ_PAGE 8
118 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
119 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
120 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
122 /* Define SLI4 Alignment requirements. */
123 #define LPFC_ALIGN_16_BYTE 16
124 #define LPFC_ALIGN_64_BYTE 64
125 #define SLI4_PAGE_SIZE 4096
127 /* Define SLI4 specific definitions. */
128 #define LPFC_MQ_CQE_BYTE_OFFSET 256
129 #define LPFC_MBX_CMD_HDR_LENGTH 16
130 #define LPFC_MBX_ERROR_RANGE 0x4000
131 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
132 #define LPFC_BMBX_BIT1_ADDR_LO 0
133 #define LPFC_RPI_HDR_COUNT 64
134 #define LPFC_HDR_TEMPLATE_SIZE 4096
135 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
136 #define LPFC_FCF_RECORD_WD_CNT 132
137 #define LPFC_ENTIRE_FCF_DATABASE 0
138 #define LPFC_DFLT_FCF_INDEX 0
140 /* Virtual function numbers */
174 /* PCI function numbers */
175 #define LPFC_PCI_FUNC0 0
176 #define LPFC_PCI_FUNC1 1
177 #define LPFC_PCI_FUNC2 2
178 #define LPFC_PCI_FUNC3 3
179 #define LPFC_PCI_FUNC4 4
181 /* SLI4 interface type-2 PDEV_CTL register */
182 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
183 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
184 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
185 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
186 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
187 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
188 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
189 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
191 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
193 /* Active interrupt test count */
194 #define LPFC_ACT_INTR_CNT 4
196 /* Algrithmns for scheduling FCP commands to WQs */
197 #define LPFC_FCP_SCHED_ROUND_ROBIN 0
198 #define LPFC_FCP_SCHED_BY_CPU 1
200 /* Delay Multiplier constant */
201 #define LPFC_DMULT_CONST 651042
202 #define LPFC_DMULT_MAX 1023
204 /* Configuration of Interrupts / sec for entire HBA port */
205 #define LPFC_MIN_IMAX 5000
206 #define LPFC_MAX_IMAX 5000000
207 #define LPFC_DEF_IMAX 150000
209 #define LPFC_MIN_CPU_MAP 0
210 #define LPFC_MAX_CPU_MAP 2
211 #define LPFC_HBA_CPU_MAP 1
212 #define LPFC_DRIVER_CPU_MAP 2 /* Default */
214 /* PORT_CAPABILITIES constants. */
215 #define LPFC_MAX_SUPPORTED_PAGES 8
221 #ifdef __BIG_ENDIAN_BITFIELD
222 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
224 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
225 #else /* __LITTLE_ENDIAN_BITFIELD */
226 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
227 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
230 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
231 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
232 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
233 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
234 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
235 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
236 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
243 /* Maximun size of immediate data that can fit into a 128 byte WQE */
244 #define LPFC_MAX_BDE_IMM_SIZE 64
246 struct lpfc_sli4_flags {
248 #define lpfc_idx_rsrc_rdy_SHIFT 0
249 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
250 #define lpfc_idx_rsrc_rdy_WORD word0
251 #define LPFC_IDX_RSRC_RDY 1
252 #define lpfc_rpi_rsrc_rdy_SHIFT 1
253 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
254 #define lpfc_rpi_rsrc_rdy_WORD word0
255 #define LPFC_RPI_RSRC_RDY 1
256 #define lpfc_vpi_rsrc_rdy_SHIFT 2
257 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
258 #define lpfc_vpi_rsrc_rdy_WORD word0
259 #define LPFC_VPI_RSRC_RDY 1
260 #define lpfc_vfi_rsrc_rdy_SHIFT 3
261 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
262 #define lpfc_vfi_rsrc_rdy_WORD word0
263 #define LPFC_VFI_RSRC_RDY 1
266 struct sli4_bls_rsp {
267 uint32_t word0_rsvd; /* Word0 must be reserved */
269 #define lpfc_abts_orig_SHIFT 0
270 #define lpfc_abts_orig_MASK 0x00000001
271 #define lpfc_abts_orig_WORD word1
272 #define LPFC_ABTS_UNSOL_RSP 1
273 #define LPFC_ABTS_UNSOL_INT 0
275 #define lpfc_abts_rxid_SHIFT 0
276 #define lpfc_abts_rxid_MASK 0x0000FFFF
277 #define lpfc_abts_rxid_WORD word2
278 #define lpfc_abts_oxid_SHIFT 16
279 #define lpfc_abts_oxid_MASK 0x0000FFFF
280 #define lpfc_abts_oxid_WORD word2
282 #define lpfc_vndr_code_SHIFT 0
283 #define lpfc_vndr_code_MASK 0x000000FF
284 #define lpfc_vndr_code_WORD word3
285 #define lpfc_rsn_expln_SHIFT 8
286 #define lpfc_rsn_expln_MASK 0x000000FF
287 #define lpfc_rsn_expln_WORD word3
288 #define lpfc_rsn_code_SHIFT 16
289 #define lpfc_rsn_code_MASK 0x000000FF
290 #define lpfc_rsn_code_WORD word3
293 uint32_t word5_rsvd; /* Word5 must be reserved */
296 /* event queue entry structure */
299 #define lpfc_eqe_resource_id_SHIFT 16
300 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
301 #define lpfc_eqe_resource_id_WORD word0
302 #define lpfc_eqe_minor_code_SHIFT 4
303 #define lpfc_eqe_minor_code_MASK 0x00000FFF
304 #define lpfc_eqe_minor_code_WORD word0
305 #define lpfc_eqe_major_code_SHIFT 1
306 #define lpfc_eqe_major_code_MASK 0x00000007
307 #define lpfc_eqe_major_code_WORD word0
308 #define lpfc_eqe_valid_SHIFT 0
309 #define lpfc_eqe_valid_MASK 0x00000001
310 #define lpfc_eqe_valid_WORD word0
313 /* completion queue entry structure (common fields for all cqe types) */
319 #define lpfc_cqe_valid_SHIFT 31
320 #define lpfc_cqe_valid_MASK 0x00000001
321 #define lpfc_cqe_valid_WORD word3
322 #define lpfc_cqe_code_SHIFT 16
323 #define lpfc_cqe_code_MASK 0x000000FF
324 #define lpfc_cqe_code_WORD word3
327 /* Completion Queue Entry Status Codes */
328 #define CQE_STATUS_SUCCESS 0x0
329 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
330 #define CQE_STATUS_REMOTE_STOP 0x2
331 #define CQE_STATUS_LOCAL_REJECT 0x3
332 #define CQE_STATUS_NPORT_RJT 0x4
333 #define CQE_STATUS_FABRIC_RJT 0x5
334 #define CQE_STATUS_NPORT_BSY 0x6
335 #define CQE_STATUS_FABRIC_BSY 0x7
336 #define CQE_STATUS_INTERMED_RSP 0x8
337 #define CQE_STATUS_LS_RJT 0x9
338 #define CQE_STATUS_CMD_REJECT 0xb
339 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
340 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
341 #define CQE_STATUS_DI_ERROR 0x16
343 /* Used when mapping CQE status to IOCB */
344 #define LPFC_IOCB_STATUS_MASK 0xf
346 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
347 #define CQE_HW_STATUS_NO_ERR 0x0
348 #define CQE_HW_STATUS_UNDERRUN 0x1
349 #define CQE_HW_STATUS_OVERRUN 0x2
351 /* Completion Queue Entry Codes */
352 #define CQE_CODE_COMPL_WQE 0x1
353 #define CQE_CODE_RELEASE_WQE 0x2
354 #define CQE_CODE_RECEIVE 0x4
355 #define CQE_CODE_XRI_ABORTED 0x5
356 #define CQE_CODE_RECEIVE_V1 0x9
357 #define CQE_CODE_NVME_ERSP 0xd
360 * Define mask value for xri_aborted and wcqe completed CQE extended status.
361 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
363 #define WCQE_PARAM_MASK 0x1FF
365 /* completion queue entry for wqe completions */
366 struct lpfc_wcqe_complete {
368 #define lpfc_wcqe_c_request_tag_SHIFT 16
369 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
370 #define lpfc_wcqe_c_request_tag_WORD word0
371 #define lpfc_wcqe_c_status_SHIFT 8
372 #define lpfc_wcqe_c_status_MASK 0x000000FF
373 #define lpfc_wcqe_c_status_WORD word0
374 #define lpfc_wcqe_c_hw_status_SHIFT 0
375 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
376 #define lpfc_wcqe_c_hw_status_WORD word0
377 #define lpfc_wcqe_c_ersp0_SHIFT 0
378 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
379 #define lpfc_wcqe_c_ersp0_WORD word0
380 uint32_t total_data_placed;
382 #define lpfc_wcqe_c_bg_edir_SHIFT 5
383 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
384 #define lpfc_wcqe_c_bg_edir_WORD parameter
385 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3
386 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
387 #define lpfc_wcqe_c_bg_tdpv_WORD parameter
388 #define lpfc_wcqe_c_bg_re_SHIFT 2
389 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
390 #define lpfc_wcqe_c_bg_re_WORD parameter
391 #define lpfc_wcqe_c_bg_ae_SHIFT 1
392 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
393 #define lpfc_wcqe_c_bg_ae_WORD parameter
394 #define lpfc_wcqe_c_bg_ge_SHIFT 0
395 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
396 #define lpfc_wcqe_c_bg_ge_WORD parameter
398 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
399 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
400 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
401 #define lpfc_wcqe_c_xb_SHIFT 28
402 #define lpfc_wcqe_c_xb_MASK 0x00000001
403 #define lpfc_wcqe_c_xb_WORD word3
404 #define lpfc_wcqe_c_pv_SHIFT 27
405 #define lpfc_wcqe_c_pv_MASK 0x00000001
406 #define lpfc_wcqe_c_pv_WORD word3
407 #define lpfc_wcqe_c_priority_SHIFT 24
408 #define lpfc_wcqe_c_priority_MASK 0x00000007
409 #define lpfc_wcqe_c_priority_WORD word3
410 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
411 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
412 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
413 #define lpfc_wcqe_c_sqhead_SHIFT 0
414 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
415 #define lpfc_wcqe_c_sqhead_WORD word3
418 /* completion queue entry for wqe release */
419 struct lpfc_wcqe_release {
423 #define lpfc_wcqe_r_wq_id_SHIFT 16
424 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
425 #define lpfc_wcqe_r_wq_id_WORD word2
426 #define lpfc_wcqe_r_wqe_index_SHIFT 0
427 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
428 #define lpfc_wcqe_r_wqe_index_WORD word2
430 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
431 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
432 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
433 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
434 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
435 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
438 struct sli4_wcqe_xri_aborted {
440 #define lpfc_wcqe_xa_status_SHIFT 8
441 #define lpfc_wcqe_xa_status_MASK 0x000000FF
442 #define lpfc_wcqe_xa_status_WORD word0
445 #define lpfc_wcqe_xa_remote_xid_SHIFT 16
446 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
447 #define lpfc_wcqe_xa_remote_xid_WORD word2
448 #define lpfc_wcqe_xa_xri_SHIFT 0
449 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
450 #define lpfc_wcqe_xa_xri_WORD word2
452 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
453 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
454 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
455 #define lpfc_wcqe_xa_ia_SHIFT 30
456 #define lpfc_wcqe_xa_ia_MASK 0x00000001
457 #define lpfc_wcqe_xa_ia_WORD word3
458 #define CQE_XRI_ABORTED_IA_REMOTE 0
459 #define CQE_XRI_ABORTED_IA_LOCAL 1
460 #define lpfc_wcqe_xa_br_SHIFT 29
461 #define lpfc_wcqe_xa_br_MASK 0x00000001
462 #define lpfc_wcqe_xa_br_WORD word3
463 #define CQE_XRI_ABORTED_BR_BA_ACC 0
464 #define CQE_XRI_ABORTED_BR_BA_RJT 1
465 #define lpfc_wcqe_xa_eo_SHIFT 28
466 #define lpfc_wcqe_xa_eo_MASK 0x00000001
467 #define lpfc_wcqe_xa_eo_WORD word3
468 #define CQE_XRI_ABORTED_EO_REMOTE 0
469 #define CQE_XRI_ABORTED_EO_LOCAL 1
470 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
471 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
472 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
475 /* completion queue entry structure for rqe completion */
478 #define lpfc_rcqe_bindex_SHIFT 16
479 #define lpfc_rcqe_bindex_MASK 0x0000FFF
480 #define lpfc_rcqe_bindex_WORD word0
481 #define lpfc_rcqe_status_SHIFT 8
482 #define lpfc_rcqe_status_MASK 0x000000FF
483 #define lpfc_rcqe_status_WORD word0
484 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
485 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
486 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
487 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
489 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
490 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
491 #define lpfc_rcqe_fcf_id_v1_WORD word1
493 #define lpfc_rcqe_length_SHIFT 16
494 #define lpfc_rcqe_length_MASK 0x0000FFFF
495 #define lpfc_rcqe_length_WORD word2
496 #define lpfc_rcqe_rq_id_SHIFT 6
497 #define lpfc_rcqe_rq_id_MASK 0x000003FF
498 #define lpfc_rcqe_rq_id_WORD word2
499 #define lpfc_rcqe_fcf_id_SHIFT 0
500 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
501 #define lpfc_rcqe_fcf_id_WORD word2
502 #define lpfc_rcqe_rq_id_v1_SHIFT 0
503 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
504 #define lpfc_rcqe_rq_id_v1_WORD word2
506 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
507 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
508 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
509 #define lpfc_rcqe_port_SHIFT 30
510 #define lpfc_rcqe_port_MASK 0x00000001
511 #define lpfc_rcqe_port_WORD word3
512 #define lpfc_rcqe_hdr_length_SHIFT 24
513 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
514 #define lpfc_rcqe_hdr_length_WORD word3
515 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
516 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
517 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
518 #define lpfc_rcqe_eof_SHIFT 8
519 #define lpfc_rcqe_eof_MASK 0x000000FF
520 #define lpfc_rcqe_eof_WORD word3
521 #define FCOE_EOFn 0x41
522 #define FCOE_EOFt 0x42
523 #define FCOE_EOFni 0x49
524 #define FCOE_EOFa 0x50
525 #define lpfc_rcqe_sof_SHIFT 0
526 #define lpfc_rcqe_sof_MASK 0x000000FF
527 #define lpfc_rcqe_sof_WORD word3
528 #define FCOE_SOFi2 0x2d
529 #define FCOE_SOFi3 0x2e
530 #define FCOE_SOFn2 0x35
531 #define FCOE_SOFn3 0x36
539 /* buffer descriptors */
544 #define lpfc_bde4_last_SHIFT 31
545 #define lpfc_bde4_last_MASK 0x00000001
546 #define lpfc_bde4_last_WORD word2
547 #define lpfc_bde4_sge_offset_SHIFT 0
548 #define lpfc_bde4_sge_offset_MASK 0x000003FF
549 #define lpfc_bde4_sge_offset_WORD word2
551 #define lpfc_bde4_length_SHIFT 0
552 #define lpfc_bde4_length_MASK 0x000000FF
553 #define lpfc_bde4_length_WORD word3
556 struct lpfc_register {
560 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
561 #define LPFC_PORT_SEM_MASK 0xF000
562 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
563 #define LPFC_UERR_STATUS_HI 0x00A4
564 #define LPFC_UERR_STATUS_LO 0x00A0
565 #define LPFC_UE_MASK_HI 0x00AC
566 #define LPFC_UE_MASK_LO 0x00A8
568 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
569 #define LPFC_SLI_INTF 0x0058
570 #define LPFC_SLI_ASIC_VER 0x009C
572 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
573 #define lpfc_port_smphr_perr_SHIFT 31
574 #define lpfc_port_smphr_perr_MASK 0x1
575 #define lpfc_port_smphr_perr_WORD word0
576 #define lpfc_port_smphr_sfi_SHIFT 30
577 #define lpfc_port_smphr_sfi_MASK 0x1
578 #define lpfc_port_smphr_sfi_WORD word0
579 #define lpfc_port_smphr_nip_SHIFT 29
580 #define lpfc_port_smphr_nip_MASK 0x1
581 #define lpfc_port_smphr_nip_WORD word0
582 #define lpfc_port_smphr_ipc_SHIFT 28
583 #define lpfc_port_smphr_ipc_MASK 0x1
584 #define lpfc_port_smphr_ipc_WORD word0
585 #define lpfc_port_smphr_scr1_SHIFT 27
586 #define lpfc_port_smphr_scr1_MASK 0x1
587 #define lpfc_port_smphr_scr1_WORD word0
588 #define lpfc_port_smphr_scr2_SHIFT 26
589 #define lpfc_port_smphr_scr2_MASK 0x1
590 #define lpfc_port_smphr_scr2_WORD word0
591 #define lpfc_port_smphr_host_scratch_SHIFT 16
592 #define lpfc_port_smphr_host_scratch_MASK 0xFF
593 #define lpfc_port_smphr_host_scratch_WORD word0
594 #define lpfc_port_smphr_port_status_SHIFT 0
595 #define lpfc_port_smphr_port_status_MASK 0xFFFF
596 #define lpfc_port_smphr_port_status_WORD word0
598 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
599 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
600 #define LPFC_POST_STAGE_HOST_RDY 0x0002
601 #define LPFC_POST_STAGE_BE_RESET 0x0003
602 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
603 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
604 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
605 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
606 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
607 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
608 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
609 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
610 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
611 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
612 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
613 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
614 #define LPFC_POST_STAGE_ARMFW_START 0x0800
615 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
616 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
617 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
618 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
619 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
620 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
621 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
622 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
623 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
624 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
625 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
626 #define LPFC_POST_STAGE_RC_DONE 0x0B07
627 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
628 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
629 #define LPFC_POST_STAGE_PORT_READY 0xC000
630 #define LPFC_POST_STAGE_PORT_UE 0xF000
632 #define LPFC_CTL_PORT_STA_OFFSET 0x404
633 #define lpfc_sliport_status_err_SHIFT 31
634 #define lpfc_sliport_status_err_MASK 0x1
635 #define lpfc_sliport_status_err_WORD word0
636 #define lpfc_sliport_status_end_SHIFT 30
637 #define lpfc_sliport_status_end_MASK 0x1
638 #define lpfc_sliport_status_end_WORD word0
639 #define lpfc_sliport_status_oti_SHIFT 29
640 #define lpfc_sliport_status_oti_MASK 0x1
641 #define lpfc_sliport_status_oti_WORD word0
642 #define lpfc_sliport_status_rn_SHIFT 24
643 #define lpfc_sliport_status_rn_MASK 0x1
644 #define lpfc_sliport_status_rn_WORD word0
645 #define lpfc_sliport_status_rdy_SHIFT 23
646 #define lpfc_sliport_status_rdy_MASK 0x1
647 #define lpfc_sliport_status_rdy_WORD word0
648 #define MAX_IF_TYPE_2_RESETS 6
650 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
651 #define lpfc_sliport_ctrl_end_SHIFT 30
652 #define lpfc_sliport_ctrl_end_MASK 0x1
653 #define lpfc_sliport_ctrl_end_WORD word0
654 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
655 #define LPFC_SLIPORT_BIG_ENDIAN 1
656 #define lpfc_sliport_ctrl_ip_SHIFT 27
657 #define lpfc_sliport_ctrl_ip_MASK 0x1
658 #define lpfc_sliport_ctrl_ip_WORD word0
659 #define LPFC_SLIPORT_INIT_PORT 1
661 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
662 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
664 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
665 #define lpfc_sliport_eqdelay_delay_SHIFT 16
666 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
667 #define lpfc_sliport_eqdelay_delay_WORD word0
668 #define lpfc_sliport_eqdelay_id_SHIFT 0
669 #define lpfc_sliport_eqdelay_id_MASK 0xfff
670 #define lpfc_sliport_eqdelay_id_WORD word0
671 #define LPFC_SEC_TO_USEC 1000000
673 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
676 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
678 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
679 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
681 #define LPFC_HST_ISR0 0x0C18
682 #define LPFC_HST_ISR1 0x0C1C
683 #define LPFC_HST_ISR2 0x0C20
684 #define LPFC_HST_ISR3 0x0C24
685 #define LPFC_HST_ISR4 0x0C28
687 #define LPFC_HST_IMR0 0x0C48
688 #define LPFC_HST_IMR1 0x0C4C
689 #define LPFC_HST_IMR2 0x0C50
690 #define LPFC_HST_IMR3 0x0C54
691 #define LPFC_HST_IMR4 0x0C58
693 #define LPFC_HST_ISCR0 0x0C78
694 #define LPFC_HST_ISCR1 0x0C7C
695 #define LPFC_HST_ISCR2 0x0C80
696 #define LPFC_HST_ISCR3 0x0C84
697 #define LPFC_HST_ISCR4 0x0C88
699 #define LPFC_SLI4_INTR0 BIT0
700 #define LPFC_SLI4_INTR1 BIT1
701 #define LPFC_SLI4_INTR2 BIT2
702 #define LPFC_SLI4_INTR3 BIT3
703 #define LPFC_SLI4_INTR4 BIT4
704 #define LPFC_SLI4_INTR5 BIT5
705 #define LPFC_SLI4_INTR6 BIT6
706 #define LPFC_SLI4_INTR7 BIT7
707 #define LPFC_SLI4_INTR8 BIT8
708 #define LPFC_SLI4_INTR9 BIT9
709 #define LPFC_SLI4_INTR10 BIT10
710 #define LPFC_SLI4_INTR11 BIT11
711 #define LPFC_SLI4_INTR12 BIT12
712 #define LPFC_SLI4_INTR13 BIT13
713 #define LPFC_SLI4_INTR14 BIT14
714 #define LPFC_SLI4_INTR15 BIT15
715 #define LPFC_SLI4_INTR16 BIT16
716 #define LPFC_SLI4_INTR17 BIT17
717 #define LPFC_SLI4_INTR18 BIT18
718 #define LPFC_SLI4_INTR19 BIT19
719 #define LPFC_SLI4_INTR20 BIT20
720 #define LPFC_SLI4_INTR21 BIT21
721 #define LPFC_SLI4_INTR22 BIT22
722 #define LPFC_SLI4_INTR23 BIT23
723 #define LPFC_SLI4_INTR24 BIT24
724 #define LPFC_SLI4_INTR25 BIT25
725 #define LPFC_SLI4_INTR26 BIT26
726 #define LPFC_SLI4_INTR27 BIT27
727 #define LPFC_SLI4_INTR28 BIT28
728 #define LPFC_SLI4_INTR29 BIT29
729 #define LPFC_SLI4_INTR30 BIT30
730 #define LPFC_SLI4_INTR31 BIT31
733 * The Doorbell registers defined here exist in different BAR
734 * register sets depending on the UCNA Port's reported if_type
735 * value. For UCNA ports running SLI4 and if_type 0, they reside in
736 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
737 * BAR0. For FC ports running SLI4 and if_type 6, they reside in
738 * BAR2. The offsets and base address are different, so the driver
739 * has to compute the register addresses accordingly
741 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
742 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
743 #define LPFC_IF6_RQ_DOORBELL 0x0080
744 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24
745 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
746 #define lpfc_rq_db_list_fm_num_posted_WORD word0
747 #define lpfc_rq_db_list_fm_index_SHIFT 16
748 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
749 #define lpfc_rq_db_list_fm_index_WORD word0
750 #define lpfc_rq_db_list_fm_id_SHIFT 0
751 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
752 #define lpfc_rq_db_list_fm_id_WORD word0
753 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16
754 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
755 #define lpfc_rq_db_ring_fm_num_posted_WORD word0
756 #define lpfc_rq_db_ring_fm_id_SHIFT 0
757 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
758 #define lpfc_rq_db_ring_fm_id_WORD word0
760 #define LPFC_ULP0_WQ_DOORBELL 0x0040
761 #define LPFC_ULP1_WQ_DOORBELL 0x0060
762 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24
763 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
764 #define lpfc_wq_db_list_fm_num_posted_WORD word0
765 #define lpfc_wq_db_list_fm_index_SHIFT 16
766 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
767 #define lpfc_wq_db_list_fm_index_WORD word0
768 #define lpfc_wq_db_list_fm_id_SHIFT 0
769 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
770 #define lpfc_wq_db_list_fm_id_WORD word0
771 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16
772 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
773 #define lpfc_wq_db_ring_fm_num_posted_WORD word0
774 #define lpfc_wq_db_ring_fm_id_SHIFT 0
775 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
776 #define lpfc_wq_db_ring_fm_id_WORD word0
778 #define LPFC_IF6_WQ_DOORBELL 0x0040
779 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24
780 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
781 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0
782 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23
783 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
784 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0
785 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16
786 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
787 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0
788 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
789 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
790 #define lpfc_if6_wq_db_list_fm_id_WORD word0
792 #define LPFC_EQCQ_DOORBELL 0x0120
793 #define lpfc_eqcq_doorbell_se_SHIFT 31
794 #define lpfc_eqcq_doorbell_se_MASK 0x0001
795 #define lpfc_eqcq_doorbell_se_WORD word0
796 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
797 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
798 #define lpfc_eqcq_doorbell_arm_SHIFT 29
799 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
800 #define lpfc_eqcq_doorbell_arm_WORD word0
801 #define lpfc_eqcq_doorbell_num_released_SHIFT 16
802 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
803 #define lpfc_eqcq_doorbell_num_released_WORD word0
804 #define lpfc_eqcq_doorbell_qt_SHIFT 10
805 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
806 #define lpfc_eqcq_doorbell_qt_WORD word0
807 #define LPFC_QUEUE_TYPE_COMPLETION 0
808 #define LPFC_QUEUE_TYPE_EVENT 1
809 #define lpfc_eqcq_doorbell_eqci_SHIFT 9
810 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
811 #define lpfc_eqcq_doorbell_eqci_WORD word0
812 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
813 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
814 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0
815 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
816 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
817 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0
818 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
819 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
820 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0
821 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
822 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
823 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0
824 #define LPFC_CQID_HI_FIELD_SHIFT 10
825 #define LPFC_EQID_HI_FIELD_SHIFT 9
827 #define LPFC_IF6_CQ_DOORBELL 0x00C0
828 #define lpfc_if6_cq_doorbell_se_SHIFT 31
829 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
830 #define lpfc_if6_cq_doorbell_se_WORD word0
831 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
832 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1
833 #define lpfc_if6_cq_doorbell_arm_SHIFT 29
834 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
835 #define lpfc_if6_cq_doorbell_arm_WORD word0
836 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16
837 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
838 #define lpfc_if6_cq_doorbell_num_released_WORD word0
839 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
840 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
841 #define lpfc_if6_cq_doorbell_cqid_WORD word0
843 #define LPFC_IF6_EQ_DOORBELL 0x0120
844 #define lpfc_if6_eq_doorbell_io_SHIFT 31
845 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
846 #define lpfc_if6_eq_doorbell_io_WORD word0
847 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
848 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1
849 #define lpfc_if6_eq_doorbell_arm_SHIFT 29
850 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
851 #define lpfc_if6_eq_doorbell_arm_WORD word0
852 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16
853 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
854 #define lpfc_if6_eq_doorbell_num_released_WORD word0
855 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
856 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
857 #define lpfc_if6_eq_doorbell_eqid_WORD word0
859 #define LPFC_BMBX 0x0160
860 #define lpfc_bmbx_addr_SHIFT 2
861 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
862 #define lpfc_bmbx_addr_WORD word0
863 #define lpfc_bmbx_hi_SHIFT 1
864 #define lpfc_bmbx_hi_MASK 0x0001
865 #define lpfc_bmbx_hi_WORD word0
866 #define lpfc_bmbx_rdy_SHIFT 0
867 #define lpfc_bmbx_rdy_MASK 0x0001
868 #define lpfc_bmbx_rdy_WORD word0
870 #define LPFC_MQ_DOORBELL 0x0140
871 #define LPFC_IF6_MQ_DOORBELL 0x0160
872 #define lpfc_mq_doorbell_num_posted_SHIFT 16
873 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
874 #define lpfc_mq_doorbell_num_posted_WORD word0
875 #define lpfc_mq_doorbell_id_SHIFT 0
876 #define lpfc_mq_doorbell_id_MASK 0xFFFF
877 #define lpfc_mq_doorbell_id_WORD word0
879 struct lpfc_sli4_cfg_mhdr {
881 #define lpfc_mbox_hdr_emb_SHIFT 0
882 #define lpfc_mbox_hdr_emb_MASK 0x00000001
883 #define lpfc_mbox_hdr_emb_WORD word1
884 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3
885 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
886 #define lpfc_mbox_hdr_sge_cnt_WORD word1
887 uint32_t payload_length;
893 union lpfc_sli4_cfg_shdr {
896 #define lpfc_mbox_hdr_opcode_SHIFT 0
897 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
898 #define lpfc_mbox_hdr_opcode_WORD word6
899 #define lpfc_mbox_hdr_subsystem_SHIFT 8
900 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
901 #define lpfc_mbox_hdr_subsystem_WORD word6
902 #define lpfc_mbox_hdr_port_number_SHIFT 16
903 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
904 #define lpfc_mbox_hdr_port_number_WORD word6
905 #define lpfc_mbox_hdr_domain_SHIFT 24
906 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
907 #define lpfc_mbox_hdr_domain_WORD word6
909 uint32_t request_length;
911 #define lpfc_mbox_hdr_version_SHIFT 0
912 #define lpfc_mbox_hdr_version_MASK 0x000000FF
913 #define lpfc_mbox_hdr_version_WORD word9
914 #define lpfc_mbox_hdr_pf_num_SHIFT 16
915 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
916 #define lpfc_mbox_hdr_pf_num_WORD word9
917 #define lpfc_mbox_hdr_vh_num_SHIFT 24
918 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
919 #define lpfc_mbox_hdr_vh_num_WORD word9
920 #define LPFC_Q_CREATE_VERSION_2 2
921 #define LPFC_Q_CREATE_VERSION_1 1
922 #define LPFC_Q_CREATE_VERSION_0 0
923 #define LPFC_OPCODE_VERSION_0 0
924 #define LPFC_OPCODE_VERSION_1 1
928 #define lpfc_mbox_hdr_opcode_SHIFT 0
929 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
930 #define lpfc_mbox_hdr_opcode_WORD word6
931 #define lpfc_mbox_hdr_subsystem_SHIFT 8
932 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
933 #define lpfc_mbox_hdr_subsystem_WORD word6
934 #define lpfc_mbox_hdr_domain_SHIFT 24
935 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
936 #define lpfc_mbox_hdr_domain_WORD word6
938 #define lpfc_mbox_hdr_status_SHIFT 0
939 #define lpfc_mbox_hdr_status_MASK 0x000000FF
940 #define lpfc_mbox_hdr_status_WORD word7
941 #define lpfc_mbox_hdr_add_status_SHIFT 8
942 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
943 #define lpfc_mbox_hdr_add_status_WORD word7
944 uint32_t response_length;
945 uint32_t actual_response_length;
949 /* Mailbox Header structures.
950 * struct mbox_header is defined for first generation SLI4_CFG mailbox
951 * calls deployed for BE-based ports.
953 * struct sli4_mbox_header is defined for second generation SLI4
954 * ports that don't deploy the SLI4_CFG mechanism.
957 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
958 union lpfc_sli4_cfg_shdr cfg_shdr;
961 #define LPFC_EXTENT_LOCAL 0
962 #define LPFC_TIMEOUT_DEFAULT 0
963 #define LPFC_EXTENT_VERSION_DEFAULT 0
965 /* Subsystem Definitions */
966 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
967 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
968 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
970 /* Device Specific Definitions */
972 /* The HOST ENDIAN defines are in Big Endian format. */
973 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
974 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
977 #define LPFC_MBOX_OPCODE_NA 0x00
978 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
979 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
980 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
981 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
982 #define LPFC_MBOX_OPCODE_NOP 0x21
983 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
984 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
985 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
986 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
987 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
988 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
989 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
990 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
991 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
992 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
993 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
994 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
995 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
996 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
997 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
998 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
999 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1000 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1001 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1002 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1003 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1004 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1005 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1006 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1007 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1008 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1009 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1010 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1011 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1012 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1013 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1014 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1015 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1018 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1019 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1020 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1021 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1022 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1023 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1024 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1025 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1026 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1027 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1028 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1029 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1030 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1031 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1032 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1034 /* Mailbox command structures */
1037 #define lpfc_eq_context_size_SHIFT 31
1038 #define lpfc_eq_context_size_MASK 0x00000001
1039 #define lpfc_eq_context_size_WORD word0
1040 #define LPFC_EQE_SIZE_4 0x0
1041 #define LPFC_EQE_SIZE_16 0x1
1042 #define lpfc_eq_context_valid_SHIFT 29
1043 #define lpfc_eq_context_valid_MASK 0x00000001
1044 #define lpfc_eq_context_valid_WORD word0
1045 #define lpfc_eq_context_autovalid_SHIFT 28
1046 #define lpfc_eq_context_autovalid_MASK 0x00000001
1047 #define lpfc_eq_context_autovalid_WORD word0
1049 #define lpfc_eq_context_count_SHIFT 26
1050 #define lpfc_eq_context_count_MASK 0x00000003
1051 #define lpfc_eq_context_count_WORD word1
1052 #define LPFC_EQ_CNT_256 0x0
1053 #define LPFC_EQ_CNT_512 0x1
1054 #define LPFC_EQ_CNT_1024 0x2
1055 #define LPFC_EQ_CNT_2048 0x3
1056 #define LPFC_EQ_CNT_4096 0x4
1058 #define lpfc_eq_context_delay_multi_SHIFT 13
1059 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1060 #define lpfc_eq_context_delay_multi_WORD word2
1064 struct eq_delay_info {
1067 uint32_t delay_multi;
1069 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8
1071 struct sgl_page_pairs {
1072 uint32_t sgl_pg0_addr_lo;
1073 uint32_t sgl_pg0_addr_hi;
1074 uint32_t sgl_pg1_addr_lo;
1075 uint32_t sgl_pg1_addr_hi;
1078 struct lpfc_mbx_post_sgl_pages {
1079 struct mbox_header header;
1081 #define lpfc_post_sgl_pages_xri_SHIFT 0
1082 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1083 #define lpfc_post_sgl_pages_xri_WORD word0
1084 #define lpfc_post_sgl_pages_xricnt_SHIFT 16
1085 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1086 #define lpfc_post_sgl_pages_xricnt_WORD word0
1087 struct sgl_page_pairs sgl_pg_pairs[1];
1090 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1091 struct lpfc_mbx_post_uembed_sgl_page1 {
1092 union lpfc_sli4_cfg_shdr cfg_shdr;
1094 struct sgl_page_pairs sgl_pg_pairs;
1097 struct lpfc_mbx_sge {
1103 struct lpfc_mbx_nembed_cmd {
1104 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1105 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
1106 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1109 struct lpfc_mbx_nembed_sge_virt {
1110 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1113 struct lpfc_mbx_eq_create {
1114 struct mbox_header header;
1118 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1119 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1120 #define lpfc_mbx_eq_create_num_pages_WORD word0
1121 struct eq_context context;
1122 struct dma_address page[LPFC_MAX_EQ_PAGE];
1126 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1127 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1128 #define lpfc_mbx_eq_create_q_id_WORD word0
1133 struct lpfc_mbx_modify_eq_delay {
1134 struct mbox_header header;
1138 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1146 struct lpfc_mbx_eq_destroy {
1147 struct mbox_header header;
1151 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1152 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1153 #define lpfc_mbx_eq_destroy_q_id_WORD word0
1161 struct lpfc_mbx_nop {
1162 struct mbox_header header;
1163 uint32_t context[2];
1168 #define lpfc_cq_context_event_SHIFT 31
1169 #define lpfc_cq_context_event_MASK 0x00000001
1170 #define lpfc_cq_context_event_WORD word0
1171 #define lpfc_cq_context_valid_SHIFT 29
1172 #define lpfc_cq_context_valid_MASK 0x00000001
1173 #define lpfc_cq_context_valid_WORD word0
1174 #define lpfc_cq_context_count_SHIFT 27
1175 #define lpfc_cq_context_count_MASK 0x00000003
1176 #define lpfc_cq_context_count_WORD word0
1177 #define LPFC_CQ_CNT_256 0x0
1178 #define LPFC_CQ_CNT_512 0x1
1179 #define LPFC_CQ_CNT_1024 0x2
1180 #define LPFC_CQ_CNT_WORD7 0x3
1181 #define lpfc_cq_context_autovalid_SHIFT 15
1182 #define lpfc_cq_context_autovalid_MASK 0x00000001
1183 #define lpfc_cq_context_autovalid_WORD word0
1185 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1186 #define lpfc_cq_eq_id_MASK 0x000000FF
1187 #define lpfc_cq_eq_id_WORD word1
1188 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1189 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1190 #define lpfc_cq_eq_id_2_WORD word1
1191 uint32_t lpfc_cq_context_count; /* Version 2 Only */
1195 struct lpfc_mbx_cq_create {
1196 struct mbox_header header;
1200 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1201 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1202 #define lpfc_mbx_cq_create_page_size_WORD word0
1203 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1204 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1205 #define lpfc_mbx_cq_create_num_pages_WORD word0
1206 struct cq_context context;
1207 struct dma_address page[LPFC_MAX_CQ_PAGE];
1211 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1212 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1213 #define lpfc_mbx_cq_create_q_id_WORD word0
1218 struct lpfc_mbx_cq_create_set {
1219 union lpfc_sli4_cfg_shdr cfg_shdr;
1223 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */
1224 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1225 #define lpfc_mbx_cq_create_set_page_size_WORD word0
1226 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1227 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1228 #define lpfc_mbx_cq_create_set_num_pages_WORD word0
1230 #define lpfc_mbx_cq_create_set_evt_SHIFT 31
1231 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1232 #define lpfc_mbx_cq_create_set_evt_WORD word1
1233 #define lpfc_mbx_cq_create_set_valid_SHIFT 29
1234 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1235 #define lpfc_mbx_cq_create_set_valid_WORD word1
1236 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27
1237 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1238 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1
1239 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25
1240 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1241 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1
1242 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15
1243 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1244 #define lpfc_mbx_cq_create_set_autovalid_WORD word1
1245 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14
1246 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1247 #define lpfc_mbx_cq_create_set_nodelay_WORD word1
1248 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12
1249 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1250 #define lpfc_mbx_cq_create_set_clswm_WORD word1
1252 #define lpfc_mbx_cq_create_set_arm_SHIFT 31
1253 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1254 #define lpfc_mbx_cq_create_set_arm_WORD word2
1255 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16
1256 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1257 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2
1258 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1259 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1260 #define lpfc_mbx_cq_create_set_num_cq_WORD word2
1262 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16
1263 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1264 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3
1265 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1266 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1267 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3
1269 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16
1270 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1271 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4
1272 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1273 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1274 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4
1276 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16
1277 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1278 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5
1279 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1280 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1281 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5
1283 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16
1284 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1285 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6
1286 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1287 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1288 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6
1290 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16
1291 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1292 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7
1293 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1294 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1295 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7
1297 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16
1298 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1299 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8
1300 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1301 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1302 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8
1304 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16
1305 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1306 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9
1307 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1308 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1309 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9
1311 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16
1312 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1313 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10
1314 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1315 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1316 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10
1317 struct dma_address page[1];
1321 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16
1322 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1323 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0
1324 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1325 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1326 #define lpfc_mbx_cq_create_set_base_id_WORD word0
1331 struct lpfc_mbx_cq_destroy {
1332 struct mbox_header header;
1336 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1337 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1338 #define lpfc_mbx_cq_destroy_q_id_WORD word0
1353 struct lpfc_mbx_wq_create {
1354 struct mbox_header header;
1356 struct { /* Version 0 Request */
1358 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1359 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1360 #define lpfc_mbx_wq_create_num_pages_WORD word0
1361 #define lpfc_mbx_wq_create_dua_SHIFT 8
1362 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1363 #define lpfc_mbx_wq_create_dua_WORD word0
1364 #define lpfc_mbx_wq_create_cq_id_SHIFT 16
1365 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1366 #define lpfc_mbx_wq_create_cq_id_WORD word0
1367 struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1369 #define lpfc_mbx_wq_create_bua_SHIFT 0
1370 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1371 #define lpfc_mbx_wq_create_bua_WORD word9
1372 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8
1373 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1374 #define lpfc_mbx_wq_create_ulp_num_WORD word9
1376 struct { /* Version 1 Request */
1377 uint32_t word0; /* Word 0 is the same as in v0 */
1379 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1380 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1381 #define lpfc_mbx_wq_create_page_size_WORD word1
1382 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1383 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15
1384 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1385 #define lpfc_mbx_wq_create_dpp_req_WORD word1
1386 #define lpfc_mbx_wq_create_doe_SHIFT 14
1387 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1388 #define lpfc_mbx_wq_create_doe_WORD word1
1389 #define lpfc_mbx_wq_create_toe_SHIFT 13
1390 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1391 #define lpfc_mbx_wq_create_toe_WORD word1
1392 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1393 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1394 #define lpfc_mbx_wq_create_wqe_size_WORD word1
1395 #define LPFC_WQ_WQE_SIZE_64 0x5
1396 #define LPFC_WQ_WQE_SIZE_128 0x6
1397 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1398 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1399 #define lpfc_mbx_wq_create_wqe_count_WORD word1
1401 struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1405 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1406 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1407 #define lpfc_mbx_wq_create_q_id_WORD word0
1408 uint32_t doorbell_offset;
1410 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1411 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1412 #define lpfc_mbx_wq_create_bar_set_WORD word2
1413 #define WQ_PCI_BAR_0_AND_1 0x00
1414 #define WQ_PCI_BAR_2_AND_3 0x01
1415 #define WQ_PCI_BAR_4_AND_5 0x02
1416 #define lpfc_mbx_wq_create_db_format_SHIFT 16
1417 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1418 #define lpfc_mbx_wq_create_db_format_WORD word2
1422 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31
1423 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1424 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0
1425 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1426 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1427 #define lpfc_mbx_wq_create_v1_q_id_WORD word0
1429 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1430 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1431 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1
1432 uint32_t doorbell_offset;
1434 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16
1435 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1436 #define lpfc_mbx_wq_create_dpp_id_WORD word3
1437 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1438 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1439 #define lpfc_mbx_wq_create_dpp_bar_WORD word3
1440 uint32_t dpp_offset;
1445 struct lpfc_mbx_wq_destroy {
1446 struct mbox_header header;
1450 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1451 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1452 #define lpfc_mbx_wq_destroy_q_id_WORD word0
1460 #define LPFC_HDR_BUF_SIZE 128
1461 #define LPFC_DATA_BUF_SIZE 2048
1462 #define LPFC_NVMET_DATA_BUF_SIZE 128
1465 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1466 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1467 #define lpfc_rq_context_rqe_count_WORD word0
1468 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1469 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1470 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1471 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1472 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */
1473 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1474 #define lpfc_rq_context_rqe_count_1_WORD word0
1475 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */
1476 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1477 #define lpfc_rq_context_rqe_size_WORD word0
1478 #define LPFC_RQE_SIZE_8 2
1479 #define LPFC_RQE_SIZE_16 3
1480 #define LPFC_RQE_SIZE_32 4
1481 #define LPFC_RQE_SIZE_64 5
1482 #define LPFC_RQE_SIZE_128 6
1483 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1484 #define lpfc_rq_context_page_size_MASK 0x000000FF
1485 #define lpfc_rq_context_page_size_WORD word0
1486 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1488 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */
1489 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1490 #define lpfc_rq_context_data_size_WORD word1
1491 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1492 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1493 #define lpfc_rq_context_hdr_size_WORD word1
1495 #define lpfc_rq_context_cq_id_SHIFT 16
1496 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1497 #define lpfc_rq_context_cq_id_WORD word2
1498 #define lpfc_rq_context_buf_size_SHIFT 0
1499 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1500 #define lpfc_rq_context_buf_size_WORD word2
1501 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1502 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1503 #define lpfc_rq_context_base_cq_WORD word2
1504 uint32_t buffer_size; /* Version 1 Only */
1507 struct lpfc_mbx_rq_create {
1508 struct mbox_header header;
1512 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1513 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1514 #define lpfc_mbx_rq_create_num_pages_WORD word0
1515 #define lpfc_mbx_rq_create_dua_SHIFT 16
1516 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1517 #define lpfc_mbx_rq_create_dua_WORD word0
1518 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1519 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1520 #define lpfc_mbx_rq_create_bqu_WORD word0
1521 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1522 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1523 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1524 struct rq_context context;
1525 struct dma_address page[LPFC_MAX_RQ_PAGE];
1529 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1530 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1531 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1532 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1533 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1534 #define lpfc_mbx_rq_create_q_id_WORD word0
1535 uint32_t doorbell_offset;
1537 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1538 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1539 #define lpfc_mbx_rq_create_bar_set_WORD word2
1540 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1541 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1542 #define lpfc_mbx_rq_create_db_format_WORD word2
1547 struct lpfc_mbx_rq_create_v2 {
1548 union lpfc_sli4_cfg_shdr cfg_shdr;
1552 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1553 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1554 #define lpfc_mbx_rq_create_num_pages_WORD word0
1555 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16
1556 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1557 #define lpfc_mbx_rq_create_rq_cnt_WORD word0
1558 #define lpfc_mbx_rq_create_dua_SHIFT 16
1559 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1560 #define lpfc_mbx_rq_create_dua_WORD word0
1561 #define lpfc_mbx_rq_create_bqu_SHIFT 17
1562 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1563 #define lpfc_mbx_rq_create_bqu_WORD word0
1564 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1565 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1566 #define lpfc_mbx_rq_create_ulp_num_WORD word0
1567 #define lpfc_mbx_rq_create_dim_SHIFT 29
1568 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1569 #define lpfc_mbx_rq_create_dim_WORD word0
1570 #define lpfc_mbx_rq_create_dfd_SHIFT 30
1571 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1572 #define lpfc_mbx_rq_create_dfd_WORD word0
1573 #define lpfc_mbx_rq_create_dnb_SHIFT 31
1574 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1575 #define lpfc_mbx_rq_create_dnb_WORD word0
1576 struct rq_context context;
1577 struct dma_address page[1];
1581 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1582 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1583 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1584 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1585 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1586 #define lpfc_mbx_rq_create_q_id_WORD word0
1587 uint32_t doorbell_offset;
1589 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1590 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1591 #define lpfc_mbx_rq_create_bar_set_WORD word2
1592 #define lpfc_mbx_rq_create_db_format_SHIFT 16
1593 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1594 #define lpfc_mbx_rq_create_db_format_WORD word2
1599 struct lpfc_mbx_rq_destroy {
1600 struct mbox_header header;
1604 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1605 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1606 #define lpfc_mbx_rq_destroy_q_id_WORD word0
1616 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1617 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1618 #define lpfc_mq_context_cq_id_WORD word0
1619 #define lpfc_mq_context_ring_size_SHIFT 16
1620 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1621 #define lpfc_mq_context_ring_size_WORD word0
1622 #define LPFC_MQ_RING_SIZE_16 0x5
1623 #define LPFC_MQ_RING_SIZE_32 0x6
1624 #define LPFC_MQ_RING_SIZE_64 0x7
1625 #define LPFC_MQ_RING_SIZE_128 0x8
1627 #define lpfc_mq_context_valid_SHIFT 31
1628 #define lpfc_mq_context_valid_MASK 0x00000001
1629 #define lpfc_mq_context_valid_WORD word1
1634 struct lpfc_mbx_mq_create {
1635 struct mbox_header header;
1639 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1640 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1641 #define lpfc_mbx_mq_create_num_pages_WORD word0
1642 struct mq_context context;
1643 struct dma_address page[LPFC_MAX_MQ_PAGE];
1647 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1648 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1649 #define lpfc_mbx_mq_create_q_id_WORD word0
1654 struct lpfc_mbx_mq_create_ext {
1655 struct mbox_header header;
1659 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1660 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1661 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1662 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1663 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1664 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1665 uint32_t async_evt_bmap;
1666 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1667 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1668 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1669 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1670 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1671 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1672 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1673 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1674 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1675 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1676 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1677 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1678 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1679 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1680 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1681 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1682 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1683 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1684 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1685 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1686 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1687 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1688 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1689 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1690 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1691 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1692 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1693 struct mq_context context;
1694 struct dma_address page[LPFC_MAX_MQ_PAGE];
1698 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1699 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1700 #define lpfc_mbx_mq_create_q_id_WORD word0
1703 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1704 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1705 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1708 struct lpfc_mbx_mq_destroy {
1709 struct mbox_header header;
1713 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1714 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1715 #define lpfc_mbx_mq_destroy_q_id_WORD word0
1723 /* Start Gen 2 SLI4 Mailbox definitions: */
1725 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1726 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1727 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1728 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1729 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1731 struct lpfc_mbx_get_rsrc_extent_info {
1732 struct mbox_header header;
1736 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1737 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1738 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1742 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1743 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1744 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1745 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1746 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1747 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1752 struct lpfc_mbx_query_fw_config {
1753 struct mbox_header header;
1755 uint32_t config_number;
1756 #define LPFC_FC_FCOE 0x00000007
1757 uint32_t asic_revision;
1758 uint32_t physical_port;
1759 uint32_t function_mode;
1760 #define LPFC_FCOE_INI_MODE 0x00000040
1761 #define LPFC_FCOE_TGT_MODE 0x00000080
1762 #define LPFC_DUA_MODE 0x00000800
1764 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1765 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1766 uint32_t ulp0_nap_words[12];
1768 uint32_t ulp1_nap_words[12];
1769 uint32_t function_capabilities;
1774 uint32_t ulp0_nap2_words[2];
1775 uint32_t ulp1_nap2_words[2];
1779 struct lpfc_mbx_set_beacon_config {
1780 struct mbox_header header;
1782 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1783 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1784 #define lpfc_mbx_set_beacon_port_num_WORD word4
1785 #define lpfc_mbx_set_beacon_port_type_SHIFT 6
1786 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1787 #define lpfc_mbx_set_beacon_port_type_WORD word4
1788 #define lpfc_mbx_set_beacon_state_SHIFT 8
1789 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1790 #define lpfc_mbx_set_beacon_state_WORD word4
1791 #define lpfc_mbx_set_beacon_duration_SHIFT 16
1792 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1793 #define lpfc_mbx_set_beacon_duration_WORD word4
1795 /* COMMON_SET_BEACON_CONFIG_V1 */
1796 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16
1797 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1798 #define lpfc_mbx_set_beacon_duration_v1_WORD word4
1799 uint32_t word5; /* RESERVED */
1802 struct lpfc_id_range {
1804 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1805 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1806 #define lpfc_mbx_rsrc_id_word4_0_WORD word5
1807 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1808 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1809 #define lpfc_mbx_rsrc_id_word4_1_WORD word5
1812 struct lpfc_mbx_set_link_diag_state {
1813 struct mbox_header header;
1817 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1818 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1819 #define lpfc_mbx_set_diag_state_diag_WORD word0
1820 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2
1821 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1822 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0
1823 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1824 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1
1825 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1826 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1827 #define lpfc_mbx_set_diag_state_link_num_WORD word0
1828 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1829 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1830 #define lpfc_mbx_set_diag_state_link_type_WORD word0
1838 struct lpfc_mbx_set_link_diag_loopback {
1839 struct mbox_header header;
1843 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1844 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1845 #define lpfc_mbx_set_diag_lpbk_type_WORD word0
1846 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1847 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1848 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1849 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1850 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1851 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1852 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1853 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1854 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1862 struct lpfc_mbx_run_link_diag_test {
1863 struct mbox_header header;
1867 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1868 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1869 #define lpfc_mbx_run_diag_test_link_num_WORD word0
1870 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1871 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1872 #define lpfc_mbx_run_diag_test_link_type_WORD word0
1874 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1875 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1876 #define lpfc_mbx_run_diag_test_test_id_WORD word1
1877 #define lpfc_mbx_run_diag_test_loops_SHIFT 16
1878 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1879 #define lpfc_mbx_run_diag_test_loops_WORD word1
1881 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1882 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1883 #define lpfc_mbx_run_diag_test_test_ver_WORD word2
1884 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1885 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1886 #define lpfc_mbx_run_diag_test_err_act_WORD word2
1895 * struct lpfc_mbx_alloc_rsrc_extents:
1896 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1897 * 6 words of header + 4 words of shared subcommand header +
1898 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1900 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1901 * for extents payload.
1903 * 212/2 (bytes per extent) = 106 extents.
1904 * 106/2 (extents per word) = 53 words.
1905 * lpfc_id_range id is statically size to 53.
1907 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1908 * extent ranges. For ALLOC, the type and cnt are required.
1909 * For GET_ALLOCATED, only the type is required.
1911 struct lpfc_mbx_alloc_rsrc_extents {
1912 struct mbox_header header;
1916 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1917 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1918 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1919 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1920 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1921 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1925 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1926 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1927 #define lpfc_mbx_rsrc_cnt_WORD word4
1928 struct lpfc_id_range id[53];
1934 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1935 * structure shares the same SHIFT/MASK/WORD defines provided in the
1936 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1937 * the structures defined above. This non-embedded structure provides for the
1938 * maximum number of extents supported by the port.
1940 struct lpfc_mbx_nembed_rsrc_extent {
1941 union lpfc_sli4_cfg_shdr cfg_shdr;
1943 struct lpfc_id_range id;
1946 struct lpfc_mbx_dealloc_rsrc_extents {
1947 struct mbox_header header;
1950 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1951 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1952 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
1957 /* Start SLI4 FCoE specific mbox structures. */
1959 struct lpfc_mbx_post_hdr_tmpl {
1960 struct mbox_header header;
1962 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1963 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1964 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1965 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1966 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1967 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1968 uint32_t rpi_paddr_lo;
1969 uint32_t rpi_paddr_hi;
1972 struct sli4_sge { /* SLI-4 */
1977 #define lpfc_sli4_sge_offset_SHIFT 0
1978 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1979 #define lpfc_sli4_sge_offset_WORD word2
1980 #define lpfc_sli4_sge_type_SHIFT 27
1981 #define lpfc_sli4_sge_type_MASK 0x0000000F
1982 #define lpfc_sli4_sge_type_WORD word2
1983 #define LPFC_SGE_TYPE_DATA 0x0
1984 #define LPFC_SGE_TYPE_DIF 0x4
1985 #define LPFC_SGE_TYPE_LSP 0x5
1986 #define LPFC_SGE_TYPE_PEDIF 0x6
1987 #define LPFC_SGE_TYPE_PESEED 0x7
1988 #define LPFC_SGE_TYPE_DISEED 0x8
1989 #define LPFC_SGE_TYPE_ENC 0x9
1990 #define LPFC_SGE_TYPE_ATM 0xA
1991 #define LPFC_SGE_TYPE_SKIP 0xC
1992 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
1993 #define lpfc_sli4_sge_last_MASK 0x00000001
1994 #define lpfc_sli4_sge_last_WORD word2
1998 struct sli4_sge_diseed { /* SLI-4 */
2000 uint32_t ref_tag_tran;
2003 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2004 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2005 #define lpfc_sli4_sge_dif_apptran_WORD word2
2006 #define lpfc_sli4_sge_dif_af_SHIFT 24
2007 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2008 #define lpfc_sli4_sge_dif_af_WORD word2
2009 #define lpfc_sli4_sge_dif_na_SHIFT 25
2010 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2011 #define lpfc_sli4_sge_dif_na_WORD word2
2012 #define lpfc_sli4_sge_dif_hi_SHIFT 26
2013 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2014 #define lpfc_sli4_sge_dif_hi_WORD word2
2015 #define lpfc_sli4_sge_dif_type_SHIFT 27
2016 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2017 #define lpfc_sli4_sge_dif_type_WORD word2
2018 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
2019 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2020 #define lpfc_sli4_sge_dif_last_WORD word2
2022 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2023 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2024 #define lpfc_sli4_sge_dif_apptag_WORD word3
2025 #define lpfc_sli4_sge_dif_bs_SHIFT 16
2026 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2027 #define lpfc_sli4_sge_dif_bs_WORD word3
2028 #define lpfc_sli4_sge_dif_ai_SHIFT 19
2029 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2030 #define lpfc_sli4_sge_dif_ai_WORD word3
2031 #define lpfc_sli4_sge_dif_me_SHIFT 20
2032 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2033 #define lpfc_sli4_sge_dif_me_WORD word3
2034 #define lpfc_sli4_sge_dif_re_SHIFT 21
2035 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2036 #define lpfc_sli4_sge_dif_re_WORD word3
2037 #define lpfc_sli4_sge_dif_ce_SHIFT 22
2038 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2039 #define lpfc_sli4_sge_dif_ce_WORD word3
2040 #define lpfc_sli4_sge_dif_nr_SHIFT 23
2041 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2042 #define lpfc_sli4_sge_dif_nr_WORD word3
2043 #define lpfc_sli4_sge_dif_oprx_SHIFT 24
2044 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2045 #define lpfc_sli4_sge_dif_oprx_WORD word3
2046 #define lpfc_sli4_sge_dif_optx_SHIFT 28
2047 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2048 #define lpfc_sli4_sge_dif_optx_WORD word3
2049 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2053 uint32_t max_rcv_size;
2054 uint32_t fka_adv_period;
2055 uint32_t fip_priority;
2057 #define lpfc_fcf_record_mac_0_SHIFT 0
2058 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2059 #define lpfc_fcf_record_mac_0_WORD word3
2060 #define lpfc_fcf_record_mac_1_SHIFT 8
2061 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2062 #define lpfc_fcf_record_mac_1_WORD word3
2063 #define lpfc_fcf_record_mac_2_SHIFT 16
2064 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2065 #define lpfc_fcf_record_mac_2_WORD word3
2066 #define lpfc_fcf_record_mac_3_SHIFT 24
2067 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2068 #define lpfc_fcf_record_mac_3_WORD word3
2070 #define lpfc_fcf_record_mac_4_SHIFT 0
2071 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2072 #define lpfc_fcf_record_mac_4_WORD word4
2073 #define lpfc_fcf_record_mac_5_SHIFT 8
2074 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2075 #define lpfc_fcf_record_mac_5_WORD word4
2076 #define lpfc_fcf_record_fcf_avail_SHIFT 16
2077 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2078 #define lpfc_fcf_record_fcf_avail_WORD word4
2079 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24
2080 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2081 #define lpfc_fcf_record_mac_addr_prov_WORD word4
2082 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
2083 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
2085 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2086 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2087 #define lpfc_fcf_record_fab_name_0_WORD word5
2088 #define lpfc_fcf_record_fab_name_1_SHIFT 8
2089 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2090 #define lpfc_fcf_record_fab_name_1_WORD word5
2091 #define lpfc_fcf_record_fab_name_2_SHIFT 16
2092 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2093 #define lpfc_fcf_record_fab_name_2_WORD word5
2094 #define lpfc_fcf_record_fab_name_3_SHIFT 24
2095 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2096 #define lpfc_fcf_record_fab_name_3_WORD word5
2098 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2099 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2100 #define lpfc_fcf_record_fab_name_4_WORD word6
2101 #define lpfc_fcf_record_fab_name_5_SHIFT 8
2102 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2103 #define lpfc_fcf_record_fab_name_5_WORD word6
2104 #define lpfc_fcf_record_fab_name_6_SHIFT 16
2105 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2106 #define lpfc_fcf_record_fab_name_6_WORD word6
2107 #define lpfc_fcf_record_fab_name_7_SHIFT 24
2108 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2109 #define lpfc_fcf_record_fab_name_7_WORD word6
2111 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2112 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2113 #define lpfc_fcf_record_fc_map_0_WORD word7
2114 #define lpfc_fcf_record_fc_map_1_SHIFT 8
2115 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2116 #define lpfc_fcf_record_fc_map_1_WORD word7
2117 #define lpfc_fcf_record_fc_map_2_SHIFT 16
2118 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2119 #define lpfc_fcf_record_fc_map_2_WORD word7
2120 #define lpfc_fcf_record_fcf_valid_SHIFT 24
2121 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2122 #define lpfc_fcf_record_fcf_valid_WORD word7
2123 #define lpfc_fcf_record_fcf_fc_SHIFT 25
2124 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2125 #define lpfc_fcf_record_fcf_fc_WORD word7
2126 #define lpfc_fcf_record_fcf_sol_SHIFT 31
2127 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2128 #define lpfc_fcf_record_fcf_sol_WORD word7
2130 #define lpfc_fcf_record_fcf_index_SHIFT 0
2131 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2132 #define lpfc_fcf_record_fcf_index_WORD word8
2133 #define lpfc_fcf_record_fcf_state_SHIFT 16
2134 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2135 #define lpfc_fcf_record_fcf_state_WORD word8
2136 uint8_t vlan_bitmap[512];
2138 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2139 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2140 #define lpfc_fcf_record_switch_name_0_WORD word137
2141 #define lpfc_fcf_record_switch_name_1_SHIFT 8
2142 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2143 #define lpfc_fcf_record_switch_name_1_WORD word137
2144 #define lpfc_fcf_record_switch_name_2_SHIFT 16
2145 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2146 #define lpfc_fcf_record_switch_name_2_WORD word137
2147 #define lpfc_fcf_record_switch_name_3_SHIFT 24
2148 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2149 #define lpfc_fcf_record_switch_name_3_WORD word137
2151 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2152 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2153 #define lpfc_fcf_record_switch_name_4_WORD word138
2154 #define lpfc_fcf_record_switch_name_5_SHIFT 8
2155 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2156 #define lpfc_fcf_record_switch_name_5_WORD word138
2157 #define lpfc_fcf_record_switch_name_6_SHIFT 16
2158 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2159 #define lpfc_fcf_record_switch_name_6_WORD word138
2160 #define lpfc_fcf_record_switch_name_7_SHIFT 24
2161 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2162 #define lpfc_fcf_record_switch_name_7_WORD word138
2165 struct lpfc_mbx_read_fcf_tbl {
2166 union lpfc_sli4_cfg_shdr cfg_shdr;
2170 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2171 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2172 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10
2179 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2180 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2181 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
2184 struct lpfc_mbx_add_fcf_tbl_entry {
2185 union lpfc_sli4_cfg_shdr cfg_shdr;
2187 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2188 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2189 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
2190 struct lpfc_mbx_sge fcf_sge;
2193 struct lpfc_mbx_del_fcf_tbl_entry {
2194 struct mbox_header header;
2196 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2197 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2198 #define lpfc_mbx_del_fcf_tbl_count_WORD word10
2199 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
2200 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2201 #define lpfc_mbx_del_fcf_tbl_index_WORD word10
2204 struct lpfc_mbx_redisc_fcf_tbl {
2205 struct mbox_header header;
2207 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2208 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2209 #define lpfc_mbx_redisc_fcf_count_WORD word10
2212 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2213 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2214 #define lpfc_mbx_redisc_fcf_index_WORD word12
2217 /* Status field for embedded SLI_CONFIG mailbox command */
2218 #define STATUS_SUCCESS 0x0
2219 #define STATUS_FAILED 0x1
2220 #define STATUS_ILLEGAL_REQUEST 0x2
2221 #define STATUS_ILLEGAL_FIELD 0x3
2222 #define STATUS_INSUFFICIENT_BUFFER 0x4
2223 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2224 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2225 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2226 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2227 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2228 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2229 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2230 #define STATUS_ASSERT_FAILED 0x1e
2231 #define STATUS_INVALID_SESSION 0x1f
2232 #define STATUS_INVALID_CONNECTION 0x20
2233 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2234 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2235 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2236 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2237 #define STATUS_FLASHROM_READ_FAILED 0x27
2238 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2239 #define STATUS_ERROR_ACITMAIN 0x2a
2240 #define STATUS_REBOOT_REQUIRED 0x2c
2241 #define STATUS_FCF_IN_USE 0x3a
2242 #define STATUS_FCF_TABLE_EMPTY 0x43
2245 * Additional status field for embedded SLI_CONFIG mailbox
2248 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2249 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2250 #define ADD_STATUS_INVALID_REQUEST 0x4B
2252 struct lpfc_mbx_sli4_config {
2253 struct mbox_header header;
2256 struct lpfc_mbx_init_vfi {
2258 #define lpfc_init_vfi_vr_SHIFT 31
2259 #define lpfc_init_vfi_vr_MASK 0x00000001
2260 #define lpfc_init_vfi_vr_WORD word1
2261 #define lpfc_init_vfi_vt_SHIFT 30
2262 #define lpfc_init_vfi_vt_MASK 0x00000001
2263 #define lpfc_init_vfi_vt_WORD word1
2264 #define lpfc_init_vfi_vf_SHIFT 29
2265 #define lpfc_init_vfi_vf_MASK 0x00000001
2266 #define lpfc_init_vfi_vf_WORD word1
2267 #define lpfc_init_vfi_vp_SHIFT 28
2268 #define lpfc_init_vfi_vp_MASK 0x00000001
2269 #define lpfc_init_vfi_vp_WORD word1
2270 #define lpfc_init_vfi_vfi_SHIFT 0
2271 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2272 #define lpfc_init_vfi_vfi_WORD word1
2274 #define lpfc_init_vfi_vpi_SHIFT 16
2275 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2276 #define lpfc_init_vfi_vpi_WORD word2
2277 #define lpfc_init_vfi_fcfi_SHIFT 0
2278 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2279 #define lpfc_init_vfi_fcfi_WORD word2
2281 #define lpfc_init_vfi_pri_SHIFT 13
2282 #define lpfc_init_vfi_pri_MASK 0x00000007
2283 #define lpfc_init_vfi_pri_WORD word3
2284 #define lpfc_init_vfi_vf_id_SHIFT 1
2285 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2286 #define lpfc_init_vfi_vf_id_WORD word3
2288 #define lpfc_init_vfi_hop_count_SHIFT 24
2289 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2290 #define lpfc_init_vfi_hop_count_WORD word4
2292 #define MBX_VFI_IN_USE 0x9F02
2295 struct lpfc_mbx_reg_vfi {
2297 #define lpfc_reg_vfi_upd_SHIFT 29
2298 #define lpfc_reg_vfi_upd_MASK 0x00000001
2299 #define lpfc_reg_vfi_upd_WORD word1
2300 #define lpfc_reg_vfi_vp_SHIFT 28
2301 #define lpfc_reg_vfi_vp_MASK 0x00000001
2302 #define lpfc_reg_vfi_vp_WORD word1
2303 #define lpfc_reg_vfi_vfi_SHIFT 0
2304 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2305 #define lpfc_reg_vfi_vfi_WORD word1
2307 #define lpfc_reg_vfi_vpi_SHIFT 16
2308 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2309 #define lpfc_reg_vfi_vpi_WORD word2
2310 #define lpfc_reg_vfi_fcfi_SHIFT 0
2311 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2312 #define lpfc_reg_vfi_fcfi_WORD word2
2314 struct ulp_bde64 bde;
2318 #define lpfc_reg_vfi_nport_id_SHIFT 0
2319 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2320 #define lpfc_reg_vfi_nport_id_WORD word10
2321 #define lpfc_reg_vfi_bbcr_SHIFT 27
2322 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2323 #define lpfc_reg_vfi_bbcr_WORD word10
2324 #define lpfc_reg_vfi_bbscn_SHIFT 28
2325 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2326 #define lpfc_reg_vfi_bbscn_WORD word10
2329 struct lpfc_mbx_init_vpi {
2331 #define lpfc_init_vpi_vfi_SHIFT 16
2332 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2333 #define lpfc_init_vpi_vfi_WORD word1
2334 #define lpfc_init_vpi_vpi_SHIFT 0
2335 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2336 #define lpfc_init_vpi_vpi_WORD word1
2339 struct lpfc_mbx_read_vpi {
2340 uint32_t word1_rsvd;
2342 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2343 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2344 #define lpfc_mbx_read_vpi_vnportid_WORD word2
2345 uint32_t word3_rsvd;
2347 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2348 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2349 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4
2350 #define lpfc_mbx_read_vpi_pb_SHIFT 15
2351 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2352 #define lpfc_mbx_read_vpi_pb_WORD word4
2353 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
2354 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2355 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4
2356 #define lpfc_mbx_read_vpi_ns_SHIFT 30
2357 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2358 #define lpfc_mbx_read_vpi_ns_WORD word4
2359 #define lpfc_mbx_read_vpi_hl_SHIFT 31
2360 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2361 #define lpfc_mbx_read_vpi_hl_WORD word4
2362 uint32_t word5_rsvd;
2364 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2365 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2366 #define lpfc_mbx_read_vpi_vpi_WORD word6
2368 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2369 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2370 #define lpfc_mbx_read_vpi_mac_0_WORD word7
2371 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8
2372 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2373 #define lpfc_mbx_read_vpi_mac_1_WORD word7
2374 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16
2375 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2376 #define lpfc_mbx_read_vpi_mac_2_WORD word7
2377 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24
2378 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2379 #define lpfc_mbx_read_vpi_mac_3_WORD word7
2381 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2382 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2383 #define lpfc_mbx_read_vpi_mac_4_WORD word8
2384 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8
2385 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2386 #define lpfc_mbx_read_vpi_mac_5_WORD word8
2387 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
2388 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2389 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8
2390 #define lpfc_mbx_read_vpi_vv_SHIFT 28
2391 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2392 #define lpfc_mbx_read_vpi_vv_WORD word8
2395 struct lpfc_mbx_unreg_vfi {
2396 uint32_t word1_rsvd;
2398 #define lpfc_unreg_vfi_vfi_SHIFT 0
2399 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2400 #define lpfc_unreg_vfi_vfi_WORD word2
2403 struct lpfc_mbx_resume_rpi {
2405 #define lpfc_resume_rpi_index_SHIFT 0
2406 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2407 #define lpfc_resume_rpi_index_WORD word1
2408 #define lpfc_resume_rpi_ii_SHIFT 30
2409 #define lpfc_resume_rpi_ii_MASK 0x00000003
2410 #define lpfc_resume_rpi_ii_WORD word1
2411 #define RESUME_INDEX_RPI 0
2412 #define RESUME_INDEX_VPI 1
2413 #define RESUME_INDEX_VFI 2
2414 #define RESUME_INDEX_FCFI 3
2418 #define REG_FCF_INVALID_QID 0xFFFF
2419 struct lpfc_mbx_reg_fcfi {
2421 #define lpfc_reg_fcfi_info_index_SHIFT 0
2422 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2423 #define lpfc_reg_fcfi_info_index_WORD word1
2424 #define lpfc_reg_fcfi_fcfi_SHIFT 16
2425 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2426 #define lpfc_reg_fcfi_fcfi_WORD word1
2428 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2429 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2430 #define lpfc_reg_fcfi_rq_id1_WORD word2
2431 #define lpfc_reg_fcfi_rq_id0_SHIFT 16
2432 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2433 #define lpfc_reg_fcfi_rq_id0_WORD word2
2435 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2436 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2437 #define lpfc_reg_fcfi_rq_id3_WORD word3
2438 #define lpfc_reg_fcfi_rq_id2_SHIFT 16
2439 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2440 #define lpfc_reg_fcfi_rq_id2_WORD word3
2442 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2443 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2444 #define lpfc_reg_fcfi_type_match0_WORD word4
2445 #define lpfc_reg_fcfi_type_mask0_SHIFT 16
2446 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2447 #define lpfc_reg_fcfi_type_mask0_WORD word4
2448 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2449 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2450 #define lpfc_reg_fcfi_rctl_match0_WORD word4
2451 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2452 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2453 #define lpfc_reg_fcfi_rctl_mask0_WORD word4
2455 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2456 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2457 #define lpfc_reg_fcfi_type_match1_WORD word5
2458 #define lpfc_reg_fcfi_type_mask1_SHIFT 16
2459 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2460 #define lpfc_reg_fcfi_type_mask1_WORD word5
2461 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2462 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2463 #define lpfc_reg_fcfi_rctl_match1_WORD word5
2464 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2465 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2466 #define lpfc_reg_fcfi_rctl_mask1_WORD word5
2468 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2469 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2470 #define lpfc_reg_fcfi_type_match2_WORD word6
2471 #define lpfc_reg_fcfi_type_mask2_SHIFT 16
2472 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2473 #define lpfc_reg_fcfi_type_mask2_WORD word6
2474 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2475 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2476 #define lpfc_reg_fcfi_rctl_match2_WORD word6
2477 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2478 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2479 #define lpfc_reg_fcfi_rctl_mask2_WORD word6
2481 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2482 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2483 #define lpfc_reg_fcfi_type_match3_WORD word7
2484 #define lpfc_reg_fcfi_type_mask3_SHIFT 16
2485 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2486 #define lpfc_reg_fcfi_type_mask3_WORD word7
2487 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2488 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2489 #define lpfc_reg_fcfi_rctl_match3_WORD word7
2490 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2491 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2492 #define lpfc_reg_fcfi_rctl_mask3_WORD word7
2494 #define lpfc_reg_fcfi_mam_SHIFT 13
2495 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2496 #define lpfc_reg_fcfi_mam_WORD word8
2497 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2498 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2499 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2500 #define lpfc_reg_fcfi_vv_SHIFT 12
2501 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2502 #define lpfc_reg_fcfi_vv_WORD word8
2503 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2504 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2505 #define lpfc_reg_fcfi_vlan_tag_WORD word8
2508 struct lpfc_mbx_reg_fcfi_mrq {
2510 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2511 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2512 #define lpfc_reg_fcfi_mrq_info_index_WORD word1
2513 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16
2514 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2515 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1
2517 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2518 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2519 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2
2520 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16
2521 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2522 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2
2524 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2525 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2526 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3
2527 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16
2528 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2529 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3
2531 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24
2532 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2533 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4
2534 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16
2535 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2536 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4
2537 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8
2538 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2539 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4
2540 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2541 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2542 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4
2544 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24
2545 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2546 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5
2547 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16
2548 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2549 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5
2550 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8
2551 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2552 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5
2553 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2554 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2555 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5
2557 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24
2558 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2559 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6
2560 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16
2561 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2562 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6
2563 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8
2564 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2565 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6
2566 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2567 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2568 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6
2570 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24
2571 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2572 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7
2573 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16
2574 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2575 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7
2576 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8
2577 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2578 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7
2579 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2580 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2581 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7
2583 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31
2584 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2585 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8
2586 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30
2587 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2588 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8
2589 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29
2590 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2591 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8
2592 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28
2593 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2594 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8
2595 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27
2596 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2597 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8
2598 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26
2599 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2600 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8
2601 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25
2602 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2603 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8
2604 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24
2605 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2606 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8
2607 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23
2608 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2609 #define lpfc_reg_fcfi_mrq_pt7_WORD word8
2610 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22
2611 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2612 #define lpfc_reg_fcfi_mrq_pt6_WORD word8
2613 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21
2614 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2615 #define lpfc_reg_fcfi_mrq_pt5_WORD word8
2616 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20
2617 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2618 #define lpfc_reg_fcfi_mrq_pt4_WORD word8
2619 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19
2620 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2621 #define lpfc_reg_fcfi_mrq_pt3_WORD word8
2622 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18
2623 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2624 #define lpfc_reg_fcfi_mrq_pt2_WORD word8
2625 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17
2626 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2627 #define lpfc_reg_fcfi_mrq_pt1_WORD word8
2628 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16
2629 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2630 #define lpfc_reg_fcfi_mrq_pt0_WORD word8
2631 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15
2632 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2633 #define lpfc_reg_fcfi_mrq_xmv_WORD word8
2634 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13
2635 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2636 #define lpfc_reg_fcfi_mrq_mode_WORD word8
2637 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12
2638 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2639 #define lpfc_reg_fcfi_mrq_vv_WORD word8
2640 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2641 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2642 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8
2644 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12
2645 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2646 #define lpfc_reg_fcfi_mrq_policy_WORD word9
2647 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8
2648 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2649 #define lpfc_reg_fcfi_mrq_filter_WORD word9
2650 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2651 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2652 #define lpfc_reg_fcfi_mrq_npairs_WORD word9
2662 struct lpfc_mbx_unreg_fcfi {
2665 #define lpfc_unreg_fcfi_SHIFT 0
2666 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2667 #define lpfc_unreg_fcfi_WORD word2
2670 struct lpfc_mbx_read_rev {
2672 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2673 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2674 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2675 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2676 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2677 #define lpfc_mbx_rd_rev_fcoe_WORD word1
2678 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2679 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2680 #define lpfc_mbx_rd_rev_cee_ver_WORD word1
2681 #define LPFC_PREDCBX_CEE_MODE 0
2682 #define LPFC_DCBX_CEE_MODE 1
2683 #define lpfc_mbx_rd_rev_vpd_SHIFT 29
2684 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2685 #define lpfc_mbx_rd_rev_vpd_WORD word1
2686 uint32_t first_hw_rev;
2687 #define LPFC_G7_ASIC_1 0xd
2688 uint32_t second_hw_rev;
2689 uint32_t word4_rsvd;
2690 uint32_t third_hw_rev;
2692 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2693 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2694 #define lpfc_mbx_rd_rev_fcph_low_WORD word6
2695 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2696 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2697 #define lpfc_mbx_rd_rev_fcph_high_WORD word6
2698 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2699 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2700 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2701 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2702 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2703 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2704 uint32_t word7_rsvd;
2706 uint8_t fw_name[16];
2707 uint32_t ulp_fw_id_rev;
2708 uint8_t ulp_fw_name[16];
2709 uint32_t word18_47_rsvd[30];
2711 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2712 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2713 #define lpfc_mbx_rd_rev_avail_len_WORD word48
2714 uint32_t vpd_paddr_low;
2715 uint32_t vpd_paddr_high;
2716 uint32_t avail_vpd_len;
2717 uint32_t rsvd_52_63[12];
2720 struct lpfc_mbx_read_config {
2722 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2723 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2724 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2726 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2727 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2728 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2729 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2730 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2731 #define lpfc_mbx_rd_conf_lnk_type_WORD word2
2732 #define LPFC_LNK_TYPE_GE 0
2733 #define LPFC_LNK_TYPE_FC 1
2734 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2735 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2736 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2737 #define lpfc_mbx_rd_conf_topology_SHIFT 24
2738 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2739 #define lpfc_mbx_rd_conf_topology_WORD word2
2742 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2743 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2744 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2747 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2748 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2749 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2750 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16
2751 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2752 #define lpfc_mbx_rd_conf_link_speed_WORD word6
2755 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2756 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2757 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8
2758 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4
2759 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2760 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8
2761 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8
2762 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2763 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8
2765 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2766 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2767 #define lpfc_mbx_rd_conf_lmt_WORD word9
2771 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2772 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2773 #define lpfc_mbx_rd_conf_xri_base_WORD word12
2774 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2775 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2776 #define lpfc_mbx_rd_conf_xri_count_WORD word12
2778 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2779 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2780 #define lpfc_mbx_rd_conf_rpi_base_WORD word13
2781 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2782 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2783 #define lpfc_mbx_rd_conf_rpi_count_WORD word13
2785 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2786 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2787 #define lpfc_mbx_rd_conf_vpi_base_WORD word14
2788 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2789 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2790 #define lpfc_mbx_rd_conf_vpi_count_WORD word14
2792 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2793 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2794 #define lpfc_mbx_rd_conf_vfi_base_WORD word15
2795 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2796 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2797 #define lpfc_mbx_rd_conf_vfi_count_WORD word15
2799 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2800 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2801 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2803 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2804 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2805 #define lpfc_mbx_rd_conf_rq_count_WORD word17
2806 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2807 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2808 #define lpfc_mbx_rd_conf_eq_count_WORD word17
2810 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2811 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2812 #define lpfc_mbx_rd_conf_wq_count_WORD word18
2813 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2814 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2815 #define lpfc_mbx_rd_conf_cq_count_WORD word18
2818 struct lpfc_mbx_request_features {
2820 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2821 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2822 #define lpfc_mbx_rq_ftr_qry_WORD word1
2824 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2825 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2826 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2827 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2828 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2829 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2830 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2831 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2832 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2833 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2834 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2835 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2836 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2837 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2838 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2839 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2840 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2841 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2842 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2843 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2844 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2845 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2846 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2847 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2848 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9
2849 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2850 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2
2851 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2852 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2853 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2854 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16
2855 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2856 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2
2858 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2859 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2860 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2861 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2862 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2863 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2864 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2865 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2866 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2867 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2868 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2869 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2870 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2871 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2872 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2873 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2874 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2875 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2876 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2877 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2878 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2879 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2880 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2881 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2882 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2883 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2884 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2885 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16
2886 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2887 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3
2890 struct lpfc_mbx_memory_dump_type3 {
2892 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
2893 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
2894 #define lpfc_mbx_memory_dump_type3_type_WORD word1
2895 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24
2896 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
2897 #define lpfc_mbx_memory_dump_type3_link_WORD word1
2899 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
2900 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
2901 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2
2902 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16
2903 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
2904 #define lpfc_mbx_memory_dump_type3_offset_WORD word2
2906 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
2907 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
2908 #define lpfc_mbx_memory_dump_type3_length_WORD word3
2911 uint32_t return_len;
2914 #define DMP_PAGE_A0 0xa0
2915 #define DMP_PAGE_A2 0xa2
2916 #define DMP_SFF_PAGE_A0_SIZE 256
2917 #define DMP_SFF_PAGE_A2_SIZE 256
2919 #define SFP_WAVELENGTH_LC1310 1310
2920 #define SFP_WAVELENGTH_LL1550 1550
2924 * * SFF-8472 TABLE 3.4
2926 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
2927 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
2928 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
2929 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
2930 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
2931 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
2932 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
2933 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
2934 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
2935 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
2936 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
2937 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
2938 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
2939 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
2940 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
2941 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
2943 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
2945 #define SSF_IDENTIFIER 0
2946 #define SSF_EXT_IDENTIFIER 1
2947 #define SSF_CONNECTOR 2
2948 #define SSF_TRANSCEIVER_CODE_B0 3
2949 #define SSF_TRANSCEIVER_CODE_B1 4
2950 #define SSF_TRANSCEIVER_CODE_B2 5
2951 #define SSF_TRANSCEIVER_CODE_B3 6
2952 #define SSF_TRANSCEIVER_CODE_B4 7
2953 #define SSF_TRANSCEIVER_CODE_B5 8
2954 #define SSF_TRANSCEIVER_CODE_B6 9
2955 #define SSF_TRANSCEIVER_CODE_B7 10
2956 #define SSF_ENCODING 11
2957 #define SSF_BR_NOMINAL 12
2958 #define SSF_RATE_IDENTIFIER 13
2959 #define SSF_LENGTH_9UM_KM 14
2960 #define SSF_LENGTH_9UM 15
2961 #define SSF_LENGTH_50UM_OM2 16
2962 #define SSF_LENGTH_62UM_OM1 17
2963 #define SFF_LENGTH_COPPER 18
2964 #define SSF_LENGTH_50UM_OM3 19
2965 #define SSF_VENDOR_NAME 20
2966 #define SSF_VENDOR_OUI 36
2967 #define SSF_VENDOR_PN 40
2968 #define SSF_VENDOR_REV 56
2969 #define SSF_WAVELENGTH_B1 60
2970 #define SSF_WAVELENGTH_B0 61
2971 #define SSF_CC_BASE 63
2972 #define SSF_OPTIONS_B1 64
2973 #define SSF_OPTIONS_B0 65
2974 #define SSF_BR_MAX 66
2975 #define SSF_BR_MIN 67
2976 #define SSF_VENDOR_SN 68
2977 #define SSF_DATE_CODE 84
2978 #define SSF_MONITORING_TYPEDIAGNOSTIC 92
2979 #define SSF_ENHANCED_OPTIONS 93
2980 #define SFF_8472_COMPLIANCE 94
2981 #define SSF_CC_EXT 95
2982 #define SSF_A0_VENDOR_SPECIFIC 96
2984 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
2986 #define SSF_TEMP_HIGH_ALARM 0
2987 #define SSF_TEMP_LOW_ALARM 2
2988 #define SSF_TEMP_HIGH_WARNING 4
2989 #define SSF_TEMP_LOW_WARNING 6
2990 #define SSF_VOLTAGE_HIGH_ALARM 8
2991 #define SSF_VOLTAGE_LOW_ALARM 10
2992 #define SSF_VOLTAGE_HIGH_WARNING 12
2993 #define SSF_VOLTAGE_LOW_WARNING 14
2994 #define SSF_BIAS_HIGH_ALARM 16
2995 #define SSF_BIAS_LOW_ALARM 18
2996 #define SSF_BIAS_HIGH_WARNING 20
2997 #define SSF_BIAS_LOW_WARNING 22
2998 #define SSF_TXPOWER_HIGH_ALARM 24
2999 #define SSF_TXPOWER_LOW_ALARM 26
3000 #define SSF_TXPOWER_HIGH_WARNING 28
3001 #define SSF_TXPOWER_LOW_WARNING 30
3002 #define SSF_RXPOWER_HIGH_ALARM 32
3003 #define SSF_RXPOWER_LOW_ALARM 34
3004 #define SSF_RXPOWER_HIGH_WARNING 36
3005 #define SSF_RXPOWER_LOW_WARNING 38
3006 #define SSF_EXT_CAL_CONSTANTS 56
3007 #define SSF_CC_DMI 95
3008 #define SFF_TEMPERATURE_B1 96
3009 #define SFF_TEMPERATURE_B0 97
3010 #define SFF_VCC_B1 98
3011 #define SFF_VCC_B0 99
3012 #define SFF_TX_BIAS_CURRENT_B1 100
3013 #define SFF_TX_BIAS_CURRENT_B0 101
3014 #define SFF_TXPOWER_B1 102
3015 #define SFF_TXPOWER_B0 103
3016 #define SFF_RXPOWER_B1 104
3017 #define SFF_RXPOWER_B0 105
3018 #define SSF_STATUS_CONTROL 110
3019 #define SSF_ALARM_FLAGS 112
3020 #define SSF_WARNING_FLAGS 116
3021 #define SSF_EXT_TATUS_CONTROL_B1 118
3022 #define SSF_EXT_TATUS_CONTROL_B0 119
3023 #define SSF_A2_VENDOR_SPECIFIC 120
3024 #define SSF_USER_EEPROM 128
3025 #define SSF_VENDOR_CONTROL 148
3029 * Tranceiver codes Fibre Channel SFF-8472
3033 struct sff_trasnceiver_codes_byte0 {
3034 uint8_t inifiband:4;
3035 uint8_t teng_ethernet:4;
3038 struct sff_trasnceiver_codes_byte1 {
3043 struct sff_trasnceiver_codes_byte2 {
3047 struct sff_trasnceiver_codes_byte3 {
3051 struct sff_trasnceiver_codes_byte4 {
3053 uint8_t fc_lw_laser:1;
3054 uint8_t fc_sw_laser:1;
3055 uint8_t fc_md_distance:1;
3056 uint8_t fc_lg_distance:1;
3057 uint8_t fc_int_distance:1;
3058 uint8_t fc_short_distance:1;
3059 uint8_t fc_vld_distance:1;
3062 struct sff_trasnceiver_codes_byte5 {
3063 uint8_t reserved1:1;
3064 uint8_t reserved2:1;
3065 uint8_t fc_sfp_active:1; /* Active cable */
3066 uint8_t fc_sfp_passive:1; /* Passive cable */
3067 uint8_t fc_lw_laser:1; /* Longwave laser */
3068 uint8_t fc_sw_laser_sl:1;
3069 uint8_t fc_sw_laser_sn:1;
3070 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */
3073 struct sff_trasnceiver_codes_byte6 {
3074 uint8_t fc_tm_sm:1; /* Single Mode */
3076 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */
3077 uint8_t fc_tm_tv:1; /* Video Coax (TV) */
3078 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */
3079 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */
3080 uint8_t fc_tm_tw:1; /* Twin Axial Pair */
3083 struct sff_trasnceiver_codes_byte7 {
3084 uint8_t fc_sp_100MB:1; /* 100 MB/sec */
3086 uint8_t fc_sp_200mb:1; /* 200 MB/sec */
3087 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */
3088 uint8_t fc_sp_400MB:1; /* 400 MB/sec */
3089 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */
3090 uint8_t fc_sp_800MB:1; /* 800 MB/sec */
3091 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */
3094 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3095 struct user_eeprom {
3096 uint8_t vendor_name[16];
3097 uint8_t vendor_oui[3];
3098 uint8_t vendor_pn[816];
3099 uint8_t vendor_rev[4];
3100 uint8_t vendor_sn[16];
3101 uint8_t datecode[6];
3102 uint8_t lot_code[2];
3103 uint8_t reserved191[57];
3106 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3107 &(~((SLI4_PAGE_SIZE)-1)))
3109 struct lpfc_sli4_parameters {
3111 #define cfg_prot_type_SHIFT 0
3112 #define cfg_prot_type_MASK 0x000000FF
3113 #define cfg_prot_type_WORD word0
3115 #define cfg_ft_SHIFT 0
3116 #define cfg_ft_MASK 0x00000001
3117 #define cfg_ft_WORD word1
3118 #define cfg_sli_rev_SHIFT 4
3119 #define cfg_sli_rev_MASK 0x0000000f
3120 #define cfg_sli_rev_WORD word1
3121 #define cfg_sli_family_SHIFT 8
3122 #define cfg_sli_family_MASK 0x0000000f
3123 #define cfg_sli_family_WORD word1
3124 #define cfg_if_type_SHIFT 12
3125 #define cfg_if_type_MASK 0x0000000f
3126 #define cfg_if_type_WORD word1
3127 #define cfg_sli_hint_1_SHIFT 16
3128 #define cfg_sli_hint_1_MASK 0x000000ff
3129 #define cfg_sli_hint_1_WORD word1
3130 #define cfg_sli_hint_2_SHIFT 24
3131 #define cfg_sli_hint_2_MASK 0x0000001f
3132 #define cfg_sli_hint_2_WORD word1
3134 #define cfg_eqav_SHIFT 31
3135 #define cfg_eqav_MASK 0x00000001
3136 #define cfg_eqav_WORD word2
3139 #define cfg_cqv_SHIFT 14
3140 #define cfg_cqv_MASK 0x00000003
3141 #define cfg_cqv_WORD word4
3142 #define cfg_cqpsize_SHIFT 16
3143 #define cfg_cqpsize_MASK 0x000000ff
3144 #define cfg_cqpsize_WORD word4
3145 #define cfg_cqav_SHIFT 31
3146 #define cfg_cqav_MASK 0x00000001
3147 #define cfg_cqav_WORD word4
3150 #define cfg_mqv_SHIFT 14
3151 #define cfg_mqv_MASK 0x00000003
3152 #define cfg_mqv_WORD word6
3155 #define cfg_wqpcnt_SHIFT 0
3156 #define cfg_wqpcnt_MASK 0x0000000f
3157 #define cfg_wqpcnt_WORD word8
3158 #define cfg_wqsize_SHIFT 8
3159 #define cfg_wqsize_MASK 0x0000000f
3160 #define cfg_wqsize_WORD word8
3161 #define cfg_wqv_SHIFT 14
3162 #define cfg_wqv_MASK 0x00000003
3163 #define cfg_wqv_WORD word8
3164 #define cfg_wqpsize_SHIFT 16
3165 #define cfg_wqpsize_MASK 0x000000ff
3166 #define cfg_wqpsize_WORD word8
3169 #define cfg_rqv_SHIFT 14
3170 #define cfg_rqv_MASK 0x00000003
3171 #define cfg_rqv_WORD word10
3173 #define cfg_rq_db_window_SHIFT 28
3174 #define cfg_rq_db_window_MASK 0x0000000f
3175 #define cfg_rq_db_window_WORD word11
3177 #define cfg_fcoe_SHIFT 0
3178 #define cfg_fcoe_MASK 0x00000001
3179 #define cfg_fcoe_WORD word12
3180 #define cfg_ext_SHIFT 1
3181 #define cfg_ext_MASK 0x00000001
3182 #define cfg_ext_WORD word12
3183 #define cfg_hdrr_SHIFT 2
3184 #define cfg_hdrr_MASK 0x00000001
3185 #define cfg_hdrr_WORD word12
3186 #define cfg_phwq_SHIFT 15
3187 #define cfg_phwq_MASK 0x00000001
3188 #define cfg_phwq_WORD word12
3189 #define cfg_oas_SHIFT 25
3190 #define cfg_oas_MASK 0x00000001
3191 #define cfg_oas_WORD word12
3192 #define cfg_loopbk_scope_SHIFT 28
3193 #define cfg_loopbk_scope_MASK 0x0000000f
3194 #define cfg_loopbk_scope_WORD word12
3195 uint32_t sge_supp_len;
3197 #define cfg_sgl_page_cnt_SHIFT 0
3198 #define cfg_sgl_page_cnt_MASK 0x0000000f
3199 #define cfg_sgl_page_cnt_WORD word14
3200 #define cfg_sgl_page_size_SHIFT 8
3201 #define cfg_sgl_page_size_MASK 0x000000ff
3202 #define cfg_sgl_page_size_WORD word14
3203 #define cfg_sgl_pp_align_SHIFT 16
3204 #define cfg_sgl_pp_align_MASK 0x000000ff
3205 #define cfg_sgl_pp_align_WORD word14
3211 #define cfg_ext_embed_cb_SHIFT 0
3212 #define cfg_ext_embed_cb_MASK 0x00000001
3213 #define cfg_ext_embed_cb_WORD word19
3214 #define cfg_mds_diags_SHIFT 1
3215 #define cfg_mds_diags_MASK 0x00000001
3216 #define cfg_mds_diags_WORD word19
3217 #define cfg_nvme_SHIFT 3
3218 #define cfg_nvme_MASK 0x00000001
3219 #define cfg_nvme_WORD word19
3220 #define cfg_xib_SHIFT 4
3221 #define cfg_xib_MASK 0x00000001
3222 #define cfg_xib_WORD word19
3223 #define cfg_eqdr_SHIFT 8
3224 #define cfg_eqdr_MASK 0x00000001
3225 #define cfg_eqdr_WORD word19
3226 #define cfg_nosr_SHIFT 9
3227 #define cfg_nosr_MASK 0x00000001
3228 #define cfg_nosr_WORD word19
3230 #define cfg_bv1s_SHIFT 10
3231 #define cfg_bv1s_MASK 0x00000001
3232 #define cfg_bv1s_WORD word19
3235 #define cfg_max_tow_xri_SHIFT 0
3236 #define cfg_max_tow_xri_MASK 0x0000ffff
3237 #define cfg_max_tow_xri_WORD word20
3239 uint32_t word21; /* RESERVED */
3240 uint32_t word22; /* RESERVED */
3241 uint32_t word23; /* RESERVED */
3244 #define cfg_frag_field_offset_SHIFT 0
3245 #define cfg_frag_field_offset_MASK 0x0000ffff
3246 #define cfg_frag_field_offset_WORD word24
3248 #define cfg_frag_field_size_SHIFT 16
3249 #define cfg_frag_field_size_MASK 0x0000ffff
3250 #define cfg_frag_field_size_WORD word24
3253 #define cfg_sgl_field_offset_SHIFT 0
3254 #define cfg_sgl_field_offset_MASK 0x0000ffff
3255 #define cfg_sgl_field_offset_WORD word25
3257 #define cfg_sgl_field_size_SHIFT 16
3258 #define cfg_sgl_field_size_MASK 0x0000ffff
3259 #define cfg_sgl_field_size_WORD word25
3261 uint32_t word26; /* Chain SGE initial value LOW */
3262 uint32_t word27; /* Chain SGE initial value HIGH */
3263 #define LPFC_NODELAY_MAX_IO 32
3266 #define LPFC_SET_UE_RECOVERY 0x10
3267 #define LPFC_SET_MDS_DIAGS 0x11
3268 struct lpfc_mbx_set_feature {
3269 struct mbox_header header;
3273 #define lpfc_mbx_set_feature_UER_SHIFT 0
3274 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3275 #define lpfc_mbx_set_feature_UER_WORD word6
3276 #define lpfc_mbx_set_feature_mds_SHIFT 0
3277 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3278 #define lpfc_mbx_set_feature_mds_WORD word6
3279 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1
3280 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3281 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6
3283 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3284 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3285 #define lpfc_mbx_set_feature_UERP_WORD word7
3286 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3287 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3288 #define lpfc_mbx_set_feature_UESR_WORD word7
3292 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3293 struct lpfc_mbx_set_host_data {
3294 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48
3295 struct mbox_header header;
3298 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3302 struct lpfc_mbx_get_sli4_parameters {
3303 struct mbox_header header;
3304 struct lpfc_sli4_parameters sli4_parameters;
3307 struct lpfc_rscr_desc_generic {
3308 #define LPFC_RSRC_DESC_WSIZE 22
3309 uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3312 struct lpfc_rsrc_desc_pcie {
3314 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3315 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3316 #define lpfc_rsrc_desc_pcie_type_WORD word0
3317 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3318 #define lpfc_rsrc_desc_pcie_length_SHIFT 8
3319 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3320 #define lpfc_rsrc_desc_pcie_length_WORD word0
3322 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3323 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3324 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1
3327 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3328 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3329 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
3330 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
3331 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3332 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
3333 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
3334 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3335 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3
3337 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3338 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3339 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
3342 struct lpfc_rsrc_desc_fcfcoe {
3344 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3345 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3346 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0
3347 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3348 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8
3349 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3350 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0
3351 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3352 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72
3353 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88
3355 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3356 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3357 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
3358 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
3359 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3360 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
3362 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3363 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3364 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
3365 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
3366 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3367 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
3369 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3370 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3371 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
3372 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
3373 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3374 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
3376 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3377 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3378 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
3379 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
3380 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3381 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
3383 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3384 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3385 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
3386 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
3387 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3388 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
3397 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3398 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3399 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
3400 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
3401 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3402 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
3403 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
3404 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3405 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
3406 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
3407 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3408 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
3409 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
3410 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3411 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
3412 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3417 uint32_t reserved[4];
3420 struct lpfc_func_cfg {
3421 #define LPFC_RSRC_DESC_MAX_NUM 2
3422 uint32_t rsrc_desc_count;
3423 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3426 struct lpfc_mbx_get_func_cfg {
3427 struct mbox_header header;
3428 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3429 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3430 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3431 struct lpfc_func_cfg func_cfg;
3434 struct lpfc_prof_cfg {
3435 #define LPFC_RSRC_DESC_MAX_NUM 2
3436 uint32_t rsrc_desc_count;
3437 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3440 struct lpfc_mbx_get_prof_cfg {
3441 struct mbox_header header;
3442 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3443 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3444 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3448 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3449 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3450 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
3451 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
3452 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3453 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
3456 struct lpfc_prof_cfg prof_cfg;
3461 struct lpfc_controller_attribute {
3462 uint32_t version_string[8];
3463 uint32_t manufacturer_name[8];
3464 uint32_t supported_modes;
3466 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3467 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3468 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17
3469 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
3470 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3471 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17
3472 uint32_t mbx_da_struct_ver;
3473 uint32_t ep_fw_da_struct_ver;
3474 uint32_t ncsi_ver_str[3];
3475 uint32_t dflt_ext_timeout;
3476 uint32_t model_number[8];
3477 uint32_t description[16];
3478 uint32_t serial_number[8];
3479 uint32_t ip_ver_str[8];
3480 uint32_t fw_ver_str[8];
3481 uint32_t bios_ver_str[8];
3482 uint32_t redboot_ver_str[8];
3483 uint32_t driver_ver_str[8];
3484 uint32_t flash_fw_ver_str[8];
3485 uint32_t functionality;
3487 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3488 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3489 #define lpfc_cntl_attr_max_cbd_len_WORD word105
3490 #define lpfc_cntl_attr_asic_rev_SHIFT 16
3491 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3492 #define lpfc_cntl_attr_asic_rev_WORD word105
3493 #define lpfc_cntl_attr_gen_guid0_SHIFT 24
3494 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3495 #define lpfc_cntl_attr_gen_guid0_WORD word105
3496 uint32_t gen_guid1_12[3];
3498 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3499 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3500 #define lpfc_cntl_attr_gen_guid13_14_WORD word109
3501 #define lpfc_cntl_attr_gen_guid15_SHIFT 16
3502 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3503 #define lpfc_cntl_attr_gen_guid15_WORD word109
3504 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
3505 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3506 #define lpfc_cntl_attr_hba_port_cnt_WORD word109
3508 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3509 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3510 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
3511 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24
3512 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3513 #define lpfc_cntl_attr_multi_func_dev_WORD word110
3515 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3516 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3517 #define lpfc_cntl_attr_cache_valid_WORD word111
3518 #define lpfc_cntl_attr_hba_status_SHIFT 8
3519 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3520 #define lpfc_cntl_attr_hba_status_WORD word111
3521 #define lpfc_cntl_attr_max_domain_SHIFT 16
3522 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3523 #define lpfc_cntl_attr_max_domain_WORD word111
3524 #define lpfc_cntl_attr_lnk_numb_SHIFT 24
3525 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3526 #define lpfc_cntl_attr_lnk_numb_WORD word111
3527 #define lpfc_cntl_attr_lnk_type_SHIFT 30
3528 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3529 #define lpfc_cntl_attr_lnk_type_WORD word111
3530 uint32_t fw_post_status;
3531 uint32_t hba_mtu[8];
3533 uint32_t reserved1[3];
3535 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3536 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3537 #define lpfc_cntl_attr_pci_vendor_id_WORD word125
3538 #define lpfc_cntl_attr_pci_device_id_SHIFT 16
3539 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3540 #define lpfc_cntl_attr_pci_device_id_WORD word125
3542 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3543 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3544 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126
3545 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
3546 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3547 #define lpfc_cntl_attr_pci_subsys_id_WORD word126
3549 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3550 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3551 #define lpfc_cntl_attr_pci_bus_num_WORD word127
3552 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8
3553 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3554 #define lpfc_cntl_attr_pci_dev_num_WORD word127
3555 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
3556 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3557 #define lpfc_cntl_attr_pci_fnc_num_WORD word127
3558 #define lpfc_cntl_attr_inf_type_SHIFT 24
3559 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3560 #define lpfc_cntl_attr_inf_type_WORD word127
3561 uint32_t unique_id[2];
3563 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3564 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3565 #define lpfc_cntl_attr_num_netfil_WORD word130
3566 uint32_t reserved2[4];
3569 struct lpfc_mbx_get_cntl_attributes {
3570 union lpfc_sli4_cfg_shdr cfg_shdr;
3571 struct lpfc_controller_attribute cntl_attr;
3574 struct lpfc_mbx_get_port_name {
3575 struct mbox_header header;
3579 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3580 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3581 #define lpfc_mbx_get_port_name_lnk_type_WORD word4
3585 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3586 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3587 #define lpfc_mbx_get_port_name_name0_WORD word4
3588 #define lpfc_mbx_get_port_name_name1_SHIFT 8
3589 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3590 #define lpfc_mbx_get_port_name_name1_WORD word4
3591 #define lpfc_mbx_get_port_name_name2_SHIFT 16
3592 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3593 #define lpfc_mbx_get_port_name_name2_WORD word4
3594 #define lpfc_mbx_get_port_name_name3_SHIFT 24
3595 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3596 #define lpfc_mbx_get_port_name_name3_WORD word4
3597 #define LPFC_LINK_NUMBER_0 0
3598 #define LPFC_LINK_NUMBER_1 1
3599 #define LPFC_LINK_NUMBER_2 2
3600 #define LPFC_LINK_NUMBER_3 3
3605 /* Mailbox Completion Queue Error Messages */
3606 #define MB_CQE_STATUS_SUCCESS 0x0
3607 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3608 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3609 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3610 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3611 #define MB_CQE_STATUS_DMA_FAILED 0x5
3613 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1
3614 struct lpfc_mbx_wr_object {
3615 struct mbox_header header;
3619 #define lpfc_wr_object_eof_SHIFT 31
3620 #define lpfc_wr_object_eof_MASK 0x00000001
3621 #define lpfc_wr_object_eof_WORD word4
3622 #define lpfc_wr_object_write_length_SHIFT 0
3623 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3624 #define lpfc_wr_object_write_length_WORD word4
3625 uint32_t write_offset;
3626 uint32_t object_name[26];
3628 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3631 uint32_t actual_write_length;
3636 /* mailbox queue entry structure */
3639 #define lpfc_mqe_status_SHIFT 16
3640 #define lpfc_mqe_status_MASK 0x0000FFFF
3641 #define lpfc_mqe_status_WORD word0
3642 #define lpfc_mqe_command_SHIFT 8
3643 #define lpfc_mqe_command_MASK 0x000000FF
3644 #define lpfc_mqe_command_WORD word0
3646 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3647 /* sli4 mailbox commands */
3648 struct lpfc_mbx_sli4_config sli4_config;
3649 struct lpfc_mbx_init_vfi init_vfi;
3650 struct lpfc_mbx_reg_vfi reg_vfi;
3651 struct lpfc_mbx_reg_vfi unreg_vfi;
3652 struct lpfc_mbx_init_vpi init_vpi;
3653 struct lpfc_mbx_resume_rpi resume_rpi;
3654 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3655 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3656 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3657 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3658 struct lpfc_mbx_reg_fcfi reg_fcfi;
3659 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3660 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3661 struct lpfc_mbx_mq_create mq_create;
3662 struct lpfc_mbx_mq_create_ext mq_create_ext;
3663 struct lpfc_mbx_eq_create eq_create;
3664 struct lpfc_mbx_modify_eq_delay eq_delay;
3665 struct lpfc_mbx_cq_create cq_create;
3666 struct lpfc_mbx_cq_create_set cq_create_set;
3667 struct lpfc_mbx_wq_create wq_create;
3668 struct lpfc_mbx_rq_create rq_create;
3669 struct lpfc_mbx_rq_create_v2 rq_create_v2;
3670 struct lpfc_mbx_mq_destroy mq_destroy;
3671 struct lpfc_mbx_eq_destroy eq_destroy;
3672 struct lpfc_mbx_cq_destroy cq_destroy;
3673 struct lpfc_mbx_wq_destroy wq_destroy;
3674 struct lpfc_mbx_rq_destroy rq_destroy;
3675 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3676 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3677 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3678 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3679 struct lpfc_mbx_nembed_cmd nembed_cmd;
3680 struct lpfc_mbx_read_rev read_rev;
3681 struct lpfc_mbx_read_vpi read_vpi;
3682 struct lpfc_mbx_read_config rd_config;
3683 struct lpfc_mbx_request_features req_ftrs;
3684 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3685 struct lpfc_mbx_query_fw_config query_fw_cfg;
3686 struct lpfc_mbx_set_beacon_config beacon_config;
3687 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3688 struct lpfc_mbx_set_link_diag_state link_diag_state;
3689 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3690 struct lpfc_mbx_run_link_diag_test link_diag_test;
3691 struct lpfc_mbx_get_func_cfg get_func_cfg;
3692 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3693 struct lpfc_mbx_wr_object wr_object;
3694 struct lpfc_mbx_get_port_name get_port_name;
3695 struct lpfc_mbx_set_feature set_feature;
3696 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3697 struct lpfc_mbx_set_host_data set_host_data;
3698 struct lpfc_mbx_nop nop;
3704 #define lpfc_mcqe_status_SHIFT 0
3705 #define lpfc_mcqe_status_MASK 0x0000FFFF
3706 #define lpfc_mcqe_status_WORD word0
3707 #define lpfc_mcqe_ext_status_SHIFT 16
3708 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3709 #define lpfc_mcqe_ext_status_WORD word0
3713 #define lpfc_trailer_valid_SHIFT 31
3714 #define lpfc_trailer_valid_MASK 0x00000001
3715 #define lpfc_trailer_valid_WORD trailer
3716 #define lpfc_trailer_async_SHIFT 30
3717 #define lpfc_trailer_async_MASK 0x00000001
3718 #define lpfc_trailer_async_WORD trailer
3719 #define lpfc_trailer_hpi_SHIFT 29
3720 #define lpfc_trailer_hpi_MASK 0x00000001
3721 #define lpfc_trailer_hpi_WORD trailer
3722 #define lpfc_trailer_completed_SHIFT 28
3723 #define lpfc_trailer_completed_MASK 0x00000001
3724 #define lpfc_trailer_completed_WORD trailer
3725 #define lpfc_trailer_consumed_SHIFT 27
3726 #define lpfc_trailer_consumed_MASK 0x00000001
3727 #define lpfc_trailer_consumed_WORD trailer
3728 #define lpfc_trailer_type_SHIFT 16
3729 #define lpfc_trailer_type_MASK 0x000000FF
3730 #define lpfc_trailer_type_WORD trailer
3731 #define lpfc_trailer_code_SHIFT 8
3732 #define lpfc_trailer_code_MASK 0x000000FF
3733 #define lpfc_trailer_code_WORD trailer
3734 #define LPFC_TRAILER_CODE_LINK 0x1
3735 #define LPFC_TRAILER_CODE_FCOE 0x2
3736 #define LPFC_TRAILER_CODE_DCBX 0x3
3737 #define LPFC_TRAILER_CODE_GRP5 0x5
3738 #define LPFC_TRAILER_CODE_FC 0x10
3739 #define LPFC_TRAILER_CODE_SLI 0x11
3742 struct lpfc_acqe_link {
3744 #define lpfc_acqe_link_speed_SHIFT 24
3745 #define lpfc_acqe_link_speed_MASK 0x000000FF
3746 #define lpfc_acqe_link_speed_WORD word0
3747 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
3748 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
3749 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
3750 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
3751 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
3752 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
3753 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
3754 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
3755 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
3756 #define lpfc_acqe_link_duplex_SHIFT 16
3757 #define lpfc_acqe_link_duplex_MASK 0x000000FF
3758 #define lpfc_acqe_link_duplex_WORD word0
3759 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
3760 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
3761 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
3762 #define lpfc_acqe_link_status_SHIFT 8
3763 #define lpfc_acqe_link_status_MASK 0x000000FF
3764 #define lpfc_acqe_link_status_WORD word0
3765 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3766 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3767 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3768 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3769 #define lpfc_acqe_link_type_SHIFT 6
3770 #define lpfc_acqe_link_type_MASK 0x00000003
3771 #define lpfc_acqe_link_type_WORD word0
3772 #define lpfc_acqe_link_number_SHIFT 0
3773 #define lpfc_acqe_link_number_MASK 0x0000003F
3774 #define lpfc_acqe_link_number_WORD word0
3776 #define lpfc_acqe_link_fault_SHIFT 0
3777 #define lpfc_acqe_link_fault_MASK 0x000000FF
3778 #define lpfc_acqe_link_fault_WORD word1
3779 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3780 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3781 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3782 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
3783 #define lpfc_acqe_logical_link_speed_SHIFT 16
3784 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3785 #define lpfc_acqe_logical_link_speed_WORD word1
3788 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3789 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3792 struct lpfc_acqe_fip {
3795 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3796 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3797 #define lpfc_acqe_fip_fcf_count_WORD word1
3798 #define lpfc_acqe_fip_event_type_SHIFT 16
3799 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3800 #define lpfc_acqe_fip_event_type_WORD word1
3803 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3804 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3805 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3806 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3807 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3810 struct lpfc_acqe_dcbx {
3817 struct lpfc_acqe_grp5 {
3819 #define lpfc_acqe_grp5_type_SHIFT 6
3820 #define lpfc_acqe_grp5_type_MASK 0x00000003
3821 #define lpfc_acqe_grp5_type_WORD word0
3822 #define lpfc_acqe_grp5_number_SHIFT 0
3823 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3824 #define lpfc_acqe_grp5_number_WORD word0
3826 #define lpfc_acqe_grp5_llink_spd_SHIFT 16
3827 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3828 #define lpfc_acqe_grp5_llink_spd_WORD word1
3833 struct lpfc_acqe_fc_la {
3835 #define lpfc_acqe_fc_la_speed_SHIFT 24
3836 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3837 #define lpfc_acqe_fc_la_speed_WORD word0
3838 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
3839 #define LPFC_FC_LA_SPEED_1G 0x1
3840 #define LPFC_FC_LA_SPEED_2G 0x2
3841 #define LPFC_FC_LA_SPEED_4G 0x4
3842 #define LPFC_FC_LA_SPEED_8G 0x8
3843 #define LPFC_FC_LA_SPEED_10G 0xA
3844 #define LPFC_FC_LA_SPEED_16G 0x10
3845 #define LPFC_FC_LA_SPEED_32G 0x20
3846 #define LPFC_FC_LA_SPEED_64G 0x21
3847 #define LPFC_FC_LA_SPEED_128G 0x22
3848 #define LPFC_FC_LA_SPEED_256G 0x23
3849 #define lpfc_acqe_fc_la_topology_SHIFT 16
3850 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3851 #define lpfc_acqe_fc_la_topology_WORD word0
3852 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3853 #define LPFC_FC_LA_TOP_P2P 0x1
3854 #define LPFC_FC_LA_TOP_FCAL 0x2
3855 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3856 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3857 #define lpfc_acqe_fc_la_att_type_SHIFT 8
3858 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3859 #define lpfc_acqe_fc_la_att_type_WORD word0
3860 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3861 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
3862 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
3863 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
3864 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
3865 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
3866 #define lpfc_acqe_fc_la_port_type_SHIFT 6
3867 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
3868 #define lpfc_acqe_fc_la_port_type_WORD word0
3869 #define LPFC_LINK_TYPE_ETHERNET 0x0
3870 #define LPFC_LINK_TYPE_FC 0x1
3871 #define lpfc_acqe_fc_la_port_number_SHIFT 0
3872 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
3873 #define lpfc_acqe_fc_la_port_number_WORD word0
3875 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16
3876 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
3877 #define lpfc_acqe_fc_la_llink_spd_WORD word1
3878 #define lpfc_acqe_fc_la_fault_SHIFT 0
3879 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
3880 #define lpfc_acqe_fc_la_fault_WORD word1
3881 #define LPFC_FC_LA_FAULT_NONE 0x0
3882 #define LPFC_FC_LA_FAULT_LOCAL 0x1
3883 #define LPFC_FC_LA_FAULT_REMOTE 0x2
3886 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
3887 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
3890 struct lpfc_acqe_misconfigured_event {
3893 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
3894 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
3895 #define lpfc_sli_misconfigured_port0_state_WORD word0
3896 #define lpfc_sli_misconfigured_port1_state_SHIFT 8
3897 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
3898 #define lpfc_sli_misconfigured_port1_state_WORD word0
3899 #define lpfc_sli_misconfigured_port2_state_SHIFT 16
3900 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
3901 #define lpfc_sli_misconfigured_port2_state_WORD word0
3902 #define lpfc_sli_misconfigured_port3_state_SHIFT 24
3903 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
3904 #define lpfc_sli_misconfigured_port3_state_WORD word0
3906 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
3907 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
3908 #define lpfc_sli_misconfigured_port0_op_WORD word1
3909 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1
3910 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
3911 #define lpfc_sli_misconfigured_port0_severity_WORD word1
3912 #define lpfc_sli_misconfigured_port1_op_SHIFT 8
3913 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
3914 #define lpfc_sli_misconfigured_port1_op_WORD word1
3915 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9
3916 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
3917 #define lpfc_sli_misconfigured_port1_severity_WORD word1
3918 #define lpfc_sli_misconfigured_port2_op_SHIFT 16
3919 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
3920 #define lpfc_sli_misconfigured_port2_op_WORD word1
3921 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17
3922 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
3923 #define lpfc_sli_misconfigured_port2_severity_WORD word1
3924 #define lpfc_sli_misconfigured_port3_op_SHIFT 24
3925 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
3926 #define lpfc_sli_misconfigured_port3_op_WORD word1
3927 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25
3928 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
3929 #define lpfc_sli_misconfigured_port3_severity_WORD word1
3931 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
3932 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
3933 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
3934 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
3935 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
3936 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
3939 struct lpfc_acqe_sli {
3940 uint32_t event_data1;
3941 uint32_t event_data2;
3944 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
3945 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
3946 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
3947 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
3948 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
3949 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
3950 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
3954 * Define the bootstrap mailbox (bmbx) region used to communicate
3955 * mailbox command between the host and port. The mailbox consists
3956 * of a payload area of 256 bytes and a completion queue of length
3959 struct lpfc_bmbx_create {
3960 struct lpfc_mqe mqe;
3961 struct lpfc_mcqe mcqe;
3964 #define SGL_ALIGN_SZ 64
3965 #define SGL_PAGE_SIZE 4096
3966 /* align SGL addr on a size boundary - adjust address up */
3967 #define NO_XRI 0xffff
3971 #define wqe_xri_tag_SHIFT 0
3972 #define wqe_xri_tag_MASK 0x0000FFFF
3973 #define wqe_xri_tag_WORD word6
3974 #define wqe_ctxt_tag_SHIFT 16
3975 #define wqe_ctxt_tag_MASK 0x0000FFFF
3976 #define wqe_ctxt_tag_WORD word6
3978 #define wqe_dif_SHIFT 0
3979 #define wqe_dif_MASK 0x00000003
3980 #define wqe_dif_WORD word7
3981 #define LPFC_WQE_DIF_PASSTHRU 1
3982 #define LPFC_WQE_DIF_STRIP 2
3983 #define LPFC_WQE_DIF_INSERT 3
3984 #define wqe_ct_SHIFT 2
3985 #define wqe_ct_MASK 0x00000003
3986 #define wqe_ct_WORD word7
3987 #define wqe_status_SHIFT 4
3988 #define wqe_status_MASK 0x0000000f
3989 #define wqe_status_WORD word7
3990 #define wqe_cmnd_SHIFT 8
3991 #define wqe_cmnd_MASK 0x000000ff
3992 #define wqe_cmnd_WORD word7
3993 #define wqe_class_SHIFT 16
3994 #define wqe_class_MASK 0x00000007
3995 #define wqe_class_WORD word7
3996 #define wqe_ar_SHIFT 19
3997 #define wqe_ar_MASK 0x00000001
3998 #define wqe_ar_WORD word7
3999 #define wqe_ag_SHIFT wqe_ar_SHIFT
4000 #define wqe_ag_MASK wqe_ar_MASK
4001 #define wqe_ag_WORD wqe_ar_WORD
4002 #define wqe_pu_SHIFT 20
4003 #define wqe_pu_MASK 0x00000003
4004 #define wqe_pu_WORD word7
4005 #define wqe_erp_SHIFT 22
4006 #define wqe_erp_MASK 0x00000001
4007 #define wqe_erp_WORD word7
4008 #define wqe_conf_SHIFT wqe_erp_SHIFT
4009 #define wqe_conf_MASK wqe_erp_MASK
4010 #define wqe_conf_WORD wqe_erp_WORD
4011 #define wqe_lnk_SHIFT 23
4012 #define wqe_lnk_MASK 0x00000001
4013 #define wqe_lnk_WORD word7
4014 #define wqe_tmo_SHIFT 24
4015 #define wqe_tmo_MASK 0x000000ff
4016 #define wqe_tmo_WORD word7
4017 uint32_t abort_tag; /* word 8 in WQE */
4019 #define wqe_reqtag_SHIFT 0
4020 #define wqe_reqtag_MASK 0x0000FFFF
4021 #define wqe_reqtag_WORD word9
4022 #define wqe_temp_rpi_SHIFT 16
4023 #define wqe_temp_rpi_MASK 0x0000FFFF
4024 #define wqe_temp_rpi_WORD word9
4025 #define wqe_rcvoxid_SHIFT 16
4026 #define wqe_rcvoxid_MASK 0x0000FFFF
4027 #define wqe_rcvoxid_WORD word9
4029 #define wqe_ebde_cnt_SHIFT 0
4030 #define wqe_ebde_cnt_MASK 0x0000000f
4031 #define wqe_ebde_cnt_WORD word10
4032 #define wqe_nvme_SHIFT 4
4033 #define wqe_nvme_MASK 0x00000001
4034 #define wqe_nvme_WORD word10
4035 #define wqe_oas_SHIFT 6
4036 #define wqe_oas_MASK 0x00000001
4037 #define wqe_oas_WORD word10
4038 #define wqe_lenloc_SHIFT 7
4039 #define wqe_lenloc_MASK 0x00000003
4040 #define wqe_lenloc_WORD word10
4041 #define LPFC_WQE_LENLOC_NONE 0
4042 #define LPFC_WQE_LENLOC_WORD3 1
4043 #define LPFC_WQE_LENLOC_WORD12 2
4044 #define LPFC_WQE_LENLOC_WORD4 3
4045 #define wqe_qosd_SHIFT 9
4046 #define wqe_qosd_MASK 0x00000001
4047 #define wqe_qosd_WORD word10
4048 #define wqe_xbl_SHIFT 11
4049 #define wqe_xbl_MASK 0x00000001
4050 #define wqe_xbl_WORD word10
4051 #define wqe_iod_SHIFT 13
4052 #define wqe_iod_MASK 0x00000001
4053 #define wqe_iod_WORD word10
4054 #define LPFC_WQE_IOD_NONE 0
4055 #define LPFC_WQE_IOD_WRITE 0
4056 #define LPFC_WQE_IOD_READ 1
4057 #define wqe_dbde_SHIFT 14
4058 #define wqe_dbde_MASK 0x00000001
4059 #define wqe_dbde_WORD word10
4060 #define wqe_wqes_SHIFT 15
4061 #define wqe_wqes_MASK 0x00000001
4062 #define wqe_wqes_WORD word10
4063 /* Note that this field overlaps above fields */
4064 #define wqe_wqid_SHIFT 1
4065 #define wqe_wqid_MASK 0x00007fff
4066 #define wqe_wqid_WORD word10
4067 #define wqe_pri_SHIFT 16
4068 #define wqe_pri_MASK 0x00000007
4069 #define wqe_pri_WORD word10
4070 #define wqe_pv_SHIFT 19
4071 #define wqe_pv_MASK 0x00000001
4072 #define wqe_pv_WORD word10
4073 #define wqe_xc_SHIFT 21
4074 #define wqe_xc_MASK 0x00000001
4075 #define wqe_xc_WORD word10
4076 #define wqe_sr_SHIFT 22
4077 #define wqe_sr_MASK 0x00000001
4078 #define wqe_sr_WORD word10
4079 #define wqe_ccpe_SHIFT 23
4080 #define wqe_ccpe_MASK 0x00000001
4081 #define wqe_ccpe_WORD word10
4082 #define wqe_ccp_SHIFT 24
4083 #define wqe_ccp_MASK 0x000000ff
4084 #define wqe_ccp_WORD word10
4086 #define wqe_cmd_type_SHIFT 0
4087 #define wqe_cmd_type_MASK 0x0000000f
4088 #define wqe_cmd_type_WORD word11
4089 #define wqe_els_id_SHIFT 4
4090 #define wqe_els_id_MASK 0x00000003
4091 #define wqe_els_id_WORD word11
4092 #define LPFC_ELS_ID_FLOGI 3
4093 #define LPFC_ELS_ID_FDISC 2
4094 #define LPFC_ELS_ID_LOGO 1
4095 #define LPFC_ELS_ID_DEFAULT 0
4096 #define wqe_irsp_SHIFT 4
4097 #define wqe_irsp_MASK 0x00000001
4098 #define wqe_irsp_WORD word11
4099 #define wqe_pbde_SHIFT 5
4100 #define wqe_pbde_MASK 0x00000001
4101 #define wqe_pbde_WORD word11
4102 #define wqe_sup_SHIFT 6
4103 #define wqe_sup_MASK 0x00000001
4104 #define wqe_sup_WORD word11
4105 #define wqe_wqec_SHIFT 7
4106 #define wqe_wqec_MASK 0x00000001
4107 #define wqe_wqec_WORD word11
4108 #define wqe_irsplen_SHIFT 8
4109 #define wqe_irsplen_MASK 0x0000000f
4110 #define wqe_irsplen_WORD word11
4111 #define wqe_cqid_SHIFT 16
4112 #define wqe_cqid_MASK 0x0000ffff
4113 #define wqe_cqid_WORD word11
4114 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4119 #define wqe_els_did_SHIFT 0
4120 #define wqe_els_did_MASK 0x00FFFFFF
4121 #define wqe_els_did_WORD word5
4122 #define wqe_xmit_bls_pt_SHIFT 28
4123 #define wqe_xmit_bls_pt_MASK 0x00000003
4124 #define wqe_xmit_bls_pt_WORD word5
4125 #define wqe_xmit_bls_ar_SHIFT 30
4126 #define wqe_xmit_bls_ar_MASK 0x00000001
4127 #define wqe_xmit_bls_ar_WORD word5
4128 #define wqe_xmit_bls_xo_SHIFT 31
4129 #define wqe_xmit_bls_xo_MASK 0x00000001
4130 #define wqe_xmit_bls_xo_WORD word5
4133 struct lpfc_wqe_generic{
4134 struct ulp_bde64 bde;
4138 struct wqe_common wqe_com;
4139 uint32_t payload[4];
4142 struct els_request64_wqe {
4143 struct ulp_bde64 bde;
4144 uint32_t payload_len;
4146 #define els_req64_sid_SHIFT 0
4147 #define els_req64_sid_MASK 0x00FFFFFF
4148 #define els_req64_sid_WORD word4
4149 #define els_req64_sp_SHIFT 24
4150 #define els_req64_sp_MASK 0x00000001
4151 #define els_req64_sp_WORD word4
4152 #define els_req64_vf_SHIFT 25
4153 #define els_req64_vf_MASK 0x00000001
4154 #define els_req64_vf_WORD word4
4155 struct wqe_did wqe_dest;
4156 struct wqe_common wqe_com; /* words 6-11 */
4158 #define els_req64_vfid_SHIFT 1
4159 #define els_req64_vfid_MASK 0x00000FFF
4160 #define els_req64_vfid_WORD word12
4161 #define els_req64_pri_SHIFT 13
4162 #define els_req64_pri_MASK 0x00000007
4163 #define els_req64_pri_WORD word12
4165 #define els_req64_hopcnt_SHIFT 24
4166 #define els_req64_hopcnt_MASK 0x000000ff
4167 #define els_req64_hopcnt_WORD word13
4169 uint32_t max_response_payload_len;
4172 struct xmit_els_rsp64_wqe {
4173 struct ulp_bde64 bde;
4174 uint32_t response_payload_len;
4176 #define els_rsp64_sid_SHIFT 0
4177 #define els_rsp64_sid_MASK 0x00FFFFFF
4178 #define els_rsp64_sid_WORD word4
4179 #define els_rsp64_sp_SHIFT 24
4180 #define els_rsp64_sp_MASK 0x00000001
4181 #define els_rsp64_sp_WORD word4
4182 struct wqe_did wqe_dest;
4183 struct wqe_common wqe_com; /* words 6-11 */
4185 #define wqe_rsp_temp_rpi_SHIFT 0
4186 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4187 #define wqe_rsp_temp_rpi_WORD word12
4188 uint32_t rsvd_13_15[3];
4191 struct xmit_bls_rsp64_wqe {
4193 /* Payload0 for BA_ACC */
4194 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16
4195 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4196 #define xmit_bls_rsp64_acc_seq_id_WORD payload0
4197 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
4198 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4199 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
4200 /* Payload0 for BA_RJT */
4201 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4202 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4203 #define xmit_bls_rsp64_rjt_vspec_WORD payload0
4204 #define xmit_bls_rsp64_rjt_expc_SHIFT 8
4205 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4206 #define xmit_bls_rsp64_rjt_expc_WORD payload0
4207 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
4208 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4209 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0
4211 #define xmit_bls_rsp64_rxid_SHIFT 0
4212 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4213 #define xmit_bls_rsp64_rxid_WORD word1
4214 #define xmit_bls_rsp64_oxid_SHIFT 16
4215 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4216 #define xmit_bls_rsp64_oxid_WORD word1
4218 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4219 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4220 #define xmit_bls_rsp64_seqcnthi_WORD word2
4221 #define xmit_bls_rsp64_seqcntlo_SHIFT 16
4222 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4223 #define xmit_bls_rsp64_seqcntlo_WORD word2
4226 struct wqe_did wqe_dest;
4227 struct wqe_common wqe_com; /* words 6-11 */
4229 #define xmit_bls_rsp64_temprpi_SHIFT 0
4230 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4231 #define xmit_bls_rsp64_temprpi_WORD word12
4232 uint32_t rsvd_13_15[3];
4235 struct wqe_rctl_dfctl {
4237 #define wqe_si_SHIFT 2
4238 #define wqe_si_MASK 0x000000001
4239 #define wqe_si_WORD word5
4240 #define wqe_la_SHIFT 3
4241 #define wqe_la_MASK 0x000000001
4242 #define wqe_la_WORD word5
4243 #define wqe_xo_SHIFT 6
4244 #define wqe_xo_MASK 0x000000001
4245 #define wqe_xo_WORD word5
4246 #define wqe_ls_SHIFT 7
4247 #define wqe_ls_MASK 0x000000001
4248 #define wqe_ls_WORD word5
4249 #define wqe_dfctl_SHIFT 8
4250 #define wqe_dfctl_MASK 0x0000000ff
4251 #define wqe_dfctl_WORD word5
4252 #define wqe_type_SHIFT 16
4253 #define wqe_type_MASK 0x0000000ff
4254 #define wqe_type_WORD word5
4255 #define wqe_rctl_SHIFT 24
4256 #define wqe_rctl_MASK 0x0000000ff
4257 #define wqe_rctl_WORD word5
4260 struct xmit_seq64_wqe {
4261 struct ulp_bde64 bde;
4263 uint32_t relative_offset;
4264 struct wqe_rctl_dfctl wge_ctl;
4265 struct wqe_common wqe_com; /* words 6-11 */
4267 uint32_t rsvd_12_15[3];
4269 struct xmit_bcast64_wqe {
4270 struct ulp_bde64 bde;
4271 uint32_t seq_payload_len;
4273 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4274 struct wqe_common wqe_com; /* words 6-11 */
4275 uint32_t rsvd_12_15[4];
4278 struct gen_req64_wqe {
4279 struct ulp_bde64 bde;
4280 uint32_t request_payload_len;
4281 uint32_t relative_offset;
4282 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4283 struct wqe_common wqe_com; /* words 6-11 */
4284 uint32_t rsvd_12_14[3];
4285 uint32_t max_response_payload_len;
4288 /* Define NVME PRLI request to fabric. NVME is a
4289 * fabric-only protocol.
4290 * Updated to red-lined v1.08 on Sept 16, 2016
4292 struct lpfc_nvme_prli {
4294 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4295 #define prli_acc_rsp_code_SHIFT 8
4296 #define prli_acc_rsp_code_MASK 0x0000000f
4297 #define prli_acc_rsp_code_WORD word1
4298 #define prli_estabImagePair_SHIFT 13
4299 #define prli_estabImagePair_MASK 0x00000001
4300 #define prli_estabImagePair_WORD word1
4301 #define prli_type_code_ext_SHIFT 16
4302 #define prli_type_code_ext_MASK 0x000000ff
4303 #define prli_type_code_ext_WORD word1
4304 #define prli_type_code_SHIFT 24
4305 #define prli_type_code_MASK 0x000000ff
4306 #define prli_type_code_WORD word1
4307 uint32_t word_rsvd2;
4308 uint32_t word_rsvd3;
4310 #define prli_fba_SHIFT 0
4311 #define prli_fba_MASK 0x00000001
4312 #define prli_fba_WORD word4
4313 #define prli_disc_SHIFT 3
4314 #define prli_disc_MASK 0x00000001
4315 #define prli_disc_WORD word4
4316 #define prli_tgt_SHIFT 4
4317 #define prli_tgt_MASK 0x00000001
4318 #define prli_tgt_WORD word4
4319 #define prli_init_SHIFT 5
4320 #define prli_init_MASK 0x00000001
4321 #define prli_init_WORD word4
4322 #define prli_conf_SHIFT 7
4323 #define prli_conf_MASK 0x00000001
4324 #define prli_conf_WORD word4
4326 #define prli_fb_sz_SHIFT 0
4327 #define prli_fb_sz_MASK 0x0000ffff
4328 #define prli_fb_sz_WORD word5
4329 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */
4332 struct create_xri_wqe {
4333 uint32_t rsrvd[5]; /* words 0-4 */
4334 struct wqe_did wqe_dest; /* word 5 */
4335 struct wqe_common wqe_com; /* words 6-11 */
4336 uint32_t rsvd_12_15[4]; /* word 12-15 */
4339 #define T_REQUEST_TAG 3
4342 struct abort_cmd_wqe {
4345 #define abort_cmd_ia_SHIFT 0
4346 #define abort_cmd_ia_MASK 0x000000001
4347 #define abort_cmd_ia_WORD word3
4348 #define abort_cmd_criteria_SHIFT 8
4349 #define abort_cmd_criteria_MASK 0x0000000ff
4350 #define abort_cmd_criteria_WORD word3
4353 struct wqe_common wqe_com; /* words 6-11 */
4354 uint32_t rsvd_12_15[4]; /* word 12-15 */
4357 struct fcp_iwrite64_wqe {
4358 struct ulp_bde64 bde;
4360 #define cmd_buff_len_SHIFT 16
4361 #define cmd_buff_len_MASK 0x00000ffff
4362 #define cmd_buff_len_WORD word3
4363 #define payload_offset_len_SHIFT 0
4364 #define payload_offset_len_MASK 0x0000ffff
4365 #define payload_offset_len_WORD word3
4366 uint32_t total_xfer_len;
4367 uint32_t initial_xfer_len;
4368 struct wqe_common wqe_com; /* words 6-11 */
4370 struct ulp_bde64 ph_bde; /* words 13-15 */
4373 struct fcp_iread64_wqe {
4374 struct ulp_bde64 bde;
4376 #define cmd_buff_len_SHIFT 16
4377 #define cmd_buff_len_MASK 0x00000ffff
4378 #define cmd_buff_len_WORD word3
4379 #define payload_offset_len_SHIFT 0
4380 #define payload_offset_len_MASK 0x0000ffff
4381 #define payload_offset_len_WORD word3
4382 uint32_t total_xfer_len; /* word 4 */
4383 uint32_t rsrvd5; /* word 5 */
4384 struct wqe_common wqe_com; /* words 6-11 */
4386 struct ulp_bde64 ph_bde; /* words 13-15 */
4389 struct fcp_icmnd64_wqe {
4390 struct ulp_bde64 bde; /* words 0-2 */
4392 #define cmd_buff_len_SHIFT 16
4393 #define cmd_buff_len_MASK 0x00000ffff
4394 #define cmd_buff_len_WORD word3
4395 #define payload_offset_len_SHIFT 0
4396 #define payload_offset_len_MASK 0x0000ffff
4397 #define payload_offset_len_WORD word3
4398 uint32_t rsrvd4; /* word 4 */
4399 uint32_t rsrvd5; /* word 5 */
4400 struct wqe_common wqe_com; /* words 6-11 */
4401 uint32_t rsvd_12_15[4]; /* word 12-15 */
4404 struct fcp_trsp64_wqe {
4405 struct ulp_bde64 bde;
4406 uint32_t response_len;
4407 uint32_t rsvd_4_5[2];
4408 struct wqe_common wqe_com; /* words 6-11 */
4409 uint32_t rsvd_12_15[4]; /* word 12-15 */
4412 struct fcp_tsend64_wqe {
4413 struct ulp_bde64 bde;
4414 uint32_t payload_offset_len;
4415 uint32_t relative_offset;
4417 struct wqe_common wqe_com; /* words 6-11 */
4418 uint32_t fcp_data_len; /* word 12 */
4419 uint32_t rsvd_13_15[3]; /* word 13-15 */
4422 struct fcp_treceive64_wqe {
4423 struct ulp_bde64 bde;
4424 uint32_t payload_offset_len;
4425 uint32_t relative_offset;
4427 struct wqe_common wqe_com; /* words 6-11 */
4428 uint32_t fcp_data_len; /* word 12 */
4429 uint32_t rsvd_13_15[3]; /* word 13-15 */
4431 #define TXRDY_PAYLOAD_LEN 12
4433 #define CMD_SEND_FRAME 0xE1
4435 struct send_frame_wqe {
4436 struct ulp_bde64 bde; /* words 0-2 */
4437 uint32_t frame_len; /* word 3 */
4438 uint32_t fc_hdr_wd0; /* word 4 */
4439 uint32_t fc_hdr_wd1; /* word 5 */
4440 struct wqe_common wqe_com; /* words 6-11 */
4441 uint32_t fc_hdr_wd2; /* word 12 */
4442 uint32_t fc_hdr_wd3; /* word 13 */
4443 uint32_t fc_hdr_wd4; /* word 14 */
4444 uint32_t fc_hdr_wd5; /* word 15 */
4449 struct lpfc_wqe_generic generic;
4450 struct fcp_icmnd64_wqe fcp_icmd;
4451 struct fcp_iread64_wqe fcp_iread;
4452 struct fcp_iwrite64_wqe fcp_iwrite;
4453 struct abort_cmd_wqe abort_cmd;
4454 struct create_xri_wqe create_xri;
4455 struct xmit_bcast64_wqe xmit_bcast64;
4456 struct xmit_seq64_wqe xmit_sequence;
4457 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4458 struct xmit_els_rsp64_wqe xmit_els_rsp;
4459 struct els_request64_wqe els_req;
4460 struct gen_req64_wqe gen_req;
4461 struct fcp_trsp64_wqe fcp_trsp;
4462 struct fcp_tsend64_wqe fcp_tsend;
4463 struct fcp_treceive64_wqe fcp_treceive;
4464 struct send_frame_wqe send_frame;
4469 struct lpfc_wqe_generic generic;
4470 struct fcp_icmnd64_wqe fcp_icmd;
4471 struct fcp_iread64_wqe fcp_iread;
4472 struct fcp_iwrite64_wqe fcp_iwrite;
4473 struct abort_cmd_wqe abort_cmd;
4474 struct create_xri_wqe create_xri;
4475 struct xmit_bcast64_wqe xmit_bcast64;
4476 struct xmit_seq64_wqe xmit_sequence;
4477 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4478 struct xmit_els_rsp64_wqe xmit_els_rsp;
4479 struct els_request64_wqe els_req;
4480 struct gen_req64_wqe gen_req;
4481 struct fcp_trsp64_wqe fcp_trsp;
4482 struct fcp_tsend64_wqe fcp_tsend;
4483 struct fcp_treceive64_wqe fcp_treceive;
4484 struct send_frame_wqe send_frame;
4487 #define MAGIC_NUMER_G6 0xFEAA0003
4488 #define MAGIC_NUMER_G7 0xFEAA0005
4490 struct lpfc_grp_hdr {
4492 uint32_t magic_number;
4494 #define lpfc_grp_hdr_file_type_SHIFT 24
4495 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4496 #define lpfc_grp_hdr_file_type_WORD word2
4497 #define lpfc_grp_hdr_id_SHIFT 16
4498 #define lpfc_grp_hdr_id_MASK 0x000000FF
4499 #define lpfc_grp_hdr_id_WORD word2
4500 uint8_t rev_name[128];
4502 uint8_t revision[32];
4505 /* Defines for WQE command type */
4506 #define FCP_COMMAND 0x0
4507 #define NVME_READ_CMD 0x0
4508 #define FCP_COMMAND_DATA_OUT 0x1
4509 #define NVME_WRITE_CMD 0x1
4510 #define FCP_COMMAND_TRECEIVE 0x2
4511 #define FCP_COMMAND_TRSP 0x3
4512 #define FCP_COMMAND_TSEND 0x7
4513 #define OTHER_COMMAND 0x8
4514 #define ELS_COMMAND_NON_FIP 0xC
4515 #define ELS_COMMAND_FIP 0xD
4517 #define LPFC_NVME_EMBED_CMD 0x0
4518 #define LPFC_NVME_EMBED_WRITE 0x1
4519 #define LPFC_NVME_EMBED_READ 0x2
4522 #define CMD_ABORT_XRI_WQE 0x0F
4523 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4524 #define CMD_XMIT_BCAST64_WQE 0x84
4525 #define CMD_ELS_REQUEST64_WQE 0x8A
4526 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4527 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4528 #define CMD_FCP_IWRITE64_WQE 0x98
4529 #define CMD_FCP_IREAD64_WQE 0x9A
4530 #define CMD_FCP_ICMND64_WQE 0x9C
4531 #define CMD_FCP_TSEND64_WQE 0x9F
4532 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4533 #define CMD_FCP_TRSP64_WQE 0xA3
4534 #define CMD_GEN_REQUEST64_WQE 0xC2
4536 #define CMD_WQE_MASK 0xff
4539 #define LPFC_FW_DUMP 1
4540 #define LPFC_FW_RESET 2
4541 #define LPFC_DV_RESET 3