drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009-2016 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get_be32(name, ptr) \
  45         ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  46 #define bf_get_le32(name, ptr) \
  47         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  48 #define bf_get(name, ptr) \
  49         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  50 #define bf_set_le32(name, ptr, value) \
  51         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  52         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  53         ~(name##_MASK << name##_SHIFT)))))
  54 #define bf_set(name, ptr, value) \
  55         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  56                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  57
  58 struct dma_address {
  59         uint32_t addr_lo;
  60         uint32_t addr_hi;
  61 };
  62
  63 struct lpfc_sli_intf {
  64         uint32_t word0;
  65 #define lpfc_sli_intf_valid_SHIFT               29
  66 #define lpfc_sli_intf_valid_MASK                0x00000007
  67 #define lpfc_sli_intf_valid_WORD                word0
  68 #define LPFC_SLI_INTF_VALID             6
  69 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  70 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  71 #define lpfc_sli_intf_sli_hint2_WORD            word0
  72 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  73 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  74 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  75 #define lpfc_sli_intf_sli_hint1_WORD            word0
  76 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  77 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  78 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  79 #define lpfc_sli_intf_if_type_SHIFT             12
  80 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  81 #define lpfc_sli_intf_if_type_WORD              word0
  82 #define LPFC_SLI_INTF_IF_TYPE_0         0
  83 #define LPFC_SLI_INTF_IF_TYPE_1         1
  84 #define LPFC_SLI_INTF_IF_TYPE_2         2
  85 #define lpfc_sli_intf_sli_family_SHIFT          8
  86 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
  87 #define lpfc_sli_intf_sli_family_WORD           word0
  88 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
  89 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
  90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
  91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
  92 #define lpfc_sli_intf_slirev_SHIFT              4
  93 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  94 #define lpfc_sli_intf_slirev_WORD               word0
  95 #define LPFC_SLI_INTF_REV_SLI3          3
  96 #define LPFC_SLI_INTF_REV_SLI4          4
  97 #define lpfc_sli_intf_func_type_SHIFT           0
  98 #define lpfc_sli_intf_func_type_MASK            0x00000001
  99 #define lpfc_sli_intf_func_type_WORD            word0
 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 102 };
 103
 104 #define LPFC_SLI4_MBX_EMBED     true
 105 #define LPFC_SLI4_MBX_NEMBED    false
 106
 107 #define LPFC_SLI4_MB_WORD_COUNT         64
 108 #define LPFC_MAX_MQ_PAGE                8
 109 #define LPFC_MAX_WQ_PAGE_V0             4
 110 #define LPFC_MAX_WQ_PAGE                8
 111 #define LPFC_MAX_CQ_PAGE                4
 112 #define LPFC_MAX_EQ_PAGE                8
 113
 114 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 115 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 116 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 117
 118 /* Define SLI4 Alignment requirements. */
 119 #define LPFC_ALIGN_16_BYTE      16
 120 #define LPFC_ALIGN_64_BYTE      64
 121
 122 /* Define SLI4 specific definitions. */
 123 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 124 #define LPFC_MBX_CMD_HDR_LENGTH 16
 125 #define LPFC_MBX_ERROR_RANGE    0x4000
 126 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 127 #define LPFC_BMBX_BIT1_ADDR_LO  0
 128 #define LPFC_RPI_HDR_COUNT      64
 129 #define LPFC_HDR_TEMPLATE_SIZE  4096
 130 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 131 #define LPFC_FCF_RECORD_WD_CNT  132
 132 #define LPFC_ENTIRE_FCF_DATABASE 0
 133 #define LPFC_DFLT_FCF_INDEX      0
 134
 135 /* Virtual function numbers */
 136 #define LPFC_VF0                0
 137 #define LPFC_VF1                1
 138 #define LPFC_VF2                2
 139 #define LPFC_VF3                3
 140 #define LPFC_VF4                4
 141 #define LPFC_VF5                5
 142 #define LPFC_VF6                6
 143 #define LPFC_VF7                7
 144 #define LPFC_VF8                8
 145 #define LPFC_VF9                9
 146 #define LPFC_VF10               10
 147 #define LPFC_VF11               11
 148 #define LPFC_VF12               12
 149 #define LPFC_VF13               13
 150 #define LPFC_VF14               14
 151 #define LPFC_VF15               15
 152 #define LPFC_VF16               16
 153 #define LPFC_VF17               17
 154 #define LPFC_VF18               18
 155 #define LPFC_VF19               19
 156 #define LPFC_VF20               20
 157 #define LPFC_VF21               21
 158 #define LPFC_VF22               22
 159 #define LPFC_VF23               23
 160 #define LPFC_VF24               24
 161 #define LPFC_VF25               25
 162 #define LPFC_VF26               26
 163 #define LPFC_VF27               27
 164 #define LPFC_VF28               28
 165 #define LPFC_VF29               29
 166 #define LPFC_VF30               30
 167 #define LPFC_VF31               31
 168
 169 /* PCI function numbers */
 170 #define LPFC_PCI_FUNC0          0
 171 #define LPFC_PCI_FUNC1          1
 172 #define LPFC_PCI_FUNC2          2
 173 #define LPFC_PCI_FUNC3          3
 174 #define LPFC_PCI_FUNC4          4
 175
 176 /* SLI4 interface type-2 PDEV_CTL register */
 177 #define LPFC_CTL_PDEV_CTL_OFFSET        0x414
 178 #define LPFC_CTL_PDEV_CTL_DRST          0x00000001
 179 #define LPFC_CTL_PDEV_CTL_FRST          0x00000002
 180 #define LPFC_CTL_PDEV_CTL_DD            0x00000004
 181 #define LPFC_CTL_PDEV_CTL_LC            0x00000008
 182 #define LPFC_CTL_PDEV_CTL_FRL_ALL       0x00
 183 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE   0x10
 184 #define LPFC_CTL_PDEV_CTL_FRL_NIC       0x20
 185
 186 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
 187
 188 /* Active interrupt test count */
 189 #define LPFC_ACT_INTR_CNT       4
 190
 191 /* Algrithmns for scheduling FCP commands to WQs */
 192 #define LPFC_FCP_SCHED_ROUND_ROBIN      0
 193 #define LPFC_FCP_SCHED_BY_CPU           1
 194
 195 /* Delay Multiplier constant */
 196 #define LPFC_DMULT_CONST       651042
 197
 198 /* Configuration of Interrupts / sec for entire HBA port */
 199 #define LPFC_MIN_IMAX          5000
 200 #define LPFC_MAX_IMAX          5000000
 201 #define LPFC_DEF_IMAX          50000
 202
 203 #define LPFC_MIN_CPU_MAP       0
 204 #define LPFC_MAX_CPU_MAP       2
 205 #define LPFC_HBA_CPU_MAP       1
 206 #define LPFC_DRIVER_CPU_MAP    2  /* Default */
 207
 208 /* PORT_CAPABILITIES constants. */
 209 #define LPFC_MAX_SUPPORTED_PAGES        8
 210
 211 struct ulp_bde64 {
 212         union ULP_BDE_TUS {
 213                 uint32_t w;
 214                 struct {
 215 #ifdef __BIG_ENDIAN_BITFIELD
 216                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 217                                                    VALUE !! */
 218                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 219 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 220                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 221                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 222                                                    VALUE !! */
 223 #endif
 224 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 225 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 226 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 227 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 228 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 229 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 230 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 231                 } f;
 232         } tus;
 233         uint32_t addrLow;
 234         uint32_t addrHigh;
 235 };
 236
 237 /* Maximun size of immediate data that can fit into a 128 byte WQE */
 238 #define LPFC_MAX_BDE_IMM_SIZE   64
 239
 240 struct lpfc_sli4_flags {
 241         uint32_t word0;
 242 #define lpfc_idx_rsrc_rdy_SHIFT         0
 243 #define lpfc_idx_rsrc_rdy_MASK          0x00000001
 244 #define lpfc_idx_rsrc_rdy_WORD          word0
 245 #define LPFC_IDX_RSRC_RDY               1
 246 #define lpfc_rpi_rsrc_rdy_SHIFT         1
 247 #define lpfc_rpi_rsrc_rdy_MASK          0x00000001
 248 #define lpfc_rpi_rsrc_rdy_WORD          word0
 249 #define LPFC_RPI_RSRC_RDY               1
 250 #define lpfc_vpi_rsrc_rdy_SHIFT         2
 251 #define lpfc_vpi_rsrc_rdy_MASK          0x00000001
 252 #define lpfc_vpi_rsrc_rdy_WORD          word0
 253 #define LPFC_VPI_RSRC_RDY               1
 254 #define lpfc_vfi_rsrc_rdy_SHIFT         3
 255 #define lpfc_vfi_rsrc_rdy_MASK          0x00000001
 256 #define lpfc_vfi_rsrc_rdy_WORD          word0
 257 #define LPFC_VFI_RSRC_RDY               1
 258 };
 259
 260 struct sli4_bls_rsp {
 261         uint32_t word0_rsvd;      /* Word0 must be reserved */
 262         uint32_t word1;
 263 #define lpfc_abts_orig_SHIFT      0
 264 #define lpfc_abts_orig_MASK       0x00000001
 265 #define lpfc_abts_orig_WORD       word1
 266 #define LPFC_ABTS_UNSOL_RSP       1
 267 #define LPFC_ABTS_UNSOL_INT       0
 268         uint32_t word2;
 269 #define lpfc_abts_rxid_SHIFT      0
 270 #define lpfc_abts_rxid_MASK       0x0000FFFF
 271 #define lpfc_abts_rxid_WORD       word2
 272 #define lpfc_abts_oxid_SHIFT      16
 273 #define lpfc_abts_oxid_MASK       0x0000FFFF
 274 #define lpfc_abts_oxid_WORD       word2
 275         uint32_t word3;
 276 #define lpfc_vndr_code_SHIFT    0
 277 #define lpfc_vndr_code_MASK     0x000000FF
 278 #define lpfc_vndr_code_WORD     word3
 279 #define lpfc_rsn_expln_SHIFT    8
 280 #define lpfc_rsn_expln_MASK     0x000000FF
 281 #define lpfc_rsn_expln_WORD     word3
 282 #define lpfc_rsn_code_SHIFT     16
 283 #define lpfc_rsn_code_MASK      0x000000FF
 284 #define lpfc_rsn_code_WORD      word3
 285
 286         uint32_t word4;
 287         uint32_t word5_rsvd;    /* Word5 must be reserved */
 288 };
 289
 290 /* event queue entry structure */
 291 struct lpfc_eqe {
 292         uint32_t word0;
 293 #define lpfc_eqe_resource_id_SHIFT      16
 294 #define lpfc_eqe_resource_id_MASK       0x0000FFFF
 295 #define lpfc_eqe_resource_id_WORD       word0
 296 #define lpfc_eqe_minor_code_SHIFT       4
 297 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 298 #define lpfc_eqe_minor_code_WORD        word0
 299 #define lpfc_eqe_major_code_SHIFT       1
 300 #define lpfc_eqe_major_code_MASK        0x00000007
 301 #define lpfc_eqe_major_code_WORD        word0
 302 #define lpfc_eqe_valid_SHIFT            0
 303 #define lpfc_eqe_valid_MASK             0x00000001
 304 #define lpfc_eqe_valid_WORD             word0
 305 };
 306
 307 /* completion queue entry structure (common fields for all cqe types) */
 308 struct lpfc_cqe {
 309         uint32_t reserved0;
 310         uint32_t reserved1;
 311         uint32_t reserved2;
 312         uint32_t word3;
 313 #define lpfc_cqe_valid_SHIFT            31
 314 #define lpfc_cqe_valid_MASK             0x00000001
 315 #define lpfc_cqe_valid_WORD             word3
 316 #define lpfc_cqe_code_SHIFT             16
 317 #define lpfc_cqe_code_MASK              0x000000FF
 318 #define lpfc_cqe_code_WORD              word3
 319 };
 320
 321 /* Completion Queue Entry Status Codes */
 322 #define CQE_STATUS_SUCCESS              0x0
 323 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 324 #define CQE_STATUS_REMOTE_STOP          0x2
 325 #define CQE_STATUS_LOCAL_REJECT         0x3
 326 #define CQE_STATUS_NPORT_RJT            0x4
 327 #define CQE_STATUS_FABRIC_RJT           0x5
 328 #define CQE_STATUS_NPORT_BSY            0x6
 329 #define CQE_STATUS_FABRIC_BSY           0x7
 330 #define CQE_STATUS_INTERMED_RSP         0x8
 331 #define CQE_STATUS_LS_RJT               0x9
 332 #define CQE_STATUS_CMD_REJECT           0xb
 333 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 334 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 335 #define CQE_STATUS_DI_ERROR             0x16
 336
 337 /* Used when mapping CQE status to IOCB */
 338 #define LPFC_IOCB_STATUS_MASK           0xf
 339
 340 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 341 #define CQE_HW_STATUS_NO_ERR            0x0
 342 #define CQE_HW_STATUS_UNDERRUN          0x1
 343 #define CQE_HW_STATUS_OVERRUN           0x2
 344
 345 /* Completion Queue Entry Codes */
 346 #define CQE_CODE_COMPL_WQE              0x1
 347 #define CQE_CODE_RELEASE_WQE            0x2
 348 #define CQE_CODE_RECEIVE                0x4
 349 #define CQE_CODE_XRI_ABORTED            0x5
 350 #define CQE_CODE_RECEIVE_V1             0x9
 351
 352 /*
 353  * Define mask value for xri_aborted and wcqe completed CQE extended status.
 354  * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
 355  */
 356 #define WCQE_PARAM_MASK         0x1FF
 357
 358 /* completion queue entry for wqe completions */
 359 struct lpfc_wcqe_complete {
 360         uint32_t word0;
 361 #define lpfc_wcqe_c_request_tag_SHIFT   16
 362 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 363 #define lpfc_wcqe_c_request_tag_WORD    word0
 364 #define lpfc_wcqe_c_status_SHIFT        8
 365 #define lpfc_wcqe_c_status_MASK         0x000000FF
 366 #define lpfc_wcqe_c_status_WORD         word0
 367 #define lpfc_wcqe_c_hw_status_SHIFT     0
 368 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 369 #define lpfc_wcqe_c_hw_status_WORD      word0
 370         uint32_t total_data_placed;
 371         uint32_t parameter;
 372 #define lpfc_wcqe_c_bg_edir_SHIFT       5
 373 #define lpfc_wcqe_c_bg_edir_MASK        0x00000001
 374 #define lpfc_wcqe_c_bg_edir_WORD        parameter
 375 #define lpfc_wcqe_c_bg_tdpv_SHIFT       3
 376 #define lpfc_wcqe_c_bg_tdpv_MASK        0x00000001
 377 #define lpfc_wcqe_c_bg_tdpv_WORD        parameter
 378 #define lpfc_wcqe_c_bg_re_SHIFT         2
 379 #define lpfc_wcqe_c_bg_re_MASK          0x00000001
 380 #define lpfc_wcqe_c_bg_re_WORD          parameter
 381 #define lpfc_wcqe_c_bg_ae_SHIFT         1
 382 #define lpfc_wcqe_c_bg_ae_MASK          0x00000001
 383 #define lpfc_wcqe_c_bg_ae_WORD          parameter
 384 #define lpfc_wcqe_c_bg_ge_SHIFT         0
 385 #define lpfc_wcqe_c_bg_ge_MASK          0x00000001
 386 #define lpfc_wcqe_c_bg_ge_WORD          parameter
 387         uint32_t word3;
 388 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 389 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 390 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 391 #define lpfc_wcqe_c_xb_SHIFT            28
 392 #define lpfc_wcqe_c_xb_MASK             0x00000001
 393 #define lpfc_wcqe_c_xb_WORD             word3
 394 #define lpfc_wcqe_c_pv_SHIFT            27
 395 #define lpfc_wcqe_c_pv_MASK             0x00000001
 396 #define lpfc_wcqe_c_pv_WORD             word3
 397 #define lpfc_wcqe_c_priority_SHIFT      24
 398 #define lpfc_wcqe_c_priority_MASK       0x00000007
 399 #define lpfc_wcqe_c_priority_WORD       word3
 400 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 401 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 402 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 403 };
 404
 405 /* completion queue entry for wqe release */
 406 struct lpfc_wcqe_release {
 407         uint32_t reserved0;
 408         uint32_t reserved1;
 409         uint32_t word2;
 410 #define lpfc_wcqe_r_wq_id_SHIFT         16
 411 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 412 #define lpfc_wcqe_r_wq_id_WORD          word2
 413 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 414 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 415 #define lpfc_wcqe_r_wqe_index_WORD      word2
 416         uint32_t word3;
 417 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 418 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 419 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 420 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 421 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 422 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 423 };
 424
 425 struct sli4_wcqe_xri_aborted {
 426         uint32_t word0;
 427 #define lpfc_wcqe_xa_status_SHIFT               8
 428 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 429 #define lpfc_wcqe_xa_status_WORD                word0
 430         uint32_t parameter;
 431         uint32_t word2;
 432 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 433 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 434 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 435 #define lpfc_wcqe_xa_xri_SHIFT          0
 436 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 437 #define lpfc_wcqe_xa_xri_WORD           word2
 438         uint32_t word3;
 439 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 440 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 441 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 442 #define lpfc_wcqe_xa_ia_SHIFT           30
 443 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 444 #define lpfc_wcqe_xa_ia_WORD            word3
 445 #define CQE_XRI_ABORTED_IA_REMOTE       0
 446 #define CQE_XRI_ABORTED_IA_LOCAL        1
 447 #define lpfc_wcqe_xa_br_SHIFT           29
 448 #define lpfc_wcqe_xa_br_MASK            0x00000001
 449 #define lpfc_wcqe_xa_br_WORD            word3
 450 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 451 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 452 #define lpfc_wcqe_xa_eo_SHIFT           28
 453 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 454 #define lpfc_wcqe_xa_eo_WORD            word3
 455 #define CQE_XRI_ABORTED_EO_REMOTE       0
 456 #define CQE_XRI_ABORTED_EO_LOCAL        1
 457 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 458 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 459 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 460 };
 461
 462 /* completion queue entry structure for rqe completion */
 463 struct lpfc_rcqe {
 464         uint32_t word0;
 465 #define lpfc_rcqe_bindex_SHIFT          16
 466 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 467 #define lpfc_rcqe_bindex_WORD           word0
 468 #define lpfc_rcqe_status_SHIFT          8
 469 #define lpfc_rcqe_status_MASK           0x000000FF
 470 #define lpfc_rcqe_status_WORD           word0
 471 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 472 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 473 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 474 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 475         uint32_t word1;
 476 #define lpfc_rcqe_fcf_id_v1_SHIFT       0
 477 #define lpfc_rcqe_fcf_id_v1_MASK        0x0000003F
 478 #define lpfc_rcqe_fcf_id_v1_WORD        word1
 479         uint32_t word2;
 480 #define lpfc_rcqe_length_SHIFT          16
 481 #define lpfc_rcqe_length_MASK           0x0000FFFF
 482 #define lpfc_rcqe_length_WORD           word2
 483 #define lpfc_rcqe_rq_id_SHIFT           6
 484 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 485 #define lpfc_rcqe_rq_id_WORD            word2
 486 #define lpfc_rcqe_fcf_id_SHIFT          0
 487 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 488 #define lpfc_rcqe_fcf_id_WORD           word2
 489 #define lpfc_rcqe_rq_id_v1_SHIFT        0
 490 #define lpfc_rcqe_rq_id_v1_MASK         0x0000FFFF
 491 #define lpfc_rcqe_rq_id_v1_WORD         word2
 492         uint32_t word3;
 493 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 494 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 495 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 496 #define lpfc_rcqe_port_SHIFT            30
 497 #define lpfc_rcqe_port_MASK             0x00000001
 498 #define lpfc_rcqe_port_WORD             word3
 499 #define lpfc_rcqe_hdr_length_SHIFT      24
 500 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 501 #define lpfc_rcqe_hdr_length_WORD       word3
 502 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 503 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 504 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 505 #define lpfc_rcqe_eof_SHIFT             8
 506 #define lpfc_rcqe_eof_MASK              0x000000FF
 507 #define lpfc_rcqe_eof_WORD              word3
 508 #define FCOE_EOFn       0x41
 509 #define FCOE_EOFt       0x42
 510 #define FCOE_EOFni      0x49
 511 #define FCOE_EOFa       0x50
 512 #define lpfc_rcqe_sof_SHIFT             0
 513 #define lpfc_rcqe_sof_MASK              0x000000FF
 514 #define lpfc_rcqe_sof_WORD              word3
 515 #define FCOE_SOFi2      0x2d
 516 #define FCOE_SOFi3      0x2e
 517 #define FCOE_SOFn2      0x35
 518 #define FCOE_SOFn3      0x36
 519 };
 520
 521 struct lpfc_rqe {
 522         uint32_t address_hi;
 523         uint32_t address_lo;
 524 };
 525
 526 /* buffer descriptors */
 527 struct lpfc_bde4 {
 528         uint32_t addr_hi;
 529         uint32_t addr_lo;
 530         uint32_t word2;
 531 #define lpfc_bde4_last_SHIFT            31
 532 #define lpfc_bde4_last_MASK             0x00000001
 533 #define lpfc_bde4_last_WORD             word2
 534 #define lpfc_bde4_sge_offset_SHIFT      0
 535 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 536 #define lpfc_bde4_sge_offset_WORD       word2
 537         uint32_t word3;
 538 #define lpfc_bde4_length_SHIFT          0
 539 #define lpfc_bde4_length_MASK           0x000000FF
 540 #define lpfc_bde4_length_WORD           word3
 541 };
 542
 543 struct lpfc_register {
 544         uint32_t word0;
 545 };
 546
 547 #define LPFC_PORT_SEM_UE_RECOVERABLE    0xE000
 548 #define LPFC_PORT_SEM_MASK              0xF000
 549 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 550 #define LPFC_UERR_STATUS_HI             0x00A4
 551 #define LPFC_UERR_STATUS_LO             0x00A0
 552 #define LPFC_UE_MASK_HI                 0x00AC
 553 #define LPFC_UE_MASK_LO                 0x00A8
 554
 555 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 556 #define LPFC_SLI_INTF                   0x0058
 557
 558 #define LPFC_CTL_PORT_SEM_OFFSET        0x400
 559 #define lpfc_port_smphr_perr_SHIFT      31
 560 #define lpfc_port_smphr_perr_MASK       0x1
 561 #define lpfc_port_smphr_perr_WORD       word0
 562 #define lpfc_port_smphr_sfi_SHIFT       30
 563 #define lpfc_port_smphr_sfi_MASK        0x1
 564 #define lpfc_port_smphr_sfi_WORD        word0
 565 #define lpfc_port_smphr_nip_SHIFT       29
 566 #define lpfc_port_smphr_nip_MASK        0x1
 567 #define lpfc_port_smphr_nip_WORD        word0
 568 #define lpfc_port_smphr_ipc_SHIFT       28
 569 #define lpfc_port_smphr_ipc_MASK        0x1
 570 #define lpfc_port_smphr_ipc_WORD        word0
 571 #define lpfc_port_smphr_scr1_SHIFT      27
 572 #define lpfc_port_smphr_scr1_MASK       0x1
 573 #define lpfc_port_smphr_scr1_WORD       word0
 574 #define lpfc_port_smphr_scr2_SHIFT      26
 575 #define lpfc_port_smphr_scr2_MASK       0x1
 576 #define lpfc_port_smphr_scr2_WORD       word0
 577 #define lpfc_port_smphr_host_scratch_SHIFT      16
 578 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 579 #define lpfc_port_smphr_host_scratch_WORD       word0
 580 #define lpfc_port_smphr_port_status_SHIFT       0
 581 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 582 #define lpfc_port_smphr_port_status_WORD        word0
 583
 584 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 585 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 586 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 587 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 588 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 589 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 590 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 591 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 592 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 593 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 594 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 595 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 596 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 597 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 598 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 599 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 600 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 601 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 602 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 603 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 604 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 605 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 606 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 607 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 608 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 609 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 610 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 611 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 612 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 613 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 614 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 615 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 616 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 617
 618 #define LPFC_CTL_PORT_STA_OFFSET        0x404
 619 #define lpfc_sliport_status_err_SHIFT   31
 620 #define lpfc_sliport_status_err_MASK    0x1
 621 #define lpfc_sliport_status_err_WORD    word0
 622 #define lpfc_sliport_status_end_SHIFT   30
 623 #define lpfc_sliport_status_end_MASK    0x1
 624 #define lpfc_sliport_status_end_WORD    word0
 625 #define lpfc_sliport_status_oti_SHIFT   29
 626 #define lpfc_sliport_status_oti_MASK    0x1
 627 #define lpfc_sliport_status_oti_WORD    word0
 628 #define lpfc_sliport_status_rn_SHIFT    24
 629 #define lpfc_sliport_status_rn_MASK     0x1
 630 #define lpfc_sliport_status_rn_WORD     word0
 631 #define lpfc_sliport_status_rdy_SHIFT   23
 632 #define lpfc_sliport_status_rdy_MASK    0x1
 633 #define lpfc_sliport_status_rdy_WORD    word0
 634 #define MAX_IF_TYPE_2_RESETS            6
 635
 636 #define LPFC_CTL_PORT_CTL_OFFSET        0x408
 637 #define lpfc_sliport_ctrl_end_SHIFT     30
 638 #define lpfc_sliport_ctrl_end_MASK      0x1
 639 #define lpfc_sliport_ctrl_end_WORD      word0
 640 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 641 #define LPFC_SLIPORT_BIG_ENDIAN    1
 642 #define lpfc_sliport_ctrl_ip_SHIFT      27
 643 #define lpfc_sliport_ctrl_ip_MASK       0x1
 644 #define lpfc_sliport_ctrl_ip_WORD       word0
 645 #define LPFC_SLIPORT_INIT_PORT  1
 646
 647 #define LPFC_CTL_PORT_ER1_OFFSET        0x40C
 648 #define LPFC_CTL_PORT_ER2_OFFSET        0x410
 649
 650 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 651  * reside in BAR 2.
 652  */
 653 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 654
 655 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 656 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 657
 658 #define LPFC_HST_ISR0           0x0C18
 659 #define LPFC_HST_ISR1           0x0C1C
 660 #define LPFC_HST_ISR2           0x0C20
 661 #define LPFC_HST_ISR3           0x0C24
 662 #define LPFC_HST_ISR4           0x0C28
 663
 664 #define LPFC_HST_IMR0           0x0C48
 665 #define LPFC_HST_IMR1           0x0C4C
 666 #define LPFC_HST_IMR2           0x0C50
 667 #define LPFC_HST_IMR3           0x0C54
 668 #define LPFC_HST_IMR4           0x0C58
 669
 670 #define LPFC_HST_ISCR0          0x0C78
 671 #define LPFC_HST_ISCR1          0x0C7C
 672 #define LPFC_HST_ISCR2          0x0C80
 673 #define LPFC_HST_ISCR3          0x0C84
 674 #define LPFC_HST_ISCR4          0x0C88
 675
 676 #define LPFC_SLI4_INTR0                 BIT0
 677 #define LPFC_SLI4_INTR1                 BIT1
 678 #define LPFC_SLI4_INTR2                 BIT2
 679 #define LPFC_SLI4_INTR3                 BIT3
 680 #define LPFC_SLI4_INTR4                 BIT4
 681 #define LPFC_SLI4_INTR5                 BIT5
 682 #define LPFC_SLI4_INTR6                 BIT6
 683 #define LPFC_SLI4_INTR7                 BIT7
 684 #define LPFC_SLI4_INTR8                 BIT8
 685 #define LPFC_SLI4_INTR9                 BIT9
 686 #define LPFC_SLI4_INTR10                BIT10
 687 #define LPFC_SLI4_INTR11                BIT11
 688 #define LPFC_SLI4_INTR12                BIT12
 689 #define LPFC_SLI4_INTR13                BIT13
 690 #define LPFC_SLI4_INTR14                BIT14
 691 #define LPFC_SLI4_INTR15                BIT15
 692 #define LPFC_SLI4_INTR16                BIT16
 693 #define LPFC_SLI4_INTR17                BIT17
 694 #define LPFC_SLI4_INTR18                BIT18
 695 #define LPFC_SLI4_INTR19                BIT19
 696 #define LPFC_SLI4_INTR20                BIT20
 697 #define LPFC_SLI4_INTR21                BIT21
 698 #define LPFC_SLI4_INTR22                BIT22
 699 #define LPFC_SLI4_INTR23                BIT23
 700 #define LPFC_SLI4_INTR24                BIT24
 701 #define LPFC_SLI4_INTR25                BIT25
 702 #define LPFC_SLI4_INTR26                BIT26
 703 #define LPFC_SLI4_INTR27                BIT27
 704 #define LPFC_SLI4_INTR28                BIT28
 705 #define LPFC_SLI4_INTR29                BIT29
 706 #define LPFC_SLI4_INTR30                BIT30
 707 #define LPFC_SLI4_INTR31                BIT31
 708
 709 /*
 710  * The Doorbell registers defined here exist in different BAR
 711  * register sets depending on the UCNA Port's reported if_type
 712  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 713  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 714  * BAR0.  The offsets are the same so the driver must account for
 715  * any base address difference.
 716  */
 717 #define LPFC_ULP0_RQ_DOORBELL           0x00A0
 718 #define LPFC_ULP1_RQ_DOORBELL           0x00C0
 719 #define lpfc_rq_db_list_fm_num_posted_SHIFT     24
 720 #define lpfc_rq_db_list_fm_num_posted_MASK      0x00FF
 721 #define lpfc_rq_db_list_fm_num_posted_WORD      word0
 722 #define lpfc_rq_db_list_fm_index_SHIFT          16
 723 #define lpfc_rq_db_list_fm_index_MASK           0x00FF
 724 #define lpfc_rq_db_list_fm_index_WORD           word0
 725 #define lpfc_rq_db_list_fm_id_SHIFT             0
 726 #define lpfc_rq_db_list_fm_id_MASK              0xFFFF
 727 #define lpfc_rq_db_list_fm_id_WORD              word0
 728 #define lpfc_rq_db_ring_fm_num_posted_SHIFT     16
 729 #define lpfc_rq_db_ring_fm_num_posted_MASK      0x3FFF
 730 #define lpfc_rq_db_ring_fm_num_posted_WORD      word0
 731 #define lpfc_rq_db_ring_fm_id_SHIFT             0
 732 #define lpfc_rq_db_ring_fm_id_MASK              0xFFFF
 733 #define lpfc_rq_db_ring_fm_id_WORD              word0
 734
 735 #define LPFC_ULP0_WQ_DOORBELL           0x0040
 736 #define LPFC_ULP1_WQ_DOORBELL           0x0060
 737 #define lpfc_wq_db_list_fm_num_posted_SHIFT     24
 738 #define lpfc_wq_db_list_fm_num_posted_MASK      0x00FF
 739 #define lpfc_wq_db_list_fm_num_posted_WORD      word0
 740 #define lpfc_wq_db_list_fm_index_SHIFT          16
 741 #define lpfc_wq_db_list_fm_index_MASK           0x00FF
 742 #define lpfc_wq_db_list_fm_index_WORD           word0
 743 #define lpfc_wq_db_list_fm_id_SHIFT             0
 744 #define lpfc_wq_db_list_fm_id_MASK              0xFFFF
 745 #define lpfc_wq_db_list_fm_id_WORD              word0
 746 #define lpfc_wq_db_ring_fm_num_posted_SHIFT     16
 747 #define lpfc_wq_db_ring_fm_num_posted_MASK      0x3FFF
 748 #define lpfc_wq_db_ring_fm_num_posted_WORD      word0
 749 #define lpfc_wq_db_ring_fm_id_SHIFT             0
 750 #define lpfc_wq_db_ring_fm_id_MASK              0xFFFF
 751 #define lpfc_wq_db_ring_fm_id_WORD              word0
 752
 753 #define LPFC_EQCQ_DOORBELL              0x0120
 754 #define lpfc_eqcq_doorbell_se_SHIFT             31
 755 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 756 #define lpfc_eqcq_doorbell_se_WORD              word0
 757 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 758 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 759 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 760 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 761 #define lpfc_eqcq_doorbell_arm_WORD             word0
 762 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 763 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 764 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 765 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 766 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 767 #define lpfc_eqcq_doorbell_qt_WORD              word0
 768 #define LPFC_QUEUE_TYPE_COMPLETION      0
 769 #define LPFC_QUEUE_TYPE_EVENT           1
 770 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 771 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 772 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 773 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT        0
 774 #define lpfc_eqcq_doorbell_cqid_lo_MASK         0x03FF
 775 #define lpfc_eqcq_doorbell_cqid_lo_WORD         word0
 776 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT        11
 777 #define lpfc_eqcq_doorbell_cqid_hi_MASK         0x001F
 778 #define lpfc_eqcq_doorbell_cqid_hi_WORD         word0
 779 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT        0
 780 #define lpfc_eqcq_doorbell_eqid_lo_MASK         0x01FF
 781 #define lpfc_eqcq_doorbell_eqid_lo_WORD         word0
 782 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT        11
 783 #define lpfc_eqcq_doorbell_eqid_hi_MASK         0x001F
 784 #define lpfc_eqcq_doorbell_eqid_hi_WORD         word0
 785 #define LPFC_CQID_HI_FIELD_SHIFT                10
 786 #define LPFC_EQID_HI_FIELD_SHIFT                9
 787
 788 #define LPFC_BMBX                       0x0160
 789 #define lpfc_bmbx_addr_SHIFT            2
 790 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 791 #define lpfc_bmbx_addr_WORD             word0
 792 #define lpfc_bmbx_hi_SHIFT              1
 793 #define lpfc_bmbx_hi_MASK               0x0001
 794 #define lpfc_bmbx_hi_WORD               word0
 795 #define lpfc_bmbx_rdy_SHIFT             0
 796 #define lpfc_bmbx_rdy_MASK              0x0001
 797 #define lpfc_bmbx_rdy_WORD              word0
 798
 799 #define LPFC_MQ_DOORBELL                        0x0140
 800 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 801 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 802 #define lpfc_mq_doorbell_num_posted_WORD        word0
 803 #define lpfc_mq_doorbell_id_SHIFT               0
 804 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 805 #define lpfc_mq_doorbell_id_WORD                word0
 806
 807 struct lpfc_sli4_cfg_mhdr {
 808         uint32_t word1;
 809 #define lpfc_mbox_hdr_emb_SHIFT         0
 810 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 811 #define lpfc_mbox_hdr_emb_WORD          word1
 812 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 813 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 814 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 815         uint32_t payload_length;
 816         uint32_t tag_lo;
 817         uint32_t tag_hi;
 818         uint32_t reserved5;
 819 };
 820
 821 union lpfc_sli4_cfg_shdr {
 822         struct {
 823                 uint32_t word6;
 824 #define lpfc_mbox_hdr_opcode_SHIFT      0
 825 #define lpfc_mbox_hdr_opcode_MASK       0x000000FF
 826 #define lpfc_mbox_hdr_opcode_WORD       word6
 827 #define lpfc_mbox_hdr_subsystem_SHIFT   8
 828 #define lpfc_mbox_hdr_subsystem_MASK    0x000000FF
 829 #define lpfc_mbox_hdr_subsystem_WORD    word6
 830 #define lpfc_mbox_hdr_port_number_SHIFT 16
 831 #define lpfc_mbox_hdr_port_number_MASK  0x000000FF
 832 #define lpfc_mbox_hdr_port_number_WORD  word6
 833 #define lpfc_mbox_hdr_domain_SHIFT      24
 834 #define lpfc_mbox_hdr_domain_MASK       0x000000FF
 835 #define lpfc_mbox_hdr_domain_WORD       word6
 836                 uint32_t timeout;
 837                 uint32_t request_length;
 838                 uint32_t word9;
 839 #define lpfc_mbox_hdr_version_SHIFT     0
 840 #define lpfc_mbox_hdr_version_MASK      0x000000FF
 841 #define lpfc_mbox_hdr_version_WORD      word9
 842 #define lpfc_mbox_hdr_pf_num_SHIFT      16
 843 #define lpfc_mbox_hdr_pf_num_MASK       0x000000FF
 844 #define lpfc_mbox_hdr_pf_num_WORD       word9
 845 #define lpfc_mbox_hdr_vh_num_SHIFT      24
 846 #define lpfc_mbox_hdr_vh_num_MASK       0x000000FF
 847 #define lpfc_mbox_hdr_vh_num_WORD       word9
 848 #define LPFC_Q_CREATE_VERSION_2 2
 849 #define LPFC_Q_CREATE_VERSION_1 1
 850 #define LPFC_Q_CREATE_VERSION_0 0
 851 #define LPFC_OPCODE_VERSION_0   0
 852 #define LPFC_OPCODE_VERSION_1   1
 853         } request;
 854         struct {
 855                 uint32_t word6;
 856 #define lpfc_mbox_hdr_opcode_SHIFT              0
 857 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 858 #define lpfc_mbox_hdr_opcode_WORD               word6
 859 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 860 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 861 #define lpfc_mbox_hdr_subsystem_WORD            word6
 862 #define lpfc_mbox_hdr_domain_SHIFT              24
 863 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 864 #define lpfc_mbox_hdr_domain_WORD               word6
 865                 uint32_t word7;
 866 #define lpfc_mbox_hdr_status_SHIFT              0
 867 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 868 #define lpfc_mbox_hdr_status_WORD               word7
 869 #define lpfc_mbox_hdr_add_status_SHIFT          8
 870 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 871 #define lpfc_mbox_hdr_add_status_WORD           word7
 872                 uint32_t response_length;
 873                 uint32_t actual_response_length;
 874         } response;
 875 };
 876
 877 /* Mailbox Header structures.
 878  * struct mbox_header is defined for first generation SLI4_CFG mailbox
 879  * calls deployed for BE-based ports.
 880  *
 881  * struct sli4_mbox_header is defined for second generation SLI4
 882  * ports that don't deploy the SLI4_CFG mechanism.
 883  */
 884 struct mbox_header {
 885         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 886         union  lpfc_sli4_cfg_shdr cfg_shdr;
 887 };
 888
 889 #define LPFC_EXTENT_LOCAL               0
 890 #define LPFC_TIMEOUT_DEFAULT            0
 891 #define LPFC_EXTENT_VERSION_DEFAULT     0
 892
 893 /* Subsystem Definitions */
 894 #define LPFC_MBOX_SUBSYSTEM_NA          0x0
 895 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 896 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 897
 898 /* Device Specific Definitions */
 899
 900 /* The HOST ENDIAN defines are in Big Endian format. */
 901 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 902 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 903
 904 /* Common Opcodes */
 905 #define LPFC_MBOX_OPCODE_NA                             0x00
 906 #define LPFC_MBOX_OPCODE_CQ_CREATE                      0x0C
 907 #define LPFC_MBOX_OPCODE_EQ_CREATE                      0x0D
 908 #define LPFC_MBOX_OPCODE_MQ_CREATE                      0x15
 909 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES            0x20
 910 #define LPFC_MBOX_OPCODE_NOP                            0x21
 911 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY                0x29
 912 #define LPFC_MBOX_OPCODE_MQ_DESTROY                     0x35
 913 #define LPFC_MBOX_OPCODE_CQ_DESTROY                     0x36
 914 #define LPFC_MBOX_OPCODE_EQ_DESTROY                     0x37
 915 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG                   0x3A
 916 #define LPFC_MBOX_OPCODE_FUNCTION_RESET                 0x3D
 917 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG       0x3E
 918 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG                0x43
 919 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG              0x45
 920 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG              0x46
 921 #define LPFC_MBOX_OPCODE_GET_PORT_NAME                  0x4D
 922 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT                  0x5A
 923 #define LPFC_MBOX_OPCODE_GET_VPD_DATA                   0x5B
 924 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION                0x73
 925 #define LPFC_MBOX_OPCODE_RESET_LICENSES                 0x74
 926 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO           0x9A
 927 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT          0x9B
 928 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT              0x9C
 929 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT            0x9D
 930 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG            0xA0
 931 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES         0xA1
 932 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG             0xA4
 933 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG             0xA5
 934 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST               0xA6
 935 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE                0xA8
 936 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG     0xA9
 937 #define LPFC_MBOX_OPCODE_READ_OBJECT                    0xAB
 938 #define LPFC_MBOX_OPCODE_WRITE_OBJECT                   0xAC
 939 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST               0xAD
 940 #define LPFC_MBOX_OPCODE_DELETE_OBJECT                  0xAE
 941 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS            0xB5
 942 #define LPFC_MBOX_OPCODE_SET_FEATURES                   0xBF
 943
 944 /* FCoE Opcodes */
 945 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 946 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 947 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 948 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 949 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 950 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 951 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 952 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 953 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 954 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 955 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
 956 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS       0x21
 957 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE           0x22
 958 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK        0x23
 959
 960 /* Mailbox command structures */
 961 struct eq_context {
 962         uint32_t word0;
 963 #define lpfc_eq_context_size_SHIFT      31
 964 #define lpfc_eq_context_size_MASK       0x00000001
 965 #define lpfc_eq_context_size_WORD       word0
 966 #define LPFC_EQE_SIZE_4                 0x0
 967 #define LPFC_EQE_SIZE_16                0x1
 968 #define lpfc_eq_context_valid_SHIFT     29
 969 #define lpfc_eq_context_valid_MASK      0x00000001
 970 #define lpfc_eq_context_valid_WORD      word0
 971         uint32_t word1;
 972 #define lpfc_eq_context_count_SHIFT     26
 973 #define lpfc_eq_context_count_MASK      0x00000003
 974 #define lpfc_eq_context_count_WORD      word1
 975 #define LPFC_EQ_CNT_256         0x0
 976 #define LPFC_EQ_CNT_512         0x1
 977 #define LPFC_EQ_CNT_1024        0x2
 978 #define LPFC_EQ_CNT_2048        0x3
 979 #define LPFC_EQ_CNT_4096        0x4
 980         uint32_t word2;
 981 #define lpfc_eq_context_delay_multi_SHIFT       13
 982 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 983 #define lpfc_eq_context_delay_multi_WORD        word2
 984         uint32_t reserved3;
 985 };
 986
 987 struct eq_delay_info {
 988         uint32_t eq_id;
 989         uint32_t phase;
 990         uint32_t delay_multi;
 991 };
 992 #define LPFC_MAX_EQ_DELAY       8
 993
 994 struct sgl_page_pairs {
 995         uint32_t sgl_pg0_addr_lo;
 996         uint32_t sgl_pg0_addr_hi;
 997         uint32_t sgl_pg1_addr_lo;
 998         uint32_t sgl_pg1_addr_hi;
 999 };
1000
1001 struct lpfc_mbx_post_sgl_pages {
1002         struct mbox_header header;
1003         uint32_t word0;
1004 #define lpfc_post_sgl_pages_xri_SHIFT   0
1005 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
1006 #define lpfc_post_sgl_pages_xri_WORD    word0
1007 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
1008 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1009 #define lpfc_post_sgl_pages_xricnt_WORD word0
1010         struct sgl_page_pairs  sgl_pg_pairs[1];
1011 };
1012
1013 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1014 struct lpfc_mbx_post_uembed_sgl_page1 {
1015         union  lpfc_sli4_cfg_shdr cfg_shdr;
1016         uint32_t word0;
1017         struct sgl_page_pairs sgl_pg_pairs;
1018 };
1019
1020 struct lpfc_mbx_sge {
1021         uint32_t pa_lo;
1022         uint32_t pa_hi;
1023         uint32_t length;
1024 };
1025
1026 struct lpfc_mbx_nembed_cmd {
1027         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1028 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
1029         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1030 };
1031
1032 struct lpfc_mbx_nembed_sge_virt {
1033         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1034 };
1035
1036 struct lpfc_mbx_eq_create {
1037         struct mbox_header header;
1038         union {
1039                 struct {
1040                         uint32_t word0;
1041 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
1042 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
1043 #define lpfc_mbx_eq_create_num_pages_WORD       word0
1044                         struct eq_context context;
1045                         struct dma_address page[LPFC_MAX_EQ_PAGE];
1046                 } request;
1047                 struct {
1048                         uint32_t word0;
1049 #define lpfc_mbx_eq_create_q_id_SHIFT   0
1050 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
1051 #define lpfc_mbx_eq_create_q_id_WORD    word0
1052                 } response;
1053         } u;
1054 };
1055
1056 struct lpfc_mbx_modify_eq_delay {
1057         struct mbox_header header;
1058         union {
1059                 struct {
1060                         uint32_t num_eq;
1061                         struct eq_delay_info eq[LPFC_MAX_EQ_DELAY];
1062                 } request;
1063                 struct {
1064                         uint32_t word0;
1065                 } response;
1066         } u;
1067 };
1068
1069 struct lpfc_mbx_eq_destroy {
1070         struct mbox_header header;
1071         union {
1072                 struct {
1073                         uint32_t word0;
1074 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
1075 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
1076 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
1077                 } request;
1078                 struct {
1079                         uint32_t word0;
1080                 } response;
1081         } u;
1082 };
1083
1084 struct lpfc_mbx_nop {
1085         struct mbox_header header;
1086         uint32_t context[2];
1087 };
1088
1089 struct cq_context {
1090         uint32_t word0;
1091 #define lpfc_cq_context_event_SHIFT     31
1092 #define lpfc_cq_context_event_MASK      0x00000001
1093 #define lpfc_cq_context_event_WORD      word0
1094 #define lpfc_cq_context_valid_SHIFT     29
1095 #define lpfc_cq_context_valid_MASK      0x00000001
1096 #define lpfc_cq_context_valid_WORD      word0
1097 #define lpfc_cq_context_count_SHIFT     27
1098 #define lpfc_cq_context_count_MASK      0x00000003
1099 #define lpfc_cq_context_count_WORD      word0
1100 #define LPFC_CQ_CNT_256         0x0
1101 #define LPFC_CQ_CNT_512         0x1
1102 #define LPFC_CQ_CNT_1024        0x2
1103         uint32_t word1;
1104 #define lpfc_cq_eq_id_SHIFT             22      /* Version 0 Only */
1105 #define lpfc_cq_eq_id_MASK              0x000000FF
1106 #define lpfc_cq_eq_id_WORD              word1
1107 #define lpfc_cq_eq_id_2_SHIFT           0       /* Version 2 Only */
1108 #define lpfc_cq_eq_id_2_MASK            0x0000FFFF
1109 #define lpfc_cq_eq_id_2_WORD            word1
1110         uint32_t reserved0;
1111         uint32_t reserved1;
1112 };
1113
1114 struct lpfc_mbx_cq_create {
1115         struct mbox_header header;
1116         union {
1117                 struct {
1118                         uint32_t word0;
1119 #define lpfc_mbx_cq_create_page_size_SHIFT      16      /* Version 2 Only */
1120 #define lpfc_mbx_cq_create_page_size_MASK       0x000000FF
1121 #define lpfc_mbx_cq_create_page_size_WORD       word0
1122 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
1123 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
1124 #define lpfc_mbx_cq_create_num_pages_WORD       word0
1125                         struct cq_context context;
1126                         struct dma_address page[LPFC_MAX_CQ_PAGE];
1127                 } request;
1128                 struct {
1129                         uint32_t word0;
1130 #define lpfc_mbx_cq_create_q_id_SHIFT   0
1131 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
1132 #define lpfc_mbx_cq_create_q_id_WORD    word0
1133                 } response;
1134         } u;
1135 };
1136
1137 struct lpfc_mbx_cq_destroy {
1138         struct mbox_header header;
1139         union {
1140                 struct {
1141                         uint32_t word0;
1142 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
1143 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
1144 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
1145                 } request;
1146                 struct {
1147                         uint32_t word0;
1148                 } response;
1149         } u;
1150 };
1151
1152 struct wq_context {
1153         uint32_t reserved0;
1154         uint32_t reserved1;
1155         uint32_t reserved2;
1156         uint32_t reserved3;
1157 };
1158
1159 struct lpfc_mbx_wq_create {
1160         struct mbox_header header;
1161         union {
1162                 struct {        /* Version 0 Request */
1163                         uint32_t word0;
1164 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
1165 #define lpfc_mbx_wq_create_num_pages_MASK       0x000000FF
1166 #define lpfc_mbx_wq_create_num_pages_WORD       word0
1167 #define lpfc_mbx_wq_create_dua_SHIFT            8
1168 #define lpfc_mbx_wq_create_dua_MASK             0x00000001
1169 #define lpfc_mbx_wq_create_dua_WORD             word0
1170 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1171 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1172 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1173                         struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1174                         uint32_t word9;
1175 #define lpfc_mbx_wq_create_bua_SHIFT            0
1176 #define lpfc_mbx_wq_create_bua_MASK             0x00000001
1177 #define lpfc_mbx_wq_create_bua_WORD             word9
1178 #define lpfc_mbx_wq_create_ulp_num_SHIFT        8
1179 #define lpfc_mbx_wq_create_ulp_num_MASK         0x000000FF
1180 #define lpfc_mbx_wq_create_ulp_num_WORD         word9
1181                 } request;
1182                 struct {        /* Version 1 Request */
1183                         uint32_t word0; /* Word 0 is the same as in v0 */
1184                         uint32_t word1;
1185 #define lpfc_mbx_wq_create_page_size_SHIFT      0
1186 #define lpfc_mbx_wq_create_page_size_MASK       0x000000FF
1187 #define lpfc_mbx_wq_create_page_size_WORD       word1
1188 #define LPFC_WQ_PAGE_SIZE_4096  0x1
1189 #define lpfc_mbx_wq_create_wqe_size_SHIFT       8
1190 #define lpfc_mbx_wq_create_wqe_size_MASK        0x0000000F
1191 #define lpfc_mbx_wq_create_wqe_size_WORD        word1
1192 #define LPFC_WQ_WQE_SIZE_64     0x5
1193 #define LPFC_WQ_WQE_SIZE_128    0x6
1194 #define lpfc_mbx_wq_create_wqe_count_SHIFT      16
1195 #define lpfc_mbx_wq_create_wqe_count_MASK       0x0000FFFF
1196 #define lpfc_mbx_wq_create_wqe_count_WORD       word1
1197                         uint32_t word2;
1198                         struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1199                 } request_1;
1200                 struct {
1201                         uint32_t word0;
1202 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1203 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1204 #define lpfc_mbx_wq_create_q_id_WORD    word0
1205                         uint32_t doorbell_offset;
1206                         uint32_t word2;
1207 #define lpfc_mbx_wq_create_bar_set_SHIFT        0
1208 #define lpfc_mbx_wq_create_bar_set_MASK         0x0000FFFF
1209 #define lpfc_mbx_wq_create_bar_set_WORD         word2
1210 #define WQ_PCI_BAR_0_AND_1      0x00
1211 #define WQ_PCI_BAR_2_AND_3      0x01
1212 #define WQ_PCI_BAR_4_AND_5      0x02
1213 #define lpfc_mbx_wq_create_db_format_SHIFT      16
1214 #define lpfc_mbx_wq_create_db_format_MASK       0x0000FFFF
1215 #define lpfc_mbx_wq_create_db_format_WORD       word2
1216                 } response;
1217         } u;
1218 };
1219
1220 struct lpfc_mbx_wq_destroy {
1221         struct mbox_header header;
1222         union {
1223                 struct {
1224                         uint32_t word0;
1225 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1226 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1227 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1228                 } request;
1229                 struct {
1230                         uint32_t word0;
1231                 } response;
1232         } u;
1233 };
1234
1235 #define LPFC_HDR_BUF_SIZE 128
1236 #define LPFC_DATA_BUF_SIZE 2048
1237 struct rq_context {
1238         uint32_t word0;
1239 #define lpfc_rq_context_rqe_count_SHIFT 16      /* Version 0 Only */
1240 #define lpfc_rq_context_rqe_count_MASK  0x0000000F
1241 #define lpfc_rq_context_rqe_count_WORD  word0
1242 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1243 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1244 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1245 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1246 #define lpfc_rq_context_rqe_count_1_SHIFT       16      /* Version 1 Only */
1247 #define lpfc_rq_context_rqe_count_1_MASK        0x0000FFFF
1248 #define lpfc_rq_context_rqe_count_1_WORD        word0
1249 #define lpfc_rq_context_rqe_size_SHIFT  8               /* Version 1 Only */
1250 #define lpfc_rq_context_rqe_size_MASK   0x0000000F
1251 #define lpfc_rq_context_rqe_size_WORD   word0
1252 #define LPFC_RQE_SIZE_8         2
1253 #define LPFC_RQE_SIZE_16        3
1254 #define LPFC_RQE_SIZE_32        4
1255 #define LPFC_RQE_SIZE_64        5
1256 #define LPFC_RQE_SIZE_128       6
1257 #define lpfc_rq_context_page_size_SHIFT 0               /* Version 1 Only */
1258 #define lpfc_rq_context_page_size_MASK  0x000000FF
1259 #define lpfc_rq_context_page_size_WORD  word0
1260 #define LPFC_RQ_PAGE_SIZE_4096  0x1
1261         uint32_t reserved1;
1262         uint32_t word2;
1263 #define lpfc_rq_context_cq_id_SHIFT     16
1264 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1265 #define lpfc_rq_context_cq_id_WORD      word2
1266 #define lpfc_rq_context_buf_size_SHIFT  0
1267 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1268 #define lpfc_rq_context_buf_size_WORD   word2
1269         uint32_t buffer_size;                           /* Version 1 Only */
1270 };
1271
1272 struct lpfc_mbx_rq_create {
1273         struct mbox_header header;
1274         union {
1275                 struct {
1276                         uint32_t word0;
1277 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1278 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1279 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1280 #define lpfc_mbx_rq_create_dua_SHIFT            16
1281 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1282 #define lpfc_mbx_rq_create_dua_WORD             word0
1283 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1284 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1285 #define lpfc_mbx_rq_create_bqu_WORD             word0
1286 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1287 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1288 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1289                         struct rq_context context;
1290                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1291                 } request;
1292                 struct {
1293                         uint32_t word0;
1294 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1295 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1296 #define lpfc_mbx_rq_create_q_id_WORD            word0
1297                         uint32_t doorbell_offset;
1298                         uint32_t word2;
1299 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1300 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1301 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1302 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1303 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1304 #define lpfc_mbx_rq_create_db_format_WORD       word2
1305                 } response;
1306         } u;
1307 };
1308
1309 struct lpfc_mbx_rq_destroy {
1310         struct mbox_header header;
1311         union {
1312                 struct {
1313                         uint32_t word0;
1314 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1315 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1316 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1317                 } request;
1318                 struct {
1319                         uint32_t word0;
1320                 } response;
1321         } u;
1322 };
1323
1324 struct mq_context {
1325         uint32_t word0;
1326 #define lpfc_mq_context_cq_id_SHIFT     22      /* Version 0 Only */
1327 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1328 #define lpfc_mq_context_cq_id_WORD      word0
1329 #define lpfc_mq_context_ring_size_SHIFT 16
1330 #define lpfc_mq_context_ring_size_MASK  0x0000000F
1331 #define lpfc_mq_context_ring_size_WORD  word0
1332 #define LPFC_MQ_RING_SIZE_16            0x5
1333 #define LPFC_MQ_RING_SIZE_32            0x6
1334 #define LPFC_MQ_RING_SIZE_64            0x7
1335 #define LPFC_MQ_RING_SIZE_128           0x8
1336         uint32_t word1;
1337 #define lpfc_mq_context_valid_SHIFT     31
1338 #define lpfc_mq_context_valid_MASK      0x00000001
1339 #define lpfc_mq_context_valid_WORD      word1
1340         uint32_t reserved2;
1341         uint32_t reserved3;
1342 };
1343
1344 struct lpfc_mbx_mq_create {
1345         struct mbox_header header;
1346         union {
1347                 struct {
1348                         uint32_t word0;
1349 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1350 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1351 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1352                         struct mq_context context;
1353                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1354                 } request;
1355                 struct {
1356                         uint32_t word0;
1357 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1358 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1359 #define lpfc_mbx_mq_create_q_id_WORD    word0
1360                 } response;
1361         } u;
1362 };
1363
1364 struct lpfc_mbx_mq_create_ext {
1365         struct mbox_header header;
1366         union {
1367                 struct {
1368                         uint32_t word0;
1369 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT  0
1370 #define lpfc_mbx_mq_create_ext_num_pages_MASK   0x0000FFFF
1371 #define lpfc_mbx_mq_create_ext_num_pages_WORD   word0
1372 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT      16      /* Version 1 Only */
1373 #define lpfc_mbx_mq_create_ext_cq_id_MASK       0x0000FFFF
1374 #define lpfc_mbx_mq_create_ext_cq_id_WORD       word0
1375                         uint32_t async_evt_bmap;
1376 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1377 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1378 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1379 #define LPFC_EVT_CODE_LINK_NO_LINK      0x0
1380 #define LPFC_EVT_CODE_LINK_10_MBIT      0x1
1381 #define LPFC_EVT_CODE_LINK_100_MBIT     0x2
1382 #define LPFC_EVT_CODE_LINK_1_GBIT       0x3
1383 #define LPFC_EVT_CODE_LINK_10_GBIT      0x4
1384 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1385 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1386 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1387 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1388 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1389 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1390 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1391 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1392 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1393 #define LPFC_EVT_CODE_FC_NO_LINK        0x0
1394 #define LPFC_EVT_CODE_FC_1_GBAUD        0x1
1395 #define LPFC_EVT_CODE_FC_2_GBAUD        0x2
1396 #define LPFC_EVT_CODE_FC_4_GBAUD        0x4
1397 #define LPFC_EVT_CODE_FC_8_GBAUD        0x8
1398 #define LPFC_EVT_CODE_FC_10_GBAUD       0xA
1399 #define LPFC_EVT_CODE_FC_16_GBAUD       0x10
1400 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1401 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1402 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1403                         struct mq_context context;
1404                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1405                 } request;
1406                 struct {
1407                         uint32_t word0;
1408 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1409 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1410 #define lpfc_mbx_mq_create_q_id_WORD    word0
1411                 } response;
1412         } u;
1413 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1414 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1415 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1416 };
1417
1418 struct lpfc_mbx_mq_destroy {
1419         struct mbox_header header;
1420         union {
1421                 struct {
1422                         uint32_t word0;
1423 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1424 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1425 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1426                 } request;
1427                 struct {
1428                         uint32_t word0;
1429                 } response;
1430         } u;
1431 };
1432
1433 /* Start Gen 2 SLI4 Mailbox definitions: */
1434
1435 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1436 #define LPFC_RSC_TYPE_FCOE_VFI  0x20
1437 #define LPFC_RSC_TYPE_FCOE_VPI  0x21
1438 #define LPFC_RSC_TYPE_FCOE_RPI  0x22
1439 #define LPFC_RSC_TYPE_FCOE_XRI  0x23
1440
1441 struct lpfc_mbx_get_rsrc_extent_info {
1442         struct mbox_header header;
1443         union {
1444                 struct {
1445                         uint32_t word4;
1446 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT        0
1447 #define lpfc_mbx_get_rsrc_extent_info_type_MASK         0x0000FFFF
1448 #define lpfc_mbx_get_rsrc_extent_info_type_WORD         word4
1449                 } req;
1450                 struct {
1451                         uint32_t word4;
1452 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT         0
1453 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK          0x0000FFFF
1454 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD          word4
1455 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT        16
1456 #define lpfc_mbx_get_rsrc_extent_info_size_MASK         0x0000FFFF
1457 #define lpfc_mbx_get_rsrc_extent_info_size_WORD         word4
1458                 } rsp;
1459         } u;
1460 };
1461
1462 struct lpfc_mbx_query_fw_config {
1463         struct mbox_header header;
1464         struct {
1465                 uint32_t config_number;
1466 #define LPFC_FC_FCOE            0x00000007
1467                 uint32_t asic_revision;
1468                 uint32_t physical_port;
1469                 uint32_t function_mode;
1470 #define LPFC_FCOE_INI_MODE      0x00000040
1471 #define LPFC_FCOE_TGT_MODE      0x00000080
1472 #define LPFC_DUA_MODE           0x00000800
1473                 uint32_t ulp0_mode;
1474 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1475 #define LPFC_ULP_FCOE_TGT_MODE  0x00000080
1476                 uint32_t ulp0_nap_words[12];
1477                 uint32_t ulp1_mode;
1478                 uint32_t ulp1_nap_words[12];
1479                 uint32_t function_capabilities;
1480                 uint32_t cqid_base;
1481                 uint32_t cqid_tot;
1482                 uint32_t eqid_base;
1483                 uint32_t eqid_tot;
1484                 uint32_t ulp0_nap2_words[2];
1485                 uint32_t ulp1_nap2_words[2];
1486         } rsp;
1487 };
1488
1489 struct lpfc_mbx_set_beacon_config {
1490         struct mbox_header header;
1491         uint32_t word4;
1492 #define lpfc_mbx_set_beacon_port_num_SHIFT              0
1493 #define lpfc_mbx_set_beacon_port_num_MASK               0x0000003F
1494 #define lpfc_mbx_set_beacon_port_num_WORD               word4
1495 #define lpfc_mbx_set_beacon_port_type_SHIFT             6
1496 #define lpfc_mbx_set_beacon_port_type_MASK              0x00000003
1497 #define lpfc_mbx_set_beacon_port_type_WORD              word4
1498 #define lpfc_mbx_set_beacon_state_SHIFT                 8
1499 #define lpfc_mbx_set_beacon_state_MASK                  0x000000FF
1500 #define lpfc_mbx_set_beacon_state_WORD                  word4
1501 #define lpfc_mbx_set_beacon_duration_SHIFT              16
1502 #define lpfc_mbx_set_beacon_duration_MASK               0x000000FF
1503 #define lpfc_mbx_set_beacon_duration_WORD               word4
1504 #define lpfc_mbx_set_beacon_status_duration_SHIFT       24
1505 #define lpfc_mbx_set_beacon_status_duration_MASK        0x000000FF
1506 #define lpfc_mbx_set_beacon_status_duration_WORD        word4
1507 };
1508
1509 struct lpfc_id_range {
1510         uint32_t word5;
1511 #define lpfc_mbx_rsrc_id_word4_0_SHIFT  0
1512 #define lpfc_mbx_rsrc_id_word4_0_MASK   0x0000FFFF
1513 #define lpfc_mbx_rsrc_id_word4_0_WORD   word5
1514 #define lpfc_mbx_rsrc_id_word4_1_SHIFT  16
1515 #define lpfc_mbx_rsrc_id_word4_1_MASK   0x0000FFFF
1516 #define lpfc_mbx_rsrc_id_word4_1_WORD   word5
1517 };
1518
1519 struct lpfc_mbx_set_link_diag_state {
1520         struct mbox_header header;
1521         union {
1522                 struct {
1523                         uint32_t word0;
1524 #define lpfc_mbx_set_diag_state_diag_SHIFT      0
1525 #define lpfc_mbx_set_diag_state_diag_MASK       0x00000001
1526 #define lpfc_mbx_set_diag_state_diag_WORD       word0
1527 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT    2
1528 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK     0x00000001
1529 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD     word0
1530 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE        0
1531 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE           1
1532 #define lpfc_mbx_set_diag_state_link_num_SHIFT  16
1533 #define lpfc_mbx_set_diag_state_link_num_MASK   0x0000003F
1534 #define lpfc_mbx_set_diag_state_link_num_WORD   word0
1535 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1536 #define lpfc_mbx_set_diag_state_link_type_MASK  0x00000003
1537 #define lpfc_mbx_set_diag_state_link_type_WORD  word0
1538                 } req;
1539                 struct {
1540                         uint32_t word0;
1541                 } rsp;
1542         } u;
1543 };
1544
1545 struct lpfc_mbx_set_link_diag_loopback {
1546         struct mbox_header header;
1547         union {
1548                 struct {
1549                         uint32_t word0;
1550 #define lpfc_mbx_set_diag_lpbk_type_SHIFT       0
1551 #define lpfc_mbx_set_diag_lpbk_type_MASK        0x00000003
1552 #define lpfc_mbx_set_diag_lpbk_type_WORD        word0
1553 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE         0x0
1554 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL        0x1
1555 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES          0x2
1556 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT   16
1557 #define lpfc_mbx_set_diag_lpbk_link_num_MASK    0x0000003F
1558 #define lpfc_mbx_set_diag_lpbk_link_num_WORD    word0
1559 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT  22
1560 #define lpfc_mbx_set_diag_lpbk_link_type_MASK   0x00000003
1561 #define lpfc_mbx_set_diag_lpbk_link_type_WORD   word0
1562                 } req;
1563                 struct {
1564                         uint32_t word0;
1565                 } rsp;
1566         } u;
1567 };
1568
1569 struct lpfc_mbx_run_link_diag_test {
1570         struct mbox_header header;
1571         union {
1572                 struct {
1573                         uint32_t word0;
1574 #define lpfc_mbx_run_diag_test_link_num_SHIFT   16
1575 #define lpfc_mbx_run_diag_test_link_num_MASK    0x0000003F
1576 #define lpfc_mbx_run_diag_test_link_num_WORD    word0
1577 #define lpfc_mbx_run_diag_test_link_type_SHIFT  22
1578 #define lpfc_mbx_run_diag_test_link_type_MASK   0x00000003
1579 #define lpfc_mbx_run_diag_test_link_type_WORD   word0
1580                         uint32_t word1;
1581 #define lpfc_mbx_run_diag_test_test_id_SHIFT    0
1582 #define lpfc_mbx_run_diag_test_test_id_MASK     0x0000FFFF
1583 #define lpfc_mbx_run_diag_test_test_id_WORD     word1
1584 #define lpfc_mbx_run_diag_test_loops_SHIFT      16
1585 #define lpfc_mbx_run_diag_test_loops_MASK       0x0000FFFF
1586 #define lpfc_mbx_run_diag_test_loops_WORD       word1
1587                         uint32_t word2;
1588 #define lpfc_mbx_run_diag_test_test_ver_SHIFT   0
1589 #define lpfc_mbx_run_diag_test_test_ver_MASK    0x0000FFFF
1590 #define lpfc_mbx_run_diag_test_test_ver_WORD    word2
1591 #define lpfc_mbx_run_diag_test_err_act_SHIFT    16
1592 #define lpfc_mbx_run_diag_test_err_act_MASK     0x000000FF
1593 #define lpfc_mbx_run_diag_test_err_act_WORD     word2
1594                 } req;
1595                 struct {
1596                         uint32_t word0;
1597                 } rsp;
1598         } u;
1599 };
1600
1601 /*
1602  * struct lpfc_mbx_alloc_rsrc_extents:
1603  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1604  * 6 words of header + 4 words of shared subcommand header +
1605  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1606  *
1607  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1608  * for extents payload.
1609  *
1610  * 212/2 (bytes per extent) = 106 extents.
1611  * 106/2 (extents per word) = 53 words.
1612  * lpfc_id_range id is statically size to 53.
1613  *
1614  * This mailbox definition is used for ALLOC or GET_ALLOCATED
1615  * extent ranges.  For ALLOC, the type and cnt are required.
1616  * For GET_ALLOCATED, only the type is required.
1617  */
1618 struct lpfc_mbx_alloc_rsrc_extents {
1619         struct mbox_header header;
1620         union {
1621                 struct {
1622                         uint32_t word4;
1623 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT  0
1624 #define lpfc_mbx_alloc_rsrc_extents_type_MASK   0x0000FFFF
1625 #define lpfc_mbx_alloc_rsrc_extents_type_WORD   word4
1626 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT   16
1627 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK    0x0000FFFF
1628 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD    word4
1629                 } req;
1630                 struct {
1631                         uint32_t word4;
1632 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1633 #define lpfc_mbx_rsrc_cnt_MASK  0x0000FFFF
1634 #define lpfc_mbx_rsrc_cnt_WORD  word4
1635                         struct lpfc_id_range id[53];
1636                 } rsp;
1637         } u;
1638 };
1639
1640 /*
1641  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1642  * structure shares the same SHIFT/MASK/WORD defines provided in the
1643  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1644  * the structures defined above.  This non-embedded structure provides for the
1645  * maximum number of extents supported by the port.
1646  */
1647 struct lpfc_mbx_nembed_rsrc_extent {
1648         union  lpfc_sli4_cfg_shdr cfg_shdr;
1649         uint32_t word4;
1650         struct lpfc_id_range id;
1651 };
1652
1653 struct lpfc_mbx_dealloc_rsrc_extents {
1654         struct mbox_header header;
1655         struct {
1656                 uint32_t word4;
1657 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT        0
1658 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK         0x0000FFFF
1659 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD         word4
1660         } req;
1661
1662 };
1663
1664 /* Start SLI4 FCoE specific mbox structures. */
1665
1666 struct lpfc_mbx_post_hdr_tmpl {
1667         struct mbox_header header;
1668         uint32_t word10;
1669 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1670 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1671 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1672 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1673 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1674 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1675         uint32_t rpi_paddr_lo;
1676         uint32_t rpi_paddr_hi;
1677 };
1678
1679 struct sli4_sge {       /* SLI-4 */
1680         uint32_t addr_hi;
1681         uint32_t addr_lo;
1682
1683         uint32_t word2;
1684 #define lpfc_sli4_sge_offset_SHIFT      0
1685 #define lpfc_sli4_sge_offset_MASK       0x07FFFFFF
1686 #define lpfc_sli4_sge_offset_WORD       word2
1687 #define lpfc_sli4_sge_type_SHIFT        27
1688 #define lpfc_sli4_sge_type_MASK         0x0000000F
1689 #define lpfc_sli4_sge_type_WORD         word2
1690 #define LPFC_SGE_TYPE_DATA              0x0
1691 #define LPFC_SGE_TYPE_DIF               0x4
1692 #define LPFC_SGE_TYPE_LSP               0x5
1693 #define LPFC_SGE_TYPE_PEDIF             0x6
1694 #define LPFC_SGE_TYPE_PESEED            0x7
1695 #define LPFC_SGE_TYPE_DISEED            0x8
1696 #define LPFC_SGE_TYPE_ENC               0x9
1697 #define LPFC_SGE_TYPE_ATM               0xA
1698 #define LPFC_SGE_TYPE_SKIP              0xC
1699 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets it */
1700 #define lpfc_sli4_sge_last_MASK         0x00000001
1701 #define lpfc_sli4_sge_last_WORD         word2
1702         uint32_t sge_len;
1703 };
1704
1705 struct sli4_sge_diseed {        /* SLI-4 */
1706         uint32_t ref_tag;
1707         uint32_t ref_tag_tran;
1708
1709         uint32_t word2;
1710 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
1711 #define lpfc_sli4_sge_dif_apptran_MASK  0x0000FFFF
1712 #define lpfc_sli4_sge_dif_apptran_WORD  word2
1713 #define lpfc_sli4_sge_dif_af_SHIFT      24
1714 #define lpfc_sli4_sge_dif_af_MASK       0x00000001
1715 #define lpfc_sli4_sge_dif_af_WORD       word2
1716 #define lpfc_sli4_sge_dif_na_SHIFT      25
1717 #define lpfc_sli4_sge_dif_na_MASK       0x00000001
1718 #define lpfc_sli4_sge_dif_na_WORD       word2
1719 #define lpfc_sli4_sge_dif_hi_SHIFT      26
1720 #define lpfc_sli4_sge_dif_hi_MASK       0x00000001
1721 #define lpfc_sli4_sge_dif_hi_WORD       word2
1722 #define lpfc_sli4_sge_dif_type_SHIFT    27
1723 #define lpfc_sli4_sge_dif_type_MASK     0x0000000F
1724 #define lpfc_sli4_sge_dif_type_WORD     word2
1725 #define lpfc_sli4_sge_dif_last_SHIFT    31 /* Last SEG in the SGL sets it */
1726 #define lpfc_sli4_sge_dif_last_MASK     0x00000001
1727 #define lpfc_sli4_sge_dif_last_WORD     word2
1728         uint32_t word3;
1729 #define lpfc_sli4_sge_dif_apptag_SHIFT  0
1730 #define lpfc_sli4_sge_dif_apptag_MASK   0x0000FFFF
1731 #define lpfc_sli4_sge_dif_apptag_WORD   word3
1732 #define lpfc_sli4_sge_dif_bs_SHIFT      16
1733 #define lpfc_sli4_sge_dif_bs_MASK       0x00000007
1734 #define lpfc_sli4_sge_dif_bs_WORD       word3
1735 #define lpfc_sli4_sge_dif_ai_SHIFT      19
1736 #define lpfc_sli4_sge_dif_ai_MASK       0x00000001
1737 #define lpfc_sli4_sge_dif_ai_WORD       word3
1738 #define lpfc_sli4_sge_dif_me_SHIFT      20
1739 #define lpfc_sli4_sge_dif_me_MASK       0x00000001
1740 #define lpfc_sli4_sge_dif_me_WORD       word3
1741 #define lpfc_sli4_sge_dif_re_SHIFT      21
1742 #define lpfc_sli4_sge_dif_re_MASK       0x00000001
1743 #define lpfc_sli4_sge_dif_re_WORD       word3
1744 #define lpfc_sli4_sge_dif_ce_SHIFT      22
1745 #define lpfc_sli4_sge_dif_ce_MASK       0x00000001
1746 #define lpfc_sli4_sge_dif_ce_WORD       word3
1747 #define lpfc_sli4_sge_dif_nr_SHIFT      23
1748 #define lpfc_sli4_sge_dif_nr_MASK       0x00000001
1749 #define lpfc_sli4_sge_dif_nr_WORD       word3
1750 #define lpfc_sli4_sge_dif_oprx_SHIFT    24
1751 #define lpfc_sli4_sge_dif_oprx_MASK     0x0000000F
1752 #define lpfc_sli4_sge_dif_oprx_WORD     word3
1753 #define lpfc_sli4_sge_dif_optx_SHIFT    28
1754 #define lpfc_sli4_sge_dif_optx_MASK     0x0000000F
1755 #define lpfc_sli4_sge_dif_optx_WORD     word3
1756 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1757 };
1758
1759 struct fcf_record {
1760         uint32_t max_rcv_size;
1761         uint32_t fka_adv_period;
1762         uint32_t fip_priority;
1763         uint32_t word3;
1764 #define lpfc_fcf_record_mac_0_SHIFT             0
1765 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1766 #define lpfc_fcf_record_mac_0_WORD              word3
1767 #define lpfc_fcf_record_mac_1_SHIFT             8
1768 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1769 #define lpfc_fcf_record_mac_1_WORD              word3
1770 #define lpfc_fcf_record_mac_2_SHIFT             16
1771 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1772 #define lpfc_fcf_record_mac_2_WORD              word3
1773 #define lpfc_fcf_record_mac_3_SHIFT             24
1774 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1775 #define lpfc_fcf_record_mac_3_WORD              word3
1776         uint32_t word4;
1777 #define lpfc_fcf_record_mac_4_SHIFT             0
1778 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1779 #define lpfc_fcf_record_mac_4_WORD              word4
1780 #define lpfc_fcf_record_mac_5_SHIFT             8
1781 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1782 #define lpfc_fcf_record_mac_5_WORD              word4
1783 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1784 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1785 #define lpfc_fcf_record_fcf_avail_WORD          word4
1786 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1787 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1788 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1789 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1790 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1791         uint32_t word5;
1792 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1793 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1794 #define lpfc_fcf_record_fab_name_0_WORD         word5
1795 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1796 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1797 #define lpfc_fcf_record_fab_name_1_WORD         word5
1798 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1799 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1800 #define lpfc_fcf_record_fab_name_2_WORD         word5
1801 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1802 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1803 #define lpfc_fcf_record_fab_name_3_WORD         word5
1804         uint32_t word6;
1805 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1806 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1807 #define lpfc_fcf_record_fab_name_4_WORD         word6
1808 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1809 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1810 #define lpfc_fcf_record_fab_name_5_WORD         word6
1811 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1812 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1813 #define lpfc_fcf_record_fab_name_6_WORD         word6
1814 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1815 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1816 #define lpfc_fcf_record_fab_name_7_WORD         word6
1817         uint32_t word7;
1818 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1819 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1820 #define lpfc_fcf_record_fc_map_0_WORD           word7
1821 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1822 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1823 #define lpfc_fcf_record_fc_map_1_WORD           word7
1824 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1825 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1826 #define lpfc_fcf_record_fc_map_2_WORD           word7
1827 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1828 #define lpfc_fcf_record_fcf_valid_MASK          0x00000001
1829 #define lpfc_fcf_record_fcf_valid_WORD          word7
1830 #define lpfc_fcf_record_fcf_fc_SHIFT            25
1831 #define lpfc_fcf_record_fcf_fc_MASK             0x00000001
1832 #define lpfc_fcf_record_fcf_fc_WORD             word7
1833 #define lpfc_fcf_record_fcf_sol_SHIFT           31
1834 #define lpfc_fcf_record_fcf_sol_MASK            0x00000001
1835 #define lpfc_fcf_record_fcf_sol_WORD            word7
1836         uint32_t word8;
1837 #define lpfc_fcf_record_fcf_index_SHIFT         0
1838 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1839 #define lpfc_fcf_record_fcf_index_WORD          word8
1840 #define lpfc_fcf_record_fcf_state_SHIFT         16
1841 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1842 #define lpfc_fcf_record_fcf_state_WORD          word8
1843         uint8_t vlan_bitmap[512];
1844         uint32_t word137;
1845 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1846 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1847 #define lpfc_fcf_record_switch_name_0_WORD      word137
1848 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1849 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1850 #define lpfc_fcf_record_switch_name_1_WORD      word137
1851 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1852 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1853 #define lpfc_fcf_record_switch_name_2_WORD      word137
1854 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1855 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1856 #define lpfc_fcf_record_switch_name_3_WORD      word137
1857         uint32_t word138;
1858 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1859 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1860 #define lpfc_fcf_record_switch_name_4_WORD      word138
1861 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1862 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1863 #define lpfc_fcf_record_switch_name_5_WORD      word138
1864 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1865 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1866 #define lpfc_fcf_record_switch_name_6_WORD      word138
1867 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1868 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1869 #define lpfc_fcf_record_switch_name_7_WORD      word138
1870 };
1871
1872 struct lpfc_mbx_read_fcf_tbl {
1873         union lpfc_sli4_cfg_shdr cfg_shdr;
1874         union {
1875                 struct {
1876                         uint32_t word10;
1877 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1878 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1879 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1880                 } request;
1881                 struct {
1882                         uint32_t eventag;
1883                 } response;
1884         } u;
1885         uint32_t word11;
1886 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1887 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1888 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1889 };
1890
1891 struct lpfc_mbx_add_fcf_tbl_entry {
1892         union lpfc_sli4_cfg_shdr cfg_shdr;
1893         uint32_t word10;
1894 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1895 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1896 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1897         struct lpfc_mbx_sge fcf_sge;
1898 };
1899
1900 struct lpfc_mbx_del_fcf_tbl_entry {
1901         struct mbox_header header;
1902         uint32_t word10;
1903 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1904 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1905 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1906 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1907 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1908 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1909 };
1910
1911 struct lpfc_mbx_redisc_fcf_tbl {
1912         struct mbox_header header;
1913         uint32_t word10;
1914 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1915 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1916 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1917         uint32_t resvd;
1918         uint32_t word12;
1919 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1920 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1921 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1922 };
1923
1924 /* Status field for embedded SLI_CONFIG mailbox command */
1925 #define STATUS_SUCCESS                                  0x0
1926 #define STATUS_FAILED                                   0x1
1927 #define STATUS_ILLEGAL_REQUEST                          0x2
1928 #define STATUS_ILLEGAL_FIELD                            0x3
1929 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1930 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1931 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1932 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1933 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1934 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1935 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1936 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1937 #define STATUS_ASSERT_FAILED                            0x1e
1938 #define STATUS_INVALID_SESSION                          0x1f
1939 #define STATUS_INVALID_CONNECTION                       0x20
1940 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1941 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1942 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1943 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1944 #define STATUS_FLASHROM_READ_FAILED                     0x27
1945 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1946 #define STATUS_ERROR_ACITMAIN                           0x2a
1947 #define STATUS_REBOOT_REQUIRED                          0x2c
1948 #define STATUS_FCF_IN_USE                               0x3a
1949 #define STATUS_FCF_TABLE_EMPTY                          0x43
1950
1951 /*
1952  * Additional status field for embedded SLI_CONFIG mailbox
1953  * command.
1954  */
1955 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE             0x67
1956
1957 struct lpfc_mbx_sli4_config {
1958         struct mbox_header header;
1959 };
1960
1961 struct lpfc_mbx_init_vfi {
1962         uint32_t word1;
1963 #define lpfc_init_vfi_vr_SHIFT          31
1964 #define lpfc_init_vfi_vr_MASK           0x00000001
1965 #define lpfc_init_vfi_vr_WORD           word1
1966 #define lpfc_init_vfi_vt_SHIFT          30
1967 #define lpfc_init_vfi_vt_MASK           0x00000001
1968 #define lpfc_init_vfi_vt_WORD           word1
1969 #define lpfc_init_vfi_vf_SHIFT          29
1970 #define lpfc_init_vfi_vf_MASK           0x00000001
1971 #define lpfc_init_vfi_vf_WORD           word1
1972 #define lpfc_init_vfi_vp_SHIFT          28
1973 #define lpfc_init_vfi_vp_MASK           0x00000001
1974 #define lpfc_init_vfi_vp_WORD           word1
1975 #define lpfc_init_vfi_vfi_SHIFT         0
1976 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1977 #define lpfc_init_vfi_vfi_WORD          word1
1978         uint32_t word2;
1979 #define lpfc_init_vfi_vpi_SHIFT         16
1980 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
1981 #define lpfc_init_vfi_vpi_WORD          word2
1982 #define lpfc_init_vfi_fcfi_SHIFT        0
1983 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1984 #define lpfc_init_vfi_fcfi_WORD         word2
1985         uint32_t word3;
1986 #define lpfc_init_vfi_pri_SHIFT         13
1987 #define lpfc_init_vfi_pri_MASK          0x00000007
1988 #define lpfc_init_vfi_pri_WORD          word3
1989 #define lpfc_init_vfi_vf_id_SHIFT       1
1990 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1991 #define lpfc_init_vfi_vf_id_WORD        word3
1992         uint32_t word4;
1993 #define lpfc_init_vfi_hop_count_SHIFT   24
1994 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1995 #define lpfc_init_vfi_hop_count_WORD    word4
1996 };
1997 #define MBX_VFI_IN_USE                  0x9F02
1998
1999
2000 struct lpfc_mbx_reg_vfi {
2001         uint32_t word1;
2002 #define lpfc_reg_vfi_upd_SHIFT          29
2003 #define lpfc_reg_vfi_upd_MASK           0x00000001
2004 #define lpfc_reg_vfi_upd_WORD           word1
2005 #define lpfc_reg_vfi_vp_SHIFT           28
2006 #define lpfc_reg_vfi_vp_MASK            0x00000001
2007 #define lpfc_reg_vfi_vp_WORD            word1
2008 #define lpfc_reg_vfi_vfi_SHIFT          0
2009 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
2010 #define lpfc_reg_vfi_vfi_WORD           word1
2011         uint32_t word2;
2012 #define lpfc_reg_vfi_vpi_SHIFT          16
2013 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
2014 #define lpfc_reg_vfi_vpi_WORD           word2
2015 #define lpfc_reg_vfi_fcfi_SHIFT         0
2016 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
2017 #define lpfc_reg_vfi_fcfi_WORD          word2
2018         uint32_t wwn[2];
2019         struct ulp_bde64 bde;
2020         uint32_t e_d_tov;
2021         uint32_t r_a_tov;
2022         uint32_t word10;
2023 #define lpfc_reg_vfi_nport_id_SHIFT             0
2024 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
2025 #define lpfc_reg_vfi_nport_id_WORD              word10
2026 };
2027
2028 struct lpfc_mbx_init_vpi {
2029         uint32_t word1;
2030 #define lpfc_init_vpi_vfi_SHIFT         16
2031 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
2032 #define lpfc_init_vpi_vfi_WORD          word1
2033 #define lpfc_init_vpi_vpi_SHIFT         0
2034 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
2035 #define lpfc_init_vpi_vpi_WORD          word1
2036 };
2037
2038 struct lpfc_mbx_read_vpi {
2039         uint32_t word1_rsvd;
2040         uint32_t word2;
2041 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
2042 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
2043 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
2044         uint32_t word3_rsvd;
2045         uint32_t word4;
2046 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
2047 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
2048 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
2049 #define lpfc_mbx_read_vpi_pb_SHIFT              15
2050 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
2051 #define lpfc_mbx_read_vpi_pb_WORD               word4
2052 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
2053 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
2054 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
2055 #define lpfc_mbx_read_vpi_ns_SHIFT              30
2056 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
2057 #define lpfc_mbx_read_vpi_ns_WORD               word4
2058 #define lpfc_mbx_read_vpi_hl_SHIFT              31
2059 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
2060 #define lpfc_mbx_read_vpi_hl_WORD               word4
2061         uint32_t word5_rsvd;
2062         uint32_t word6;
2063 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
2064 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
2065 #define lpfc_mbx_read_vpi_vpi_WORD              word6
2066         uint32_t word7;
2067 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
2068 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
2069 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
2070 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
2071 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
2072 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
2073 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
2074 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
2075 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
2076 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
2077 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
2078 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
2079         uint32_t word8;
2080 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
2081 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
2082 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
2083 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
2084 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
2085 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
2086 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
2087 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
2088 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
2089 #define lpfc_mbx_read_vpi_vv_SHIFT              28
2090 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
2091 #define lpfc_mbx_read_vpi_vv_WORD               word8
2092 };
2093
2094 struct lpfc_mbx_unreg_vfi {
2095         uint32_t word1_rsvd;
2096         uint32_t word2;
2097 #define lpfc_unreg_vfi_vfi_SHIFT        0
2098 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
2099 #define lpfc_unreg_vfi_vfi_WORD         word2
2100 };
2101
2102 struct lpfc_mbx_resume_rpi {
2103         uint32_t word1;
2104 #define lpfc_resume_rpi_index_SHIFT     0
2105 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
2106 #define lpfc_resume_rpi_index_WORD      word1
2107 #define lpfc_resume_rpi_ii_SHIFT        30
2108 #define lpfc_resume_rpi_ii_MASK         0x00000003
2109 #define lpfc_resume_rpi_ii_WORD         word1
2110 #define RESUME_INDEX_RPI                0
2111 #define RESUME_INDEX_VPI                1
2112 #define RESUME_INDEX_VFI                2
2113 #define RESUME_INDEX_FCFI               3
2114         uint32_t event_tag;
2115 };
2116
2117 #define REG_FCF_INVALID_QID     0xFFFF
2118 struct lpfc_mbx_reg_fcfi {
2119         uint32_t word1;
2120 #define lpfc_reg_fcfi_info_index_SHIFT  0
2121 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
2122 #define lpfc_reg_fcfi_info_index_WORD   word1
2123 #define lpfc_reg_fcfi_fcfi_SHIFT        16
2124 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
2125 #define lpfc_reg_fcfi_fcfi_WORD         word1
2126         uint32_t word2;
2127 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
2128 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
2129 #define lpfc_reg_fcfi_rq_id1_WORD       word2
2130 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
2131 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
2132 #define lpfc_reg_fcfi_rq_id0_WORD       word2
2133         uint32_t word3;
2134 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
2135 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
2136 #define lpfc_reg_fcfi_rq_id3_WORD       word3
2137 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
2138 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
2139 #define lpfc_reg_fcfi_rq_id2_WORD       word3
2140         uint32_t word4;
2141 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2142 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
2143 #define lpfc_reg_fcfi_type_match0_WORD  word4
2144 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
2145 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
2146 #define lpfc_reg_fcfi_type_mask0_WORD   word4
2147 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2148 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
2149 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
2150 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
2151 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
2152 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
2153         uint32_t word5;
2154 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2155 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
2156 #define lpfc_reg_fcfi_type_match1_WORD  word5
2157 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
2158 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
2159 #define lpfc_reg_fcfi_type_mask1_WORD   word5
2160 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2161 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
2162 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
2163 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
2164 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
2165 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
2166         uint32_t word6;
2167 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2168 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
2169 #define lpfc_reg_fcfi_type_match2_WORD  word6
2170 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
2171 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
2172 #define lpfc_reg_fcfi_type_mask2_WORD   word6
2173 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2174 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
2175 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
2176 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
2177 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
2178 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
2179         uint32_t word7;
2180 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2181 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
2182 #define lpfc_reg_fcfi_type_match3_WORD  word7
2183 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
2184 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
2185 #define lpfc_reg_fcfi_type_mask3_WORD   word7
2186 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2187 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
2188 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
2189 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
2190 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
2191 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
2192         uint32_t word8;
2193 #define lpfc_reg_fcfi_mam_SHIFT         13
2194 #define lpfc_reg_fcfi_mam_MASK          0x00000003
2195 #define lpfc_reg_fcfi_mam_WORD          word8
2196 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
2197 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
2198 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
2199 #define lpfc_reg_fcfi_vv_SHIFT          12
2200 #define lpfc_reg_fcfi_vv_MASK           0x00000001
2201 #define lpfc_reg_fcfi_vv_WORD           word8
2202 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
2203 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
2204 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
2205 };
2206
2207 struct lpfc_mbx_unreg_fcfi {
2208         uint32_t word1_rsv;
2209         uint32_t word2;
2210 #define lpfc_unreg_fcfi_SHIFT           0
2211 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
2212 #define lpfc_unreg_fcfi_WORD            word2
2213 };
2214
2215 struct lpfc_mbx_read_rev {
2216         uint32_t word1;
2217 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
2218 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
2219 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
2220 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
2221 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
2222 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
2223 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
2224 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
2225 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
2226 #define LPFC_PREDCBX_CEE_MODE   0
2227 #define LPFC_DCBX_CEE_MODE      1
2228 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
2229 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
2230 #define lpfc_mbx_rd_rev_vpd_WORD                word1
2231         uint32_t first_hw_rev;
2232         uint32_t second_hw_rev;
2233         uint32_t word4_rsvd;
2234         uint32_t third_hw_rev;
2235         uint32_t word6;
2236 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
2237 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
2238 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
2239 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
2240 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
2241 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
2242 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
2243 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
2244 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
2245 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
2246 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
2247 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
2248         uint32_t word7_rsvd;
2249         uint32_t fw_id_rev;
2250         uint8_t  fw_name[16];
2251         uint32_t ulp_fw_id_rev;
2252         uint8_t  ulp_fw_name[16];
2253         uint32_t word18_47_rsvd[30];
2254         uint32_t word48;
2255 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
2256 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
2257 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
2258         uint32_t vpd_paddr_low;
2259         uint32_t vpd_paddr_high;
2260         uint32_t avail_vpd_len;
2261         uint32_t rsvd_52_63[12];
2262 };
2263
2264 struct lpfc_mbx_read_config {
2265         uint32_t word1;
2266 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT     31
2267 #define lpfc_mbx_rd_conf_extnts_inuse_MASK      0x00000001
2268 #define lpfc_mbx_rd_conf_extnts_inuse_WORD      word1
2269         uint32_t word2;
2270 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT         0
2271 #define lpfc_mbx_rd_conf_lnk_numb_MASK          0x0000003F
2272 #define lpfc_mbx_rd_conf_lnk_numb_WORD          word2
2273 #define lpfc_mbx_rd_conf_lnk_type_SHIFT         6
2274 #define lpfc_mbx_rd_conf_lnk_type_MASK          0x00000003
2275 #define lpfc_mbx_rd_conf_lnk_type_WORD          word2
2276 #define LPFC_LNK_TYPE_GE        0
2277 #define LPFC_LNK_TYPE_FC        1
2278 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT          8
2279 #define lpfc_mbx_rd_conf_lnk_ldv_MASK           0x00000001
2280 #define lpfc_mbx_rd_conf_lnk_ldv_WORD           word2
2281 #define lpfc_mbx_rd_conf_topology_SHIFT         24
2282 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
2283 #define lpfc_mbx_rd_conf_topology_WORD          word2
2284         uint32_t rsvd_3;
2285         uint32_t word4;
2286 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
2287 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
2288 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
2289         uint32_t rsvd_5;
2290         uint32_t word6;
2291 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
2292 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
2293 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
2294         uint32_t rsvd_7;
2295         uint32_t rsvd_8;
2296         uint32_t word9;
2297 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
2298 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
2299 #define lpfc_mbx_rd_conf_lmt_WORD               word9
2300         uint32_t rsvd_10;
2301         uint32_t rsvd_11;
2302         uint32_t word12;
2303 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
2304 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
2305 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
2306 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
2307 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
2308 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
2309         uint32_t word13;
2310 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
2311 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
2312 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
2313 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
2314 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
2315 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
2316         uint32_t word14;
2317 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
2318 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
2319 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
2320 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
2321 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
2322 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
2323         uint32_t word15;
2324 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2325 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2326 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2327 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2328 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2329 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2330         uint32_t word16;
2331 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
2332 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
2333 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
2334         uint32_t word17;
2335 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
2336 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
2337 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
2338 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
2339 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
2340 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
2341         uint32_t word18;
2342 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
2343 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
2344 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
2345 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
2346 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
2347 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
2348 };
2349
2350 struct lpfc_mbx_request_features {
2351         uint32_t word1;
2352 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
2353 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
2354 #define lpfc_mbx_rq_ftr_qry_WORD                word1
2355         uint32_t word2;
2356 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
2357 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
2358 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
2359 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
2360 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
2361 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
2362 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
2363 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
2364 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
2365 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
2366 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
2367 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
2368 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
2369 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
2370 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
2371 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
2372 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
2373 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
2374 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
2375 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
2376 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
2377 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
2378 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
2379 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
2380 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
2381 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
2382 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
2383         uint32_t word3;
2384 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
2385 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
2386 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
2387 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
2388 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
2389 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
2390 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
2391 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
2392 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
2393 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
2394 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
2395 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
2396 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
2397 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
2398 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
2399 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
2400 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
2401 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
2402 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
2403 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
2404 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
2405 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
2406 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
2407 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
2408 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
2409 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
2410 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
2411 };
2412
2413 struct lpfc_mbx_supp_pages {
2414         uint32_t word1;
2415 #define qs_SHIFT                                0
2416 #define qs_MASK                                 0x00000001
2417 #define qs_WORD                                 word1
2418 #define wr_SHIFT                                1
2419 #define wr_MASK                                 0x00000001
2420 #define wr_WORD                                 word1
2421 #define pf_SHIFT                                8
2422 #define pf_MASK                                 0x000000ff
2423 #define pf_WORD                                 word1
2424 #define cpn_SHIFT                               16
2425 #define cpn_MASK                                0x000000ff
2426 #define cpn_WORD                                word1
2427         uint32_t word2;
2428 #define list_offset_SHIFT                       0
2429 #define list_offset_MASK                        0x000000ff
2430 #define list_offset_WORD                        word2
2431 #define next_offset_SHIFT                       8
2432 #define next_offset_MASK                        0x000000ff
2433 #define next_offset_WORD                        word2
2434 #define elem_cnt_SHIFT                          16
2435 #define elem_cnt_MASK                           0x000000ff
2436 #define elem_cnt_WORD                           word2
2437         uint32_t word3;
2438 #define pn_0_SHIFT                              24
2439 #define pn_0_MASK                               0x000000ff
2440 #define pn_0_WORD                               word3
2441 #define pn_1_SHIFT                              16
2442 #define pn_1_MASK                               0x000000ff
2443 #define pn_1_WORD                               word3
2444 #define pn_2_SHIFT                              8
2445 #define pn_2_MASK                               0x000000ff
2446 #define pn_2_WORD                               word3
2447 #define pn_3_SHIFT                              0
2448 #define pn_3_MASK                               0x000000ff
2449 #define pn_3_WORD                               word3
2450         uint32_t word4;
2451 #define pn_4_SHIFT                              24
2452 #define pn_4_MASK                               0x000000ff
2453 #define pn_4_WORD                               word4
2454 #define pn_5_SHIFT                              16
2455 #define pn_5_MASK                               0x000000ff
2456 #define pn_5_WORD                               word4
2457 #define pn_6_SHIFT                              8
2458 #define pn_6_MASK                               0x000000ff
2459 #define pn_6_WORD                               word4
2460 #define pn_7_SHIFT                              0
2461 #define pn_7_MASK                               0x000000ff
2462 #define pn_7_WORD                               word4
2463         uint32_t rsvd[27];
2464 #define LPFC_SUPP_PAGES                 0
2465 #define LPFC_BLOCK_GUARD_PROFILES       1
2466 #define LPFC_SLI4_PARAMETERS            2
2467 };
2468
2469 struct lpfc_mbx_memory_dump_type3 {
2470         uint32_t word1;
2471 #define lpfc_mbx_memory_dump_type3_type_SHIFT    0
2472 #define lpfc_mbx_memory_dump_type3_type_MASK     0x0000000f
2473 #define lpfc_mbx_memory_dump_type3_type_WORD     word1
2474 #define lpfc_mbx_memory_dump_type3_link_SHIFT    24
2475 #define lpfc_mbx_memory_dump_type3_link_MASK     0x000000ff
2476 #define lpfc_mbx_memory_dump_type3_link_WORD     word1
2477         uint32_t word2;
2478 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT  0
2479 #define lpfc_mbx_memory_dump_type3_page_no_MASK   0x0000ffff
2480 #define lpfc_mbx_memory_dump_type3_page_no_WORD   word2
2481 #define lpfc_mbx_memory_dump_type3_offset_SHIFT   16
2482 #define lpfc_mbx_memory_dump_type3_offset_MASK    0x0000ffff
2483 #define lpfc_mbx_memory_dump_type3_offset_WORD    word2
2484         uint32_t word3;
2485 #define lpfc_mbx_memory_dump_type3_length_SHIFT  0
2486 #define lpfc_mbx_memory_dump_type3_length_MASK   0x00ffffff
2487 #define lpfc_mbx_memory_dump_type3_length_WORD   word3
2488         uint32_t addr_lo;
2489         uint32_t addr_hi;
2490         uint32_t return_len;
2491 };
2492
2493 #define DMP_PAGE_A0             0xa0
2494 #define DMP_PAGE_A2             0xa2
2495 #define DMP_SFF_PAGE_A0_SIZE    256
2496 #define DMP_SFF_PAGE_A2_SIZE    256
2497
2498 #define SFP_WAVELENGTH_LC1310   1310
2499 #define SFP_WAVELENGTH_LL1550   1550
2500
2501
2502 /*
2503  *  * SFF-8472 TABLE 3.4
2504  *   */
2505 #define  SFF_PG0_CONNECTOR_UNKNOWN    0x00   /* Unknown  */
2506 #define  SFF_PG0_CONNECTOR_SC         0x01   /* SC       */
2507 #define  SFF_PG0_CONNECTOR_FC_COPPER1 0x02   /* FC style 1 copper connector */
2508 #define  SFF_PG0_CONNECTOR_FC_COPPER2 0x03   /* FC style 2 copper connector */
2509 #define  SFF_PG0_CONNECTOR_BNC        0x04   /* BNC / TNC */
2510 #define  SFF_PG0_CONNECTOR__FC_COAX   0x05   /* FC coaxial headers */
2511 #define  SFF_PG0_CONNECTOR_FIBERJACK  0x06   /* FiberJack */
2512 #define  SFF_PG0_CONNECTOR_LC         0x07   /* LC        */
2513 #define  SFF_PG0_CONNECTOR_MT         0x08   /* MT - RJ   */
2514 #define  SFF_PG0_CONNECTOR_MU         0x09   /* MU        */
2515 #define  SFF_PG0_CONNECTOR_SF         0x0A   /* SG        */
2516 #define  SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
2517 #define  SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
2518 #define  SFF_PG0_CONNECTOR_HSSDC_II   0x20   /* HSSDC II */
2519 #define  SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
2520 #define  SFF_PG0_CONNECTOR_RJ45       0x22  /* RJ45 */
2521
2522 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
2523
2524 #define SSF_IDENTIFIER                  0
2525 #define SSF_EXT_IDENTIFIER              1
2526 #define SSF_CONNECTOR                   2
2527 #define SSF_TRANSCEIVER_CODE_B0         3
2528 #define SSF_TRANSCEIVER_CODE_B1         4
2529 #define SSF_TRANSCEIVER_CODE_B2         5
2530 #define SSF_TRANSCEIVER_CODE_B3         6
2531 #define SSF_TRANSCEIVER_CODE_B4         7
2532 #define SSF_TRANSCEIVER_CODE_B5         8
2533 #define SSF_TRANSCEIVER_CODE_B6         9
2534 #define SSF_TRANSCEIVER_CODE_B7         10
2535 #define SSF_ENCODING                    11
2536 #define SSF_BR_NOMINAL                  12
2537 #define SSF_RATE_IDENTIFIER             13
2538 #define SSF_LENGTH_9UM_KM               14
2539 #define SSF_LENGTH_9UM                  15
2540 #define SSF_LENGTH_50UM_OM2             16
2541 #define SSF_LENGTH_62UM_OM1             17
2542 #define SFF_LENGTH_COPPER               18
2543 #define SSF_LENGTH_50UM_OM3             19
2544 #define SSF_VENDOR_NAME                 20
2545 #define SSF_VENDOR_OUI                  36
2546 #define SSF_VENDOR_PN                   40
2547 #define SSF_VENDOR_REV                  56
2548 #define SSF_WAVELENGTH_B1               60
2549 #define SSF_WAVELENGTH_B0               61
2550 #define SSF_CC_BASE                     63
2551 #define SSF_OPTIONS_B1                  64
2552 #define SSF_OPTIONS_B0                  65
2553 #define SSF_BR_MAX                      66
2554 #define SSF_BR_MIN                      67
2555 #define SSF_VENDOR_SN                   68
2556 #define SSF_DATE_CODE                   84
2557 #define SSF_MONITORING_TYPEDIAGNOSTIC   92
2558 #define SSF_ENHANCED_OPTIONS            93
2559 #define SFF_8472_COMPLIANCE             94
2560 #define SSF_CC_EXT                      95
2561 #define SSF_A0_VENDOR_SPECIFIC          96
2562
2563 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
2564
2565 #define SSF_TEMP_HIGH_ALARM             0
2566 #define SSF_TEMP_LOW_ALARM              2
2567 #define SSF_TEMP_HIGH_WARNING           4
2568 #define SSF_TEMP_LOW_WARNING            6
2569 #define SSF_VOLTAGE_HIGH_ALARM          8
2570 #define SSF_VOLTAGE_LOW_ALARM           10
2571 #define SSF_VOLTAGE_HIGH_WARNING        12
2572 #define SSF_VOLTAGE_LOW_WARNING         14
2573 #define SSF_BIAS_HIGH_ALARM             16
2574 #define SSF_BIAS_LOW_ALARM              18
2575 #define SSF_BIAS_HIGH_WARNING           20
2576 #define SSF_BIAS_LOW_WARNING            22
2577 #define SSF_TXPOWER_HIGH_ALARM          24
2578 #define SSF_TXPOWER_LOW_ALARM           26
2579 #define SSF_TXPOWER_HIGH_WARNING        28
2580 #define SSF_TXPOWER_LOW_WARNING         30
2581 #define SSF_RXPOWER_HIGH_ALARM          32
2582 #define SSF_RXPOWER_LOW_ALARM           34
2583 #define SSF_RXPOWER_HIGH_WARNING        36
2584 #define SSF_RXPOWER_LOW_WARNING         38
2585 #define SSF_EXT_CAL_CONSTANTS           56
2586 #define SSF_CC_DMI                      95
2587 #define SFF_TEMPERATURE_B1              96
2588 #define SFF_TEMPERATURE_B0              97
2589 #define SFF_VCC_B1                      98
2590 #define SFF_VCC_B0                      99
2591 #define SFF_TX_BIAS_CURRENT_B1          100
2592 #define SFF_TX_BIAS_CURRENT_B0          101
2593 #define SFF_TXPOWER_B1                  102
2594 #define SFF_TXPOWER_B0                  103
2595 #define SFF_RXPOWER_B1                  104
2596 #define SFF_RXPOWER_B0                  105
2597 #define SSF_STATUS_CONTROL              110
2598 #define SSF_ALARM_FLAGS                 112
2599 #define SSF_WARNING_FLAGS               116
2600 #define SSF_EXT_TATUS_CONTROL_B1        118
2601 #define SSF_EXT_TATUS_CONTROL_B0        119
2602 #define SSF_A2_VENDOR_SPECIFIC          120
2603 #define SSF_USER_EEPROM                 128
2604 #define SSF_VENDOR_CONTROL              148
2605
2606
2607 /*
2608  * Tranceiver codes Fibre Channel SFF-8472
2609  * Table 3.5.
2610  */
2611
2612 struct sff_trasnceiver_codes_byte0 {
2613         uint8_t inifiband:4;
2614         uint8_t teng_ethernet:4;
2615 };
2616
2617 struct sff_trasnceiver_codes_byte1 {
2618         uint8_t  sonet:6;
2619         uint8_t  escon:2;
2620 };
2621
2622 struct sff_trasnceiver_codes_byte2 {
2623         uint8_t  soNet:8;
2624 };
2625
2626 struct sff_trasnceiver_codes_byte3 {
2627         uint8_t ethernet:8;
2628 };
2629
2630 struct sff_trasnceiver_codes_byte4 {
2631         uint8_t fc_el_lo:1;
2632         uint8_t fc_lw_laser:1;
2633         uint8_t fc_sw_laser:1;
2634         uint8_t fc_md_distance:1;
2635         uint8_t fc_lg_distance:1;
2636         uint8_t fc_int_distance:1;
2637         uint8_t fc_short_distance:1;
2638         uint8_t fc_vld_distance:1;
2639 };
2640
2641 struct sff_trasnceiver_codes_byte5 {
2642         uint8_t reserved1:1;
2643         uint8_t reserved2:1;
2644         uint8_t fc_sfp_active:1;  /* Active cable   */
2645         uint8_t fc_sfp_passive:1; /* Passive cable  */
2646         uint8_t fc_lw_laser:1;     /* Longwave laser */
2647         uint8_t fc_sw_laser_sl:1;
2648         uint8_t fc_sw_laser_sn:1;
2649         uint8_t fc_el_hi:1;        /* Electrical enclosure high bit */
2650 };
2651
2652 struct sff_trasnceiver_codes_byte6 {
2653         uint8_t fc_tm_sm:1;      /* Single Mode */
2654         uint8_t reserved:1;
2655         uint8_t fc_tm_m6:1;       /* Multimode, 62.5um (M6) */
2656         uint8_t fc_tm_tv:1;      /* Video Coax (TV) */
2657         uint8_t fc_tm_mi:1;      /* Miniature Coax (MI) */
2658         uint8_t fc_tm_tp:1;      /* Twisted Pair (TP) */
2659         uint8_t fc_tm_tw:1;      /* Twin Axial Pair  */
2660 };
2661
2662 struct sff_trasnceiver_codes_byte7 {
2663         uint8_t fc_sp_100MB:1;   /*  100 MB/sec */
2664         uint8_t reserve:1;
2665         uint8_t fc_sp_200mb:1;   /*  200 MB/sec */
2666         uint8_t fc_sp_3200MB:1;  /* 3200 MB/sec */
2667         uint8_t fc_sp_400MB:1;   /*  400 MB/sec */
2668         uint8_t fc_sp_1600MB:1;  /* 1600 MB/sec */
2669         uint8_t fc_sp_800MB:1;   /*  800 MB/sec */
2670         uint8_t fc_sp_1200MB:1;  /* 1200 MB/sec */
2671 };
2672
2673 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
2674 struct user_eeprom {
2675         uint8_t vendor_name[16];
2676         uint8_t vendor_oui[3];
2677         uint8_t vendor_pn[816];
2678         uint8_t vendor_rev[4];
2679         uint8_t vendor_sn[16];
2680         uint8_t datecode[6];
2681         uint8_t lot_code[2];
2682         uint8_t reserved191[57];
2683 };
2684
2685 struct lpfc_mbx_pc_sli4_params {
2686         uint32_t word1;
2687 #define qs_SHIFT                                0
2688 #define qs_MASK                                 0x00000001
2689 #define qs_WORD                                 word1
2690 #define wr_SHIFT                                1
2691 #define wr_MASK                                 0x00000001
2692 #define wr_WORD                                 word1
2693 #define pf_SHIFT                                8
2694 #define pf_MASK                                 0x000000ff
2695 #define pf_WORD                                 word1
2696 #define cpn_SHIFT                               16
2697 #define cpn_MASK                                0x000000ff
2698 #define cpn_WORD                                word1
2699         uint32_t word2;
2700 #define if_type_SHIFT                           0
2701 #define if_type_MASK                            0x00000007
2702 #define if_type_WORD                            word2
2703 #define sli_rev_SHIFT                           4
2704 #define sli_rev_MASK                            0x0000000f
2705 #define sli_rev_WORD                            word2
2706 #define sli_family_SHIFT                        8
2707 #define sli_family_MASK                         0x000000ff
2708 #define sli_family_WORD                         word2
2709 #define featurelevel_1_SHIFT                    16
2710 #define featurelevel_1_MASK                     0x000000ff
2711 #define featurelevel_1_WORD                     word2
2712 #define featurelevel_2_SHIFT                    24
2713 #define featurelevel_2_MASK                     0x0000001f
2714 #define featurelevel_2_WORD                     word2
2715         uint32_t word3;
2716 #define fcoe_SHIFT                              0
2717 #define fcoe_MASK                               0x00000001
2718 #define fcoe_WORD                               word3
2719 #define fc_SHIFT                                1
2720 #define fc_MASK                                 0x00000001
2721 #define fc_WORD                                 word3
2722 #define nic_SHIFT                               2
2723 #define nic_MASK                                0x00000001
2724 #define nic_WORD                                word3
2725 #define iscsi_SHIFT                             3
2726 #define iscsi_MASK                              0x00000001
2727 #define iscsi_WORD                              word3
2728 #define rdma_SHIFT                              4
2729 #define rdma_MASK                               0x00000001
2730 #define rdma_WORD                               word3
2731         uint32_t sge_supp_len;
2732 #define SLI4_PAGE_SIZE 4096
2733         uint32_t word5;
2734 #define if_page_sz_SHIFT                        0
2735 #define if_page_sz_MASK                         0x0000ffff
2736 #define if_page_sz_WORD                         word5
2737 #define loopbk_scope_SHIFT                      24
2738 #define loopbk_scope_MASK                       0x0000000f
2739 #define loopbk_scope_WORD                       word5
2740 #define rq_db_window_SHIFT                      28
2741 #define rq_db_window_MASK                       0x0000000f
2742 #define rq_db_window_WORD                       word5
2743         uint32_t word6;
2744 #define eq_pages_SHIFT                          0
2745 #define eq_pages_MASK                           0x0000000f
2746 #define eq_pages_WORD                           word6
2747 #define eqe_size_SHIFT                          8
2748 #define eqe_size_MASK                           0x000000ff
2749 #define eqe_size_WORD                           word6
2750         uint32_t word7;
2751 #define cq_pages_SHIFT                          0
2752 #define cq_pages_MASK                           0x0000000f
2753 #define cq_pages_WORD                           word7
2754 #define cqe_size_SHIFT                          8
2755 #define cqe_size_MASK                           0x000000ff
2756 #define cqe_size_WORD                           word7
2757         uint32_t word8;
2758 #define mq_pages_SHIFT                          0
2759 #define mq_pages_MASK                           0x0000000f
2760 #define mq_pages_WORD                           word8
2761 #define mqe_size_SHIFT                          8
2762 #define mqe_size_MASK                           0x000000ff
2763 #define mqe_size_WORD                           word8
2764 #define mq_elem_cnt_SHIFT                       16
2765 #define mq_elem_cnt_MASK                        0x000000ff
2766 #define mq_elem_cnt_WORD                        word8
2767         uint32_t word9;
2768 #define wq_pages_SHIFT                          0
2769 #define wq_pages_MASK                           0x0000ffff
2770 #define wq_pages_WORD                           word9
2771 #define wqe_size_SHIFT                          8
2772 #define wqe_size_MASK                           0x000000ff
2773 #define wqe_size_WORD                           word9
2774         uint32_t word10;
2775 #define rq_pages_SHIFT                          0
2776 #define rq_pages_MASK                           0x0000ffff
2777 #define rq_pages_WORD                           word10
2778 #define rqe_size_SHIFT                          8
2779 #define rqe_size_MASK                           0x000000ff
2780 #define rqe_size_WORD                           word10
2781         uint32_t word11;
2782 #define hdr_pages_SHIFT                         0
2783 #define hdr_pages_MASK                          0x0000000f
2784 #define hdr_pages_WORD                          word11
2785 #define hdr_size_SHIFT                          8
2786 #define hdr_size_MASK                           0x0000000f
2787 #define hdr_size_WORD                           word11
2788 #define hdr_pp_align_SHIFT                      16
2789 #define hdr_pp_align_MASK                       0x0000ffff
2790 #define hdr_pp_align_WORD                       word11
2791         uint32_t word12;
2792 #define sgl_pages_SHIFT                         0
2793 #define sgl_pages_MASK                          0x0000000f
2794 #define sgl_pages_WORD                          word12
2795 #define sgl_pp_align_SHIFT                      16
2796 #define sgl_pp_align_MASK                       0x0000ffff
2797 #define sgl_pp_align_WORD                       word12
2798         uint32_t rsvd_13_63[51];
2799 };
2800 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
2801                                &(~((SLI4_PAGE_SIZE)-1)))
2802
2803 struct lpfc_sli4_parameters {
2804         uint32_t word0;
2805 #define cfg_prot_type_SHIFT                     0
2806 #define cfg_prot_type_MASK                      0x000000FF
2807 #define cfg_prot_type_WORD                      word0
2808         uint32_t word1;
2809 #define cfg_ft_SHIFT                            0
2810 #define cfg_ft_MASK                             0x00000001
2811 #define cfg_ft_WORD                             word1
2812 #define cfg_sli_rev_SHIFT                       4
2813 #define cfg_sli_rev_MASK                        0x0000000f
2814 #define cfg_sli_rev_WORD                        word1
2815 #define cfg_sli_family_SHIFT                    8
2816 #define cfg_sli_family_MASK                     0x0000000f
2817 #define cfg_sli_family_WORD                     word1
2818 #define cfg_if_type_SHIFT                       12
2819 #define cfg_if_type_MASK                        0x0000000f
2820 #define cfg_if_type_WORD                        word1
2821 #define cfg_sli_hint_1_SHIFT                    16
2822 #define cfg_sli_hint_1_MASK                     0x000000ff
2823 #define cfg_sli_hint_1_WORD                     word1
2824 #define cfg_sli_hint_2_SHIFT                    24
2825 #define cfg_sli_hint_2_MASK                     0x0000001f
2826 #define cfg_sli_hint_2_WORD                     word1
2827         uint32_t word2;
2828         uint32_t word3;
2829         uint32_t word4;
2830 #define cfg_cqv_SHIFT                           14
2831 #define cfg_cqv_MASK                            0x00000003
2832 #define cfg_cqv_WORD                            word4
2833         uint32_t word5;
2834         uint32_t word6;
2835 #define cfg_mqv_SHIFT                           14
2836 #define cfg_mqv_MASK                            0x00000003
2837 #define cfg_mqv_WORD                            word6
2838         uint32_t word7;
2839         uint32_t word8;
2840 #define cfg_wqsize_SHIFT                        8
2841 #define cfg_wqsize_MASK                         0x0000000f
2842 #define cfg_wqsize_WORD                         word8
2843 #define cfg_wqv_SHIFT                           14
2844 #define cfg_wqv_MASK                            0x00000003
2845 #define cfg_wqv_WORD                            word8
2846         uint32_t word9;
2847         uint32_t word10;
2848 #define cfg_rqv_SHIFT                           14
2849 #define cfg_rqv_MASK                            0x00000003
2850 #define cfg_rqv_WORD                            word10
2851         uint32_t word11;
2852 #define cfg_rq_db_window_SHIFT                  28
2853 #define cfg_rq_db_window_MASK                   0x0000000f
2854 #define cfg_rq_db_window_WORD                   word11
2855         uint32_t word12;
2856 #define cfg_fcoe_SHIFT                          0
2857 #define cfg_fcoe_MASK                           0x00000001
2858 #define cfg_fcoe_WORD                           word12
2859 #define cfg_ext_SHIFT                           1
2860 #define cfg_ext_MASK                            0x00000001
2861 #define cfg_ext_WORD                            word12
2862 #define cfg_hdrr_SHIFT                          2
2863 #define cfg_hdrr_MASK                           0x00000001
2864 #define cfg_hdrr_WORD                           word12
2865 #define cfg_phwq_SHIFT                          15
2866 #define cfg_phwq_MASK                           0x00000001
2867 #define cfg_phwq_WORD                           word12
2868 #define cfg_oas_SHIFT                           25
2869 #define cfg_oas_MASK                            0x00000001
2870 #define cfg_oas_WORD                            word12
2871 #define cfg_loopbk_scope_SHIFT                  28
2872 #define cfg_loopbk_scope_MASK                   0x0000000f
2873 #define cfg_loopbk_scope_WORD                   word12
2874         uint32_t sge_supp_len;
2875         uint32_t word14;
2876 #define cfg_sgl_page_cnt_SHIFT                  0
2877 #define cfg_sgl_page_cnt_MASK                   0x0000000f
2878 #define cfg_sgl_page_cnt_WORD                   word14
2879 #define cfg_sgl_page_size_SHIFT                 8
2880 #define cfg_sgl_page_size_MASK                  0x000000ff
2881 #define cfg_sgl_page_size_WORD                  word14
2882 #define cfg_sgl_pp_align_SHIFT                  16
2883 #define cfg_sgl_pp_align_MASK                   0x000000ff
2884 #define cfg_sgl_pp_align_WORD                   word14
2885         uint32_t word15;
2886         uint32_t word16;
2887         uint32_t word17;
2888         uint32_t word18;
2889         uint32_t word19;
2890 #define cfg_ext_embed_cb_SHIFT                  0
2891 #define cfg_ext_embed_cb_MASK                   0x00000001
2892 #define cfg_ext_embed_cb_WORD                   word19
2893 #define cfg_mds_diags_SHIFT                     1
2894 #define cfg_mds_diags_MASK                      0x00000001
2895 #define cfg_mds_diags_WORD                      word19
2896 };
2897
2898 #define LPFC_SET_UE_RECOVERY            0x10
2899 #define LPFC_SET_MDS_DIAGS              0x11
2900 struct lpfc_mbx_set_feature {
2901         struct mbox_header header;
2902         uint32_t feature;
2903         uint32_t param_len;
2904         uint32_t word6;
2905 #define lpfc_mbx_set_feature_UER_SHIFT  0
2906 #define lpfc_mbx_set_feature_UER_MASK   0x00000001
2907 #define lpfc_mbx_set_feature_UER_WORD   word6
2908 #define lpfc_mbx_set_feature_mds_SHIFT  0
2909 #define lpfc_mbx_set_feature_mds_MASK   0x00000001
2910 #define lpfc_mbx_set_feature_mds_WORD   word6
2911 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT  1
2912 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK   0x00000001
2913 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD   word6
2914         uint32_t word7;
2915 #define lpfc_mbx_set_feature_UERP_SHIFT 0
2916 #define lpfc_mbx_set_feature_UERP_MASK  0x0000ffff
2917 #define lpfc_mbx_set_feature_UERP_WORD  word7
2918 #define lpfc_mbx_set_feature_UESR_SHIFT 16
2919 #define lpfc_mbx_set_feature_UESR_MASK  0x0000ffff
2920 #define lpfc_mbx_set_feature_UESR_WORD  word7
2921 };
2922
2923
2924 struct lpfc_mbx_get_sli4_parameters {
2925         struct mbox_header header;
2926         struct lpfc_sli4_parameters sli4_parameters;
2927 };
2928
2929 struct lpfc_rscr_desc_generic {
2930 #define LPFC_RSRC_DESC_WSIZE                    22
2931         uint32_t desc[LPFC_RSRC_DESC_WSIZE];
2932 };
2933
2934 struct lpfc_rsrc_desc_pcie {
2935         uint32_t word0;
2936 #define lpfc_rsrc_desc_pcie_type_SHIFT          0
2937 #define lpfc_rsrc_desc_pcie_type_MASK           0x000000ff
2938 #define lpfc_rsrc_desc_pcie_type_WORD           word0
2939 #define LPFC_RSRC_DESC_TYPE_PCIE                0x40
2940 #define lpfc_rsrc_desc_pcie_length_SHIFT        8
2941 #define lpfc_rsrc_desc_pcie_length_MASK         0x000000ff
2942 #define lpfc_rsrc_desc_pcie_length_WORD         word0
2943         uint32_t word1;
2944 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT         0
2945 #define lpfc_rsrc_desc_pcie_pfnum_MASK          0x000000ff
2946 #define lpfc_rsrc_desc_pcie_pfnum_WORD          word1
2947         uint32_t reserved;
2948         uint32_t word3;
2949 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT     0
2950 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK      0x000000ff
2951 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD      word3
2952 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT        8
2953 #define lpfc_rsrc_desc_pcie_pf_sta_MASK         0x000000ff
2954 #define lpfc_rsrc_desc_pcie_pf_sta_WORD         word3
2955 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT       16
2956 #define lpfc_rsrc_desc_pcie_pf_type_MASK        0x000000ff
2957 #define lpfc_rsrc_desc_pcie_pf_type_WORD        word3
2958         uint32_t word4;
2959 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT     0
2960 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK      0x0000ffff
2961 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD      word4
2962 };
2963
2964 struct lpfc_rsrc_desc_fcfcoe {
2965         uint32_t word0;
2966 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT        0
2967 #define lpfc_rsrc_desc_fcfcoe_type_MASK         0x000000ff
2968 #define lpfc_rsrc_desc_fcfcoe_type_WORD         word0
2969 #define LPFC_RSRC_DESC_TYPE_FCFCOE              0x43
2970 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT      8
2971 #define lpfc_rsrc_desc_fcfcoe_length_MASK       0x000000ff
2972 #define lpfc_rsrc_desc_fcfcoe_length_WORD       word0
2973 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD      0
2974 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH    72
2975 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH    88
2976         uint32_t word1;
2977 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT       0
2978 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK        0x000000ff
2979 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD        word1
2980 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT       16
2981 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
2982 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
2983         uint32_t word2;
2984 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT     0
2985 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK      0x0000ffff
2986 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD      word2
2987 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT     16
2988 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK      0x0000ffff
2989 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD      word2
2990         uint32_t word3;
2991 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT      0
2992 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK       0x0000ffff
2993 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD       word3
2994 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT      16
2995 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK       0x0000ffff
2996 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD       word3
2997         uint32_t word4;
2998 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT      0
2999 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK       0x0000ffff
3000 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD       word4
3001 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT     16
3002 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK      0x0000ffff
3003 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD      word4
3004         uint32_t word5;
3005 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT    0
3006 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK     0x0000ffff
3007 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD     word5
3008 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT     16
3009 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK      0x0000ffff
3010 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD      word5
3011         uint32_t word6;
3012         uint32_t word7;
3013         uint32_t word8;
3014         uint32_t word9;
3015         uint32_t word10;
3016         uint32_t word11;
3017         uint32_t word12;
3018         uint32_t word13;
3019 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT      0
3020 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK       0x0000003f
3021 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD       word13
3022 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
3023 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK       0x00000003
3024 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD       word13
3025 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT         8
3026 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK          0x00000001
3027 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD          word13
3028 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT         9
3029 #define lpfc_rsrc_desc_fcfcoe_lld_MASK          0x00000001
3030 #define lpfc_rsrc_desc_fcfcoe_lld_WORD          word13
3031 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT      16
3032 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK       0x0000ffff
3033 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD       word13
3034 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3035         uint32_t bw_min;
3036         uint32_t bw_max;
3037         uint32_t iops_min;
3038         uint32_t iops_max;
3039         uint32_t reserved[4];
3040 };
3041
3042 struct lpfc_func_cfg {
3043 #define LPFC_RSRC_DESC_MAX_NUM                  2
3044         uint32_t rsrc_desc_count;
3045         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3046 };
3047
3048 struct lpfc_mbx_get_func_cfg {
3049         struct mbox_header header;
3050 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3051 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3052 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3053         struct lpfc_func_cfg func_cfg;
3054 };
3055
3056 struct lpfc_prof_cfg {
3057 #define LPFC_RSRC_DESC_MAX_NUM                  2
3058         uint32_t rsrc_desc_count;
3059         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3060 };
3061
3062 struct lpfc_mbx_get_prof_cfg {
3063         struct mbox_header header;
3064 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3065 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3066 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3067         union {
3068                 struct {
3069                         uint32_t word10;
3070 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT     0
3071 #define lpfc_mbx_get_prof_cfg_prof_id_MASK      0x000000ff
3072 #define lpfc_mbx_get_prof_cfg_prof_id_WORD      word10
3073 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT     8
3074 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK      0x00000003
3075 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD      word10
3076                 } request;
3077                 struct {
3078                         struct lpfc_prof_cfg prof_cfg;
3079                 } response;
3080         } u;
3081 };
3082
3083 struct lpfc_controller_attribute {
3084         uint32_t version_string[8];
3085         uint32_t manufacturer_name[8];
3086         uint32_t supported_modes;
3087         uint32_t word17;
3088 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT       0
3089 #define lpfc_cntl_attr_eprom_ver_lo_MASK        0x000000ff
3090 #define lpfc_cntl_attr_eprom_ver_lo_WORD        word17
3091 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT       8
3092 #define lpfc_cntl_attr_eprom_ver_hi_MASK        0x000000ff
3093 #define lpfc_cntl_attr_eprom_ver_hi_WORD        word17
3094         uint32_t mbx_da_struct_ver;
3095         uint32_t ep_fw_da_struct_ver;
3096         uint32_t ncsi_ver_str[3];
3097         uint32_t dflt_ext_timeout;
3098         uint32_t model_number[8];
3099         uint32_t description[16];
3100         uint32_t serial_number[8];
3101         uint32_t ip_ver_str[8];
3102         uint32_t fw_ver_str[8];
3103         uint32_t bios_ver_str[8];
3104         uint32_t redboot_ver_str[8];
3105         uint32_t driver_ver_str[8];
3106         uint32_t flash_fw_ver_str[8];
3107         uint32_t functionality;
3108         uint32_t word105;
3109 #define lpfc_cntl_attr_max_cbd_len_SHIFT        0
3110 #define lpfc_cntl_attr_max_cbd_len_MASK         0x0000ffff
3111 #define lpfc_cntl_attr_max_cbd_len_WORD         word105
3112 #define lpfc_cntl_attr_asic_rev_SHIFT           16
3113 #define lpfc_cntl_attr_asic_rev_MASK            0x000000ff
3114 #define lpfc_cntl_attr_asic_rev_WORD            word105
3115 #define lpfc_cntl_attr_gen_guid0_SHIFT          24
3116 #define lpfc_cntl_attr_gen_guid0_MASK           0x000000ff
3117 #define lpfc_cntl_attr_gen_guid0_WORD           word105
3118         uint32_t gen_guid1_12[3];
3119         uint32_t word109;
3120 #define lpfc_cntl_attr_gen_guid13_14_SHIFT      0
3121 #define lpfc_cntl_attr_gen_guid13_14_MASK       0x0000ffff
3122 #define lpfc_cntl_attr_gen_guid13_14_WORD       word109
3123 #define lpfc_cntl_attr_gen_guid15_SHIFT         16
3124 #define lpfc_cntl_attr_gen_guid15_MASK          0x000000ff
3125 #define lpfc_cntl_attr_gen_guid15_WORD          word109
3126 #define lpfc_cntl_attr_hba_port_cnt_SHIFT       24
3127 #define lpfc_cntl_attr_hba_port_cnt_MASK        0x000000ff
3128 #define lpfc_cntl_attr_hba_port_cnt_WORD        word109
3129         uint32_t word110;
3130 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT       0
3131 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK        0x0000ffff
3132 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD        word110
3133 #define lpfc_cntl_attr_multi_func_dev_SHIFT     24
3134 #define lpfc_cntl_attr_multi_func_dev_MASK      0x000000ff
3135 #define lpfc_cntl_attr_multi_func_dev_WORD      word110
3136         uint32_t word111;
3137 #define lpfc_cntl_attr_cache_valid_SHIFT        0
3138 #define lpfc_cntl_attr_cache_valid_MASK         0x000000ff
3139 #define lpfc_cntl_attr_cache_valid_WORD         word111
3140 #define lpfc_cntl_attr_hba_status_SHIFT         8
3141 #define lpfc_cntl_attr_hba_status_MASK          0x000000ff
3142 #define lpfc_cntl_attr_hba_status_WORD          word111
3143 #define lpfc_cntl_attr_max_domain_SHIFT         16
3144 #define lpfc_cntl_attr_max_domain_MASK          0x000000ff
3145 #define lpfc_cntl_attr_max_domain_WORD          word111
3146 #define lpfc_cntl_attr_lnk_numb_SHIFT           24
3147 #define lpfc_cntl_attr_lnk_numb_MASK            0x0000003f
3148 #define lpfc_cntl_attr_lnk_numb_WORD            word111
3149 #define lpfc_cntl_attr_lnk_type_SHIFT           30
3150 #define lpfc_cntl_attr_lnk_type_MASK            0x00000003
3151 #define lpfc_cntl_attr_lnk_type_WORD            word111
3152         uint32_t fw_post_status;
3153         uint32_t hba_mtu[8];
3154         uint32_t word121;
3155         uint32_t reserved1[3];
3156         uint32_t word125;
3157 #define lpfc_cntl_attr_pci_vendor_id_SHIFT      0
3158 #define lpfc_cntl_attr_pci_vendor_id_MASK       0x0000ffff
3159 #define lpfc_cntl_attr_pci_vendor_id_WORD       word125
3160 #define lpfc_cntl_attr_pci_device_id_SHIFT      16
3161 #define lpfc_cntl_attr_pci_device_id_MASK       0x0000ffff
3162 #define lpfc_cntl_attr_pci_device_id_WORD       word125
3163         uint32_t word126;
3164 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT      0
3165 #define lpfc_cntl_attr_pci_subvdr_id_MASK       0x0000ffff
3166 #define lpfc_cntl_attr_pci_subvdr_id_WORD       word126
3167 #define lpfc_cntl_attr_pci_subsys_id_SHIFT      16
3168 #define lpfc_cntl_attr_pci_subsys_id_MASK       0x0000ffff
3169 #define lpfc_cntl_attr_pci_subsys_id_WORD       word126
3170         uint32_t word127;
3171 #define lpfc_cntl_attr_pci_bus_num_SHIFT        0
3172 #define lpfc_cntl_attr_pci_bus_num_MASK         0x000000ff
3173 #define lpfc_cntl_attr_pci_bus_num_WORD         word127
3174 #define lpfc_cntl_attr_pci_dev_num_SHIFT        8
3175 #define lpfc_cntl_attr_pci_dev_num_MASK         0x000000ff
3176 #define lpfc_cntl_attr_pci_dev_num_WORD         word127
3177 #define lpfc_cntl_attr_pci_fnc_num_SHIFT        16
3178 #define lpfc_cntl_attr_pci_fnc_num_MASK         0x000000ff
3179 #define lpfc_cntl_attr_pci_fnc_num_WORD         word127
3180 #define lpfc_cntl_attr_inf_type_SHIFT           24
3181 #define lpfc_cntl_attr_inf_type_MASK            0x000000ff
3182 #define lpfc_cntl_attr_inf_type_WORD            word127
3183         uint32_t unique_id[2];
3184         uint32_t word130;
3185 #define lpfc_cntl_attr_num_netfil_SHIFT         0
3186 #define lpfc_cntl_attr_num_netfil_MASK          0x000000ff
3187 #define lpfc_cntl_attr_num_netfil_WORD          word130
3188         uint32_t reserved2[4];
3189 };
3190
3191 struct lpfc_mbx_get_cntl_attributes {
3192         union  lpfc_sli4_cfg_shdr cfg_shdr;
3193         struct lpfc_controller_attribute cntl_attr;
3194 };
3195
3196 struct lpfc_mbx_get_port_name {
3197         struct mbox_header header;
3198         union {
3199                 struct {
3200                         uint32_t word4;
3201 #define lpfc_mbx_get_port_name_lnk_type_SHIFT   0
3202 #define lpfc_mbx_get_port_name_lnk_type_MASK    0x00000003
3203 #define lpfc_mbx_get_port_name_lnk_type_WORD    word4
3204                 } request;
3205                 struct {
3206                         uint32_t word4;
3207 #define lpfc_mbx_get_port_name_name0_SHIFT      0
3208 #define lpfc_mbx_get_port_name_name0_MASK       0x000000FF
3209 #define lpfc_mbx_get_port_name_name0_WORD       word4
3210 #define lpfc_mbx_get_port_name_name1_SHIFT      8
3211 #define lpfc_mbx_get_port_name_name1_MASK       0x000000FF
3212 #define lpfc_mbx_get_port_name_name1_WORD       word4
3213 #define lpfc_mbx_get_port_name_name2_SHIFT      16
3214 #define lpfc_mbx_get_port_name_name2_MASK       0x000000FF
3215 #define lpfc_mbx_get_port_name_name2_WORD       word4
3216 #define lpfc_mbx_get_port_name_name3_SHIFT      24
3217 #define lpfc_mbx_get_port_name_name3_MASK       0x000000FF
3218 #define lpfc_mbx_get_port_name_name3_WORD       word4
3219 #define LPFC_LINK_NUMBER_0                      0
3220 #define LPFC_LINK_NUMBER_1                      1
3221 #define LPFC_LINK_NUMBER_2                      2
3222 #define LPFC_LINK_NUMBER_3                      3
3223                 } response;
3224         } u;
3225 };
3226
3227 /* Mailbox Completion Queue Error Messages */
3228 #define MB_CQE_STATUS_SUCCESS                   0x0
3229 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
3230 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
3231 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
3232 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
3233 #define MB_CQE_STATUS_DMA_FAILED                0x5
3234
3235 #define LPFC_MBX_WR_CONFIG_MAX_BDE              1
3236 struct lpfc_mbx_wr_object {
3237         struct mbox_header header;
3238         union {
3239                 struct {
3240                         uint32_t word4;
3241 #define lpfc_wr_object_eof_SHIFT                31
3242 #define lpfc_wr_object_eof_MASK                 0x00000001
3243 #define lpfc_wr_object_eof_WORD                 word4
3244 #define lpfc_wr_object_write_length_SHIFT       0
3245 #define lpfc_wr_object_write_length_MASK        0x00FFFFFF
3246 #define lpfc_wr_object_write_length_WORD        word4
3247                         uint32_t write_offset;
3248                         uint32_t object_name[26];
3249                         uint32_t bde_count;
3250                         struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3251                 } request;
3252                 struct {
3253                         uint32_t actual_write_length;
3254                 } response;
3255         } u;
3256 };
3257
3258 /* mailbox queue entry structure */
3259 struct lpfc_mqe {
3260         uint32_t word0;
3261 #define lpfc_mqe_status_SHIFT           16
3262 #define lpfc_mqe_status_MASK            0x0000FFFF
3263 #define lpfc_mqe_status_WORD            word0
3264 #define lpfc_mqe_command_SHIFT          8
3265 #define lpfc_mqe_command_MASK           0x000000FF
3266 #define lpfc_mqe_command_WORD           word0
3267         union {
3268                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3269                 /* sli4 mailbox commands */
3270                 struct lpfc_mbx_sli4_config sli4_config;
3271                 struct lpfc_mbx_init_vfi init_vfi;
3272                 struct lpfc_mbx_reg_vfi reg_vfi;
3273                 struct lpfc_mbx_reg_vfi unreg_vfi;
3274                 struct lpfc_mbx_init_vpi init_vpi;
3275                 struct lpfc_mbx_resume_rpi resume_rpi;
3276                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3277                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3278                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3279                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3280                 struct lpfc_mbx_reg_fcfi reg_fcfi;
3281                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3282                 struct lpfc_mbx_mq_create mq_create;
3283                 struct lpfc_mbx_mq_create_ext mq_create_ext;
3284                 struct lpfc_mbx_eq_create eq_create;
3285                 struct lpfc_mbx_modify_eq_delay eq_delay;
3286                 struct lpfc_mbx_cq_create cq_create;
3287                 struct lpfc_mbx_wq_create wq_create;
3288                 struct lpfc_mbx_rq_create rq_create;
3289                 struct lpfc_mbx_mq_destroy mq_destroy;
3290                 struct lpfc_mbx_eq_destroy eq_destroy;
3291                 struct lpfc_mbx_cq_destroy cq_destroy;
3292                 struct lpfc_mbx_wq_destroy wq_destroy;
3293                 struct lpfc_mbx_rq_destroy rq_destroy;
3294                 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3295                 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3296                 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3297                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3298                 struct lpfc_mbx_nembed_cmd nembed_cmd;
3299                 struct lpfc_mbx_read_rev read_rev;
3300                 struct lpfc_mbx_read_vpi read_vpi;
3301                 struct lpfc_mbx_read_config rd_config;
3302                 struct lpfc_mbx_request_features req_ftrs;
3303                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3304                 struct lpfc_mbx_query_fw_config query_fw_cfg;
3305                 struct lpfc_mbx_set_beacon_config beacon_config;
3306                 struct lpfc_mbx_supp_pages supp_pages;
3307                 struct lpfc_mbx_pc_sli4_params sli4_params;
3308                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3309                 struct lpfc_mbx_set_link_diag_state link_diag_state;
3310                 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3311                 struct lpfc_mbx_run_link_diag_test link_diag_test;
3312                 struct lpfc_mbx_get_func_cfg get_func_cfg;
3313                 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3314                 struct lpfc_mbx_wr_object wr_object;
3315                 struct lpfc_mbx_get_port_name get_port_name;
3316                 struct lpfc_mbx_set_feature  set_feature;
3317                 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3318                 struct lpfc_mbx_nop nop;
3319         } un;
3320 };
3321
3322 struct lpfc_mcqe {
3323         uint32_t word0;
3324 #define lpfc_mcqe_status_SHIFT          0
3325 #define lpfc_mcqe_status_MASK           0x0000FFFF
3326 #define lpfc_mcqe_status_WORD           word0
3327 #define lpfc_mcqe_ext_status_SHIFT      16
3328 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
3329 #define lpfc_mcqe_ext_status_WORD       word0
3330         uint32_t mcqe_tag0;
3331         uint32_t mcqe_tag1;
3332         uint32_t trailer;
3333 #define lpfc_trailer_valid_SHIFT        31
3334 #define lpfc_trailer_valid_MASK         0x00000001
3335 #define lpfc_trailer_valid_WORD         trailer
3336 #define lpfc_trailer_async_SHIFT        30
3337 #define lpfc_trailer_async_MASK         0x00000001
3338 #define lpfc_trailer_async_WORD         trailer
3339 #define lpfc_trailer_hpi_SHIFT          29
3340 #define lpfc_trailer_hpi_MASK           0x00000001
3341 #define lpfc_trailer_hpi_WORD           trailer
3342 #define lpfc_trailer_completed_SHIFT    28
3343 #define lpfc_trailer_completed_MASK     0x00000001
3344 #define lpfc_trailer_completed_WORD     trailer
3345 #define lpfc_trailer_consumed_SHIFT     27
3346 #define lpfc_trailer_consumed_MASK      0x00000001
3347 #define lpfc_trailer_consumed_WORD      trailer
3348 #define lpfc_trailer_type_SHIFT         16
3349 #define lpfc_trailer_type_MASK          0x000000FF
3350 #define lpfc_trailer_type_WORD          trailer
3351 #define lpfc_trailer_code_SHIFT         8
3352 #define lpfc_trailer_code_MASK          0x000000FF
3353 #define lpfc_trailer_code_WORD          trailer
3354 #define LPFC_TRAILER_CODE_LINK  0x1
3355 #define LPFC_TRAILER_CODE_FCOE  0x2
3356 #define LPFC_TRAILER_CODE_DCBX  0x3
3357 #define LPFC_TRAILER_CODE_GRP5  0x5
3358 #define LPFC_TRAILER_CODE_FC    0x10
3359 #define LPFC_TRAILER_CODE_SLI   0x11
3360 };
3361
3362 struct lpfc_acqe_link {
3363         uint32_t word0;
3364 #define lpfc_acqe_link_speed_SHIFT              24
3365 #define lpfc_acqe_link_speed_MASK               0x000000FF
3366 #define lpfc_acqe_link_speed_WORD               word0
3367 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
3368 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
3369 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
3370 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
3371 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
3372 #define LPFC_ASYNC_LINK_SPEED_20GBPS            0x5
3373 #define LPFC_ASYNC_LINK_SPEED_25GBPS            0x6
3374 #define LPFC_ASYNC_LINK_SPEED_40GBPS            0x7
3375 #define LPFC_ASYNC_LINK_SPEED_100GBPS           0x8
3376 #define lpfc_acqe_link_duplex_SHIFT             16
3377 #define lpfc_acqe_link_duplex_MASK              0x000000FF
3378 #define lpfc_acqe_link_duplex_WORD              word0
3379 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
3380 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
3381 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
3382 #define lpfc_acqe_link_status_SHIFT             8
3383 #define lpfc_acqe_link_status_MASK              0x000000FF
3384 #define lpfc_acqe_link_status_WORD              word0
3385 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
3386 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
3387 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
3388 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
3389 #define lpfc_acqe_link_type_SHIFT               6
3390 #define lpfc_acqe_link_type_MASK                0x00000003
3391 #define lpfc_acqe_link_type_WORD                word0
3392 #define lpfc_acqe_link_number_SHIFT             0
3393 #define lpfc_acqe_link_number_MASK              0x0000003F
3394 #define lpfc_acqe_link_number_WORD              word0
3395         uint32_t word1;
3396 #define lpfc_acqe_link_fault_SHIFT      0
3397 #define lpfc_acqe_link_fault_MASK       0x000000FF
3398 #define lpfc_acqe_link_fault_WORD       word1
3399 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
3400 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
3401 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
3402 #define lpfc_acqe_logical_link_speed_SHIFT      16
3403 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
3404 #define lpfc_acqe_logical_link_speed_WORD       word1
3405         uint32_t event_tag;
3406         uint32_t trailer;
3407 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
3408 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
3409 };
3410
3411 struct lpfc_acqe_fip {
3412         uint32_t index;
3413         uint32_t word1;
3414 #define lpfc_acqe_fip_fcf_count_SHIFT           0
3415 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
3416 #define lpfc_acqe_fip_fcf_count_WORD            word1
3417 #define lpfc_acqe_fip_event_type_SHIFT          16
3418 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
3419 #define lpfc_acqe_fip_event_type_WORD           word1
3420         uint32_t event_tag;
3421         uint32_t trailer;
3422 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
3423 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
3424 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
3425 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
3426 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
3427 };
3428
3429 struct lpfc_acqe_dcbx {
3430         uint32_t tlv_ttl;
3431         uint32_t reserved;
3432         uint32_t event_tag;
3433         uint32_t trailer;
3434 };
3435
3436 struct lpfc_acqe_grp5 {
3437         uint32_t word0;
3438 #define lpfc_acqe_grp5_type_SHIFT               6
3439 #define lpfc_acqe_grp5_type_MASK                0x00000003
3440 #define lpfc_acqe_grp5_type_WORD                word0
3441 #define lpfc_acqe_grp5_number_SHIFT             0
3442 #define lpfc_acqe_grp5_number_MASK              0x0000003F
3443 #define lpfc_acqe_grp5_number_WORD              word0
3444         uint32_t word1;
3445 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
3446 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
3447 #define lpfc_acqe_grp5_llink_spd_WORD   word1
3448         uint32_t event_tag;
3449         uint32_t trailer;
3450 };
3451
3452 struct lpfc_acqe_fc_la {
3453         uint32_t word0;
3454 #define lpfc_acqe_fc_la_speed_SHIFT             24
3455 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
3456 #define lpfc_acqe_fc_la_speed_WORD              word0
3457 #define LPFC_FC_LA_SPEED_UNKNOWN                0x0
3458 #define LPFC_FC_LA_SPEED_1G             0x1
3459 #define LPFC_FC_LA_SPEED_2G             0x2
3460 #define LPFC_FC_LA_SPEED_4G             0x4
3461 #define LPFC_FC_LA_SPEED_8G             0x8
3462 #define LPFC_FC_LA_SPEED_10G            0xA
3463 #define LPFC_FC_LA_SPEED_16G            0x10
3464 #define LPFC_FC_LA_SPEED_32G            0x20
3465 #define lpfc_acqe_fc_la_topology_SHIFT          16
3466 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
3467 #define lpfc_acqe_fc_la_topology_WORD           word0
3468 #define LPFC_FC_LA_TOP_UNKOWN           0x0
3469 #define LPFC_FC_LA_TOP_P2P              0x1
3470 #define LPFC_FC_LA_TOP_FCAL             0x2
3471 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
3472 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
3473 #define lpfc_acqe_fc_la_att_type_SHIFT          8
3474 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
3475 #define lpfc_acqe_fc_la_att_type_WORD           word0
3476 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
3477 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
3478 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
3479 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN   0x4
3480 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK    0x5
3481 #define lpfc_acqe_fc_la_port_type_SHIFT         6
3482 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
3483 #define lpfc_acqe_fc_la_port_type_WORD          word0
3484 #define LPFC_LINK_TYPE_ETHERNET         0x0
3485 #define LPFC_LINK_TYPE_FC               0x1
3486 #define lpfc_acqe_fc_la_port_number_SHIFT       0
3487 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
3488 #define lpfc_acqe_fc_la_port_number_WORD        word0
3489         uint32_t word1;
3490 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
3491 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
3492 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
3493 #define lpfc_acqe_fc_la_fault_SHIFT             0
3494 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
3495 #define lpfc_acqe_fc_la_fault_WORD              word1
3496 #define LPFC_FC_LA_FAULT_NONE           0x0
3497 #define LPFC_FC_LA_FAULT_LOCAL          0x1
3498 #define LPFC_FC_LA_FAULT_REMOTE         0x2
3499         uint32_t event_tag;
3500         uint32_t trailer;
3501 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
3502 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
3503 };
3504
3505 struct lpfc_acqe_misconfigured_event {
3506         struct {
3507         uint32_t word0;
3508 #define lpfc_sli_misconfigured_port0_state_SHIFT        0
3509 #define lpfc_sli_misconfigured_port0_state_MASK         0x000000FF
3510 #define lpfc_sli_misconfigured_port0_state_WORD         word0
3511 #define lpfc_sli_misconfigured_port1_state_SHIFT        8
3512 #define lpfc_sli_misconfigured_port1_state_MASK         0x000000FF
3513 #define lpfc_sli_misconfigured_port1_state_WORD         word0
3514 #define lpfc_sli_misconfigured_port2_state_SHIFT        16
3515 #define lpfc_sli_misconfigured_port2_state_MASK         0x000000FF
3516 #define lpfc_sli_misconfigured_port2_state_WORD         word0
3517 #define lpfc_sli_misconfigured_port3_state_SHIFT        24
3518 #define lpfc_sli_misconfigured_port3_state_MASK         0x000000FF
3519 #define lpfc_sli_misconfigured_port3_state_WORD         word0
3520         uint32_t word1;
3521 #define lpfc_sli_misconfigured_port0_op_SHIFT           0
3522 #define lpfc_sli_misconfigured_port0_op_MASK            0x00000001
3523 #define lpfc_sli_misconfigured_port0_op_WORD            word1
3524 #define lpfc_sli_misconfigured_port0_severity_SHIFT     1
3525 #define lpfc_sli_misconfigured_port0_severity_MASK      0x00000003
3526 #define lpfc_sli_misconfigured_port0_severity_WORD      word1
3527 #define lpfc_sli_misconfigured_port1_op_SHIFT           8
3528 #define lpfc_sli_misconfigured_port1_op_MASK            0x00000001
3529 #define lpfc_sli_misconfigured_port1_op_WORD            word1
3530 #define lpfc_sli_misconfigured_port1_severity_SHIFT     9
3531 #define lpfc_sli_misconfigured_port1_severity_MASK      0x00000003
3532 #define lpfc_sli_misconfigured_port1_severity_WORD      word1
3533 #define lpfc_sli_misconfigured_port2_op_SHIFT           16
3534 #define lpfc_sli_misconfigured_port2_op_MASK            0x00000001
3535 #define lpfc_sli_misconfigured_port2_op_WORD            word1
3536 #define lpfc_sli_misconfigured_port2_severity_SHIFT     17
3537 #define lpfc_sli_misconfigured_port2_severity_MASK      0x00000003
3538 #define lpfc_sli_misconfigured_port2_severity_WORD      word1
3539 #define lpfc_sli_misconfigured_port3_op_SHIFT           24
3540 #define lpfc_sli_misconfigured_port3_op_MASK            0x00000001
3541 #define lpfc_sli_misconfigured_port3_op_WORD            word1
3542 #define lpfc_sli_misconfigured_port3_severity_SHIFT     25
3543 #define lpfc_sli_misconfigured_port3_severity_MASK      0x00000003
3544 #define lpfc_sli_misconfigured_port3_severity_WORD      word1
3545         } theEvent;
3546 #define LPFC_SLI_EVENT_STATUS_VALID                     0x00
3547 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT       0x01
3548 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE        0x02
3549 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED       0x03
3550 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED       0x04
3551 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED       0x05
3552 };
3553
3554 struct lpfc_acqe_sli {
3555         uint32_t event_data1;
3556         uint32_t event_data2;
3557         uint32_t reserved;
3558         uint32_t trailer;
3559 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
3560 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
3561 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
3562 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
3563 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
3564 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED       0x9
3565 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT        0xA
3566 };
3567
3568 /*
3569  * Define the bootstrap mailbox (bmbx) region used to communicate
3570  * mailbox command between the host and port. The mailbox consists
3571  * of a payload area of 256 bytes and a completion queue of length
3572  * 16 bytes.
3573  */
3574 struct lpfc_bmbx_create {
3575         struct lpfc_mqe mqe;
3576         struct lpfc_mcqe mcqe;
3577 };
3578
3579 #define SGL_ALIGN_SZ 64
3580 #define SGL_PAGE_SIZE 4096
3581 /* align SGL addr on a size boundary - adjust address up */
3582 #define NO_XRI  0xffff
3583
3584 struct wqe_common {
3585         uint32_t word6;
3586 #define wqe_xri_tag_SHIFT     0
3587 #define wqe_xri_tag_MASK      0x0000FFFF
3588 #define wqe_xri_tag_WORD      word6
3589 #define wqe_ctxt_tag_SHIFT    16
3590 #define wqe_ctxt_tag_MASK     0x0000FFFF
3591 #define wqe_ctxt_tag_WORD     word6
3592         uint32_t word7;
3593 #define wqe_dif_SHIFT         0
3594 #define wqe_dif_MASK          0x00000003
3595 #define wqe_dif_WORD          word7
3596 #define LPFC_WQE_DIF_PASSTHRU   1
3597 #define LPFC_WQE_DIF_STRIP      2
3598 #define LPFC_WQE_DIF_INSERT     3
3599 #define wqe_ct_SHIFT          2
3600 #define wqe_ct_MASK           0x00000003
3601 #define wqe_ct_WORD           word7
3602 #define wqe_status_SHIFT      4
3603 #define wqe_status_MASK       0x0000000f
3604 #define wqe_status_WORD       word7
3605 #define wqe_cmnd_SHIFT        8
3606 #define wqe_cmnd_MASK         0x000000ff
3607 #define wqe_cmnd_WORD         word7
3608 #define wqe_class_SHIFT       16
3609 #define wqe_class_MASK        0x00000007
3610 #define wqe_class_WORD        word7
3611 #define wqe_ar_SHIFT          19
3612 #define wqe_ar_MASK           0x00000001
3613 #define wqe_ar_WORD           word7
3614 #define wqe_ag_SHIFT          wqe_ar_SHIFT
3615 #define wqe_ag_MASK           wqe_ar_MASK
3616 #define wqe_ag_WORD           wqe_ar_WORD
3617 #define wqe_pu_SHIFT          20
3618 #define wqe_pu_MASK           0x00000003
3619 #define wqe_pu_WORD           word7
3620 #define wqe_erp_SHIFT         22
3621 #define wqe_erp_MASK          0x00000001
3622 #define wqe_erp_WORD          word7
3623 #define wqe_conf_SHIFT        wqe_erp_SHIFT
3624 #define wqe_conf_MASK         wqe_erp_MASK
3625 #define wqe_conf_WORD         wqe_erp_WORD
3626 #define wqe_lnk_SHIFT         23
3627 #define wqe_lnk_MASK          0x00000001
3628 #define wqe_lnk_WORD          word7
3629 #define wqe_tmo_SHIFT         24
3630 #define wqe_tmo_MASK          0x000000ff
3631 #define wqe_tmo_WORD          word7
3632         uint32_t abort_tag; /* word 8 in WQE */
3633         uint32_t word9;
3634 #define wqe_reqtag_SHIFT      0
3635 #define wqe_reqtag_MASK       0x0000FFFF
3636 #define wqe_reqtag_WORD       word9
3637 #define wqe_temp_rpi_SHIFT    16
3638 #define wqe_temp_rpi_MASK     0x0000FFFF
3639 #define wqe_temp_rpi_WORD     word9
3640 #define wqe_rcvoxid_SHIFT     16
3641 #define wqe_rcvoxid_MASK      0x0000FFFF
3642 #define wqe_rcvoxid_WORD      word9
3643         uint32_t word10;
3644 #define wqe_ebde_cnt_SHIFT    0
3645 #define wqe_ebde_cnt_MASK     0x0000000f
3646 #define wqe_ebde_cnt_WORD     word10
3647 #define wqe_oas_SHIFT         6
3648 #define wqe_oas_MASK          0x00000001
3649 #define wqe_oas_WORD          word10
3650 #define wqe_lenloc_SHIFT      7
3651 #define wqe_lenloc_MASK       0x00000003
3652 #define wqe_lenloc_WORD       word10
3653 #define LPFC_WQE_LENLOC_NONE            0
3654 #define LPFC_WQE_LENLOC_WORD3   1
3655 #define LPFC_WQE_LENLOC_WORD12  2
3656 #define LPFC_WQE_LENLOC_WORD4   3
3657 #define wqe_qosd_SHIFT        9
3658 #define wqe_qosd_MASK         0x00000001
3659 #define wqe_qosd_WORD         word10
3660 #define wqe_xbl_SHIFT         11
3661 #define wqe_xbl_MASK          0x00000001
3662 #define wqe_xbl_WORD          word10
3663 #define wqe_iod_SHIFT         13
3664 #define wqe_iod_MASK          0x00000001
3665 #define wqe_iod_WORD          word10
3666 #define LPFC_WQE_IOD_WRITE      0
3667 #define LPFC_WQE_IOD_READ       1
3668 #define wqe_dbde_SHIFT        14
3669 #define wqe_dbde_MASK         0x00000001
3670 #define wqe_dbde_WORD         word10
3671 #define wqe_wqes_SHIFT        15
3672 #define wqe_wqes_MASK         0x00000001
3673 #define wqe_wqes_WORD         word10
3674 /* Note that this field overlaps above fields */
3675 #define wqe_wqid_SHIFT        1
3676 #define wqe_wqid_MASK         0x00007fff
3677 #define wqe_wqid_WORD         word10
3678 #define wqe_pri_SHIFT         16
3679 #define wqe_pri_MASK          0x00000007
3680 #define wqe_pri_WORD          word10
3681 #define wqe_pv_SHIFT          19
3682 #define wqe_pv_MASK           0x00000001
3683 #define wqe_pv_WORD           word10
3684 #define wqe_xc_SHIFT          21
3685 #define wqe_xc_MASK           0x00000001
3686 #define wqe_xc_WORD           word10
3687 #define wqe_sr_SHIFT          22
3688 #define wqe_sr_MASK           0x00000001
3689 #define wqe_sr_WORD           word10
3690 #define wqe_ccpe_SHIFT        23
3691 #define wqe_ccpe_MASK         0x00000001
3692 #define wqe_ccpe_WORD         word10
3693 #define wqe_ccp_SHIFT         24
3694 #define wqe_ccp_MASK          0x000000ff
3695 #define wqe_ccp_WORD          word10
3696         uint32_t word11;
3697 #define wqe_cmd_type_SHIFT    0
3698 #define wqe_cmd_type_MASK     0x0000000f
3699 #define wqe_cmd_type_WORD     word11
3700 #define wqe_els_id_SHIFT      4
3701 #define wqe_els_id_MASK       0x00000003
3702 #define wqe_els_id_WORD       word11
3703 #define LPFC_ELS_ID_FLOGI       3
3704 #define LPFC_ELS_ID_FDISC       2
3705 #define LPFC_ELS_ID_LOGO        1
3706 #define LPFC_ELS_ID_DEFAULT     0
3707 #define wqe_wqec_SHIFT        7
3708 #define wqe_wqec_MASK         0x00000001
3709 #define wqe_wqec_WORD         word11
3710 #define wqe_cqid_SHIFT        16
3711 #define wqe_cqid_MASK         0x0000ffff
3712 #define wqe_cqid_WORD         word11
3713 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
3714 };
3715
3716 struct wqe_did {
3717         uint32_t word5;
3718 #define wqe_els_did_SHIFT         0
3719 #define wqe_els_did_MASK          0x00FFFFFF
3720 #define wqe_els_did_WORD          word5
3721 #define wqe_xmit_bls_pt_SHIFT         28
3722 #define wqe_xmit_bls_pt_MASK          0x00000003
3723 #define wqe_xmit_bls_pt_WORD          word5
3724 #define wqe_xmit_bls_ar_SHIFT         30
3725 #define wqe_xmit_bls_ar_MASK          0x00000001
3726 #define wqe_xmit_bls_ar_WORD          word5
3727 #define wqe_xmit_bls_xo_SHIFT         31
3728 #define wqe_xmit_bls_xo_MASK          0x00000001
3729 #define wqe_xmit_bls_xo_WORD          word5
3730 };
3731
3732 struct lpfc_wqe_generic{
3733         struct ulp_bde64 bde;
3734         uint32_t word3;
3735         uint32_t word4;
3736         uint32_t word5;
3737         struct wqe_common wqe_com;
3738         uint32_t payload[4];
3739 };
3740
3741 struct els_request64_wqe {
3742         struct ulp_bde64 bde;
3743         uint32_t payload_len;
3744         uint32_t word4;
3745 #define els_req64_sid_SHIFT         0
3746 #define els_req64_sid_MASK          0x00FFFFFF
3747 #define els_req64_sid_WORD          word4
3748 #define els_req64_sp_SHIFT          24
3749 #define els_req64_sp_MASK           0x00000001
3750 #define els_req64_sp_WORD           word4
3751 #define els_req64_vf_SHIFT          25
3752 #define els_req64_vf_MASK           0x00000001
3753 #define els_req64_vf_WORD           word4
3754         struct wqe_did  wqe_dest;
3755         struct wqe_common wqe_com; /* words 6-11 */
3756         uint32_t word12;
3757 #define els_req64_vfid_SHIFT        1
3758 #define els_req64_vfid_MASK         0x00000FFF
3759 #define els_req64_vfid_WORD         word12
3760 #define els_req64_pri_SHIFT         13
3761 #define els_req64_pri_MASK          0x00000007
3762 #define els_req64_pri_WORD          word12
3763         uint32_t word13;
3764 #define els_req64_hopcnt_SHIFT      24
3765 #define els_req64_hopcnt_MASK       0x000000ff
3766 #define els_req64_hopcnt_WORD       word13
3767         uint32_t word14;
3768         uint32_t max_response_payload_len;
3769 };
3770
3771 struct xmit_els_rsp64_wqe {
3772         struct ulp_bde64 bde;
3773         uint32_t response_payload_len;
3774         uint32_t word4;
3775 #define els_rsp64_sid_SHIFT         0
3776 #define els_rsp64_sid_MASK          0x00FFFFFF
3777 #define els_rsp64_sid_WORD          word4
3778 #define els_rsp64_sp_SHIFT          24
3779 #define els_rsp64_sp_MASK           0x00000001
3780 #define els_rsp64_sp_WORD           word4
3781         struct wqe_did wqe_dest;
3782         struct wqe_common wqe_com; /* words 6-11 */
3783         uint32_t word12;
3784 #define wqe_rsp_temp_rpi_SHIFT    0
3785 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
3786 #define wqe_rsp_temp_rpi_WORD     word12
3787         uint32_t rsvd_13_15[3];
3788 };
3789
3790 struct xmit_bls_rsp64_wqe {
3791         uint32_t payload0;
3792 /* Payload0 for BA_ACC */
3793 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
3794 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
3795 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
3796 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
3797 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
3798 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
3799 /* Payload0 for BA_RJT */
3800 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
3801 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
3802 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
3803 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
3804 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
3805 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
3806 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
3807 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
3808 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
3809         uint32_t word1;
3810 #define xmit_bls_rsp64_rxid_SHIFT  0
3811 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
3812 #define xmit_bls_rsp64_rxid_WORD   word1
3813 #define xmit_bls_rsp64_oxid_SHIFT  16
3814 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
3815 #define xmit_bls_rsp64_oxid_WORD   word1
3816         uint32_t word2;
3817 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
3818 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
3819 #define xmit_bls_rsp64_seqcnthi_WORD   word2
3820 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
3821 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
3822 #define xmit_bls_rsp64_seqcntlo_WORD   word2
3823         uint32_t rsrvd3;
3824         uint32_t rsrvd4;
3825         struct wqe_did  wqe_dest;
3826         struct wqe_common wqe_com; /* words 6-11 */
3827         uint32_t word12;
3828 #define xmit_bls_rsp64_temprpi_SHIFT  0
3829 #define xmit_bls_rsp64_temprpi_MASK   0x0000ffff
3830 #define xmit_bls_rsp64_temprpi_WORD   word12
3831         uint32_t rsvd_13_15[3];
3832 };
3833
3834 struct wqe_rctl_dfctl {
3835         uint32_t word5;
3836 #define wqe_si_SHIFT 2
3837 #define wqe_si_MASK  0x000000001
3838 #define wqe_si_WORD  word5
3839 #define wqe_la_SHIFT 3
3840 #define wqe_la_MASK  0x000000001
3841 #define wqe_la_WORD  word5
3842 #define wqe_xo_SHIFT    6
3843 #define wqe_xo_MASK     0x000000001
3844 #define wqe_xo_WORD     word5
3845 #define wqe_ls_SHIFT 7
3846 #define wqe_ls_MASK  0x000000001
3847 #define wqe_ls_WORD  word5
3848 #define wqe_dfctl_SHIFT 8
3849 #define wqe_dfctl_MASK  0x0000000ff
3850 #define wqe_dfctl_WORD  word5
3851 #define wqe_type_SHIFT 16
3852 #define wqe_type_MASK  0x0000000ff
3853 #define wqe_type_WORD  word5
3854 #define wqe_rctl_SHIFT 24
3855 #define wqe_rctl_MASK  0x0000000ff
3856 #define wqe_rctl_WORD  word5
3857 };
3858
3859 struct xmit_seq64_wqe {
3860         struct ulp_bde64 bde;
3861         uint32_t rsvd3;
3862         uint32_t relative_offset;
3863         struct wqe_rctl_dfctl wge_ctl;
3864         struct wqe_common wqe_com; /* words 6-11 */
3865         uint32_t xmit_len;
3866         uint32_t rsvd_12_15[3];
3867 };
3868 struct xmit_bcast64_wqe {
3869         struct ulp_bde64 bde;
3870         uint32_t seq_payload_len;
3871         uint32_t rsvd4;
3872         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3873         struct wqe_common wqe_com;     /* words 6-11 */
3874         uint32_t rsvd_12_15[4];
3875 };
3876
3877 struct gen_req64_wqe {
3878         struct ulp_bde64 bde;
3879         uint32_t request_payload_len;
3880         uint32_t relative_offset;
3881         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3882         struct wqe_common wqe_com;     /* words 6-11 */
3883         uint32_t rsvd_12_14[3];
3884         uint32_t max_response_payload_len;
3885 };
3886
3887 struct create_xri_wqe {
3888         uint32_t rsrvd[5];           /* words 0-4 */
3889         struct wqe_did  wqe_dest;  /* word 5 */
3890         struct wqe_common wqe_com; /* words 6-11 */
3891         uint32_t rsvd_12_15[4];         /* word 12-15 */
3892 };
3893
3894 #define T_REQUEST_TAG 3
3895 #define T_XRI_TAG 1
3896
3897 struct abort_cmd_wqe {
3898         uint32_t rsrvd[3];
3899         uint32_t word3;
3900 #define abort_cmd_ia_SHIFT  0
3901 #define abort_cmd_ia_MASK  0x000000001
3902 #define abort_cmd_ia_WORD  word3
3903 #define abort_cmd_criteria_SHIFT  8
3904 #define abort_cmd_criteria_MASK  0x0000000ff
3905 #define abort_cmd_criteria_WORD  word3
3906         uint32_t rsrvd4;
3907         uint32_t rsrvd5;
3908         struct wqe_common wqe_com;     /* words 6-11 */
3909         uint32_t rsvd_12_15[4];         /* word 12-15 */
3910 };
3911
3912 struct fcp_iwrite64_wqe {
3913         struct ulp_bde64 bde;
3914         uint32_t word3;
3915 #define cmd_buff_len_SHIFT  16
3916 #define cmd_buff_len_MASK  0x00000ffff
3917 #define cmd_buff_len_WORD  word3
3918 #define payload_offset_len_SHIFT 0
3919 #define payload_offset_len_MASK 0x0000ffff
3920 #define payload_offset_len_WORD word3
3921         uint32_t total_xfer_len;
3922         uint32_t initial_xfer_len;
3923         struct wqe_common wqe_com;     /* words 6-11 */
3924         uint32_t rsrvd12;
3925         struct ulp_bde64 ph_bde;       /* words 13-15 */
3926 };
3927
3928 struct fcp_iread64_wqe {
3929         struct ulp_bde64 bde;
3930         uint32_t word3;
3931 #define cmd_buff_len_SHIFT  16
3932 #define cmd_buff_len_MASK  0x00000ffff
3933 #define cmd_buff_len_WORD  word3
3934 #define payload_offset_len_SHIFT 0
3935 #define payload_offset_len_MASK 0x0000ffff
3936 #define payload_offset_len_WORD word3
3937         uint32_t total_xfer_len;       /* word 4 */
3938         uint32_t rsrvd5;               /* word 5 */
3939         struct wqe_common wqe_com;     /* words 6-11 */
3940         uint32_t rsrvd12;
3941         struct ulp_bde64 ph_bde;       /* words 13-15 */
3942 };
3943
3944 struct fcp_icmnd64_wqe {
3945         struct ulp_bde64 bde;          /* words 0-2 */
3946         uint32_t word3;
3947 #define cmd_buff_len_SHIFT  16
3948 #define cmd_buff_len_MASK  0x00000ffff
3949 #define cmd_buff_len_WORD  word3
3950 #define payload_offset_len_SHIFT 0
3951 #define payload_offset_len_MASK 0x0000ffff
3952 #define payload_offset_len_WORD word3
3953         uint32_t rsrvd4;               /* word 4 */
3954         uint32_t rsrvd5;               /* word 5 */
3955         struct wqe_common wqe_com;     /* words 6-11 */
3956         uint32_t rsvd_12_15[4];        /* word 12-15 */
3957 };
3958
3959
3960 union lpfc_wqe {
3961         uint32_t words[16];
3962         struct lpfc_wqe_generic generic;
3963         struct fcp_icmnd64_wqe fcp_icmd;
3964         struct fcp_iread64_wqe fcp_iread;
3965         struct fcp_iwrite64_wqe fcp_iwrite;
3966         struct abort_cmd_wqe abort_cmd;
3967         struct create_xri_wqe create_xri;
3968         struct xmit_bcast64_wqe xmit_bcast64;
3969         struct xmit_seq64_wqe xmit_sequence;
3970         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
3971         struct xmit_els_rsp64_wqe xmit_els_rsp;
3972         struct els_request64_wqe els_req;
3973         struct gen_req64_wqe gen_req;
3974 };
3975
3976 union lpfc_wqe128 {
3977         uint32_t words[32];
3978         struct lpfc_wqe_generic generic;
3979         struct fcp_icmnd64_wqe fcp_icmd;
3980         struct fcp_iread64_wqe fcp_iread;
3981         struct fcp_iwrite64_wqe fcp_iwrite;
3982         struct xmit_seq64_wqe xmit_sequence;
3983         struct gen_req64_wqe gen_req;
3984 };
3985
3986 #define LPFC_GROUP_OJECT_MAGIC_NUM              0xfeaa0001
3987 #define LPFC_FILE_TYPE_GROUP                    0xf7
3988 #define LPFC_FILE_ID_GROUP                      0xa2
3989 struct lpfc_grp_hdr {
3990         uint32_t size;
3991         uint32_t magic_number;
3992         uint32_t word2;
3993 #define lpfc_grp_hdr_file_type_SHIFT    24
3994 #define lpfc_grp_hdr_file_type_MASK     0x000000FF
3995 #define lpfc_grp_hdr_file_type_WORD     word2
3996 #define lpfc_grp_hdr_id_SHIFT           16
3997 #define lpfc_grp_hdr_id_MASK            0x000000FF
3998 #define lpfc_grp_hdr_id_WORD            word2
3999         uint8_t rev_name[128];
4000         uint8_t date[12];
4001         uint8_t revision[32];
4002 };
4003
4004 #define FCP_COMMAND 0x0
4005 #define FCP_COMMAND_DATA_OUT 0x1
4006 #define ELS_COMMAND_NON_FIP 0xC
4007 #define ELS_COMMAND_FIP 0xD
4008 #define OTHER_COMMAND 0x8
4009
4010 #define LPFC_FW_DUMP    1
4011 #define LPFC_FW_RESET   2
4012 #define LPFC_DV_RESET   3