1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define SCR_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
33 #define PT2PT_LocalID 1
34 #define PT2PT_RemoteID 2
36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
44 #define FCELSSIZE 1024 /* maximum ELS transfer size */
46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
78 /* Structure is in Big Endian format */
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET 0x1
97 #define FC4_FEATURE_INIT 0x2
98 #define FC4_FEATURE_NVME_DISC 0x4
100 struct lpfc_sli_ct_request {
101 /* Structure is in Big Endian format */
102 union CtRevisionId RevisionId;
107 union CtCommandResponse CommandResponse;
111 uint8_t VendorUnique;
112 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
117 uint8_t PortType; /* for GID_PT requests */
120 uint8_t Fc4Type; /* for GID_FT requests */
133 uint32_t PortId; /* For RFT_ID requests */
135 #ifdef __BIG_ENDIAN_BITFIELD
138 uint32_t fcpReg:1; /* Type 8 */
140 uint32_t ipReg:1; /* Type 5 */
142 #else /* __LITTLE_ENDIAN_BITFIELD */
144 uint32_t fcpReg:1; /* Type 8 */
147 uint32_t ipReg:1; /* Type 5 */
154 uint32_t PortId; /* For RNN_ID requests */
157 struct rsnn { /* For RSNN_ID requests */
160 uint8_t symbname[255];
162 struct da_id { /* For DA_ID requests */
165 struct rspn { /* For RSPN_ID requests */
168 uint8_t symbname[255];
180 uint32_t fc4_types[8];
182 #define FCP_TYPE_FEATURE_OFFSET 7
187 uint8_t type_code; /* type=8 for FCP */
192 #define LPFC_MAX_CT_SIZE (60 * 4096)
194 #define SLI_CT_REVISION 1
195 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
198 sizeof(struct gid_ff))
199 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
212 sizeof(struct da_id))
213 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
220 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
221 #define SLI_CT_TIME_SERVICE 0xFB
222 #define SLI_CT_DIRECTORY_SERVICE 0xFC
223 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
226 * Directory Service Subtypes
229 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
235 #define SLI_CT_RESPONSE_FS_RJT 0x8001
236 #define SLI_CT_RESPONSE_FS_ACC 0x8002
242 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
243 #define SLI_CT_INVALID_COMMAND 0x01
244 #define SLI_CT_INVALID_VERSION 0x02
245 #define SLI_CT_LOGICAL_ERROR 0x03
246 #define SLI_CT_INVALID_IU_SIZE 0x04
247 #define SLI_CT_LOGICAL_BUSY 0x05
248 #define SLI_CT_PROTOCOL_ERROR 0x07
249 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
250 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
251 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
252 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
253 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
254 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
255 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
256 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
257 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
258 #define SLI_CT_VENDOR_UNIQUE 0xff
261 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
264 #define SLI_CT_NO_PORT_ID 0x01
265 #define SLI_CT_NO_PORT_NAME 0x02
266 #define SLI_CT_NO_NODE_NAME 0x03
267 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
268 #define SLI_CT_NO_IP_ADDRESS 0x05
269 #define SLI_CT_NO_IPA 0x06
270 #define SLI_CT_NO_FC4_TYPES 0x07
271 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
272 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
273 #define SLI_CT_NO_PORT_TYPE 0x0A
274 #define SLI_CT_ACCESS_DENIED 0x10
275 #define SLI_CT_INVALID_PORT_ID 0x11
276 #define SLI_CT_DATABASE_EMPTY 0x12
279 * Name Server Command Codes
282 #define SLI_CTNS_GA_NXT 0x0100
283 #define SLI_CTNS_GPN_ID 0x0112
284 #define SLI_CTNS_GNN_ID 0x0113
285 #define SLI_CTNS_GCS_ID 0x0114
286 #define SLI_CTNS_GFT_ID 0x0117
287 #define SLI_CTNS_GSPN_ID 0x0118
288 #define SLI_CTNS_GPT_ID 0x011A
289 #define SLI_CTNS_GFF_ID 0x011F
290 #define SLI_CTNS_GID_PN 0x0121
291 #define SLI_CTNS_GID_NN 0x0131
292 #define SLI_CTNS_GIP_NN 0x0135
293 #define SLI_CTNS_GIPA_NN 0x0136
294 #define SLI_CTNS_GSNN_NN 0x0139
295 #define SLI_CTNS_GNN_IP 0x0153
296 #define SLI_CTNS_GIPA_IP 0x0156
297 #define SLI_CTNS_GID_FT 0x0171
298 #define SLI_CTNS_GID_FF 0x01F1
299 #define SLI_CTNS_GID_PT 0x01A1
300 #define SLI_CTNS_RPN_ID 0x0212
301 #define SLI_CTNS_RNN_ID 0x0213
302 #define SLI_CTNS_RCS_ID 0x0214
303 #define SLI_CTNS_RFT_ID 0x0217
304 #define SLI_CTNS_RSPN_ID 0x0218
305 #define SLI_CTNS_RPT_ID 0x021A
306 #define SLI_CTNS_RFF_ID 0x021F
307 #define SLI_CTNS_RIP_NN 0x0235
308 #define SLI_CTNS_RIPA_NN 0x0236
309 #define SLI_CTNS_RSNN_NN 0x0239
310 #define SLI_CTNS_DA_ID 0x0300
316 #define SLI_CTPT_N_PORT 0x01
317 #define SLI_CTPT_NL_PORT 0x02
318 #define SLI_CTPT_FNL_PORT 0x03
319 #define SLI_CTPT_IP 0x04
320 #define SLI_CTPT_FCP 0x08
321 #define SLI_CTPT_NVME 0x28
322 #define SLI_CTPT_NX_PORT 0x7F
323 #define SLI_CTPT_F_PORT 0x81
324 #define SLI_CTPT_FL_PORT 0x82
325 #define SLI_CTPT_E_PORT 0x84
327 #define SLI_CT_LAST_ENTRY 0x80000000
329 /* Fibre Channel Service Parameter definitions */
331 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
332 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
333 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
334 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
336 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
337 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
338 #define FC_PH3 0x20 /* FC-PH-3 version */
340 #define FF_FRAME_SIZE 2048
345 #ifdef __BIG_ENDIAN_BITFIELD
346 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
347 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
349 #else /* __LITTLE_ENDIAN_BITFIELD */
350 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
352 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
355 #define NAME_IEEE 0x1 /* IEEE name - nameType */
356 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
357 #define NAME_FC_TYPE 0x3 /* FC native name type */
358 #define NAME_IP_TYPE 0x4 /* IP address */
359 #define NAME_CCITT_TYPE 0xC
360 #define NAME_CCITT_GR_TYPE 0xE
361 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
363 uint8_t IEEE[6]; /* FC IEEE address */
371 uint8_t fcphHigh; /* FC Word 0, byte 0 */
374 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
377 * Word 1 Bit 31 in common service parameter is overloaded.
378 * Word 1 Bit 31 in FLOGI request is multiple NPort request
379 * Word 1 Bit 31 in FLOGI response is clean address bit
381 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
383 * Word 1 Bit 30 in common service parameter is overloaded.
384 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
385 * Word 1 Bit 30 in PLOGI request is random offset
387 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
389 * Word 1 Bit 29 in common service parameter is overloaded.
390 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
391 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
393 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
394 #ifdef __BIG_ENDIAN_BITFIELD
395 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
396 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
397 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
398 uint16_t fPort:1; /* FC Word 1, bit 28 */
399 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
400 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
401 uint16_t multicast:1; /* FC Word 1, bit 25 */
402 uint16_t broadcast:1; /* FC Word 1, bit 24 */
404 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
405 uint16_t simplex:1; /* FC Word 1, bit 22 */
406 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
407 uint16_t dhd:1; /* FC Word 1, bit 18 */
408 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
409 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
410 #else /* __LITTLE_ENDIAN_BITFIELD */
411 uint16_t broadcast:1; /* FC Word 1, bit 24 */
412 uint16_t multicast:1; /* FC Word 1, bit 25 */
413 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
414 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
415 uint16_t fPort:1; /* FC Word 1, bit 28 */
416 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
417 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
418 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
420 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
421 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
422 uint16_t dhd:1; /* FC Word 1, bit 18 */
423 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
424 uint16_t simplex:1; /* FC Word 1, bit 22 */
425 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
428 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
429 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
432 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
434 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
435 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
437 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
439 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
442 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
446 #ifdef __BIG_ENDIAN_BITFIELD
447 uint8_t classValid:1; /* FC Word 0, bit 31 */
448 uint8_t intermix:1; /* FC Word 0, bit 30 */
449 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
450 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
451 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
452 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
453 #else /* __LITTLE_ENDIAN_BITFIELD */
454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
455 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
456 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
457 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
458 uint8_t intermix:1; /* FC Word 0, bit 30 */
459 uint8_t classValid:1; /* FC Word 0, bit 31 */
463 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
465 #ifdef __BIG_ENDIAN_BITFIELD
466 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
467 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
468 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
469 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
470 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
471 #else /* __LITTLE_ENDIAN_BITFIELD */
472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
473 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
474 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
475 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
476 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
479 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
481 #ifdef __BIG_ENDIAN_BITFIELD
482 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
483 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
484 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
485 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
486 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
487 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
488 #else /* __LITTLE_ENDIAN_BITFIELD */
489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
490 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
491 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
492 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
493 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
494 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
497 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
498 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
499 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
501 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
502 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
503 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
504 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
506 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
507 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
508 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
509 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
512 #define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/
514 struct serv_parm { /* Structure is in Big Endian format */
516 struct lpfc_name portName;
517 struct lpfc_name nodeName;
518 struct class_parms cls1;
519 struct class_parms cls2;
520 struct class_parms cls3;
521 struct class_parms cls4;
523 uint8_t vendorVersion[16];
526 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
528 #define LPFC_VV_SUPPRESS_RSP 1
534 * Virtual Fabric Tagging Header
536 struct fc_vft_header {
538 #define fc_vft_hdr_r_ctl_SHIFT 24
539 #define fc_vft_hdr_r_ctl_MASK 0xFF
540 #define fc_vft_hdr_r_ctl_WORD word0
541 #define fc_vft_hdr_ver_SHIFT 22
542 #define fc_vft_hdr_ver_MASK 0x3
543 #define fc_vft_hdr_ver_WORD word0
544 #define fc_vft_hdr_type_SHIFT 18
545 #define fc_vft_hdr_type_MASK 0xF
546 #define fc_vft_hdr_type_WORD word0
547 #define fc_vft_hdr_e_SHIFT 16
548 #define fc_vft_hdr_e_MASK 0x1
549 #define fc_vft_hdr_e_WORD word0
550 #define fc_vft_hdr_priority_SHIFT 13
551 #define fc_vft_hdr_priority_MASK 0x7
552 #define fc_vft_hdr_priority_WORD word0
553 #define fc_vft_hdr_vf_id_SHIFT 1
554 #define fc_vft_hdr_vf_id_MASK 0xFFF
555 #define fc_vft_hdr_vf_id_WORD word0
557 #define fc_vft_hdr_hopct_SHIFT 24
558 #define fc_vft_hdr_hopct_MASK 0xFF
559 #define fc_vft_hdr_hopct_WORD word1
563 * Extended Link Service LS_COMMAND codes (Payload Word 0)
565 #ifdef __BIG_ENDIAN_BITFIELD
566 #define ELS_CMD_MASK 0xffff0000
567 #define ELS_RSP_MASK 0xff000000
568 #define ELS_CMD_LS_RJT 0x01000000
569 #define ELS_CMD_ACC 0x02000000
570 #define ELS_CMD_PLOGI 0x03000000
571 #define ELS_CMD_FLOGI 0x04000000
572 #define ELS_CMD_LOGO 0x05000000
573 #define ELS_CMD_ABTX 0x06000000
574 #define ELS_CMD_RCS 0x07000000
575 #define ELS_CMD_RES 0x08000000
576 #define ELS_CMD_RSS 0x09000000
577 #define ELS_CMD_RSI 0x0A000000
578 #define ELS_CMD_ESTS 0x0B000000
579 #define ELS_CMD_ESTC 0x0C000000
580 #define ELS_CMD_ADVC 0x0D000000
581 #define ELS_CMD_RTV 0x0E000000
582 #define ELS_CMD_RLS 0x0F000000
583 #define ELS_CMD_ECHO 0x10000000
584 #define ELS_CMD_TEST 0x11000000
585 #define ELS_CMD_RRQ 0x12000000
586 #define ELS_CMD_REC 0x13000000
587 #define ELS_CMD_RDP 0x18000000
588 #define ELS_CMD_PRLI 0x20100014
589 #define ELS_CMD_NVMEPRLI 0x20140018
590 #define ELS_CMD_PRLO 0x21100014
591 #define ELS_CMD_PRLO_ACC 0x02100014
592 #define ELS_CMD_PDISC 0x50000000
593 #define ELS_CMD_FDISC 0x51000000
594 #define ELS_CMD_ADISC 0x52000000
595 #define ELS_CMD_FARP 0x54000000
596 #define ELS_CMD_FARPR 0x55000000
597 #define ELS_CMD_RPS 0x56000000
598 #define ELS_CMD_RPL 0x57000000
599 #define ELS_CMD_FAN 0x60000000
600 #define ELS_CMD_RSCN 0x61040000
601 #define ELS_CMD_SCR 0x62000000
602 #define ELS_CMD_RNID 0x78000000
603 #define ELS_CMD_LIRR 0x7A000000
604 #define ELS_CMD_LCB 0x81000000
605 #else /* __LITTLE_ENDIAN_BITFIELD */
606 #define ELS_CMD_MASK 0xffff
607 #define ELS_RSP_MASK 0xff
608 #define ELS_CMD_LS_RJT 0x01
609 #define ELS_CMD_ACC 0x02
610 #define ELS_CMD_PLOGI 0x03
611 #define ELS_CMD_FLOGI 0x04
612 #define ELS_CMD_LOGO 0x05
613 #define ELS_CMD_ABTX 0x06
614 #define ELS_CMD_RCS 0x07
615 #define ELS_CMD_RES 0x08
616 #define ELS_CMD_RSS 0x09
617 #define ELS_CMD_RSI 0x0A
618 #define ELS_CMD_ESTS 0x0B
619 #define ELS_CMD_ESTC 0x0C
620 #define ELS_CMD_ADVC 0x0D
621 #define ELS_CMD_RTV 0x0E
622 #define ELS_CMD_RLS 0x0F
623 #define ELS_CMD_ECHO 0x10
624 #define ELS_CMD_TEST 0x11
625 #define ELS_CMD_RRQ 0x12
626 #define ELS_CMD_REC 0x13
627 #define ELS_CMD_RDP 0x18
628 #define ELS_CMD_PRLI 0x14001020
629 #define ELS_CMD_NVMEPRLI 0x18001420
630 #define ELS_CMD_PRLO 0x14001021
631 #define ELS_CMD_PRLO_ACC 0x14001002
632 #define ELS_CMD_PDISC 0x50
633 #define ELS_CMD_FDISC 0x51
634 #define ELS_CMD_ADISC 0x52
635 #define ELS_CMD_FARP 0x54
636 #define ELS_CMD_FARPR 0x55
637 #define ELS_CMD_RPS 0x56
638 #define ELS_CMD_RPL 0x57
639 #define ELS_CMD_FAN 0x60
640 #define ELS_CMD_RSCN 0x0461
641 #define ELS_CMD_SCR 0x62
642 #define ELS_CMD_RNID 0x78
643 #define ELS_CMD_LIRR 0x7A
644 #define ELS_CMD_LCB 0x81
648 * LS_RJT Payload Definition
651 struct ls_rjt { /* Structure is in Big Endian format */
655 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
657 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
658 /* LS_RJT reason codes */
659 #define LSRJT_INVALID_CMD 0x01
660 #define LSRJT_LOGICAL_ERR 0x03
661 #define LSRJT_LOGICAL_BSY 0x05
662 #define LSRJT_PROTOCOL_ERR 0x07
663 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
664 #define LSRJT_CMD_UNSUPPORTED 0x0B
665 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
667 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
668 /* LS_RJT reason explanation */
669 #define LSEXP_NOTHING_MORE 0x00
670 #define LSEXP_SPARM_OPTIONS 0x01
671 #define LSEXP_SPARM_ICTL 0x03
672 #define LSEXP_SPARM_RCTL 0x05
673 #define LSEXP_SPARM_RCV_SIZE 0x07
674 #define LSEXP_SPARM_CONCUR_SEQ 0x09
675 #define LSEXP_SPARM_CREDIT 0x0B
676 #define LSEXP_INVALID_PNAME 0x0D
677 #define LSEXP_INVALID_NNAME 0x0E
678 #define LSEXP_INVALID_CSP 0x0F
679 #define LSEXP_INVALID_ASSOC_HDR 0x11
680 #define LSEXP_ASSOC_HDR_REQ 0x13
681 #define LSEXP_INVALID_O_SID 0x15
682 #define LSEXP_INVALID_OX_RX 0x17
683 #define LSEXP_CMD_IN_PROGRESS 0x19
684 #define LSEXP_PORT_LOGIN_REQ 0x1E
685 #define LSEXP_INVALID_NPORT_ID 0x1F
686 #define LSEXP_INVALID_SEQ_ID 0x21
687 #define LSEXP_INVALID_XCHG 0x23
688 #define LSEXP_INACTIVE_XCHG 0x25
689 #define LSEXP_RQ_REQUIRED 0x27
690 #define LSEXP_OUT_OF_RESOURCE 0x29
691 #define LSEXP_CANT_GIVE_DATA 0x2A
692 #define LSEXP_REQ_UNSUPPORTED 0x2C
693 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
699 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
702 typedef struct _LOGO { /* Structure is in Big Endian format */
704 uint32_t nPortId32; /* Access nPortId as a word */
706 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
707 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
708 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
709 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
712 struct lpfc_name portName; /* N_port name field */
716 * FCP Login (PRLI Request / ACC) Payload Definition
719 #define PRLX_PAGE_LEN 0x10
720 #define TPRLO_PAGE_LEN 0x14
722 typedef struct _PRLI { /* Structure is in Big Endian format */
723 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
725 #define PRLI_FCP_TYPE 0x08
726 #define PRLI_NVME_TYPE 0x28
727 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
729 #ifdef __BIG_ENDIAN_BITFIELD
730 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
731 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
732 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
734 /* ACC = imagePairEstablished */
735 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
736 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
737 #else /* __LITTLE_ENDIAN_BITFIELD */
738 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
739 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
740 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
741 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
742 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
743 /* ACC = imagePairEstablished */
746 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
747 #define PRLI_NO_RESOURCES 0x2
748 #define PRLI_INIT_INCOMPLETE 0x3
749 #define PRLI_NO_SUCH_PA 0x4
750 #define PRLI_PREDEF_CONFIG 0x5
751 #define PRLI_PARTIAL_SUCCESS 0x6
752 #define PRLI_INVALID_PAGE_CNT 0x7
753 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
755 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
757 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
759 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
760 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
762 #ifdef __BIG_ENDIAN_BITFIELD
763 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
764 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
765 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
766 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
767 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
768 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
769 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
770 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
771 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
772 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
773 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
774 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
775 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
776 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
777 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
778 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
779 #else /* __LITTLE_ENDIAN_BITFIELD */
780 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
781 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
782 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
783 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
784 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
785 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
786 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
787 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
788 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
789 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
790 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
791 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
792 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
793 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
794 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
795 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
800 * FCP Logout (PRLO Request / ACC) Payload Definition
803 typedef struct _PRLO { /* Structure is in Big Endian format */
804 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
806 #define PRLO_FCP_TYPE 0x08
807 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
809 #ifdef __BIG_ENDIAN_BITFIELD
810 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
811 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
812 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
813 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
814 #else /* __LITTLE_ENDIAN_BITFIELD */
815 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
816 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
817 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
818 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
821 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
822 #define PRLO_NO_SUCH_IMAGE 0x4
823 #define PRLO_INVALID_PAGE_CNT 0x7
825 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
827 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
829 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
831 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
834 typedef struct _ADISC { /* Structure is in Big Endian format */
836 struct lpfc_name portName;
837 struct lpfc_name nodeName;
841 typedef struct _FARP { /* Structure is in Big Endian format */
844 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
846 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
847 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
848 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
849 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
851 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
855 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
856 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
857 struct lpfc_name OportName;
858 struct lpfc_name OnodeName;
859 struct lpfc_name RportName;
860 struct lpfc_name RnodeName;
865 typedef struct _FAN { /* Structure is in Big Endian format */
867 struct lpfc_name FportName;
868 struct lpfc_name FnodeName;
871 typedef struct _SCR { /* Structure is in Big Endian format */
876 #define SCR_FUNC_FABRIC 0x01
877 #define SCR_FUNC_NPORT 0x02
878 #define SCR_FUNC_FULL 0x03
879 #define SCR_CLEAR 0xff
882 typedef struct _RNID_TOP_DISC {
883 struct lpfc_name portName;
887 #define RNID_HOST 0xa
888 #define RNID_DRIVER 0xd
890 uint32_t attachedNodes;
892 #define RNID_IPV4 0x1
893 #define RNID_IPV6 0x2
898 #define RNID_TD_SUPPORT 0x1
899 #define RNID_LP_VALID 0x2
902 typedef struct _RNID { /* Structure is in Big Endian format */
904 #define RNID_TOPOLOGY_DISC 0xdf
908 struct lpfc_name portName;
909 struct lpfc_name nodeName;
911 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
915 typedef struct _RPS { /* Structure is in Big Endian format */
918 struct lpfc_name portName;
922 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
925 uint32_t linkFailureCnt;
926 uint32_t lossSyncCnt;
927 uint32_t lossSignalCnt;
928 uint32_t primSeqErrCnt;
929 uint32_t invalidXmitWord;
933 struct RLS { /* Structure is in Big Endian format */
935 #define rls_rsvd_SHIFT 24
936 #define rls_rsvd_MASK 0x000000ff
937 #define rls_rsvd_WORD rls
938 #define rls_did_SHIFT 0
939 #define rls_did_MASK 0x00ffffff
940 #define rls_did_WORD rls
943 struct RLS_RSP { /* Structure is in Big Endian format */
944 uint32_t linkFailureCnt;
945 uint32_t lossSyncCnt;
946 uint32_t lossSignalCnt;
947 uint32_t primSeqErrCnt;
948 uint32_t invalidXmitWord;
952 struct RRQ { /* Structure is in Big Endian format */
954 #define rrq_rsvd_SHIFT 24
955 #define rrq_rsvd_MASK 0x000000ff
956 #define rrq_rsvd_WORD rrq
957 #define rrq_did_SHIFT 0
958 #define rrq_did_MASK 0x00ffffff
959 #define rrq_did_WORD rrq
961 #define rrq_oxid_SHIFT 16
962 #define rrq_oxid_MASK 0xffff
963 #define rrq_oxid_WORD rrq_exchg
964 #define rrq_rxid_SHIFT 0
965 #define rrq_rxid_MASK 0xffff
966 #define rrq_rxid_WORD rrq_exchg
969 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
970 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
972 struct RTV_RSP { /* Structure is in Big Endian format */
976 #define qtov_rsvd0_SHIFT 28
977 #define qtov_rsvd0_MASK 0x0000000f
978 #define qtov_rsvd0_WORD qtov /* reserved */
979 #define qtov_edtovres_SHIFT 27
980 #define qtov_edtovres_MASK 0x00000001
981 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
982 #define qtov__rsvd1_SHIFT 19
983 #define qtov_rsvd1_MASK 0x0000003f
984 #define qtov_rsvd1_WORD qtov /* reserved */
985 #define qtov_rttov_SHIFT 18
986 #define qtov_rttov_MASK 0x00000001
987 #define qtov_rttov_WORD qtov /* R_T_TOV value */
988 #define qtov_rsvd2_SHIFT 0
989 #define qtov_rsvd2_MASK 0x0003ffff
990 #define qtov_rsvd2_WORD qtov /* reserved */
994 typedef struct _RPL { /* Structure is in Big Endian format */
999 typedef struct _PORT_NUM_BLK {
1002 struct lpfc_name portName;
1005 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
1008 PORT_NUM_BLK port_num_blk;
1011 /* This is used for RSCN command */
1012 typedef struct _D_ID { /* Structure is in Big Endian format */
1016 #ifdef __BIG_ENDIAN_BITFIELD
1021 #else /* __LITTLE_ENDIAN_BITFIELD */
1031 #define RSCN_ADDRESS_FORMAT_PORT 0x0
1032 #define RSCN_ADDRESS_FORMAT_AREA 0x1
1033 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1034 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1035 #define RSCN_ADDRESS_FORMAT_MASK 0x3
1038 * Structure to define all ELS Payload types
1041 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1042 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1047 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1048 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1049 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1050 PRLI prli; /* Payload for PRLI/ACC */
1051 PRLO prlo; /* Payload for PRLO/ACC */
1052 ADISC adisc; /* Payload for ADISC/ACC */
1053 FARP farp; /* Payload for FARP/ACC */
1054 FAN fan; /* Payload for FAN */
1055 SCR scr; /* Payload for SCR/ACC */
1056 RNID rnid; /* Payload for RNID */
1057 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1062 * Link Cable Beacon (LCB) ELS Frame
1065 struct fc_lcb_request_frame {
1066 uint32_t lcb_command; /* ELS command opcode (0x81) */
1067 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1068 #define LPFC_LCB_ON 0x1
1069 #define LPFC_LCB_OFF 0x2
1070 uint8_t reserved[3];
1072 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1073 #define LPFC_LCB_GREEN 0x1
1074 #define LPFC_LCB_AMBER 0x2
1075 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1076 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1080 * Link Cable Beacon (LCB) ELS Response Frame
1082 struct fc_lcb_res_frame {
1083 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1084 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1085 uint8_t reserved[3];
1086 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1087 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1088 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1092 * Read Diagnostic Parameters (RDP) ELS frame.
1094 #define SFF_PG0_IDENT_SFP 0x3
1096 #define SFP_FLAG_PT_OPTICAL 0x0
1097 #define SFP_FLAG_PT_SWLASER 0x01
1098 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1099 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1100 #define SFP_FLAG_PT_MASK 0x0F
1101 #define SFP_FLAG_PT_SHIFT 0
1103 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1104 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1105 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1107 #define SFP_FLAG_IS_DESC_VALID 0x01
1108 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1109 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1111 #define SFP_FLAG_CT_UNKNOWN 0x0
1112 #define SFP_FLAG_CT_SFP_PLUS 0x01
1113 #define SFP_FLAG_CT_MASK 0x3C
1114 #define SFP_FLAG_CT_SHIFT 6
1116 struct fc_rdp_port_name_info {
1123 * Link Error Status Block Structure (FC-FS-3) for RDP
1124 * This similar to RPS ELS
1126 struct fc_link_status {
1127 uint32_t link_failure_cnt;
1128 uint32_t loss_of_synch_cnt;
1129 uint32_t loss_of_signal_cnt;
1130 uint32_t primitive_seq_proto_err;
1131 uint32_t invalid_trans_word;
1132 uint32_t invalid_crc_cnt;
1136 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1137 struct fc_rdp_port_name_desc {
1138 uint32_t tag; /* 0001 0003h */
1139 uint32_t length; /* set to size of payload struct */
1140 struct fc_rdp_port_name_info port_names;
1144 struct fc_rdp_fec_info {
1145 uint32_t CorrectedBlocks;
1146 uint32_t UncorrectableBlocks;
1149 #define RDP_FEC_DESC_TAG 0x00010005
1150 struct fc_fec_rdp_desc {
1153 struct fc_rdp_fec_info info;
1156 struct fc_rdp_link_error_status_payload_info {
1157 struct fc_link_status link_status; /* 24 bytes */
1158 uint32_t port_type; /* bits 31-30 only */
1161 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1162 struct fc_rdp_link_error_status_desc {
1163 uint32_t tag; /* 0001 0002h */
1164 uint32_t length; /* set to size of payload struct */
1165 struct fc_rdp_link_error_status_payload_info info;
1168 #define VN_PT_PHY_UNKNOWN 0x00
1169 #define VN_PT_PHY_PF_PORT 0x01
1170 #define VN_PT_PHY_ETH_MAC 0x10
1171 #define VN_PT_PHY_SHIFT 30
1173 #define RDP_PS_1GB 0x8000
1174 #define RDP_PS_2GB 0x4000
1175 #define RDP_PS_4GB 0x2000
1176 #define RDP_PS_10GB 0x1000
1177 #define RDP_PS_8GB 0x0800
1178 #define RDP_PS_16GB 0x0400
1179 #define RDP_PS_32GB 0x0200
1181 #define RDP_CAP_USER_CONFIGURED 0x0002
1182 #define RDP_CAP_UNKNOWN 0x0001
1183 #define RDP_PS_UNKNOWN 0x0002
1184 #define RDP_PS_NOT_ESTABLISHED 0x0001
1186 struct fc_rdp_port_speed {
1187 uint16_t capabilities;
1191 struct fc_rdp_port_speed_info {
1192 struct fc_rdp_port_speed port_speed;
1195 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1196 struct fc_rdp_port_speed_desc {
1197 uint32_t tag; /* 00010001h */
1198 uint32_t length; /* set to size of payload struct */
1199 struct fc_rdp_port_speed_info info;
1202 #define RDP_NPORT_ID_SIZE 4
1203 #define RDP_N_PORT_DESC_TAG 0x00000003
1204 struct fc_rdp_nport_desc {
1205 uint32_t tag; /* 0000 0003h, big endian */
1206 uint32_t length; /* size of RDP_N_PORT_ID struct */
1207 uint32_t nport_id : 12;
1208 uint32_t reserved : 8;
1212 struct fc_rdp_link_service_info {
1213 uint32_t els_req; /* Request payload word 0 value.*/
1216 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1217 struct fc_rdp_link_service_desc {
1218 uint32_t tag; /* Descriptor tag 1 */
1219 uint32_t length; /* set to size of payload struct. */
1220 struct fc_rdp_link_service_info payload;
1221 /* must be ELS req Word 0(0x18) */
1224 struct fc_rdp_sfp_info {
1225 uint16_t temperature;
1233 #define RDP_SFP_DESC_TAG 0x00010000
1234 struct fc_rdp_sfp_desc {
1236 uint32_t length; /* set to size of sfp_info struct */
1237 struct fc_rdp_sfp_info sfp_info;
1240 /* Buffer Credit Descriptor */
1241 struct fc_rdp_bbc_info {
1242 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1243 uint32_t attached_port_bbc;
1244 uint32_t rtt; /* Round trip time */
1246 #define RDP_BBC_DESC_TAG 0x00010006
1247 struct fc_rdp_bbc_desc {
1250 struct fc_rdp_bbc_info bbc_info;
1253 /* Optical Element Type Transgression Flags */
1254 #define RDP_OET_LOW_WARNING 0x1
1255 #define RDP_OET_HIGH_WARNING 0x2
1256 #define RDP_OET_LOW_ALARM 0x4
1257 #define RDP_OET_HIGH_ALARM 0x8
1259 #define RDP_OED_TEMPERATURE 0x1
1260 #define RDP_OED_VOLTAGE 0x2
1261 #define RDP_OED_TXBIAS 0x3
1262 #define RDP_OED_TXPOWER 0x4
1263 #define RDP_OED_RXPOWER 0x5
1265 #define RDP_OED_TYPE_SHIFT 28
1266 /* Optical Element Data descriptor */
1267 struct fc_rdp_oed_info {
1270 uint16_t hi_warning;
1271 uint16_t lo_warning;
1272 uint32_t function_flags;
1274 #define RDP_OED_DESC_TAG 0x00010007
1275 struct fc_rdp_oed_sfp_desc {
1278 struct fc_rdp_oed_info oed_info;
1281 /* Optical Product Data descriptor */
1282 struct fc_rdp_opd_sfp_info {
1283 uint8_t vendor_name[16];
1284 uint8_t model_number[16];
1285 uint8_t serial_number[16];
1286 uint8_t revision[4];
1290 #define RDP_OPD_DESC_TAG 0x00010008
1291 struct fc_rdp_opd_sfp_desc {
1294 struct fc_rdp_opd_sfp_info opd_info;
1297 struct fc_rdp_req_frame {
1298 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1299 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1300 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1304 struct fc_rdp_res_frame {
1305 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1306 uint32_t length; /* FC Word 1 */
1307 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1308 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1309 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1310 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1311 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1312 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1313 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1314 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1315 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1316 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1317 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1318 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1319 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1320 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1324 /******** FDMI ********/
1326 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1327 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1329 /* Definitions for HBA / Port attribute entries */
1331 /* Attribute Entry */
1332 struct lpfc_fdmi_attr_entry {
1335 uint8_t AttrTypes[32];
1336 uint8_t AttrString[256];
1337 struct lpfc_name AttrWWN;
1341 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1342 /* Structure is in Big Endian format */
1343 uint32_t AttrType:16;
1344 uint32_t AttrLen:16;
1345 /* Marks start of Value (ATTRIBUTE_ENTRY) */
1346 struct lpfc_fdmi_attr_entry AttrValue;
1350 * HBA Attribute Block
1352 struct lpfc_fdmi_attr_block {
1353 uint32_t EntryCnt; /* Number of HBA attribute entries */
1354 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1360 struct lpfc_fdmi_port_entry {
1361 struct lpfc_name PortName;
1367 struct lpfc_fdmi_hba_ident {
1368 struct lpfc_name PortName;
1372 * Registered Port List Format
1374 struct lpfc_fdmi_reg_port_list {
1376 struct lpfc_fdmi_port_entry pe;
1380 * Register HBA(RHBA)
1382 struct lpfc_fdmi_reg_hba {
1383 struct lpfc_fdmi_hba_ident hi;
1384 struct lpfc_fdmi_reg_port_list rpl;
1388 * Register HBA Attributes (RHAT)
1390 struct lpfc_fdmi_reg_hbaattr {
1391 struct lpfc_name HBA_PortName;
1392 struct lpfc_fdmi_attr_block ab;
1396 * Register Port Attributes (RPA)
1398 struct lpfc_fdmi_reg_portattr {
1399 struct lpfc_name PortName;
1400 struct lpfc_fdmi_attr_block ab;
1404 * HBA MAnagement Operations Command Codes
1406 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1407 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1408 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1409 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1410 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1411 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1412 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1413 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1414 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1415 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1416 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1417 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1418 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1420 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1423 * HBA Attribute Types
1425 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1426 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1427 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1428 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1429 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1430 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1431 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1432 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1433 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1434 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1435 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1436 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1437 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1438 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1439 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1440 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1441 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1442 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1444 /* Bit mask for all individual HBA attributes */
1445 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1446 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1447 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1448 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1449 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1450 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1451 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1452 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1453 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1454 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1455 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1456 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1457 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1458 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1459 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1460 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1461 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1462 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1464 /* Bit mask for FDMI-1 defined HBA attributes */
1465 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1467 /* Bit mask for FDMI-2 defined HBA attributes */
1468 /* Skip vendor_info and bios_state */
1469 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1472 * Port Attrubute Types
1474 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1475 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1476 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1477 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1478 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1479 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1480 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1481 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1482 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1483 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1484 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1485 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1486 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1487 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1488 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1489 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1490 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1491 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1492 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1493 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1494 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1495 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1496 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1498 /* Bit mask for all individual PORT attributes */
1499 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1500 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1501 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1502 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1503 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1504 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1505 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1506 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1507 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1508 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1509 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1510 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1511 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1512 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1513 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1514 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1515 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1516 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1517 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1518 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1519 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1520 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1521 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1523 /* Bit mask for FDMI-1 defined PORT attributes */
1524 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1526 /* Bit mask for FDMI-2 defined PORT attributes */
1527 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1529 /* Bit mask for Smart SAN defined PORT attributes */
1530 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1532 /* Defines for PORT port state attribute */
1533 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1534 #define LPFC_FDMI_PORTSTATE_ONLINE 2
1536 /* Defines for PORT port type attribute */
1537 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1538 #define LPFC_FDMI_PORTTYPE_NPORT 1
1539 #define LPFC_FDMI_PORTTYPE_NLPORT 2
1542 * Begin HBA configuration parameters.
1543 * The PCI configuration register BAR assignments are:
1544 * BAR0, offset 0x10 - SLIM base memory address
1545 * BAR1, offset 0x14 - SLIM base memory high address
1546 * BAR2, offset 0x18 - REGISTER base memory address
1547 * BAR3, offset 0x1c - REGISTER base memory high address
1548 * BAR4, offset 0x20 - BIU I/O registers
1549 * BAR5, offset 0x24 - REGISTER base io high address
1552 /* Number of rings currently used and available. */
1553 #define MAX_SLI3_CONFIGURED_RINGS 3
1554 #define MAX_SLI3_RINGS 4
1556 /* IOCB / Mailbox is owned by FireFly */
1559 /* IOCB / Mailbox is owned by Host */
1562 /* Number of 4-byte words in an IOCB. */
1563 #define IOCB_WORD_SZ 8
1565 /* network headers for Dfctl field */
1566 #define FC_NET_HDR 0x20
1568 /* Start FireFly Register definitions */
1569 #define PCI_VENDOR_ID_EMULEX 0x10df
1570 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1571 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1572 #define PCI_DEVICE_ID_BALIUS 0xe131
1573 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1574 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1575 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1576 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1577 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1578 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1579 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1580 #define PCI_DEVICE_ID_SAT_MID 0xf015
1581 #define PCI_DEVICE_ID_RFLY 0xf095
1582 #define PCI_DEVICE_ID_PFLY 0xf098
1583 #define PCI_DEVICE_ID_LP101 0xf0a1
1584 #define PCI_DEVICE_ID_TFLY 0xf0a5
1585 #define PCI_DEVICE_ID_BSMB 0xf0d1
1586 #define PCI_DEVICE_ID_BMID 0xf0d5
1587 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1588 #define PCI_DEVICE_ID_ZMID 0xf0e5
1589 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1590 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1591 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1592 #define PCI_DEVICE_ID_SAT 0xf100
1593 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1594 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1595 #define PCI_DEVICE_ID_FALCON 0xf180
1596 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1597 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1598 #define PCI_DEVICE_ID_CENTAUR 0xf900
1599 #define PCI_DEVICE_ID_PEGASUS 0xf980
1600 #define PCI_DEVICE_ID_THOR 0xfa00
1601 #define PCI_DEVICE_ID_VIPER 0xfb00
1602 #define PCI_DEVICE_ID_LP10000S 0xfc00
1603 #define PCI_DEVICE_ID_LP11000S 0xfc10
1604 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1605 #define PCI_DEVICE_ID_SAT_S 0xfc40
1606 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1607 #define PCI_DEVICE_ID_HELIOS 0xfd00
1608 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1609 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1610 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1611 #define PCI_DEVICE_ID_HORNET 0xfe05
1612 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1613 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1614 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1615 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1616 #define PCI_DEVICE_ID_TOMCAT 0x0714
1617 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1618 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1620 #define JEDEC_ID_ADDRESS 0x0080001c
1621 #define FIREFLY_JEDEC_ID 0x1ACC
1622 #define SUPERFLY_JEDEC_ID 0x0020
1623 #define DRAGONFLY_JEDEC_ID 0x0021
1624 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1625 #define CENTAUR_2G_JEDEC_ID 0x0026
1626 #define CENTAUR_1G_JEDEC_ID 0x0028
1627 #define PEGASUS_ORION_JEDEC_ID 0x0036
1628 #define PEGASUS_JEDEC_ID 0x0038
1629 #define THOR_JEDEC_ID 0x0012
1630 #define HELIOS_JEDEC_ID 0x0364
1631 #define ZEPHYR_JEDEC_ID 0x0577
1632 #define VIPER_JEDEC_ID 0x4838
1633 #define SATURN_JEDEC_ID 0x1004
1634 #define HORNET_JDEC_ID 0x2057706D
1636 #define JEDEC_ID_MASK 0x0FFFF000
1637 #define JEDEC_ID_SHIFT 12
1638 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1640 typedef struct { /* FireFly BIU registers */
1641 uint32_t hostAtt; /* See definitions for Host Attention
1643 uint32_t chipAtt; /* See definitions for Chip Attention
1645 uint32_t hostStatus; /* See definitions for Host Status register */
1646 uint32_t hostControl; /* See definitions for Host Control register */
1647 uint32_t buiConfig; /* See definitions for BIU configuration
1651 /* IO Register size in bytes */
1652 #define FF_REG_AREA_SIZE 256
1654 /* Host Attention Register */
1656 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1658 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1659 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1660 #define HA_R0ATT 0x00000008 /* Bit 3 */
1661 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1662 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1663 #define HA_R1ATT 0x00000080 /* Bit 7 */
1664 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1665 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1666 #define HA_R2ATT 0x00000800 /* Bit 11 */
1667 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1668 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1669 #define HA_R3ATT 0x00008000 /* Bit 15 */
1670 #define HA_LATT 0x20000000 /* Bit 29 */
1671 #define HA_MBATT 0x40000000 /* Bit 30 */
1672 #define HA_ERATT 0x80000000 /* Bit 31 */
1674 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1675 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1676 #define HA_RXATT 0x00000008 /* Bit 3 */
1677 #define HA_RXMASK 0x0000000f
1679 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1680 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1681 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1682 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1686 #define HA_R2_POS 11
1687 #define HA_R3_POS 15
1688 #define HA_LE_POS 29
1689 #define HA_MB_POS 30
1690 #define HA_ER_POS 31
1691 /* Chip Attention Register */
1693 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1695 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1696 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1697 #define CA_R0ATT 0x00000008 /* Bit 3 */
1698 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1699 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1700 #define CA_R1ATT 0x00000080 /* Bit 7 */
1701 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1702 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1703 #define CA_R2ATT 0x00000800 /* Bit 11 */
1704 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1705 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1706 #define CA_R3ATT 0x00008000 /* Bit 15 */
1707 #define CA_MBATT 0x40000000 /* Bit 30 */
1709 /* Host Status Register */
1711 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1713 #define HS_MBRDY 0x00400000 /* Bit 22 */
1714 #define HS_FFRDY 0x00800000 /* Bit 23 */
1715 #define HS_FFER8 0x01000000 /* Bit 24 */
1716 #define HS_FFER7 0x02000000 /* Bit 25 */
1717 #define HS_FFER6 0x04000000 /* Bit 26 */
1718 #define HS_FFER5 0x08000000 /* Bit 27 */
1719 #define HS_FFER4 0x10000000 /* Bit 28 */
1720 #define HS_FFER3 0x20000000 /* Bit 29 */
1721 #define HS_FFER2 0x40000000 /* Bit 30 */
1722 #define HS_FFER1 0x80000000 /* Bit 31 */
1723 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1724 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1725 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1726 /* Host Control Register */
1728 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1730 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1731 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1732 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1733 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1734 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1735 #define HC_INITHBI 0x02000000 /* Bit 25 */
1736 #define HC_INITMB 0x04000000 /* Bit 26 */
1737 #define HC_INITFF 0x08000000 /* Bit 27 */
1738 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1739 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1741 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1742 #define MSIX_DFLT_ID 0
1743 #define MSIX_RNG0_ID 0
1744 #define MSIX_RNG1_ID 1
1745 #define MSIX_RNG2_ID 2
1746 #define MSIX_RNG3_ID 3
1748 #define MSIX_LINK_ID 4
1749 #define MSIX_MBOX_ID 5
1751 #define MSIX_SPARE0_ID 6
1752 #define MSIX_SPARE1_ID 7
1754 /* Mailbox Commands */
1755 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1756 #define MBX_LOAD_SM 0x01
1757 #define MBX_READ_NV 0x02
1758 #define MBX_WRITE_NV 0x03
1759 #define MBX_RUN_BIU_DIAG 0x04
1760 #define MBX_INIT_LINK 0x05
1761 #define MBX_DOWN_LINK 0x06
1762 #define MBX_CONFIG_LINK 0x07
1763 #define MBX_CONFIG_RING 0x09
1764 #define MBX_RESET_RING 0x0A
1765 #define MBX_READ_CONFIG 0x0B
1766 #define MBX_READ_RCONFIG 0x0C
1767 #define MBX_READ_SPARM 0x0D
1768 #define MBX_READ_STATUS 0x0E
1769 #define MBX_READ_RPI 0x0F
1770 #define MBX_READ_XRI 0x10
1771 #define MBX_READ_REV 0x11
1772 #define MBX_READ_LNK_STAT 0x12
1773 #define MBX_REG_LOGIN 0x13
1774 #define MBX_UNREG_LOGIN 0x14
1775 #define MBX_CLEAR_LA 0x16
1776 #define MBX_DUMP_MEMORY 0x17
1777 #define MBX_DUMP_CONTEXT 0x18
1778 #define MBX_RUN_DIAGS 0x19
1779 #define MBX_RESTART 0x1A
1780 #define MBX_UPDATE_CFG 0x1B
1781 #define MBX_DOWN_LOAD 0x1C
1782 #define MBX_DEL_LD_ENTRY 0x1D
1783 #define MBX_RUN_PROGRAM 0x1E
1784 #define MBX_SET_MASK 0x20
1785 #define MBX_SET_VARIABLE 0x21
1786 #define MBX_UNREG_D_ID 0x23
1787 #define MBX_KILL_BOARD 0x24
1788 #define MBX_CONFIG_FARP 0x25
1789 #define MBX_BEACON 0x2A
1790 #define MBX_CONFIG_MSI 0x30
1791 #define MBX_HEARTBEAT 0x31
1792 #define MBX_WRITE_VPARMS 0x32
1793 #define MBX_ASYNCEVT_ENABLE 0x33
1794 #define MBX_READ_EVENT_LOG_STATUS 0x37
1795 #define MBX_READ_EVENT_LOG 0x38
1796 #define MBX_WRITE_EVENT_LOG 0x39
1798 #define MBX_PORT_CAPABILITIES 0x3B
1799 #define MBX_PORT_IOV_CONTROL 0x3C
1801 #define MBX_CONFIG_HBQ 0x7C
1802 #define MBX_LOAD_AREA 0x81
1803 #define MBX_RUN_BIU_DIAG64 0x84
1804 #define MBX_CONFIG_PORT 0x88
1805 #define MBX_READ_SPARM64 0x8D
1806 #define MBX_READ_RPI64 0x8F
1807 #define MBX_REG_LOGIN64 0x93
1808 #define MBX_READ_TOPOLOGY 0x95
1809 #define MBX_REG_VPI 0x96
1810 #define MBX_UNREG_VPI 0x97
1812 #define MBX_WRITE_WWN 0x98
1813 #define MBX_SET_DEBUG 0x99
1814 #define MBX_LOAD_EXP_ROM 0x9C
1815 #define MBX_SLI4_CONFIG 0x9B
1816 #define MBX_SLI4_REQ_FTRS 0x9D
1817 #define MBX_MAX_CMDS 0x9E
1818 #define MBX_RESUME_RPI 0x9E
1819 #define MBX_SLI2_CMD_MASK 0x80
1820 #define MBX_REG_VFI 0x9F
1821 #define MBX_REG_FCFI 0xA0
1822 #define MBX_UNREG_VFI 0xA1
1823 #define MBX_UNREG_FCFI 0xA2
1824 #define MBX_INIT_VFI 0xA3
1825 #define MBX_INIT_VPI 0xA4
1826 #define MBX_ACCESS_VDATA 0xA5
1827 #define MBX_REG_FCFI_MRQ 0xAF
1829 #define MBX_AUTH_PORT 0xF8
1830 #define MBX_SECURITY_MGMT 0xF9
1834 #define CMD_RCV_SEQUENCE_CX 0x01
1835 #define CMD_XMIT_SEQUENCE_CR 0x02
1836 #define CMD_XMIT_SEQUENCE_CX 0x03
1837 #define CMD_XMIT_BCAST_CN 0x04
1838 #define CMD_XMIT_BCAST_CX 0x05
1839 #define CMD_QUE_RING_BUF_CN 0x06
1840 #define CMD_QUE_XRI_BUF_CX 0x07
1841 #define CMD_IOCB_CONTINUE_CN 0x08
1842 #define CMD_RET_XRI_BUF_CX 0x09
1843 #define CMD_ELS_REQUEST_CR 0x0A
1844 #define CMD_ELS_REQUEST_CX 0x0B
1845 #define CMD_RCV_ELS_REQ_CX 0x0D
1846 #define CMD_ABORT_XRI_CN 0x0E
1847 #define CMD_ABORT_XRI_CX 0x0F
1848 #define CMD_CLOSE_XRI_CN 0x10
1849 #define CMD_CLOSE_XRI_CX 0x11
1850 #define CMD_CREATE_XRI_CR 0x12
1851 #define CMD_CREATE_XRI_CX 0x13
1852 #define CMD_GET_RPI_CN 0x14
1853 #define CMD_XMIT_ELS_RSP_CX 0x15
1854 #define CMD_GET_RPI_CR 0x16
1855 #define CMD_XRI_ABORTED_CX 0x17
1856 #define CMD_FCP_IWRITE_CR 0x18
1857 #define CMD_FCP_IWRITE_CX 0x19
1858 #define CMD_FCP_IREAD_CR 0x1A
1859 #define CMD_FCP_IREAD_CX 0x1B
1860 #define CMD_FCP_ICMND_CR 0x1C
1861 #define CMD_FCP_ICMND_CX 0x1D
1862 #define CMD_FCP_TSEND_CX 0x1F
1863 #define CMD_FCP_TRECEIVE_CX 0x21
1864 #define CMD_FCP_TRSP_CX 0x23
1865 #define CMD_FCP_AUTO_TRSP_CX 0x29
1867 #define CMD_ADAPTER_MSG 0x20
1868 #define CMD_ADAPTER_DUMP 0x22
1870 /* SLI_2 IOCB Command Set */
1872 #define CMD_ASYNC_STATUS 0x7C
1873 #define CMD_RCV_SEQUENCE64_CX 0x81
1874 #define CMD_XMIT_SEQUENCE64_CR 0x82
1875 #define CMD_XMIT_SEQUENCE64_CX 0x83
1876 #define CMD_XMIT_BCAST64_CN 0x84
1877 #define CMD_XMIT_BCAST64_CX 0x85
1878 #define CMD_QUE_RING_BUF64_CN 0x86
1879 #define CMD_QUE_XRI_BUF64_CX 0x87
1880 #define CMD_IOCB_CONTINUE64_CN 0x88
1881 #define CMD_RET_XRI_BUF64_CX 0x89
1882 #define CMD_ELS_REQUEST64_CR 0x8A
1883 #define CMD_ELS_REQUEST64_CX 0x8B
1884 #define CMD_ABORT_MXRI64_CN 0x8C
1885 #define CMD_RCV_ELS_REQ64_CX 0x8D
1886 #define CMD_XMIT_ELS_RSP64_CX 0x95
1887 #define CMD_XMIT_BLS_RSP64_CX 0x97
1888 #define CMD_FCP_IWRITE64_CR 0x98
1889 #define CMD_FCP_IWRITE64_CX 0x99
1890 #define CMD_FCP_IREAD64_CR 0x9A
1891 #define CMD_FCP_IREAD64_CX 0x9B
1892 #define CMD_FCP_ICMND64_CR 0x9C
1893 #define CMD_FCP_ICMND64_CX 0x9D
1894 #define CMD_FCP_TSEND64_CX 0x9F
1895 #define CMD_FCP_TRECEIVE64_CX 0xA1
1896 #define CMD_FCP_TRSP64_CX 0xA3
1898 #define CMD_QUE_XRI64_CX 0xB3
1899 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1900 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1901 #define CMD_IOCB_RET_XRI64_CX 0xB9
1902 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1904 #define CMD_GEN_REQUEST64_CR 0xC2
1905 #define CMD_GEN_REQUEST64_CX 0xC3
1907 /* Unhandled SLI-3 Commands */
1908 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1909 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1910 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1911 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1912 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1913 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1914 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1915 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1916 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1917 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1918 #define CMD_IOCB_LOGENTRY_CN 0x94
1919 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1921 /* Data Security SLI Commands */
1922 #define DSSCMD_IWRITE64_CR 0xF8
1923 #define DSSCMD_IWRITE64_CX 0xF9
1924 #define DSSCMD_IREAD64_CR 0xFA
1925 #define DSSCMD_IREAD64_CX 0xFB
1927 #define CMD_MAX_IOCB_CMD 0xFB
1928 #define CMD_IOCB_MASK 0xff
1930 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1932 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1936 #define MBX_SUCCESS 0
1937 #define MBXERR_NUM_RINGS 1
1938 #define MBXERR_NUM_IOCBS 2
1939 #define MBXERR_IOCBS_EXCEEDED 3
1940 #define MBXERR_BAD_RING_NUMBER 4
1941 #define MBXERR_MASK_ENTRIES_RANGE 5
1942 #define MBXERR_MASKS_EXCEEDED 6
1943 #define MBXERR_BAD_PROFILE 7
1944 #define MBXERR_BAD_DEF_CLASS 8
1945 #define MBXERR_BAD_MAX_RESPONDER 9
1946 #define MBXERR_BAD_MAX_ORIGINATOR 10
1947 #define MBXERR_RPI_REGISTERED 11
1948 #define MBXERR_RPI_FULL 12
1949 #define MBXERR_NO_RESOURCES 13
1950 #define MBXERR_BAD_RCV_LENGTH 14
1951 #define MBXERR_DMA_ERROR 15
1952 #define MBXERR_ERROR 16
1953 #define MBXERR_LINK_DOWN 0x33
1954 #define MBXERR_SEC_NO_PERMISSION 0xF02
1955 #define MBX_NOT_FINISHED 255
1957 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1958 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1960 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1968 * Begin Structure Definitions for Mailbox Commands
1972 #ifdef __BIG_ENDIAN_BITFIELD
1977 #else /* __LITTLE_ENDIAN_BITFIELD */
1986 uint32_t bdeAddress;
1987 #ifdef __BIG_ENDIAN_BITFIELD
1988 uint32_t bdeReserved:4;
1989 uint32_t bdeAddrHigh:4;
1990 uint32_t bdeSize:24;
1991 #else /* __LITTLE_ENDIAN_BITFIELD */
1992 uint32_t bdeSize:24;
1993 uint32_t bdeAddrHigh:4;
1994 uint32_t bdeReserved:4;
1998 typedef struct ULP_BDL { /* SLI-2 */
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000 uint32_t bdeFlags:8; /* BDL Flags */
2001 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2002 #else /* __LITTLE_ENDIAN_BITFIELD */
2003 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2004 uint32_t bdeFlags:8; /* BDL Flags */
2007 uint32_t addrLow; /* Address 0:31 */
2008 uint32_t addrHigh; /* Address 32:63 */
2009 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2013 * BlockGuard Definitions
2016 enum lpfc_protgrp_type {
2017 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2018 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2019 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2020 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2023 /* PDE Descriptors */
2024 #define LPFC_PDE5_DESCRIPTOR 0x85
2025 #define LPFC_PDE6_DESCRIPTOR 0x86
2026 #define LPFC_PDE7_DESCRIPTOR 0x87
2028 /* BlockGuard Opcodes */
2029 #define BG_OP_IN_NODIF_OUT_CRC 0x0
2030 #define BG_OP_IN_CRC_OUT_NODIF 0x1
2031 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
2032 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
2033 #define BG_OP_IN_CRC_OUT_CRC 0x4
2034 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
2035 #define BG_OP_IN_CRC_OUT_CSUM 0x6
2036 #define BG_OP_IN_CSUM_OUT_CRC 0x7
2037 #define BG_OP_RAW_MODE 0x8
2041 #define pde5_type_SHIFT 24
2042 #define pde5_type_MASK 0x000000ff
2043 #define pde5_type_WORD word0
2044 #define pde5_rsvd0_SHIFT 0
2045 #define pde5_rsvd0_MASK 0x00ffffff
2046 #define pde5_rsvd0_WORD word0
2047 uint32_t reftag; /* Reference Tag Value */
2048 uint32_t reftagtr; /* Reference Tag Translation Value */
2053 #define pde6_type_SHIFT 24
2054 #define pde6_type_MASK 0x000000ff
2055 #define pde6_type_WORD word0
2056 #define pde6_rsvd0_SHIFT 0
2057 #define pde6_rsvd0_MASK 0x00ffffff
2058 #define pde6_rsvd0_WORD word0
2060 #define pde6_rsvd1_SHIFT 26
2061 #define pde6_rsvd1_MASK 0x0000003f
2062 #define pde6_rsvd1_WORD word1
2063 #define pde6_na_SHIFT 25
2064 #define pde6_na_MASK 0x00000001
2065 #define pde6_na_WORD word1
2066 #define pde6_rsvd2_SHIFT 16
2067 #define pde6_rsvd2_MASK 0x000001FF
2068 #define pde6_rsvd2_WORD word1
2069 #define pde6_apptagtr_SHIFT 0
2070 #define pde6_apptagtr_MASK 0x0000ffff
2071 #define pde6_apptagtr_WORD word1
2073 #define pde6_optx_SHIFT 28
2074 #define pde6_optx_MASK 0x0000000f
2075 #define pde6_optx_WORD word2
2076 #define pde6_oprx_SHIFT 24
2077 #define pde6_oprx_MASK 0x0000000f
2078 #define pde6_oprx_WORD word2
2079 #define pde6_nr_SHIFT 23
2080 #define pde6_nr_MASK 0x00000001
2081 #define pde6_nr_WORD word2
2082 #define pde6_ce_SHIFT 22
2083 #define pde6_ce_MASK 0x00000001
2084 #define pde6_ce_WORD word2
2085 #define pde6_re_SHIFT 21
2086 #define pde6_re_MASK 0x00000001
2087 #define pde6_re_WORD word2
2088 #define pde6_ae_SHIFT 20
2089 #define pde6_ae_MASK 0x00000001
2090 #define pde6_ae_WORD word2
2091 #define pde6_ai_SHIFT 19
2092 #define pde6_ai_MASK 0x00000001
2093 #define pde6_ai_WORD word2
2094 #define pde6_bs_SHIFT 16
2095 #define pde6_bs_MASK 0x00000007
2096 #define pde6_bs_WORD word2
2097 #define pde6_apptagval_SHIFT 0
2098 #define pde6_apptagval_MASK 0x0000ffff
2099 #define pde6_apptagval_WORD word2
2104 #define pde7_type_SHIFT 24
2105 #define pde7_type_MASK 0x000000ff
2106 #define pde7_type_WORD word0
2107 #define pde7_rsvd0_SHIFT 0
2108 #define pde7_rsvd0_MASK 0x00ffffff
2109 #define pde7_rsvd0_WORD word0
2114 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2117 #ifdef __BIG_ENDIAN_BITFIELD
2119 uint32_t acknowledgment:1;
2121 uint32_t erase_or_prog:1;
2122 uint32_t update_flash:1;
2123 uint32_t update_ram:1;
2125 uint32_t load_cmplt:1;
2126 #else /* __LITTLE_ENDIAN_BITFIELD */
2127 uint32_t load_cmplt:1;
2129 uint32_t update_ram:1;
2130 uint32_t update_flash:1;
2131 uint32_t erase_or_prog:1;
2133 uint32_t acknowledgment:1;
2137 uint32_t dl_to_adr_low;
2138 uint32_t dl_to_adr_high;
2141 uint32_t dl_from_mbx_offset;
2142 struct ulp_bde dl_from_bde;
2143 struct ulp_bde64 dl_from_bde64;
2148 /* Structure for MB Command READ_NVPARM (02) */
2151 uint32_t rsvd1[3]; /* Read as all one's */
2152 uint32_t rsvd2; /* Read as all zero's */
2153 uint32_t portname[2]; /* N_PORT name */
2154 uint32_t nodename[2]; /* NODE name */
2156 #ifdef __BIG_ENDIAN_BITFIELD
2157 uint32_t pref_DID:24;
2158 uint32_t hardAL_PA:8;
2159 #else /* __LITTLE_ENDIAN_BITFIELD */
2160 uint32_t hardAL_PA:8;
2161 uint32_t pref_DID:24;
2164 uint32_t rsvd3[21]; /* Read as all one's */
2167 /* Structure for MB Command WRITE_NVPARMS (03) */
2170 uint32_t rsvd1[3]; /* Must be all one's */
2171 uint32_t rsvd2; /* Must be all zero's */
2172 uint32_t portname[2]; /* N_PORT name */
2173 uint32_t nodename[2]; /* NODE name */
2175 #ifdef __BIG_ENDIAN_BITFIELD
2176 uint32_t pref_DID:24;
2177 uint32_t hardAL_PA:8;
2178 #else /* __LITTLE_ENDIAN_BITFIELD */
2179 uint32_t hardAL_PA:8;
2180 uint32_t pref_DID:24;
2183 uint32_t rsvd3[21]; /* Must be all one's */
2186 /* Structure for MB Command RUN_BIU_DIAG (04) */
2187 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2193 struct ulp_bde xmit_bde;
2194 struct ulp_bde rcv_bde;
2197 struct ulp_bde64 xmit_bde64;
2198 struct ulp_bde64 rcv_bde64;
2203 /* Structure for MB command READ_EVENT_LOG (0x38) */
2204 struct READ_EVENT_LOG_VAR {
2206 #define lpfc_event_log_SHIFT 29
2207 #define lpfc_event_log_MASK 0x00000001
2208 #define lpfc_event_log_WORD word1
2209 #define USE_MAILBOX_RESPONSE 1
2211 struct ulp_bde64 rcv_bde64;
2214 /* Structure for MB Command INIT_LINK (05) */
2217 #ifdef __BIG_ENDIAN_BITFIELD
2219 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2220 #else /* __LITTLE_ENDIAN_BITFIELD */
2221 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2225 #ifdef __BIG_ENDIAN_BITFIELD
2226 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2228 uint16_t link_flags;
2229 #else /* __LITTLE_ENDIAN_BITFIELD */
2230 uint16_t link_flags;
2232 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2235 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2236 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2237 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2238 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2239 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2240 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2241 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2243 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2244 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2245 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2247 uint32_t link_speed;
2248 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2249 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2250 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2251 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2252 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2253 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2254 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2255 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2259 /* Structure for MB Command DOWN_LINK (06) */
2265 /* Structure for MB Command CONFIG_LINK (07) */
2268 #ifdef __BIG_ENDIAN_BITFIELD
2271 uint32_t cr_delay:6;
2272 uint32_t cr_count:8;
2275 #else /* __LITTLE_ENDIAN_BITFIELD */
2278 uint32_t cr_count:8;
2279 uint32_t cr_delay:6;
2293 #ifdef __BIG_ENDIAN_BITFIELD
2298 #else /* __LITTLE_ENDIAN_BITFIELD */
2305 #ifdef __BIG_ENDIAN_BITFIELD
2306 uint32_t rrq_enable:1;
2307 uint32_t rrq_immed:1;
2309 uint32_t ack0_enable:1;
2310 #else /* __LITTLE_ENDIAN_BITFIELD */
2311 uint32_t ack0_enable:1;
2313 uint32_t rrq_immed:1;
2314 uint32_t rrq_enable:1;
2318 /* Structure for MB Command PART_SLIM (08)
2319 * will be removed since SLI1 is no longer supported!
2322 #ifdef __BIG_ENDIAN_BITFIELD
2327 #else /* __LITTLE_ENDIAN_BITFIELD */
2336 #ifdef __BIG_ENDIAN_BITFIELD
2337 uint32_t unused1:24;
2339 #else /* __LITTLE_ENDIAN_BITFIELD */
2341 uint32_t unused1:24;
2344 RING_DEF ringdef[4];
2348 /* Structure for MB Command CONFIG_RING (09) */
2351 #ifdef __BIG_ENDIAN_BITFIELD
2354 uint32_t recvNotify:1;
2359 #else /* __LITTLE_ENDIAN_BITFIELD */
2364 uint32_t recvNotify:1;
2369 #ifdef __BIG_ENDIAN_BITFIELD
2370 uint16_t maxRespXchg;
2371 uint16_t maxOrigXchg;
2372 #else /* __LITTLE_ENDIAN_BITFIELD */
2373 uint16_t maxOrigXchg;
2374 uint16_t maxRespXchg;
2380 /* Structure for MB Command RESET_RING (10) */
2386 /* Structure for MB Command READ_CONFIG (11) */
2389 #ifdef __BIG_ENDIAN_BITFIELD
2392 uint32_t cr_delay:6;
2393 uint32_t cr_count:8;
2396 #else /* __LITTLE_ENDIAN_BITFIELD */
2399 uint32_t cr_count:8;
2400 uint32_t cr_delay:6;
2405 #ifdef __BIG_ENDIAN_BITFIELD
2406 uint32_t topology:8;
2408 #else /* __LITTLE_ENDIAN_BITFIELD */
2410 uint32_t topology:8;
2413 /* Defines for topology (defined previously) */
2414 #ifdef __BIG_ENDIAN_BITFIELD
2419 #else /* __LITTLE_ENDIAN_BITFIELD */
2432 #define LMT_RESERVED 0x000 /* Not used */
2433 #define LMT_1Gb 0x004
2434 #define LMT_2Gb 0x008
2435 #define LMT_4Gb 0x040
2436 #define LMT_8Gb 0x080
2437 #define LMT_10Gb 0x100
2438 #define LMT_16Gb 0x200
2439 #define LMT_32Gb 0x400
2446 uint32_t avail_iocb;
2454 /* Structure for MB Command READ_RCONFIG (12) */
2457 #ifdef __BIG_ENDIAN_BITFIELD
2459 uint32_t recvNotify:1;
2464 #else /* __LITTLE_ENDIAN_BITFIELD */
2469 uint32_t recvNotify:1;
2473 #ifdef __BIG_ENDIAN_BITFIELD
2476 #else /* __LITTLE_ENDIAN_BITFIELD */
2483 #ifdef __BIG_ENDIAN_BITFIELD
2484 uint16_t cmdRingOffset;
2485 uint16_t cmdEntryCnt;
2486 uint16_t rspRingOffset;
2487 uint16_t rspEntryCnt;
2488 uint16_t nextCmdOffset;
2490 uint16_t nextRspOffset;
2492 #else /* __LITTLE_ENDIAN_BITFIELD */
2493 uint16_t cmdEntryCnt;
2494 uint16_t cmdRingOffset;
2495 uint16_t rspEntryCnt;
2496 uint16_t rspRingOffset;
2498 uint16_t nextCmdOffset;
2500 uint16_t nextRspOffset;
2504 /* Structure for MB Command READ_SPARM (13) */
2505 /* Structure for MB Command READ_SPARM64 (0x8D) */
2511 struct ulp_bde sp; /* This BDE points to struct serv_parm
2513 struct ulp_bde64 sp64;
2515 #ifdef __BIG_ENDIAN_BITFIELD
2518 #else /* __LITTLE_ENDIAN_BITFIELD */
2524 /* Structure for MB Command READ_STATUS (14) */
2527 #ifdef __BIG_ENDIAN_BITFIELD
2529 uint32_t clrCounters:1;
2530 uint16_t activeXriCnt;
2531 uint16_t activeRpiCnt;
2532 #else /* __LITTLE_ENDIAN_BITFIELD */
2533 uint32_t clrCounters:1;
2535 uint16_t activeRpiCnt;
2536 uint16_t activeXriCnt;
2539 uint32_t xmitByteCnt;
2540 uint32_t rcvByteCnt;
2541 uint32_t xmitFrameCnt;
2542 uint32_t rcvFrameCnt;
2543 uint32_t xmitSeqCnt;
2545 uint32_t totalOrigExchanges;
2546 uint32_t totalRespExchanges;
2547 uint32_t rcvPbsyCnt;
2548 uint32_t rcvFbsyCnt;
2551 /* Structure for MB Command READ_RPI (15) */
2552 /* Structure for MB Command READ_RPI64 (0x8F) */
2555 #ifdef __BIG_ENDIAN_BITFIELD
2560 #else /* __LITTLE_ENDIAN_BITFIELD */
2569 struct ulp_bde64 sp64;
2574 /* Structure for MB Command READ_XRI (16) */
2577 #ifdef __BIG_ENDIAN_BITFIELD
2594 uint32_t exchOrig:1;
2595 #else /* __LITTLE_ENDIAN_BITFIELD */
2610 uint32_t exchOrig:1;
2616 /* Structure for MB Command READ_REV (17) */
2619 #ifdef __BIG_ENDIAN_BITFIELD
2627 #else /* __LITTLE_ENDIAN_BITFIELD */
2642 #ifdef __BIG_ENDIAN_BITFIELD
2647 uint16_t ProgFixLvl:2;
2648 uint16_t ProgDistType:2;
2650 #else /* __LITTLE_ENDIAN_BITFIELD */
2652 uint16_t ProgDistType:2;
2653 uint16_t ProgFixLvl:2;
2663 #ifdef __BIG_ENDIAN_BITFIELD
2664 uint8_t feaLevelHigh;
2665 uint8_t feaLevelLow;
2668 #else /* __LITTLE_ENDIAN_BITFIELD */
2671 uint8_t feaLevelLow;
2672 uint8_t feaLevelHigh;
2675 uint32_t postKernRev;
2677 uint8_t opFwName[16];
2679 uint8_t sli1FwName[16];
2681 uint8_t sli2FwName[16];
2683 uint32_t RandomData[6];
2686 /* Structure for MB Command READ_LINK_STAT (18) */
2691 #define lpfc_read_link_stat_rec_SHIFT 0
2692 #define lpfc_read_link_stat_rec_MASK 0x1
2693 #define lpfc_read_link_stat_rec_WORD word0
2695 #define lpfc_read_link_stat_gec_SHIFT 1
2696 #define lpfc_read_link_stat_gec_MASK 0x1
2697 #define lpfc_read_link_stat_gec_WORD word0
2699 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2700 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2701 #define lpfc_read_link_stat_w02oftow23of_WORD word0
2703 #define lpfc_read_link_stat_rsvd_SHIFT 24
2704 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2705 #define lpfc_read_link_stat_rsvd_WORD word0
2707 #define lpfc_read_link_stat_gec2_SHIFT 29
2708 #define lpfc_read_link_stat_gec2_MASK 0x1
2709 #define lpfc_read_link_stat_gec2_WORD word0
2711 #define lpfc_read_link_stat_clrc_SHIFT 30
2712 #define lpfc_read_link_stat_clrc_MASK 0x1
2713 #define lpfc_read_link_stat_clrc_WORD word0
2715 #define lpfc_read_link_stat_clof_SHIFT 31
2716 #define lpfc_read_link_stat_clof_MASK 0x1
2717 #define lpfc_read_link_stat_clof_WORD word0
2719 uint32_t linkFailureCnt;
2720 uint32_t lossSyncCnt;
2721 uint32_t lossSignalCnt;
2722 uint32_t primSeqErrCnt;
2723 uint32_t invalidXmitWord;
2725 uint32_t primSeqTimeout;
2726 uint32_t elasticOverrun;
2727 uint32_t arbTimeout;
2728 uint32_t advRecBufCredit;
2729 uint32_t curRecBufCredit;
2730 uint32_t advTransBufCredit;
2731 uint32_t curTransBufCredit;
2732 uint32_t recEofCount;
2733 uint32_t recEofdtiCount;
2734 uint32_t recEofniCount;
2735 uint32_t recSofcount;
2738 uint32_t recDrpXriCount;
2739 uint32_t fecCorrBlkCount;
2740 uint32_t fecUncorrBlkCount;
2743 /* Structure for MB Command REG_LOGIN (19) */
2744 /* Structure for MB Command REG_LOGIN64 (0x93) */
2747 #ifdef __BIG_ENDIAN_BITFIELD
2752 #else /* __LITTLE_ENDIAN_BITFIELD */
2761 struct ulp_bde64 sp64;
2764 #ifdef __BIG_ENDIAN_BITFIELD
2767 #else /* __LITTLE_ENDIAN_BITFIELD */
2774 /* Word 30 contents for REG_LOGIN */
2777 #ifdef __BIG_ENDIAN_BITFIELD
2779 uint16_t wd30_class:4;
2781 #else /* __LITTLE_ENDIAN_BITFIELD */
2783 uint16_t wd30_class:4;
2790 /* Structure for MB Command UNREG_LOGIN (20) */
2793 #ifdef __BIG_ENDIAN_BITFIELD
2802 #else /* __LITTLE_ENDIAN_BITFIELD */
2814 /* Structure for MB Command REG_VPI (0x96) */
2816 #ifdef __BIG_ENDIAN_BITFIELD
2825 #else /* __LITTLE_ENDIAN */
2837 /* Structure for MB Command UNREG_VPI (0x97) */
2840 #ifdef __BIG_ENDIAN_BITFIELD
2843 #else /* __LITTLE_ENDIAN */
2850 #ifdef __BIG_ENDIAN_BITFIELD
2853 #else /* __LITTLE_ENDIAN */
2859 /* Structure for MB Command UNREG_D_ID (0x23) */
2867 #ifdef __BIG_ENDIAN_BITFIELD
2876 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2877 struct lpfc_mbx_read_top {
2878 uint32_t eventTag; /* Event tag */
2880 #define lpfc_mbx_read_top_fa_SHIFT 12
2881 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2882 #define lpfc_mbx_read_top_fa_WORD word2
2883 #define lpfc_mbx_read_top_mm_SHIFT 11
2884 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2885 #define lpfc_mbx_read_top_mm_WORD word2
2886 #define lpfc_mbx_read_top_pb_SHIFT 9
2887 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2888 #define lpfc_mbx_read_top_pb_WORD word2
2889 #define lpfc_mbx_read_top_il_SHIFT 8
2890 #define lpfc_mbx_read_top_il_MASK 0x00000001
2891 #define lpfc_mbx_read_top_il_WORD word2
2892 #define lpfc_mbx_read_top_att_type_SHIFT 0
2893 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2894 #define lpfc_mbx_read_top_att_type_WORD word2
2895 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2896 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2897 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2898 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
2900 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2901 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2902 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2903 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2904 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2905 #define lpfc_mbx_read_top_lip_alps_WORD word3
2906 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2907 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2908 #define lpfc_mbx_read_top_lip_type_WORD word3
2909 #define lpfc_mbx_read_top_topology_SHIFT 0
2910 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2911 #define lpfc_mbx_read_top_topology_WORD word3
2912 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2913 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2914 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2915 /* store the LILP AL_PA position map into */
2916 struct ulp_bde64 lilpBde64;
2917 #define LPFC_ALPA_MAP_SIZE 128
2919 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2920 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2921 #define lpfc_mbx_read_top_ld_lu_WORD word7
2922 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2923 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2924 #define lpfc_mbx_read_top_ld_tf_WORD word7
2925 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2926 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2927 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2928 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2929 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2930 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2931 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2932 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2933 #define lpfc_mbx_read_top_ld_tx_WORD word7
2934 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2935 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2936 #define lpfc_mbx_read_top_ld_rx_WORD word7
2938 #define lpfc_mbx_read_top_lu_SHIFT 31
2939 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2940 #define lpfc_mbx_read_top_lu_WORD word8
2941 #define lpfc_mbx_read_top_tf_SHIFT 30
2942 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2943 #define lpfc_mbx_read_top_tf_WORD word8
2944 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2945 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2946 #define lpfc_mbx_read_top_link_spd_WORD word8
2947 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2948 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2949 #define lpfc_mbx_read_top_nl_port_WORD word8
2950 #define lpfc_mbx_read_top_tx_SHIFT 2
2951 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2952 #define lpfc_mbx_read_top_tx_WORD word8
2953 #define lpfc_mbx_read_top_rx_SHIFT 0
2954 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2955 #define lpfc_mbx_read_top_rx_WORD word8
2956 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2957 #define LPFC_LINK_SPEED_1GHZ 0x04
2958 #define LPFC_LINK_SPEED_2GHZ 0x08
2959 #define LPFC_LINK_SPEED_4GHZ 0x10
2960 #define LPFC_LINK_SPEED_8GHZ 0x20
2961 #define LPFC_LINK_SPEED_10GHZ 0x40
2962 #define LPFC_LINK_SPEED_16GHZ 0x80
2963 #define LPFC_LINK_SPEED_32GHZ 0x90
2966 /* Structure for MB Command CLEAR_LA (22) */
2969 uint32_t eventTag; /* Event tag */
2973 /* Structure for MB Command DUMP */
2976 #ifdef __BIG_ENDIAN_BITFIELD
2982 uint32_t entry_index:16;
2983 uint32_t region_id:16;
2984 #else /* __LITTLE_ENDIAN_BITFIELD */
2990 uint32_t region_id:16;
2991 uint32_t entry_index:16;
2994 uint32_t sli4_length;
2996 uint32_t resp_offset;
2999 #define DMP_MEM_REG 0x1
3000 #define DMP_NV_PARAMS 0x2
3001 #define DMP_LMSD 0x3 /* Link Module Serial Data */
3002 #define DMP_WELL_KNOWN 0x4
3004 #define DMP_REGION_VPD 0xe
3005 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3006 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3007 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3009 #define DMP_REGION_VPORT 0x16 /* VPort info region */
3010 #define DMP_VPORT_REGION_SIZE 0x200
3011 #define DMP_MBOX_OFFSET_WORD 0x5
3013 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
3014 #define DMP_RGN23_SIZE 0x400
3016 #define WAKE_UP_PARMS_REGION_ID 4
3017 #define WAKE_UP_PARMS_WORD_SIZE 15
3024 #define VPORT_INFO_SIG 0x32324752
3025 #define VPORT_INFO_REV_MASK 0xff
3026 #define VPORT_INFO_REV 0x1
3027 #define MAX_STATIC_VPORT_COUNT 16
3028 struct static_vport_info {
3031 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3035 /* Option rom version structure */
3037 #ifdef __BIG_ENDIAN_BITFIELD
3040 uint32_t ver:4; /* Major Version */
3041 uint32_t rev:4; /* Revision */
3042 uint32_t lev:2; /* Level */
3043 uint32_t dist:2; /* Dist Type */
3044 uint32_t num:4; /* number after dist type */
3045 #else /* __LITTLE_ENDIAN_BITFIELD */
3046 uint32_t num:4; /* number after dist type */
3047 uint32_t dist:2; /* Dist Type */
3048 uint32_t lev:2; /* Level */
3049 uint32_t rev:4; /* Revision */
3050 uint32_t ver:4; /* Major Version */
3056 /* Structure for MB Command UPDATE_CFG (0x1B) */
3058 struct update_cfg_var {
3059 #ifdef __BIG_ENDIAN_BITFIELD
3067 uint32_t entry_length:16;
3068 uint32_t region_id:16;
3069 #else /* __LITTLE_ENDIAN_BITFIELD */
3077 uint32_t region_id:16;
3078 uint32_t entry_length:16;
3083 uint32_t data_offset;
3087 #ifdef __BIG_ENDIAN_BITFIELD
3092 #else /* __LITTLE_ENDIAN */
3101 /* Structure for MB Command CONFIG_HBQ (7c) */
3103 struct config_hbq_var {
3104 #ifdef __BIG_ENDIAN_BITFIELD
3106 uint32_t recvNotify :1; /* Receive Notification */
3107 uint32_t numMask :8; /* # Mask Entries */
3108 uint32_t profile :8; /* Selection Profile */
3110 #else /* __LITTLE_ENDIAN */
3112 uint32_t profile :8; /* Selection Profile */
3113 uint32_t numMask :8; /* # Mask Entries */
3114 uint32_t recvNotify :1; /* Receive Notification */
3118 #ifdef __BIG_ENDIAN_BITFIELD
3121 uint32_t ringMask :4;
3122 #else /* __LITTLE_ENDIAN */
3123 uint32_t ringMask :4;
3128 #ifdef __BIG_ENDIAN_BITFIELD
3129 uint32_t entry_count :16;
3131 uint32_t headerLen :8;
3132 #else /* __LITTLE_ENDIAN */
3133 uint32_t headerLen :8;
3135 uint32_t entry_count :16;
3138 uint32_t hbqaddrLow;
3139 uint32_t hbqaddrHigh;
3141 #ifdef __BIG_ENDIAN_BITFIELD
3143 uint32_t logEntry :1;
3144 #else /* __LITTLE_ENDIAN */
3145 uint32_t logEntry :1;
3149 uint32_t rsvd6; /* w7 */
3150 uint32_t rsvd7; /* w8 */
3151 uint32_t rsvd8; /* w9 */
3153 struct hbq_mask hbqMasks[6];
3157 uint32_t allprofiles[12];
3160 #ifdef __BIG_ENDIAN_BITFIELD
3161 uint32_t seqlenoff :16;
3162 uint32_t maxlen :16;
3163 #else /* __LITTLE_ENDIAN */
3164 uint32_t maxlen :16;
3165 uint32_t seqlenoff :16;
3167 #ifdef __BIG_ENDIAN_BITFIELD
3169 uint32_t seqlenbcnt :4;
3170 #else /* __LITTLE_ENDIAN */
3171 uint32_t seqlenbcnt :4;
3178 #ifdef __BIG_ENDIAN_BITFIELD
3179 uint32_t seqlenoff :16;
3180 uint32_t maxlen :16;
3181 #else /* __LITTLE_ENDIAN */
3182 uint32_t maxlen :16;
3183 uint32_t seqlenoff :16;
3185 #ifdef __BIG_ENDIAN_BITFIELD
3186 uint32_t cmdcodeoff :28;
3188 uint32_t seqlenbcnt :4;
3189 #else /* __LITTLE_ENDIAN */
3190 uint32_t seqlenbcnt :4;
3192 uint32_t cmdcodeoff :28;
3194 uint32_t cmdmatch[8];
3200 #ifdef __BIG_ENDIAN_BITFIELD
3201 uint32_t seqlenoff :16;
3202 uint32_t maxlen :16;
3203 #else /* __LITTLE_ENDIAN */
3204 uint32_t maxlen :16;
3205 uint32_t seqlenoff :16;
3207 #ifdef __BIG_ENDIAN_BITFIELD
3208 uint32_t cmdcodeoff :28;
3210 uint32_t seqlenbcnt :4;
3211 #else /* __LITTLE_ENDIAN */
3212 uint32_t seqlenbcnt :4;
3214 uint32_t cmdcodeoff :28;
3216 uint32_t cmdmatch[8];
3227 /* Structure for MB Command CONFIG_PORT (0x88) */
3229 #ifdef __BIG_ENDIAN_BITFIELD
3234 uint32_t sli_mode : 4;
3235 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3237 #else /* __LITTLE_ENDIAN */
3238 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3240 uint32_t sli_mode : 4;
3247 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3248 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3249 uint32_t hbainit[5];
3250 #ifdef __BIG_ENDIAN_BITFIELD
3251 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3252 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3253 #else /* __LITTLE_ENDIAN */
3254 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3255 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3258 #ifdef __BIG_ENDIAN_BITFIELD
3259 uint32_t rsvd1 : 19; /* Reserved */
3260 uint32_t cdss : 1; /* Configure Data Security SLI */
3261 uint32_t casabt : 1; /* Configure async abts status notice */
3262 uint32_t rsvd2 : 2; /* Reserved */
3263 uint32_t cbg : 1; /* Configure BlockGuard */
3264 uint32_t cmv : 1; /* Configure Max VPIs */
3265 uint32_t ccrp : 1; /* Config Command Ring Polling */
3266 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3267 uint32_t chbs : 1; /* Cofigure Host Backing store */
3268 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3269 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3270 uint32_t cmx : 1; /* Configure Max XRIs */
3271 uint32_t cmr : 1; /* Configure Max RPIs */
3272 #else /* __LITTLE_ENDIAN */
3273 uint32_t cmr : 1; /* Configure Max RPIs */
3274 uint32_t cmx : 1; /* Configure Max XRIs */
3275 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3276 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3277 uint32_t chbs : 1; /* Cofigure Host Backing store */
3278 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3279 uint32_t ccrp : 1; /* Config Command Ring Polling */
3280 uint32_t cmv : 1; /* Configure Max VPIs */
3281 uint32_t cbg : 1; /* Configure BlockGuard */
3282 uint32_t rsvd2 : 2; /* Reserved */
3283 uint32_t casabt : 1; /* Configure async abts status notice */
3284 uint32_t cdss : 1; /* Configure Data Security SLI */
3285 uint32_t rsvd1 : 19; /* Reserved */
3287 #ifdef __BIG_ENDIAN_BITFIELD
3288 uint32_t rsvd3 : 19; /* Reserved */
3289 uint32_t gdss : 1; /* Configure Data Security SLI */
3290 uint32_t gasabt : 1; /* Grant async abts status notice */
3291 uint32_t rsvd4 : 2; /* Reserved */
3292 uint32_t gbg : 1; /* Grant BlockGuard */
3293 uint32_t gmv : 1; /* Grant Max VPIs */
3294 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3295 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3296 uint32_t ghbs : 1; /* Grant Host Backing Store */
3297 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3298 uint32_t gerbm : 1; /* Grant ERBM Request */
3299 uint32_t gmx : 1; /* Grant Max XRIs */
3300 uint32_t gmr : 1; /* Grant Max RPIs */
3301 #else /* __LITTLE_ENDIAN */
3302 uint32_t gmr : 1; /* Grant Max RPIs */
3303 uint32_t gmx : 1; /* Grant Max XRIs */
3304 uint32_t gerbm : 1; /* Grant ERBM Request */
3305 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3306 uint32_t ghbs : 1; /* Grant Host Backing Store */
3307 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3308 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3309 uint32_t gmv : 1; /* Grant Max VPIs */
3310 uint32_t gbg : 1; /* Grant BlockGuard */
3311 uint32_t rsvd4 : 2; /* Reserved */
3312 uint32_t gasabt : 1; /* Grant async abts status notice */
3313 uint32_t gdss : 1; /* Configure Data Security SLI */
3314 uint32_t rsvd3 : 19; /* Reserved */
3317 #ifdef __BIG_ENDIAN_BITFIELD
3318 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3319 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3320 #else /* __LITTLE_ENDIAN */
3321 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3322 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3325 #ifdef __BIG_ENDIAN_BITFIELD
3326 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3327 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3328 #else /* __LITTLE_ENDIAN */
3329 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3330 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3333 uint32_t rsvd6; /* Reserved */
3335 #ifdef __BIG_ENDIAN_BITFIELD
3336 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3337 uint32_t fips_level : 4; /* FIPS Level */
3338 uint32_t sec_err : 9; /* security crypto error */
3339 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3340 #else /* __LITTLE_ENDIAN */
3341 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3342 uint32_t sec_err : 9; /* security crypto error */
3343 uint32_t fips_level : 4; /* FIPS Level */
3344 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3349 /* Structure for MB Command CONFIG_MSI (0x30) */
3350 struct config_msi_var {
3351 #ifdef __BIG_ENDIAN_BITFIELD
3352 uint32_t dfltMsgNum:8; /* Default message number */
3353 uint32_t rsvd1:11; /* Reserved */
3354 uint32_t NID:5; /* Number of secondary attention IDs */
3355 uint32_t rsvd2:5; /* Reserved */
3356 uint32_t dfltPresent:1; /* Default message number present */
3357 uint32_t addFlag:1; /* Add association flag */
3358 uint32_t reportFlag:1; /* Report association flag */
3359 #else /* __LITTLE_ENDIAN_BITFIELD */
3360 uint32_t reportFlag:1; /* Report association flag */
3361 uint32_t addFlag:1; /* Add association flag */
3362 uint32_t dfltPresent:1; /* Default message number present */
3363 uint32_t rsvd2:5; /* Reserved */
3364 uint32_t NID:5; /* Number of secondary attention IDs */
3365 uint32_t rsvd1:11; /* Reserved */
3366 uint32_t dfltMsgNum:8; /* Default message number */
3368 uint32_t attentionConditions[2];
3369 uint8_t attentionId[16];
3370 uint8_t messageNumberByHA[64];
3371 uint8_t messageNumberByID[16];
3372 uint32_t autoClearHA[2];
3373 #ifdef __BIG_ENDIAN_BITFIELD
3375 uint32_t autoClearID:16;
3376 #else /* __LITTLE_ENDIAN_BITFIELD */
3377 uint32_t autoClearID:16;
3383 /* SLI-2 Port Control Block */
3386 #define SLIMOFF 0x30 /* WORD */
3388 typedef struct _SLI2_RDSC {
3389 uint32_t cmdEntries;
3390 uint32_t cmdAddrLow;
3391 uint32_t cmdAddrHigh;
3393 uint32_t rspEntries;
3394 uint32_t rspAddrLow;
3395 uint32_t rspAddrHigh;
3398 typedef struct _PCB {
3399 #ifdef __BIG_ENDIAN_BITFIELD
3401 #define TYPE_NATIVE_SLI2 0x01
3403 #define FEATURE_INITIAL_SLI2 0x01
3406 #else /* __LITTLE_ENDIAN_BITFIELD */
3410 #define FEATURE_INITIAL_SLI2 0x01
3412 #define TYPE_NATIVE_SLI2 0x01
3415 uint32_t mailBoxSize;
3417 uint32_t mbAddrHigh;
3419 uint32_t hgpAddrLow;
3420 uint32_t hgpAddrHigh;
3422 uint32_t pgpAddrLow;
3423 uint32_t pgpAddrHigh;
3424 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3429 #ifdef __BIG_ENDIAN_BITFIELD
3431 uint32_t discardFarp:1;
3432 uint32_t IPEnable:1;
3433 uint32_t nodeName:1;
3434 uint32_t portName:1;
3435 uint32_t filterEnable:1;
3436 #else /* __LITTLE_ENDIAN_BITFIELD */
3437 uint32_t filterEnable:1;
3438 uint32_t portName:1;
3439 uint32_t nodeName:1;
3440 uint32_t IPEnable:1;
3441 uint32_t discardFarp:1;
3445 uint8_t portname[8]; /* Used to be struct lpfc_name */
3446 uint8_t nodename[8];
3453 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3456 #ifdef __BIG_ENDIAN_BITFIELD
3458 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3459 #else /* __LITTLE_ENDIAN */
3460 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3463 } ASYNCEVT_ENABLE_VAR;
3465 /* Union of all Mailbox Command types */
3466 #define MAILBOX_CMD_WSIZE 32
3467 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3468 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3469 #define MAILBOX_EXT_WSIZE 512
3470 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3471 #define MAILBOX_HBA_EXT_OFFSET 0x100
3472 /* max mbox xmit size is a page size for sysfs IO operations */
3473 #define MAILBOX_SYSFS_MAX 4096
3476 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3477 * feature/max ring number
3479 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3480 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3481 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3482 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3483 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3484 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3485 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3486 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3487 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3488 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3489 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3490 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3491 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3492 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3493 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3494 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3495 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3496 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3497 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3498 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3499 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3500 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3501 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3502 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3505 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3506 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3507 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3508 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3509 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3510 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3511 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3512 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3515 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3519 * SLI-2 specific structures
3533 uint32_t unused1[16];
3534 struct lpfc_hgp host[MAX_SLI3_RINGS];
3535 struct lpfc_pgp port[MAX_SLI3_RINGS];
3539 struct lpfc_hgp host[MAX_SLI3_RINGS];
3540 uint32_t reserved[8];
3541 uint32_t hbq_put[16];
3545 struct lpfc_pgp port[MAX_SLI3_RINGS];
3546 uint32_t hbq_get[16];
3550 struct sli2_desc s2;
3551 struct sli3_desc s3;
3552 struct sli3_pgp s3_pgp;
3556 #ifdef __BIG_ENDIAN_BITFIELD
3559 uint8_t mbxReserved:6;
3561 uint8_t mbxOwner:1; /* Low order bit first word */
3562 #else /* __LITTLE_ENDIAN_BITFIELD */
3563 uint8_t mbxOwner:1; /* Low order bit first word */
3565 uint8_t mbxReserved:6;
3575 * Begin Structure Definitions for IOCB Commands
3579 #ifdef __BIG_ENDIAN_BITFIELD
3583 uint8_t statLocalError;
3584 #else /* __LITTLE_ENDIAN_BITFIELD */
3585 uint8_t statLocalError;
3590 /* statRsn P/F_RJT reason codes */
3591 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3592 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3593 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3594 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3595 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3596 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3597 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3598 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3599 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3600 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3601 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3602 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3603 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3604 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3605 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3606 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3607 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3608 #define RJT_PROT_ERR 0x12 /* Protocol error */
3609 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3610 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3611 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3612 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3613 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3614 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3615 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3616 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3618 #define IOERR_SUCCESS 0x00 /* statLocalError */
3619 #define IOERR_MISSING_CONTINUE 0x01
3620 #define IOERR_SEQUENCE_TIMEOUT 0x02
3621 #define IOERR_INTERNAL_ERROR 0x03
3622 #define IOERR_INVALID_RPI 0x04
3623 #define IOERR_NO_XRI 0x05
3624 #define IOERR_ILLEGAL_COMMAND 0x06
3625 #define IOERR_XCHG_DROPPED 0x07
3626 #define IOERR_ILLEGAL_FIELD 0x08
3627 #define IOERR_BAD_CONTINUE 0x09
3628 #define IOERR_TOO_MANY_BUFFERS 0x0A
3629 #define IOERR_RCV_BUFFER_WAITING 0x0B
3630 #define IOERR_NO_CONNECTION 0x0C
3631 #define IOERR_TX_DMA_FAILED 0x0D
3632 #define IOERR_RX_DMA_FAILED 0x0E
3633 #define IOERR_ILLEGAL_FRAME 0x0F
3634 #define IOERR_EXTRA_DATA 0x10
3635 #define IOERR_NO_RESOURCES 0x11
3636 #define IOERR_RESERVED 0x12
3637 #define IOERR_ILLEGAL_LENGTH 0x13
3638 #define IOERR_UNSUPPORTED_FEATURE 0x14
3639 #define IOERR_ABORT_IN_PROGRESS 0x15
3640 #define IOERR_ABORT_REQUESTED 0x16
3641 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3642 #define IOERR_LOOP_OPEN_FAILURE 0x18
3643 #define IOERR_RING_RESET 0x19
3644 #define IOERR_LINK_DOWN 0x1A
3645 #define IOERR_CORRUPTED_DATA 0x1B
3646 #define IOERR_CORRUPTED_RPI 0x1C
3647 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3648 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3649 #define IOERR_DUP_FRAME 0x1F
3650 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3651 #define IOERR_BAD_HOST_ADDRESS 0x21
3652 #define IOERR_RCV_HDRBUF_WAITING 0x22
3653 #define IOERR_MISSING_HDR_BUFFER 0x23
3654 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3655 #define IOERR_ABORTMULT_REQUESTED 0x25
3656 #define IOERR_BUFFER_SHORTAGE 0x28
3657 #define IOERR_DEFAULT 0x29
3658 #define IOERR_CNT 0x2A
3659 #define IOERR_SLER_FAILURE 0x46
3660 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3661 #define IOERR_SLER_REC_RJT_ERR 0x48
3662 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3663 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3664 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3665 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3666 #define IOERR_SLER_ABTS_ERR 0x4E
3667 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3668 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3669 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3670 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3671 #define IOERR_DRVR_MASK 0x100
3672 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3673 #define IOERR_SLI_BRESET 0x102
3674 #define IOERR_SLI_ABORTED 0x103
3675 #define IOERR_PARAM_MASK 0x1ff
3680 #ifdef __BIG_ENDIAN_BITFIELD
3681 uint8_t Rctl; /* R_CTL field */
3682 uint8_t Type; /* TYPE field */
3683 uint8_t Dfctl; /* DF_CTL field */
3684 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3685 #else /* __LITTLE_ENDIAN_BITFIELD */
3686 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3687 uint8_t Dfctl; /* DF_CTL field */
3688 uint8_t Type; /* TYPE field */
3689 uint8_t Rctl; /* R_CTL field */
3692 #define BC 0x02 /* Broadcast Received - Fctl */
3693 #define SI 0x04 /* Sequence Initiative */
3694 #define LA 0x08 /* Ignore Link Attention state */
3695 #define LS 0x80 /* Last Sequence */
3700 /* IOCB Command template for a generic response */
3702 uint32_t reserved[4];
3706 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3708 struct ulp_bde xrsqbde[2];
3709 uint32_t xrsqRo; /* Starting Relative Offset */
3710 WORD5 w5; /* Header control/status word */
3713 /* IOCB Command template for ELS_REQUEST */
3715 struct ulp_bde elsReq;
3716 struct ulp_bde elsRsp;
3718 #ifdef __BIG_ENDIAN_BITFIELD
3719 uint32_t word4Rsvd:7;
3722 uint32_t word5Rsvd:8;
3723 uint32_t remoteID:24;
3724 #else /* __LITTLE_ENDIAN_BITFIELD */
3727 uint32_t word4Rsvd:7;
3728 uint32_t remoteID:24;
3729 uint32_t word5Rsvd:8;
3733 /* IOCB Command template for RCV_ELS_REQ */
3735 struct ulp_bde elsReq[2];
3738 #ifdef __BIG_ENDIAN_BITFIELD
3739 uint32_t word5Rsvd:8;
3740 uint32_t remoteID:24;
3741 #else /* __LITTLE_ENDIAN_BITFIELD */
3742 uint32_t remoteID:24;
3743 uint32_t word5Rsvd:8;
3747 /* IOCB Command template for ABORT / CLOSE_XRI */
3751 #define ABORT_TYPE_ABTX 0x00000000
3752 #define ABORT_TYPE_ABTS 0x00000001
3754 #ifdef __BIG_ENDIAN_BITFIELD
3755 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3756 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3757 #else /* __LITTLE_ENDIAN_BITFIELD */
3758 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3759 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3763 /* IOCB Command template for ABORT_MXRI64 */
3771 /* IOCB Command template for GET_RPI */
3775 #ifdef __BIG_ENDIAN_BITFIELD
3776 uint32_t word5Rsvd:8;
3777 uint32_t remoteID:24;
3778 #else /* __LITTLE_ENDIAN_BITFIELD */
3779 uint32_t remoteID:24;
3780 uint32_t word5Rsvd:8;
3784 /* IOCB Command template for all FCP Initiator commands */
3786 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3787 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3789 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3792 /* IOCB Command template for all FCP Target commands */
3794 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3795 uint32_t fcpt_Offset;
3796 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3799 /* SLI-2 IOCB structure definitions */
3801 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3804 uint32_t xrsqRo; /* Starting Relative Offset */
3805 WORD5 w5; /* Header control/status word */
3808 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3809 #define xmit_els_remoteID xrsqRo
3811 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3813 struct ulp_bde64 rcvBde;
3815 uint32_t xrsqRo; /* Starting Relative Offset */
3816 WORD5 w5; /* Header control/status word */
3819 /* IOCB Command template for ELS_REQUEST64 */
3822 #ifdef __BIG_ENDIAN_BITFIELD
3823 uint32_t word4Rsvd:7;
3826 uint32_t word5Rsvd:8;
3827 uint32_t remoteID:24;
3828 #else /* __LITTLE_ENDIAN_BITFIELD */
3831 uint32_t word4Rsvd:7;
3832 uint32_t remoteID:24;
3833 uint32_t word5Rsvd:8;
3837 /* IOCB Command template for GEN_REQUEST64 */
3840 uint32_t xrsqRo; /* Starting Relative Offset */
3841 WORD5 w5; /* Header control/status word */
3844 /* IOCB Command template for RCV_ELS_REQ64 */
3846 struct ulp_bde64 elsReq;
3850 #ifdef __BIG_ENDIAN_BITFIELD
3851 uint32_t word5Rsvd:8;
3852 uint32_t remoteID:24;
3853 #else /* __LITTLE_ENDIAN_BITFIELD */
3854 uint32_t remoteID:24;
3855 uint32_t word5Rsvd:8;
3859 /* IOCB Command template for RCV_SEQ64 */
3861 struct ulp_bde64 elsReq;
3864 #ifdef __BIG_ENDIAN_BITFIELD
3874 #else /* __LITTLE_ENDIAN_BITFIELD */
3887 /* IOCB Command template for all 64 bit FCP Initiator commands */
3891 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3894 /* IOCB Command template for all 64 bit FCP Target commands */
3897 uint32_t fcpt_Offset;
3898 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3901 /* IOCB Command template for Async Status iocb commands */
3905 #ifdef __BIG_ENDIAN_BITFIELD
3906 uint16_t evt_code; /* High order bits word 5 */
3907 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3908 #else /* __LITTLE_ENDIAN_BITFIELD */
3909 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3910 uint16_t evt_code; /* Low order bits word 5 */
3913 #define ASYNC_TEMP_WARN 0x100
3914 #define ASYNC_TEMP_SAFE 0x101
3915 #define ASYNC_STATUS_CN 0x102
3917 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3918 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3921 #ifdef __BIG_ENDIAN_BITFIELD
3927 #else /* __LITTLE_ENDIAN */
3934 uint32_t word10Rsvd;
3935 uint32_t acc_len; /* accumulated length */
3936 struct ulp_bde64 bde2;
3939 /* Structure used for a single HBQ entry */
3940 struct lpfc_hbq_entry {
3941 struct ulp_bde64 bde;
3942 uint32_t buffer_tag;
3945 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3947 struct lpfc_hbq_entry buff;
3950 } QUE_XRI64_CX_FIELDS;
3952 struct que_xri64cx_ext_fields {
3953 uint32_t iotag64_low;
3954 uint32_t iotag64_high;
3955 uint32_t ebde_count;
3957 struct lpfc_hbq_entry buff[5];
3960 struct sli3_bg_fields {
3961 uint32_t filler[6]; /* word 8-13 in IOCB */
3962 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3963 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3964 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3965 #define BGS_BIDIR_BG_PROF_SHIFT 24
3966 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3967 #define BGS_BIDIR_ERR_COND_SHIFT 16
3968 #define BGS_BG_PROFILE_MASK 0x0000ff00
3969 #define BGS_BG_PROFILE_SHIFT 8
3970 #define BGS_INVALID_PROF_MASK 0x00000020
3971 #define BGS_INVALID_PROF_SHIFT 5
3972 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3973 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3974 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3975 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3976 #define BGS_REFTAG_ERR_MASK 0x00000004
3977 #define BGS_REFTAG_ERR_SHIFT 2
3978 #define BGS_APPTAG_ERR_MASK 0x00000002
3979 #define BGS_APPTAG_ERR_SHIFT 1
3980 #define BGS_GUARD_ERR_MASK 0x00000001
3981 #define BGS_GUARD_ERR_SHIFT 0
3982 uint32_t bgstat; /* word 15 - BlockGuard Status */
3985 static inline uint32_t
3986 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3988 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3989 BGS_BIDIR_BG_PROF_SHIFT;
3992 static inline uint32_t
3993 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3995 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3996 BGS_BIDIR_ERR_COND_SHIFT;
3999 static inline uint32_t
4000 lpfc_bgs_get_bg_prof(uint32_t bgstat)
4002 return (bgstat & BGS_BG_PROFILE_MASK) >>
4003 BGS_BG_PROFILE_SHIFT;
4006 static inline uint32_t
4007 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4009 return (bgstat & BGS_INVALID_PROF_MASK) >>
4010 BGS_INVALID_PROF_SHIFT;
4013 static inline uint32_t
4014 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4016 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4017 BGS_UNINIT_DIF_BLOCK_SHIFT;
4020 static inline uint32_t
4021 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4023 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4024 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4027 static inline uint32_t
4028 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4030 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4031 BGS_REFTAG_ERR_SHIFT;
4034 static inline uint32_t
4035 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4037 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4038 BGS_APPTAG_ERR_SHIFT;
4041 static inline uint32_t
4042 lpfc_bgs_get_guard_err(uint32_t bgstat)
4044 return (bgstat & BGS_GUARD_ERR_MASK) >>
4045 BGS_GUARD_ERR_SHIFT;
4048 #define LPFC_EXT_DATA_BDE_COUNT 3
4049 struct fcp_irw_ext {
4050 uint32_t io_tag64_low;
4051 uint32_t io_tag64_high;
4052 #ifdef __BIG_ENDIAN_BITFIELD
4057 #else /* __LITTLE_ENDIAN */
4064 struct ulp_bde64 rbde; /* response bde */
4065 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4066 uint8_t icd[32]; /* immediate command data (32 bytes) */
4069 typedef struct _IOCB { /* IOCB structure */
4071 GENERIC_RSP grsp; /* Generic response */
4072 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4073 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4074 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4075 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4076 A_MXRI64 amxri; /* abort multiple xri command overlay */
4077 GET_RPI getrpi; /* GET_RPI template */
4078 FCPI_FIELDS fcpi; /* FCP Initiator template */
4079 FCPT_FIELDS fcpt; /* FCP target template */
4081 /* SLI-2 structures */
4083 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4085 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4086 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4087 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4088 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4089 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4090 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4091 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4092 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4093 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4094 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4095 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4099 #ifdef __BIG_ENDIAN_BITFIELD
4100 uint16_t ulpContext; /* High order bits word 6 */
4101 uint16_t ulpIoTag; /* Low order bits word 6 */
4102 #else /* __LITTLE_ENDIAN_BITFIELD */
4103 uint16_t ulpIoTag; /* Low order bits word 6 */
4104 uint16_t ulpContext; /* High order bits word 6 */
4108 #ifdef __BIG_ENDIAN_BITFIELD
4109 uint16_t ulpContext; /* High order bits word 6 */
4110 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4111 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4112 #else /* __LITTLE_ENDIAN_BITFIELD */
4113 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4114 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4115 uint16_t ulpContext; /* High order bits word 6 */
4119 #define ulpContext un1.t1.ulpContext
4120 #define ulpIoTag un1.t1.ulpIoTag
4121 #define ulpIoTag0 un1.t2.ulpIoTag0
4123 #ifdef __BIG_ENDIAN_BITFIELD
4124 uint32_t ulpTimeout:8;
4126 uint32_t ulpFCP2Rcvy:1;
4129 uint32_t ulpClass:3;
4130 uint32_t ulpCommand:8;
4131 uint32_t ulpStatus:4;
4132 uint32_t ulpBdeCount:2;
4134 uint32_t ulpOwner:1; /* Low order bit word 7 */
4135 #else /* __LITTLE_ENDIAN_BITFIELD */
4136 uint32_t ulpOwner:1; /* Low order bit word 7 */
4138 uint32_t ulpBdeCount:2;
4139 uint32_t ulpStatus:4;
4140 uint32_t ulpCommand:8;
4141 uint32_t ulpClass:3;
4144 uint32_t ulpFCP2Rcvy:1;
4146 uint32_t ulpTimeout:8;
4150 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4152 /* words 8-31 used for que_xri_cx iocb */
4153 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4154 struct fcp_irw_ext fcp_ext;
4155 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4157 /* words 8-15 for BlockGuard */
4158 struct sli3_bg_fields sli3_bg;
4161 #define ulpCt_h ulpXS
4162 #define ulpCt_l ulpFCP2Rcvy
4164 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4165 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4166 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4167 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4168 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4169 #define PARM_NPIV_DID 3
4170 #define CLASS1 0 /* Class 1 */
4171 #define CLASS2 1 /* Class 2 */
4172 #define CLASS3 2 /* Class 3 */
4173 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4175 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4176 #define IOSTAT_FCP_RSP_ERROR 0x1
4177 #define IOSTAT_REMOTE_STOP 0x2
4178 #define IOSTAT_LOCAL_REJECT 0x3
4179 #define IOSTAT_NPORT_RJT 0x4
4180 #define IOSTAT_FABRIC_RJT 0x5
4181 #define IOSTAT_NPORT_BSY 0x6
4182 #define IOSTAT_FABRIC_BSY 0x7
4183 #define IOSTAT_INTERMED_RSP 0x8
4184 #define IOSTAT_LS_RJT 0x9
4185 #define IOSTAT_BA_RJT 0xA
4186 #define IOSTAT_RSVD1 0xB
4187 #define IOSTAT_RSVD2 0xC
4188 #define IOSTAT_RSVD3 0xD
4189 #define IOSTAT_RSVD4 0xE
4190 #define IOSTAT_NEED_BUFFER 0xF
4191 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4192 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4193 #define IOSTAT_CNT 0x11
4198 #define SLI1_SLIM_SIZE (4 * 1024)
4200 /* Up to 498 IOCBs will fit into 16k
4201 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4203 #define SLI2_SLIM_SIZE (64 * 1024)
4205 /* Maximum IOCBs that will fit in SLI2 slim */
4206 #define MAX_SLI2_IOCB 498
4207 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4208 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4209 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4211 /* HBQ entries are 4 words each = 4k */
4212 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4213 lpfc_sli_hbq_count())
4215 struct lpfc_sli2_slim {
4217 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4219 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4223 * This function checks PCI device to allow special handling for LC HBAs.
4226 * device : struct pci_dev 's device field
4232 lpfc_is_LC_HBA(unsigned short device)
4234 if ((device == PCI_DEVICE_ID_TFLY) ||
4235 (device == PCI_DEVICE_ID_PFLY) ||
4236 (device == PCI_DEVICE_ID_LP101) ||
4237 (device == PCI_DEVICE_ID_BMID) ||
4238 (device == PCI_DEVICE_ID_BSMB) ||
4239 (device == PCI_DEVICE_ID_ZMID) ||
4240 (device == PCI_DEVICE_ID_ZSMB) ||
4241 (device == PCI_DEVICE_ID_SAT_MID) ||
4242 (device == PCI_DEVICE_ID_SAT_SMB) ||
4243 (device == PCI_DEVICE_ID_RFLY))
4250 * Determine if an IOCB failed because of a link event or firmware reset.
4254 lpfc_error_lost_link(IOCB_t *iocbp)
4256 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4257 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4258 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4259 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4262 #define MENLO_TRANSPORT_TYPE 0xfe
4263 #define MENLO_CONTEXT 0
4265 #define MENLO_TIMEOUT 30
4266 #define SETVAR_MLOMNT 0x103107
4267 #define SETVAR_MLORST 0x103007
4269 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */