GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / scsi / hpsa_cmd.h
1 /*
2  *    Disk Array driver for HP Smart Array SAS controllers
3  *    Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
4  *    Copyright 2016 Microsemi Corporation
5  *    Copyright 2014-2015 PMC-Sierra, Inc.
6  *    Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
7  *
8  *    This program is free software; you can redistribute it and/or modify
9  *    it under the terms of the GNU General Public License as published by
10  *    the Free Software Foundation; version 2 of the License.
11  *
12  *    This program is distributed in the hope that it will be useful,
13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
15  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
16  *
17  *    Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
18  *
19  */
20 #ifndef HPSA_CMD_H
21 #define HPSA_CMD_H
22
23 /* general boundary defintions */
24 #define SENSEINFOBYTES          32 /* may vary between hbas */
25 #define SG_ENTRIES_IN_CMD       32 /* Max SG entries excluding chain blocks */
26 #define HPSA_SG_CHAIN           0x80000000
27 #define HPSA_SG_LAST            0x40000000
28 #define MAXREPLYQS              256
29
30 /* Command Status value */
31 #define CMD_SUCCESS             0x0000
32 #define CMD_TARGET_STATUS       0x0001
33 #define CMD_DATA_UNDERRUN       0x0002
34 #define CMD_DATA_OVERRUN        0x0003
35 #define CMD_INVALID             0x0004
36 #define CMD_PROTOCOL_ERR        0x0005
37 #define CMD_HARDWARE_ERR        0x0006
38 #define CMD_CONNECTION_LOST     0x0007
39 #define CMD_ABORTED             0x0008
40 #define CMD_ABORT_FAILED        0x0009
41 #define CMD_UNSOLICITED_ABORT   0x000A
42 #define CMD_TIMEOUT             0x000B
43 #define CMD_UNABORTABLE         0x000C
44 #define CMD_TMF_STATUS          0x000D
45 #define CMD_IOACCEL_DISABLED    0x000E
46 #define CMD_CTLR_LOCKUP         0xffff
47 /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
48  * it is a value defined by the driver that commands can be marked
49  * with when a controller lockup has been detected by the driver
50  */
51
52 /* TMF function status values */
53 #define CISS_TMF_COMPLETE       0x00
54 #define CISS_TMF_INVALID_FRAME  0x02
55 #define CISS_TMF_NOT_SUPPORTED  0x04
56 #define CISS_TMF_FAILED         0x05
57 #define CISS_TMF_SUCCESS        0x08
58 #define CISS_TMF_WRONG_LUN      0x09
59 #define CISS_TMF_OVERLAPPED_TAG 0x0a
60
61 /* Unit Attentions ASC's as defined for the MSA2012sa */
62 #define POWER_OR_RESET                  0x29
63 #define STATE_CHANGED                   0x2a
64 #define UNIT_ATTENTION_CLEARED          0x2f
65 #define LUN_FAILED                      0x3e
66 #define REPORT_LUNS_CHANGED             0x3f
67
68 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
69
70         /* These ASCQ's defined for ASC = POWER_OR_RESET */
71 #define POWER_ON_RESET                  0x00
72 #define POWER_ON_REBOOT                 0x01
73 #define SCSI_BUS_RESET                  0x02
74 #define MSA_TARGET_RESET                0x03
75 #define CONTROLLER_FAILOVER             0x04
76 #define TRANSCEIVER_SE                  0x05
77 #define TRANSCEIVER_LVD                 0x06
78
79         /* These ASCQ's defined for ASC = STATE_CHANGED */
80 #define RESERVATION_PREEMPTED           0x03
81 #define ASYM_ACCESS_CHANGED             0x06
82 #define LUN_CAPACITY_CHANGED            0x09
83
84 /* transfer direction */
85 #define XFER_NONE               0x00
86 #define XFER_WRITE              0x01
87 #define XFER_READ               0x02
88 #define XFER_RSVD               0x03
89
90 /* task attribute */
91 #define ATTR_UNTAGGED           0x00
92 #define ATTR_SIMPLE             0x04
93 #define ATTR_HEADOFQUEUE        0x05
94 #define ATTR_ORDERED            0x06
95 #define ATTR_ACA                0x07
96
97 /* cdb type */
98 #define TYPE_CMD                0x00
99 #define TYPE_MSG                0x01
100 #define TYPE_IOACCEL2_CMD       0x81 /* 0x81 is not used by hardware */
101
102 /* Message Types  */
103 #define HPSA_TASK_MANAGEMENT    0x00
104 #define HPSA_RESET              0x01
105 #define HPSA_SCAN               0x02
106 #define HPSA_NOOP               0x03
107
108 #define HPSA_CTLR_RESET_TYPE    0x00
109 #define HPSA_BUS_RESET_TYPE     0x01
110 #define HPSA_TARGET_RESET_TYPE  0x03
111 #define HPSA_LUN_RESET_TYPE     0x04
112 #define HPSA_NEXUS_RESET_TYPE   0x05
113
114 /* Task Management Functions */
115 #define HPSA_TMF_ABORT_TASK     0x00
116 #define HPSA_TMF_ABORT_TASK_SET 0x01
117 #define HPSA_TMF_CLEAR_ACA      0x02
118 #define HPSA_TMF_CLEAR_TASK_SET 0x03
119 #define HPSA_TMF_QUERY_TASK     0x04
120 #define HPSA_TMF_QUERY_TASK_SET 0x05
121 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
122
123
124
125 /* config space register offsets */
126 #define CFG_VENDORID            0x00
127 #define CFG_DEVICEID            0x02
128 #define CFG_I2OBAR              0x10
129 #define CFG_MEM1BAR             0x14
130
131 /* i2o space register offsets */
132 #define I2O_IBDB_SET            0x20
133 #define I2O_IBDB_CLEAR          0x70
134 #define I2O_INT_STATUS          0x30
135 #define I2O_INT_MASK            0x34
136 #define I2O_IBPOST_Q            0x40
137 #define I2O_OBPOST_Q            0x44
138 #define I2O_DMA1_CFG            0x214
139
140 /* Configuration Table */
141 #define CFGTBL_ChangeReq        0x00000001l
142 #define CFGTBL_AccCmds          0x00000001l
143 #define DOORBELL_CTLR_RESET     0x00000004l
144 #define DOORBELL_CTLR_RESET2    0x00000020l
145 #define DOORBELL_CLEAR_EVENTS   0x00000040l
146 #define DOORBELL_GENERATE_CHKPT 0x00000080l
147
148 #define CFGTBL_Trans_Simple     0x00000002l
149 #define CFGTBL_Trans_Performant 0x00000004l
150 #define CFGTBL_Trans_io_accel1  0x00000080l
151 #define CFGTBL_Trans_io_accel2  0x00000100l
152 #define CFGTBL_Trans_use_short_tags 0x20000000l
153 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
154
155 #define CFGTBL_BusType_Ultra2   0x00000001l
156 #define CFGTBL_BusType_Ultra3   0x00000002l
157 #define CFGTBL_BusType_Fibre1G  0x00000100l
158 #define CFGTBL_BusType_Fibre2G  0x00000200l
159
160 /* VPD Inquiry types */
161 #define HPSA_INQUIRY_FAILED             0x02
162 #define HPSA_VPD_SUPPORTED_PAGES        0x00
163 #define HPSA_VPD_LV_DEVICE_ID           0x83
164 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
165 #define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
166 #define HPSA_VPD_LV_STATUS              0xC3
167 #define HPSA_VPD_HEADER_SZ              4
168
169 /* Logical volume states */
170 #define HPSA_VPD_LV_STATUS_UNSUPPORTED                  0xff
171 #define HPSA_LV_OK                                      0x0
172 #define HPSA_LV_FAILED                                  0x01
173 #define HPSA_LV_NOT_AVAILABLE                           0x0b
174 #define HPSA_LV_UNDERGOING_ERASE                        0x0F
175 #define HPSA_LV_UNDERGOING_RPI                          0x12
176 #define HPSA_LV_PENDING_RPI                             0x13
177 #define HPSA_LV_ENCRYPTED_NO_KEY                        0x14
178 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER    0x15
179 #define HPSA_LV_UNDERGOING_ENCRYPTION                   0x16
180 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING          0x17
181 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER   0x18
182 #define HPSA_LV_PENDING_ENCRYPTION                      0x19
183 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING             0x1A
184
185 struct vals32 {
186         u32   lower;
187         u32   upper;
188 };
189
190 union u64bit {
191         struct vals32 val32;
192         u64 val;
193 };
194
195 /* FIXME this is a per controller value (barf!) */
196 #define HPSA_MAX_LUN 1024
197 #define HPSA_MAX_PHYS_LUN 1024
198 #define MAX_EXT_TARGETS 32
199 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
200         MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
201
202 /* SCSI-3 Commands */
203 #pragma pack(1)
204
205 #define HPSA_INQUIRY 0x12
206 struct InquiryData {
207         u8 data_byte[36];
208 };
209
210 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
211 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
212 #define HPSA_REPORT_PHYS_EXTENDED 0x02
213 #define HPSA_CISS_READ  0xc0    /* CISS Read */
214 #define HPSA_GET_RAID_MAP 0xc8  /* CISS Get RAID Layout Map */
215
216 #define RAID_MAP_MAX_ENTRIES   256
217
218 struct raid_map_disk_data {
219         u32   ioaccel_handle;         /**< Handle to access this disk via the
220                                         *  I/O accelerator */
221         u8    xor_mult[2];            /**< XOR multipliers for this position,
222                                         *  valid for data disks only */
223         u8    reserved[2];
224 };
225
226 struct raid_map_data {
227         __le32   structure_size;        /* Size of entire structure in bytes */
228         __le32   volume_blk_size;       /* bytes / block in the volume */
229         __le64   volume_blk_cnt;        /* logical blocks on the volume */
230         u8    phys_blk_shift;           /* Shift factor to convert between
231                                          * units of logical blocks and physical
232                                          * disk blocks */
233         u8    parity_rotation_shift;    /* Shift factor to convert between units
234                                          * of logical stripes and physical
235                                          * stripes */
236         __le16   strip_size;            /* blocks used on each disk / stripe */
237         __le64   disk_starting_blk;     /* First disk block used in volume */
238         __le64   disk_blk_cnt;          /* disk blocks used by volume / disk */
239         __le16   data_disks_per_row;    /* data disk entries / row in the map */
240         __le16   metadata_disks_per_row;/* mirror/parity disk entries / row
241                                          * in the map */
242         __le16   row_cnt;               /* rows in each layout map */
243         __le16   layout_map_count;      /* layout maps (1 map per mirror/parity
244                                          * group) */
245         __le16   flags;                 /* Bit 0 set if encryption enabled */
246 #define RAID_MAP_FLAG_ENCRYPT_ON  0x01
247         __le16   dekindex;              /* Data encryption key index. */
248         u8    reserved[16];
249         struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
250 };
251
252 struct ReportLUNdata {
253         u8 LUNListLength[4];
254         u8 extended_response_flag;
255         u8 reserved[3];
256         u8 LUN[HPSA_MAX_LUN][8];
257 };
258
259 struct ext_report_lun_entry {
260         u8 lunid[8];
261 #define MASKED_DEVICE(x) ((x)[3] & 0xC0)
262 #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
263 #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
264 #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
265                         GET_BMIC_LEVEL_TWO_TARGET((lunid)))
266         u8 wwid[8];
267         u8 device_type;
268         u8 device_flags;
269         u8 lun_count; /* multi-lun device, how many luns */
270         u8 redundant_paths;
271         u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
272 };
273
274 struct ReportExtendedLUNdata {
275         u8 LUNListLength[4];
276         u8 extended_response_flag;
277         u8 reserved[3];
278         struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
279 };
280
281 struct SenseSubsystem_info {
282         u8 reserved[36];
283         u8 portname[8];
284         u8 reserved1[1108];
285 };
286
287 /* BMIC commands */
288 #define BMIC_READ 0x26
289 #define BMIC_WRITE 0x27
290 #define BMIC_CACHE_FLUSH 0xc2
291 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
292 #define BMIC_FLASH_FIRMWARE 0xF7
293 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
294 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
295 #define BMIC_IDENTIFY_CONTROLLER 0x11
296 #define BMIC_SET_DIAG_OPTIONS 0xF4
297 #define BMIC_SENSE_DIAG_OPTIONS 0xF5
298 #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000
299 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
300 #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65
301
302 /* Command List Structure */
303 union SCSI3Addr {
304         struct {
305                 u8 Dev;
306                 u8 Bus:6;
307                 u8 Mode:2;        /* b00 */
308         } PeripDev;
309         struct {
310                 u8 DevLSB;
311                 u8 DevMSB:6;
312                 u8 Mode:2;        /* b01 */
313         } LogDev;
314         struct {
315                 u8 Dev:5;
316                 u8 Bus:3;
317                 u8 Targ:6;
318                 u8 Mode:2;        /* b10 */
319         } LogUnit;
320 };
321
322 struct PhysDevAddr {
323         u32             TargetId:24;
324         u32             Bus:6;
325         u32             Mode:2;
326         /* 2 level target device addr */
327         union SCSI3Addr  Target[2];
328 };
329
330 struct LogDevAddr {
331         u32            VolId:30;
332         u32            Mode:2;
333         u8             reserved[4];
334 };
335
336 union LUNAddr {
337         u8               LunAddrBytes[8];
338         union SCSI3Addr    SCSI3Lun[4];
339         struct PhysDevAddr PhysDev;
340         struct LogDevAddr  LogDev;
341 };
342
343 struct CommandListHeader {
344         u8              ReplyQueue;
345         u8              SGList;
346         __le16          SGTotal;
347         __le64          tag;
348         union LUNAddr     LUN;
349 };
350
351 struct RequestBlock {
352         u8   CDBLen;
353         /*
354          * type_attr_dir:
355          * type: low 3 bits
356          * attr: middle 3 bits
357          * dir: high 2 bits
358          */
359         u8      type_attr_dir;
360 #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
361                                 (((a) & 0x07) << 3) |\
362                                 ((t) & 0x07))
363 #define GET_TYPE(tad) ((tad) & 0x07)
364 #define GET_ATTR(tad) (((tad) >> 3) & 0x07)
365 #define GET_DIR(tad) (((tad) >> 6) & 0x03)
366         u16  Timeout;
367         u8   CDB[16];
368 };
369
370 struct ErrDescriptor {
371         __le64 Addr;
372         __le32 Len;
373 };
374
375 struct SGDescriptor {
376         __le64 Addr;
377         __le32 Len;
378         __le32 Ext;
379 };
380
381 union MoreErrInfo {
382         struct {
383                 u8  Reserved[3];
384                 u8  Type;
385                 u32 ErrorInfo;
386         } Common_Info;
387         struct {
388                 u8  Reserved[2];
389                 u8  offense_size; /* size of offending entry */
390                 u8  offense_num;  /* byte # of offense 0-base */
391                 u32 offense_value;
392         } Invalid_Cmd;
393 };
394 struct ErrorInfo {
395         u8               ScsiStatus;
396         u8               SenseLen;
397         u16              CommandStatus;
398         u32              ResidualCnt;
399         union MoreErrInfo  MoreErrInfo;
400         u8               SenseInfo[SENSEINFOBYTES];
401 };
402 /* Command types */
403 #define CMD_IOCTL_PEND  0x01
404 #define CMD_SCSI        0x03
405 #define CMD_IOACCEL1    0x04
406 #define CMD_IOACCEL2    0x05
407 #define IOACCEL2_TMF    0x06
408
409 #define DIRECT_LOOKUP_SHIFT 4
410 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
411
412 #define HPSA_ERROR_BIT          0x02
413 struct ctlr_info; /* defined in hpsa.h */
414 /* The size of this structure needs to be divisible by 128
415  * on all architectures.  The low 4 bits of the addresses
416  * are used as follows:
417  *
418  * bit 0: to device, used to indicate "performant mode" command
419  *        from device, indidcates error status.
420  * bit 1-3: to device, indicates block fetch table entry for
421  *          reducing DMA in fetching commands from host memory.
422  */
423
424 #define COMMANDLIST_ALIGNMENT 128
425 struct CommandList {
426         struct CommandListHeader Header;
427         struct RequestBlock      Request;
428         struct ErrDescriptor     ErrDesc;
429         struct SGDescriptor      SG[SG_ENTRIES_IN_CMD];
430         /* information associated with the command */
431         u32                        busaddr; /* physical addr of this record */
432         struct ErrorInfo *err_info; /* pointer to the allocated mem */
433         struct ctlr_info           *h;
434         int                        cmd_type;
435         long                       cmdindex;
436         struct completion *waiting;
437         struct scsi_cmnd *scsi_cmd;
438         struct work_struct work;
439
440         /*
441          * For commands using either of the two "ioaccel" paths to
442          * bypass the RAID stack and go directly to the physical disk
443          * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
444          * i/o is destined.  We need to store that here because the command
445          * may potentially encounter TASK SET FULL and need to be resubmitted
446          * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
447          * not used.
448          */
449         struct hpsa_scsi_dev_t *phys_disk;
450
451         int abort_pending;
452         struct hpsa_scsi_dev_t *device;
453         atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
454 } __aligned(COMMANDLIST_ALIGNMENT);
455
456 /* Max S/G elements in I/O accelerator command */
457 #define IOACCEL1_MAXSGENTRIES           24
458 #define IOACCEL2_MAXSGENTRIES           28
459
460 /*
461  * Structure for I/O accelerator (mode 1) commands.
462  * Note that this structure must be 128-byte aligned in size.
463  */
464 #define IOACCEL1_COMMANDLIST_ALIGNMENT 128
465 struct io_accel1_cmd {
466         __le16 dev_handle;              /* 0x00 - 0x01 */
467         u8  reserved1;                  /* 0x02 */
468         u8  function;                   /* 0x03 */
469         u8  reserved2[8];               /* 0x04 - 0x0B */
470         u32 err_info;                   /* 0x0C - 0x0F */
471         u8  reserved3[2];               /* 0x10 - 0x11 */
472         u8  err_info_len;               /* 0x12 */
473         u8  reserved4;                  /* 0x13 */
474         u8  sgl_offset;                 /* 0x14 */
475         u8  reserved5[7];               /* 0x15 - 0x1B */
476         __le32 transfer_len;            /* 0x1C - 0x1F */
477         u8  reserved6[4];               /* 0x20 - 0x23 */
478         __le16 io_flags;                /* 0x24 - 0x25 */
479         u8  reserved7[14];              /* 0x26 - 0x33 */
480         u8  LUN[8];                     /* 0x34 - 0x3B */
481         __le32 control;                 /* 0x3C - 0x3F */
482         u8  CDB[16];                    /* 0x40 - 0x4F */
483         u8  reserved8[16];              /* 0x50 - 0x5F */
484         __le16 host_context_flags;      /* 0x60 - 0x61 */
485         __le16 timeout_sec;             /* 0x62 - 0x63 */
486         u8  ReplyQueue;                 /* 0x64 */
487         u8  reserved9[3];               /* 0x65 - 0x67 */
488         __le64 tag;                     /* 0x68 - 0x6F */
489         __le64 host_addr;               /* 0x70 - 0x77 */
490         u8  CISS_LUN[8];                /* 0x78 - 0x7F */
491         struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
492 } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
493
494 #define IOACCEL1_FUNCTION_SCSIIO        0x00
495 #define IOACCEL1_SGLOFFSET              32
496
497 #define IOACCEL1_IOFLAGS_IO_REQ         0x4000
498 #define IOACCEL1_IOFLAGS_CDBLEN_MASK    0x001F
499 #define IOACCEL1_IOFLAGS_CDBLEN_MAX     16
500
501 #define IOACCEL1_CONTROL_NODATAXFER     0x00000000
502 #define IOACCEL1_CONTROL_DATA_OUT       0x01000000
503 #define IOACCEL1_CONTROL_DATA_IN        0x02000000
504 #define IOACCEL1_CONTROL_TASKPRIO_MASK  0x00007800
505 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
506 #define IOACCEL1_CONTROL_SIMPLEQUEUE    0x00000000
507 #define IOACCEL1_CONTROL_HEADOFQUEUE    0x00000100
508 #define IOACCEL1_CONTROL_ORDEREDQUEUE   0x00000200
509 #define IOACCEL1_CONTROL_ACA            0x00000400
510
511 #define IOACCEL1_HCFLAGS_CISS_FORMAT    0x0013
512
513 #define IOACCEL1_BUSADDR_CMDTYPE        0x00000060
514
515 struct ioaccel2_sg_element {
516         __le64 address;
517         __le32 length;
518         u8 reserved[3];
519         u8 chain_indicator;
520 #define IOACCEL2_CHAIN 0x80
521 #define IOACCEL2_LAST_SG 0x40
522 };
523
524 /*
525  * SCSI Response Format structure for IO Accelerator Mode 2
526  */
527 struct io_accel2_scsi_response {
528         u8 IU_type;
529 #define IOACCEL2_IU_TYPE_SRF                    0x60
530         u8 reserved1[3];
531         u8 req_id[4];           /* request identifier */
532         u8 reserved2[4];
533         u8 serv_response;               /* service response */
534 #define IOACCEL2_SERV_RESPONSE_COMPLETE         0x000
535 #define IOACCEL2_SERV_RESPONSE_FAILURE          0x001
536 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE     0x002
537 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS      0x003
538 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED     0x004
539 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN    0x005
540         u8 status;                      /* status */
541 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD       0x00
542 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND   0x02
543 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY       0x08
544 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON    0x18
545 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL   0x28
546 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED    0x40
547 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED     0x0E
548 #define IOACCEL2_STATUS_SR_IO_ERROR             0x01
549 #define IOACCEL2_STATUS_SR_IO_ABORTED           0x02
550 #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE    0x03
551 #define IOACCEL2_STATUS_SR_INVALID_DEVICE       0x04
552 #define IOACCEL2_STATUS_SR_UNDERRUN             0x51
553 #define IOACCEL2_STATUS_SR_OVERRUN              0x75
554         u8 data_present;                /* low 2 bits */
555 #define IOACCEL2_NO_DATAPRESENT         0x000
556 #define IOACCEL2_RESPONSE_DATAPRESENT   0x001
557 #define IOACCEL2_SENSE_DATA_PRESENT     0x002
558 #define IOACCEL2_RESERVED               0x003
559         u8 sense_data_len;              /* sense/response data length */
560         u8 resid_cnt[4];                /* residual count */
561         u8 sense_data_buff[32];         /* sense/response data buffer */
562 };
563
564 /*
565  * Structure for I/O accelerator (mode 2 or m2) commands.
566  * Note that this structure must be 128-byte aligned in size.
567  */
568 #define IOACCEL2_COMMANDLIST_ALIGNMENT 128
569 struct io_accel2_cmd {
570         u8  IU_type;                    /* IU Type */
571         u8  direction;                  /* direction, memtype, and encryption */
572 #define IOACCEL2_DIRECTION_MASK         0x03 /* bits 0,1: direction  */
573 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
574                                              /*     0b=PCIe, 1b=DDR */
575 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
576                                              /*     0=off, 1=on */
577         u8  reply_queue;                /* Reply Queue ID */
578         u8  reserved1;                  /* Reserved */
579         __le32 scsi_nexus;              /* Device Handle */
580         __le32 Tag;                     /* cciss tag, lower 4 bytes only */
581         __le32 tweak_lower;             /* Encryption tweak, lower 4 bytes */
582         u8  cdb[16];                    /* SCSI Command Descriptor Block */
583         u8  cciss_lun[8];               /* 8 byte SCSI address */
584         __le32 data_len;                /* Total bytes to transfer */
585         u8  cmd_priority_task_attr;     /* priority and task attrs */
586 #define IOACCEL2_PRIORITY_MASK 0x78
587 #define IOACCEL2_ATTR_MASK 0x07
588         u8  sg_count;                   /* Number of sg elements */
589         __le16 dekindex;                /* Data encryption key index */
590         __le64 err_ptr;                 /* Error Pointer */
591         __le32 err_len;                 /* Error Length*/
592         __le32 tweak_upper;             /* Encryption tweak, upper 4 bytes */
593         struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
594         struct io_accel2_scsi_response error_data;
595 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
596
597 /*
598  * defines for Mode 2 command struct
599  * FIXME: this can't be all I need mfm
600  */
601 #define IOACCEL2_IU_TYPE        0x40
602 #define IOACCEL2_IU_TMF_TYPE    0x41
603 #define IOACCEL2_DIR_NO_DATA    0x00
604 #define IOACCEL2_DIR_DATA_IN    0x01
605 #define IOACCEL2_DIR_DATA_OUT   0x02
606 #define IOACCEL2_TMF_ABORT      0x01
607 /*
608  * SCSI Task Management Request format for Accelerator Mode 2
609  */
610 struct hpsa_tmf_struct {
611         u8 iu_type;             /* Information Unit Type */
612         u8 reply_queue;         /* Reply Queue ID */
613         u8 tmf;                 /* Task Management Function */
614         u8 reserved1;           /* byte 3 Reserved */
615         __le32 it_nexus;        /* SCSI I-T Nexus */
616         u8 lun_id[8];           /* LUN ID for TMF request */
617         __le64 tag;             /* cciss tag associated w/ request */
618         __le64 abort_tag;       /* cciss tag of SCSI cmd or TMF to abort */
619         __le64 error_ptr;               /* Error Pointer */
620         __le32 error_len;               /* Error Length */
621 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
622
623 /* Configuration Table Structure */
624 struct HostWrite {
625         __le32          TransportRequest;
626         __le32          command_pool_addr_hi;
627         __le32          CoalIntDelay;
628         __le32          CoalIntCount;
629 };
630
631 #define SIMPLE_MODE     0x02
632 #define PERFORMANT_MODE 0x04
633 #define MEMQ_MODE       0x08
634 #define IOACCEL_MODE_1  0x80
635
636 #define DRIVER_SUPPORT_UA_ENABLE        0x00000001
637
638 struct CfgTable {
639         u8              Signature[4];
640         __le32          SpecValence;
641         __le32          TransportSupport;
642         __le32          TransportActive;
643         struct HostWrite HostWrite;
644         __le32          CmdsOutMax;
645         __le32          BusTypes;
646         __le32          TransMethodOffset;
647         u8              ServerName[16];
648         __le32          HeartBeat;
649         __le32          driver_support;
650 #define                 ENABLE_SCSI_PREFETCH            0x100
651 #define                 ENABLE_UNIT_ATTN                0x01
652         __le32          MaxScatterGatherElements;
653         __le32          MaxLogicalUnits;
654         __le32          MaxPhysicalDevices;
655         __le32          MaxPhysicalDrivesPerLogicalUnit;
656         __le32          MaxPerformantModeCommands;
657         __le32          MaxBlockFetch;
658         __le32          PowerConservationSupport;
659         __le32          PowerConservationEnable;
660         __le32          TMFSupportFlags;
661         u8              TMFTagMask[8];
662         u8              reserved[0x78 - 0x70];
663         __le32          misc_fw_support;                /* offset 0x78 */
664 #define                 MISC_FW_DOORBELL_RESET          0x02
665 #define                 MISC_FW_DOORBELL_RESET2         0x010
666 #define                 MISC_FW_RAID_OFFLOAD_BASIC      0x020
667 #define                 MISC_FW_EVENT_NOTIFY            0x080
668         u8              driver_version[32];
669         __le32          max_cached_write_size;
670         u8              driver_scratchpad[16];
671         __le32          max_error_info_length;
672         __le32          io_accel_max_embedded_sg_count;
673         __le32          io_accel_request_size_offset;
674         __le32          event_notify;
675 #define         HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
676 #define         HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
677         __le32          clear_event_notify;
678 };
679
680 #define NUM_BLOCKFETCH_ENTRIES 8
681 struct TransTable_struct {
682         __le32          BlockFetch[NUM_BLOCKFETCH_ENTRIES];
683         __le32          RepQSize;
684         __le32          RepQCount;
685         __le32          RepQCtrAddrLow32;
686         __le32          RepQCtrAddrHigh32;
687 #define MAX_REPLY_QUEUES 64
688         struct vals32  RepQAddr[MAX_REPLY_QUEUES];
689 };
690
691 struct hpsa_pci_info {
692         unsigned char   bus;
693         unsigned char   dev_fn;
694         unsigned short  domain;
695         u32             board_id;
696 };
697
698 struct bmic_identify_controller {
699         u8      configured_logical_drive_count; /* offset 0 */
700         u8      pad1[153];
701         __le16  extended_logical_unit_count;    /* offset 154 */
702         u8      pad2[136];
703         u8      controller_mode;        /* offset 292 */
704         u8      pad3[32];
705 };
706
707
708 struct bmic_identify_physical_device {
709         u8    scsi_bus;          /* SCSI Bus number on controller */
710         u8    scsi_id;           /* SCSI ID on this bus */
711         __le16 block_size;           /* sector size in bytes */
712         __le32 total_blocks;         /* number for sectors on drive */
713         __le32 reserved_blocks;   /* controller reserved (RIS) */
714         u8    model[40];         /* Physical Drive Model */
715         u8    serial_number[40]; /* Drive Serial Number */
716         u8    firmware_revision[8]; /* drive firmware revision */
717         u8    scsi_inquiry_bits; /* inquiry byte 7 bits */
718         u8    compaq_drive_stamp; /* 0 means drive not stamped */
719         u8    last_failure_reason;
720 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG              0x01
721 #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS                     0x02
722 #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS                      0x03
723 #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND                    0x04
724 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED                       0x05
725 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP       0x06
726 #define BMIC_LAST_FAILURE_TIMEOUT                               0x07
727 #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED                      0x08
728 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1                        0x09
729 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2                        0x0a
730 #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE                   0x0b
731 #define BMIC_LAST_FAILURE_NOT_READY                             0x0c
732 #define BMIC_LAST_FAILURE_HARDWARE_ERROR                        0x0d
733 #define BMIC_LAST_FAILURE_ABORTED_COMMAND                       0x0e
734 #define BMIC_LAST_FAILURE_WRITE_PROTECTED                       0x0f
735 #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER            0x10
736 #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR                   0x11
737 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG                 0x12
738 #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED            0x13
739 #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG                   0x14
740 #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED             0x15
741 #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED                0x16
742 #define BMIC_LAST_FAILURE_INQUIRY_FAILED                        0x17
743 #define BMIC_LAST_FAILURE_NON_DISK_DEVICE                       0x18
744 #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED                  0x19
745 #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE                    0x1a
746 #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED         0x1b
747 #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED            0x1c
748 #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP               0x1d
749 #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED           0x1e
750 #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR                  0x1f
751 #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS                   0x20
752 #define BMIC_LAST_FAILURE_WRONG_REPLACE                         0x21
753 #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED                0x22
754 #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED                 0x23
755 #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE               0x24
756 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG            0x25
757 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG            0x26
758 #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED               0x27
759 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY                   0x28
760 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED                0x29
761 #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY                 0x2a
762 #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED                  0x2b
763
764 #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED                  0x37
765 #define BMIC_LAST_FAILURE_PHY_RESET_FAILED                      0x38
766 #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE           0x40
767 #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED                      0x41
768 #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT                0x42
769 #define BMIC_LAST_FAILURE_OFFLINE_ERASE                         0x80
770 #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL                     0x81
771 #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX                0x82
772 #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE                0x83
773
774         u8     flags;
775         u8     more_flags;
776         u8     scsi_lun;          /* SCSI LUN for phys drive */
777         u8     yet_more_flags;
778         u8     even_more_flags;
779         __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
780         u8     phys_connector[2];         /* connector number on controller */
781         u8     phys_box_on_bus;  /* phys enclosure this drive resides */
782         u8     phys_bay_in_box;  /* phys drv bay this drive resides */
783         __le32 rpm;              /* Drive rotational speed in rpm */
784         u8     device_type;       /* type of drive */
785 #define BMIC_DEVICE_TYPE_CONTROLLER     0x07
786
787         u8     sata_version;     /* only valid when drive_type is SATA */
788         __le64 big_total_block_count;
789         __le64 ris_starting_lba;
790         __le32 ris_size;
791         u8     wwid[20];
792         u8     controller_phy_map[32];
793         __le16 phy_count;
794         u8     phy_connected_dev_type[256];
795         u8     phy_to_drive_bay_num[256];
796         __le16 phy_to_attached_dev_index[256];
797         u8     box_index;
798         u8     reserved;
799         __le16 extra_physical_drive_flags;
800 #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
801         (idphydrv->extra_physical_drive_flags & (1 << 10))
802         u8     negotiated_link_rate[256];
803         u8     phy_to_phy_map[256];
804         u8     redundant_path_present_map;
805         u8     redundant_path_failure_map;
806         u8     active_path_number;
807         __le16 alternate_paths_phys_connector[8];
808         u8     alternate_paths_phys_box_on_port[8];
809         u8     multi_lun_device_lun_count;
810         u8     minimum_good_fw_revision[8];
811         u8     unique_inquiry_bytes[20];
812         u8     current_temperature_degreesC;
813         u8     temperature_threshold_degreesC;
814         u8     max_temperature_degreesC;
815         u8     logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
816         __le16 current_queue_depth_limit;
817         u8     reserved_switch_stuff[60];
818         __le16 power_on_hours; /* valid only if gas gauge supported */
819         __le16 percent_endurance_used; /* valid only if gas gauge supported. */
820 #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
821         ((idphydrv->percent_endurance_used & 0x80) || \
822          (idphydrv->percent_endurance_used > 10000))
823         u8     drive_authentication;
824 #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
825         (idphydrv->drive_authentication == 0x80)
826         u8     smart_carrier_authentication;
827 #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
828         (idphydrv->smart_carrier_authentication != 0x0)
829 #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
830         (idphydrv->smart_carrier_authentication == 0x01)
831         u8     smart_carrier_app_fw_version;
832         u8     smart_carrier_bootloader_fw_version;
833         u8     sanitize_support_flags;
834         u8     drive_key_flags;
835         u8     encryption_key_name[64];
836         __le32 misc_drive_flags;
837         __le16 dek_index;
838         __le16 hba_drive_encryption_flags;
839         __le16 max_overwrite_time;
840         __le16 max_block_erase_time;
841         __le16 max_crypto_erase_time;
842         u8     device_connector_info[5];
843         u8     connector_name[8][8];
844         u8     page_83_id[16];
845         u8     max_link_rate[256];
846         u8     neg_phys_link_rate[256];
847         u8     box_conn_name[8];
848 } __attribute((aligned(512)));
849
850 struct bmic_sense_subsystem_info {
851         u8      primary_slot_number;
852         u8      reserved[3];
853         u8      chasis_serial_number[32];
854         u8      primary_world_wide_id[8];
855         u8      primary_array_serial_number[32]; /* NULL terminated */
856         u8      primary_cache_serial_number[32]; /* NULL terminated */
857         u8      reserved_2[8];
858         u8      secondary_array_serial_number[32];
859         u8      secondary_cache_serial_number[32];
860         u8      pad[332];
861 };
862
863 struct bmic_sense_storage_box_params {
864         u8      reserved[36];
865         u8      inquiry_valid;
866         u8      reserved_1[68];
867         u8      phys_box_on_port;
868         u8      reserved_2[22];
869         u16     connection_info;
870         u8      reserver_3[84];
871         u8      phys_connector[2];
872         u8      reserved_4[296];
873 };
874
875 #pragma pack()
876 #endif /* HPSA_CMD_H */