2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2016 Microsemi Corporation
4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
22 #include <scsi/scsicam.h>
29 struct access_method {
30 void (*submit_command)(struct ctlr_info *h,
31 struct CommandList *c);
32 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
33 bool (*intr_pending)(struct ctlr_info *h);
34 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
37 /* for SAS hosts and SAS expanders */
38 struct hpsa_sas_node {
39 struct device *parent_dev;
40 struct list_head port_list_head;
43 struct hpsa_sas_port {
44 struct list_head port_list_entry;
46 struct sas_port *port;
48 struct list_head phy_list_head;
49 struct hpsa_sas_node *parent_node;
50 struct sas_rphy *rphy;
54 struct list_head phy_list_entry;
56 struct hpsa_sas_port *parent_port;
61 struct hpsa_scsi_dev_t {
63 int bus, target, lun; /* as presented to the OS */
64 unsigned char scsi3addr[8]; /* as presented to the HW */
65 u8 physical_device : 1;
67 u8 removed : 1; /* device is marked for death */
68 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
69 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
71 u64 eli; /* from report diags. */
72 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
73 unsigned char model[16]; /* bytes 16-31 of inquiry data */
74 unsigned char rev; /* byte 2 of inquiry data */
75 unsigned char raid_level; /* from inquiry page 0xC1 */
76 unsigned char volume_offline; /* discovered via TUR or VPD */
77 u16 queue_depth; /* max queue_depth for this device */
78 atomic_t reset_cmds_out; /* Count of commands to-be affected */
79 atomic_t ioaccel_cmds_out; /* Only used for physical devices
80 * counts commands sent to physical
81 * device via "ioaccel" path.
88 u16 phys_connector[8];
89 int offload_config; /* I/O accel RAID offload configured */
90 int offload_enabled; /* I/O accel RAID offload enabled */
91 int offload_to_be_enabled;
92 int hba_ioaccel_enabled;
93 int offload_to_mirror; /* Send next I/O accelerator RAID
94 * offload request to mirror drive
96 struct raid_map_data raid_map; /* I/O accelerator RAID map */
99 * Pointers from logical drive map indices to the phys drives that
100 * make those logical drives. Note, multiple logical drives may
101 * share physical drives. You can have for instance 5 physical
102 * drives with 3 logical drives each using those same 5 physical
103 * disks. We need these pointers for counting i/o's out to physical
104 * devices in order to honor physical device queue depth limits.
106 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
109 struct hpsa_sas_port *sas_port;
110 int external; /* 1-from external array 0-not <0-unknown */
113 struct reply_queue_buffer {
122 struct bmic_controller_parameters {
124 u8 enable_command_list_verification;
125 u8 backed_out_write_drives;
126 u16 stripes_for_parity;
127 u8 parity_distribution_mode_flags;
128 u16 max_driver_requests;
129 u16 elevator_trend_count;
131 u8 force_scan_complete;
132 u8 scsi_transfer_mode;
136 u8 host_sdb_asic_fix;
137 u8 pdpi_burst_from_host_disabled;
138 char software_name[64];
139 char hardware_name[32];
141 u8 snapshot_priority;
143 u8 post_prompt_timeout;
144 u8 automatic_drive_slamming;
147 u8 cache_nvram_flags;
148 u8 drive_config_flags;
150 u8 temp_warning_level;
151 u8 temp_shutdown_level;
152 u8 temp_condition_reset;
153 u8 max_coalesce_commands;
154 u32 max_coalesce_delay;
162 unsigned int *reply_map;
166 struct pci_dev *pdev;
171 int nr_cmds; /* Number of commands allowed on this controller */
172 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
173 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
174 struct CfgTable __iomem *cfgtable;
175 int interrupts_enabled;
177 atomic_t commands_outstanding;
178 # define PERF_MODE_INT 0
179 # define DOORBELL_INT 1
180 # define SIMPLE_MODE_INT 2
181 # define MEMQ_MODE_INT 3
182 unsigned int msix_vectors;
183 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
184 struct access_method access;
186 /* queue and queue Info */
191 u8 max_cmd_sg_entries;
193 struct SGDescriptor **cmd_sg_list;
194 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
196 /* pointers to command and error info pool */
197 struct CommandList *cmd_pool;
198 dma_addr_t cmd_pool_dhandle;
199 struct io_accel1_cmd *ioaccel_cmd_pool;
200 dma_addr_t ioaccel_cmd_pool_dhandle;
201 struct io_accel2_cmd *ioaccel2_cmd_pool;
202 dma_addr_t ioaccel2_cmd_pool_dhandle;
203 struct ErrorInfo *errinfo_pool;
204 dma_addr_t errinfo_pool_dhandle;
205 unsigned long *cmd_pool_bits;
208 spinlock_t scan_lock;
209 wait_queue_head_t scan_wait_queue;
211 struct Scsi_Host *scsi_host;
212 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
213 int ndevices; /* number of used elements in .dev[] array. */
214 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
216 * Performant mode tables.
220 struct TransTable_struct __iomem *transtable;
221 unsigned long transMethod;
223 /* cap concurrent passthrus at some reasonable maximum */
224 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
225 atomic_t passthru_cmds_avail;
228 * Performant mode completion buffers
230 size_t reply_queue_size;
231 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
233 u32 *blockFetchTable;
234 u32 *ioaccel1_blockFetchTable;
235 u32 *ioaccel2_blockFetchTable;
236 u32 __iomem *ioaccel2_bft2_regs;
237 unsigned char *hba_inquiry_data;
242 u64 last_intr_timestamp;
244 u64 last_heartbeat_timestamp;
245 u32 heartbeat_sample_interval;
246 atomic_t firmware_flash_in_progress;
247 u32 __percpu *lockup_detected;
248 struct delayed_work monitor_ctlr_work;
249 struct delayed_work rescan_ctlr_work;
250 struct delayed_work event_monitor_work;
251 int remove_in_progress;
252 /* Address of h->q[x] is passed to intr handler to know which queue */
253 u8 q[MAX_REPLY_QUEUES];
254 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
255 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
256 #define HPSATMF_BITS_SUPPORTED (1 << 0)
257 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
258 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
259 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
260 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
261 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
262 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
263 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
264 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
265 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
266 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
267 #define HPSATMF_MASK_SUPPORTED (1 << 16)
268 #define HPSATMF_LOG_LUN_RESET (1 << 17)
269 #define HPSATMF_LOG_NEX_RESET (1 << 18)
270 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
271 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
272 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
273 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
274 #define HPSATMF_LOG_QRY_TASK (1 << 23)
275 #define HPSATMF_LOG_QRY_TSET (1 << 24)
276 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
278 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
279 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
280 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
281 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
282 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
283 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
284 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
286 #define RESCAN_REQUIRED_EVENT_BITS \
287 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
288 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
289 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
290 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
291 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
292 spinlock_t offline_device_lock;
293 struct list_head offline_device_list;
294 int acciopath_status;
296 int raid_offload_debug;
297 int discovery_polling;
299 struct ReportLUNdata *lastlogicals;
300 int needs_abort_tags_swizzled;
301 struct workqueue_struct *resubmit_wq;
302 struct workqueue_struct *rescan_ctlr_wq;
303 struct workqueue_struct *monitor_ctlr_wq;
304 atomic_t abort_cmds_available;
305 wait_queue_head_t event_sync_wait_queue;
306 struct mutex reset_mutex;
307 u8 reset_in_progress;
308 struct hpsa_sas_node *sas_host;
309 spinlock_t reset_lock;
312 struct offline_device_entry {
313 unsigned char scsi3addr[8];
314 struct list_head offline_list;
317 #define HPSA_ABORT_MSG 0
318 #define HPSA_DEVICE_RESET_MSG 1
319 #define HPSA_RESET_TYPE_CONTROLLER 0x00
320 #define HPSA_RESET_TYPE_BUS 0x01
321 #define HPSA_RESET_TYPE_LUN 0x04
322 #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
323 #define HPSA_MSG_SEND_RETRY_LIMIT 10
324 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
326 /* Maximum time in seconds driver will wait for command completions
327 * when polling before giving up.
329 #define HPSA_MAX_POLL_TIME_SECS (20)
331 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
332 * how many times to retry TEST UNIT READY on a device
333 * while waiting for it to become ready before giving up.
334 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
335 * between sending TURs while waiting for a device
338 #define HPSA_TUR_RETRY_LIMIT (20)
339 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
341 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
342 * to become ready, in seconds, before giving up on it.
343 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
344 * between polling the board to see if it is ready, in
345 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
346 * HPSA_BOARD_READY_ITERATIONS are derived from those.
348 #define HPSA_BOARD_READY_WAIT_SECS (120)
349 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
350 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
351 #define HPSA_BOARD_READY_POLL_INTERVAL \
352 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
353 #define HPSA_BOARD_READY_ITERATIONS \
354 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
355 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
356 #define HPSA_BOARD_NOT_READY_ITERATIONS \
357 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
358 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
359 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
360 #define HPSA_POST_RESET_NOOP_RETRIES (12)
362 /* Defining the diffent access_menthods */
364 * Memory mapped FIFO interface (SMART 53xx cards)
366 #define SA5_DOORBELL 0x20
367 #define SA5_REQUEST_PORT_OFFSET 0x40
368 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
369 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
370 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
371 #define SA5_REPLY_PORT_OFFSET 0x44
372 #define SA5_INTR_STATUS 0x30
373 #define SA5_SCRATCHPAD_OFFSET 0xB0
375 #define SA5_CTCFG_OFFSET 0xB4
376 #define SA5_CTMEM_OFFSET 0xB8
378 #define SA5_INTR_OFF 0x08
379 #define SA5B_INTR_OFF 0x04
380 #define SA5_INTR_PENDING 0x08
381 #define SA5B_INTR_PENDING 0x04
382 #define FIFO_EMPTY 0xffffffff
383 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
385 #define HPSA_ERROR_BIT 0x02
387 /* Performant mode flags */
388 #define SA5_PERF_INTR_PENDING 0x04
389 #define SA5_PERF_INTR_OFF 0x05
390 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
391 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
392 #define SA5_OUTDB_CLEAR 0xA0
393 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
394 #define SA5_OUTDB_STATUS 0x9C
397 #define HPSA_INTR_ON 1
398 #define HPSA_INTR_OFF 0
401 * Inbound Post Queue offsets for IO Accelerator Mode 2
403 #define IOACCEL2_INBOUND_POSTQ_32 0x48
404 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
405 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
407 #define HPSA_PHYSICAL_DEVICE_BUS 0
408 #define HPSA_RAID_VOLUME_BUS 1
409 #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
410 #define HPSA_HBA_BUS 0
411 #define HPSA_LEGACY_HBA_BUS 3
414 Send the command to the hardware
416 static void SA5_submit_command(struct ctlr_info *h,
417 struct CommandList *c)
419 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
420 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
423 static void SA5_submit_command_no_read(struct ctlr_info *h,
424 struct CommandList *c)
426 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
429 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
430 struct CommandList *c)
432 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
436 * This card is the opposite of the other cards.
437 * 0 turns interrupts on...
438 * 0x08 turns them off...
440 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
442 if (val) { /* Turn interrupts on */
443 h->interrupts_enabled = 1;
444 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
445 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
446 } else { /* Turn them off */
447 h->interrupts_enabled = 0;
449 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
450 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
455 * Variant of the above; 0x04 turns interrupts off...
457 static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val)
459 if (val) { /* Turn interrupts on */
460 h->interrupts_enabled = 1;
461 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
462 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
463 } else { /* Turn them off */
464 h->interrupts_enabled = 0;
465 writel(SA5B_INTR_OFF,
466 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
467 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
471 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
473 if (val) { /* turn on interrupts */
474 h->interrupts_enabled = 1;
475 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
476 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
478 h->interrupts_enabled = 0;
479 writel(SA5_PERF_INTR_OFF,
480 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
481 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
485 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
487 struct reply_queue_buffer *rq = &h->reply_queue[q];
488 unsigned long register_value = FIFO_EMPTY;
490 /* msi auto clears the interrupt pending bit. */
491 if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) {
492 /* flush the controller write of the reply queue by reading
493 * outbound doorbell status register.
495 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
496 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
497 /* Do a read in order to flush the write to the controller
500 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
503 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
504 register_value = rq->head[rq->current_entry];
506 atomic_dec(&h->commands_outstanding);
508 register_value = FIFO_EMPTY;
510 /* Check for wraparound */
511 if (rq->current_entry == h->max_commands) {
512 rq->current_entry = 0;
515 return register_value;
519 * returns value read from hardware.
520 * returns FIFO_EMPTY if there is nothing to read
522 static unsigned long SA5_completed(struct ctlr_info *h,
523 __attribute__((unused)) u8 q)
525 unsigned long register_value
526 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
528 if (register_value != FIFO_EMPTY)
529 atomic_dec(&h->commands_outstanding);
532 if (register_value != FIFO_EMPTY)
533 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
536 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
539 return register_value;
542 * Returns true if an interrupt is pending..
544 static bool SA5_intr_pending(struct ctlr_info *h)
546 unsigned long register_value =
547 readl(h->vaddr + SA5_INTR_STATUS);
548 return register_value & SA5_INTR_PENDING;
551 static bool SA5_performant_intr_pending(struct ctlr_info *h)
553 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
558 /* Read outbound doorbell to flush */
559 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
560 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
563 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
565 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
567 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
569 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
574 * Returns true if an interrupt is pending..
576 static bool SA5B_intr_pending(struct ctlr_info *h)
578 return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING;
581 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
582 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
583 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
584 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
586 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
589 struct reply_queue_buffer *rq = &h->reply_queue[q];
591 BUG_ON(q >= h->nreply_queues);
593 register_value = rq->head[rq->current_entry];
594 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
595 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
596 if (++rq->current_entry == rq->size)
597 rq->current_entry = 0;
601 * Don't really need to write the new index after each command,
602 * but with current driver design this is easiest.
605 writel((q << 24) | rq->current_entry, h->vaddr +
606 IOACCEL_MODE1_CONSUMER_INDEX);
607 atomic_dec(&h->commands_outstanding);
609 return (unsigned long) register_value;
612 static struct access_method SA5_access = {
613 .submit_command = SA5_submit_command,
614 .set_intr_mask = SA5_intr_mask,
615 .intr_pending = SA5_intr_pending,
616 .command_completed = SA5_completed,
619 /* Duplicate entry of the above to mark unsupported boards */
620 static struct access_method SA5A_access = {
621 .submit_command = SA5_submit_command,
622 .set_intr_mask = SA5_intr_mask,
623 .intr_pending = SA5_intr_pending,
624 .command_completed = SA5_completed,
627 static struct access_method SA5B_access = {
628 .submit_command = SA5_submit_command,
629 .set_intr_mask = SA5B_intr_mask,
630 .intr_pending = SA5B_intr_pending,
631 .command_completed = SA5_completed,
634 static struct access_method SA5_ioaccel_mode1_access = {
635 .submit_command = SA5_submit_command,
636 .set_intr_mask = SA5_performant_intr_mask,
637 .intr_pending = SA5_ioaccel_mode1_intr_pending,
638 .command_completed = SA5_ioaccel_mode1_completed,
641 static struct access_method SA5_ioaccel_mode2_access = {
642 .submit_command = SA5_submit_command_ioaccel2,
643 .set_intr_mask = SA5_performant_intr_mask,
644 .intr_pending = SA5_performant_intr_pending,
645 .command_completed = SA5_performant_completed,
648 static struct access_method SA5_performant_access = {
649 .submit_command = SA5_submit_command,
650 .set_intr_mask = SA5_performant_intr_mask,
651 .intr_pending = SA5_performant_intr_pending,
652 .command_completed = SA5_performant_completed,
655 static struct access_method SA5_performant_access_no_read = {
656 .submit_command = SA5_submit_command_no_read,
657 .set_intr_mask = SA5_performant_intr_mask,
658 .intr_pending = SA5_performant_intr_pending,
659 .command_completed = SA5_performant_completed,
665 struct access_method *access;