1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2017 Hisilicon Limited.
7 #define DRV_NAME "hisi_sas_v3_hw"
9 /* global registers need init */
10 #define DLVRY_QUEUE_ENABLE 0x0
11 #define IOST_BASE_ADDR_LO 0x8
12 #define IOST_BASE_ADDR_HI 0xc
13 #define ITCT_BASE_ADDR_LO 0x10
14 #define ITCT_BASE_ADDR_HI 0x14
15 #define IO_BROKEN_MSG_ADDR_LO 0x18
16 #define IO_BROKEN_MSG_ADDR_HI 0x1c
17 #define PHY_CONTEXT 0x20
18 #define PHY_STATE 0x24
19 #define PHY_PORT_NUM_MA 0x28
20 #define PHY_CONN_RATE 0x30
22 #define ITCT_CLR_EN_OFF 16
23 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
24 #define ITCT_DEV_OFF 0
25 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
26 #define SAS_AXI_USER3 0x50
27 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
28 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
29 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
30 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
31 #define CFG_MAX_TAG 0x68
32 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
33 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
34 #define HGC_GET_ITV_TIME 0x90
35 #define DEVICE_MSG_WORK_MODE 0x94
36 #define OPENA_WT_CONTI_TIME 0x9c
37 #define I_T_NEXUS_LOSS_TIME 0xa0
38 #define MAX_CON_TIME_LIMIT_TIME 0xa4
39 #define BUS_INACTIVE_LIMIT_TIME 0xa8
40 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
41 #define CQ_INT_CONVERGE_EN 0xb0
42 #define CFG_AGING_TIME 0xbc
43 #define HGC_DFX_CFG2 0xc0
44 #define CFG_ABT_SET_QUERY_IPTT 0xd4
45 #define CFG_SET_ABORTED_IPTT_OFF 0
46 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
47 #define CFG_SET_ABORTED_EN_OFF 12
48 #define CFG_ABT_SET_IPTT_DONE 0xd8
49 #define CFG_ABT_SET_IPTT_DONE_OFF 0
50 #define HGC_IOMB_PROC1_STATUS 0x104
51 #define HGC_LM_DFX_STATUS2 0x128
52 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
53 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
54 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
55 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
56 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
57 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
58 #define HGC_CQE_ECC_ADDR 0x13c
59 #define HGC_CQE_ECC_1B_ADDR_OFF 0
60 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
61 #define HGC_CQE_ECC_MB_ADDR_OFF 8
62 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
63 #define HGC_IOST_ECC_ADDR 0x140
64 #define HGC_IOST_ECC_1B_ADDR_OFF 0
65 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
66 #define HGC_IOST_ECC_MB_ADDR_OFF 16
67 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
68 #define HGC_DQE_ECC_ADDR 0x144
69 #define HGC_DQE_ECC_1B_ADDR_OFF 0
70 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
71 #define HGC_DQE_ECC_MB_ADDR_OFF 16
72 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
73 #define CHNL_INT_STATUS 0x148
75 #define HGC_ITCT_ECC_ADDR 0x150
76 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
77 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
78 HGC_ITCT_ECC_1B_ADDR_OFF)
79 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
80 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
81 HGC_ITCT_ECC_MB_ADDR_OFF)
82 #define HGC_AXI_FIFO_ERR_INFO 0x154
83 #define AXI_ERR_INFO_OFF 0
84 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
85 #define FIFO_ERR_INFO_OFF 8
86 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
87 #define TAB_RD_TYPE 0x15c
88 #define INT_COAL_EN 0x19c
89 #define OQ_INT_COAL_TIME 0x1a0
90 #define OQ_INT_COAL_CNT 0x1a4
91 #define ENT_INT_COAL_TIME 0x1a8
92 #define ENT_INT_COAL_CNT 0x1ac
93 #define OQ_INT_SRC 0x1b0
94 #define OQ_INT_SRC_MSK 0x1b4
95 #define ENT_INT_SRC1 0x1b8
96 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
97 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
98 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
99 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
100 #define ENT_INT_SRC2 0x1bc
101 #define ENT_INT_SRC3 0x1c0
102 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
103 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
104 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
105 #define ENT_INT_SRC3_AXI_OFF 11
106 #define ENT_INT_SRC3_FIFO_OFF 12
107 #define ENT_INT_SRC3_LM_OFF 14
108 #define ENT_INT_SRC3_ITC_INT_OFF 15
109 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
110 #define ENT_INT_SRC3_ABT_OFF 16
111 #define ENT_INT_SRC3_DQE_POISON_OFF 18
112 #define ENT_INT_SRC3_IOST_POISON_OFF 19
113 #define ENT_INT_SRC3_ITCT_POISON_OFF 20
114 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
115 #define ENT_INT_SRC_MSK1 0x1c4
116 #define ENT_INT_SRC_MSK2 0x1c8
117 #define ENT_INT_SRC_MSK3 0x1cc
118 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
119 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
120 #define CHNL_ENT_INT_MSK 0x1d4
121 #define HGC_COM_INT_MSK 0x1d8
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
123 #define SAS_ECC_INTR 0x1e8
124 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
125 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
126 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
127 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
128 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
130 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
131 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
133 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
134 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
135 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
136 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
138 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
140 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
142 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
144 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
145 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
146 #define SAS_ECC_INTR_MSK 0x1ec
147 #define HGC_ERR_STAT_EN 0x238
148 #define CQE_SEND_CNT 0x248
149 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
150 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
151 #define DLVRY_Q_0_DEPTH 0x268
152 #define DLVRY_Q_0_WR_PTR 0x26c
153 #define DLVRY_Q_0_RD_PTR 0x270
154 #define HYPER_STREAM_ID_EN_CFG 0xc80
155 #define OQ0_INT_SRC_MSK 0xc90
156 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
157 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
158 #define COMPL_Q_0_DEPTH 0x4e8
159 #define COMPL_Q_0_WR_PTR 0x4ec
160 #define COMPL_Q_0_RD_PTR 0x4f0
161 #define HGC_RXM_DFX_STATUS14 0xae8
162 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
163 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
164 HGC_RXM_DFX_STATUS14_MEM0_OFF)
165 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
166 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
167 HGC_RXM_DFX_STATUS14_MEM1_OFF)
168 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
169 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
170 HGC_RXM_DFX_STATUS14_MEM2_OFF)
171 #define HGC_RXM_DFX_STATUS15 0xaec
172 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
173 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
174 HGC_RXM_DFX_STATUS15_MEM3_OFF)
175 #define AWQOS_AWCACHE_CFG 0xc84
176 #define ARQOS_ARCACHE_CFG 0xc88
177 #define HILINK_ERR_DFX 0xe04
178 #define SAS_GPIO_CFG_0 0x1000
179 #define SAS_GPIO_CFG_1 0x1004
180 #define SAS_GPIO_TX_0_1 0x1040
181 #define SAS_CFG_DRIVE_VLD 0x1070
183 /* phy registers requiring init */
184 #define PORT_BASE (0x2000)
185 #define PHY_CFG (PORT_BASE + 0x0)
186 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
187 #define PHY_CFG_ENA_OFF 0
188 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
189 #define PHY_CFG_DC_OPT_OFF 2
190 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
191 #define PHY_CFG_PHY_RST_OFF 3
192 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
193 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
194 #define CFG_PROG_PHY_LINK_RATE_OFF 0
195 #define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
196 #define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
197 #define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
198 #define PHY_CTRL (PORT_BASE + 0x14)
199 #define PHY_CTRL_RESET_OFF 0
200 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
201 #define CMD_HDR_PIR_OFF 8
202 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
203 #define SERDES_CFG (PORT_BASE + 0x1c)
204 #define CFG_ALOS_CHK_DISABLE_OFF 9
205 #define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
206 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
207 #define CFG_BIST_MODE_SEL_OFF 0
208 #define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
209 #define CFG_LOOP_TEST_MODE_OFF 14
210 #define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
211 #define CFG_RX_BIST_EN_OFF 16
212 #define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
213 #define CFG_TX_BIST_EN_OFF 17
214 #define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
215 #define CFG_BIST_TEST_OFF 18
216 #define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
217 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
218 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
219 #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
220 #define SL_CFG (PORT_BASE + 0x84)
221 #define AIP_LIMIT (PORT_BASE + 0x90)
222 #define SL_CONTROL (PORT_BASE + 0x94)
223 #define SL_CONTROL_NOTIFY_EN_OFF 0
224 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
225 #define SL_CTA_OFF 17
226 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
227 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
228 #define RX_BCAST_CHG_OFF 1
229 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
230 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
231 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
232 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
233 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
234 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
235 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
236 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
237 #define TXID_AUTO (PORT_BASE + 0xb8)
239 #define CT3_MSK (0x1 << CT3_OFF)
240 #define TX_HARDRST_OFF 2
241 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
242 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
243 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
244 #define STP_LINK_TIMER (PORT_BASE + 0x120)
245 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
246 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
247 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
248 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
249 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
250 #define CHL_INT0 (PORT_BASE + 0x1b4)
251 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
252 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
253 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
254 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
255 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
256 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
257 #define CHL_INT0_NOT_RDY_OFF 4
258 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
259 #define CHL_INT0_PHY_RDY_OFF 5
260 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
261 #define CHL_INT1 (PORT_BASE + 0x1b8)
262 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
263 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
264 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
265 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
266 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
267 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
268 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
269 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
270 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
271 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
272 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
273 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
274 #define CHL_INT2 (PORT_BASE + 0x1bc)
275 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
276 #define CHL_INT2_RX_DISP_ERR_OFF 28
277 #define CHL_INT2_RX_CODE_ERR_OFF 29
278 #define CHL_INT2_RX_INVLD_DW_OFF 30
279 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
280 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
281 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
282 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
283 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
284 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
285 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
286 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
287 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
288 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
289 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
290 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
291 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
292 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
293 #define DMA_TX_STATUS_BUSY_OFF 0
294 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
295 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
296 #define DMA_RX_STATUS_BUSY_OFF 0
297 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
299 #define COARSETUNE_TIME (PORT_BASE + 0x304)
300 #define TXDEEMPH_G1 (PORT_BASE + 0x350)
301 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
302 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
303 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
304 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
305 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
307 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
308 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
309 #error Max ITCT exceeded
312 #define AXI_MASTER_CFG_BASE (0x5000)
313 #define AM_CTRL_GLOBAL (0x0)
314 #define AM_CTRL_SHUTDOWN_REQ_OFF 0
315 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
316 #define AM_CURR_TRANS_RETURN (0x150)
318 #define AM_CFG_MAX_TRANS (0x5010)
319 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
320 #define AXI_CFG (0x5100)
321 #define AM_ROB_ECC_ERR_ADDR (0x510c)
322 #define AM_ROB_ECC_ERR_ADDR_OFF 0
323 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
325 /* RAS registers need init */
326 #define RAS_BASE (0x6000)
327 #define SAS_RAS_INTR0 (RAS_BASE)
328 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
329 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
330 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
331 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
332 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
333 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
335 /* HW dma structures */
336 /* Delivery queue header */
338 #define CMD_HDR_ABORT_FLAG_OFF 0
339 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
340 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
341 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
342 #define CMD_HDR_RESP_REPORT_OFF 5
343 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
344 #define CMD_HDR_TLR_CTRL_OFF 6
345 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
346 #define CMD_HDR_PORT_OFF 18
347 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
348 #define CMD_HDR_PRIORITY_OFF 27
349 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
350 #define CMD_HDR_CMD_OFF 29
351 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
353 #define CMD_HDR_UNCON_CMD_OFF 3
354 #define CMD_HDR_DIR_OFF 5
355 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
356 #define CMD_HDR_RESET_OFF 7
357 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
358 #define CMD_HDR_VDTL_OFF 10
359 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
360 #define CMD_HDR_FRAME_TYPE_OFF 11
361 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
362 #define CMD_HDR_DEV_ID_OFF 16
363 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
365 #define CMD_HDR_CFL_OFF 0
366 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
367 #define CMD_HDR_NCQ_TAG_OFF 10
368 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
369 #define CMD_HDR_MRFL_OFF 15
370 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
371 #define CMD_HDR_SG_MOD_OFF 24
372 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
374 #define CMD_HDR_IPTT_OFF 0
375 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
377 #define CMD_HDR_DIF_SGL_LEN_OFF 0
378 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
379 #define CMD_HDR_DATA_SGL_LEN_OFF 16
380 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
382 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
383 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
384 #define CMD_HDR_ABORT_IPTT_OFF 16
385 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
387 /* Completion header */
389 #define CMPLT_HDR_CMPLT_OFF 0
390 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
391 #define CMPLT_HDR_ERROR_PHASE_OFF 2
392 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
393 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
394 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
395 #define CMPLT_HDR_RSPNS_GOOD_OFF 11
396 #define CMPLT_HDR_RSPNS_GOOD_MSK (0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
397 #define CMPLT_HDR_ERX_OFF 12
398 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
399 #define CMPLT_HDR_ABORT_STAT_OFF 13
400 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
402 #define STAT_IO_NOT_VALID 0x1
403 #define STAT_IO_NO_DEVICE 0x2
404 #define STAT_IO_COMPLETE 0x3
405 #define STAT_IO_ABORTED 0x4
407 #define CMPLT_HDR_IPTT_OFF 0
408 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
409 #define CMPLT_HDR_DEV_ID_OFF 16
410 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
412 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
413 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
417 #define ITCT_HDR_DEV_TYPE_OFF 0
418 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
419 #define ITCT_HDR_VALID_OFF 2
420 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
421 #define ITCT_HDR_MCR_OFF 5
422 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
423 #define ITCT_HDR_VLN_OFF 9
424 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
425 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
426 #define ITCT_HDR_AWT_CONTINUE_OFF 25
427 #define ITCT_HDR_PORT_ID_OFF 28
428 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
430 #define ITCT_HDR_INLT_OFF 0
431 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
432 #define ITCT_HDR_RTOLT_OFF 48
433 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
435 struct hisi_sas_protect_iu_v3_hw {
445 struct hisi_sas_complete_v3_hdr {
452 struct hisi_sas_err_record_v3 {
454 __le32 trans_tx_fail_type;
457 __le32 trans_rx_fail_type;
460 __le16 dma_tx_err_type;
461 __le16 sipc_rx_err_type;
464 __le32 dma_rx_err_type;
467 #define RX_DATA_LEN_UNDERFLOW_OFF 6
468 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
470 #define RX_FIS_STATUS_ERR_OFF 0
471 #define RX_FIS_STATUS_ERR_MSK (1 << RX_FIS_STATUS_ERR_OFF)
473 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
474 #define HISI_SAS_MSI_COUNT_V3_HW 32
476 #define DIR_NO_DATA 0
478 #define DIR_TO_DEVICE 2
479 #define DIR_RESERVED 3
481 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
482 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
483 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
484 ((fis.command == ATA_CMD_DEV_RESET) && \
485 ((fis.control & ATA_SRST) != 0)))
487 #define T10_INSRT_EN_OFF 0
488 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
489 #define T10_RMV_EN_OFF 1
490 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
491 #define T10_RPLC_EN_OFF 2
492 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
493 #define T10_CHK_EN_OFF 3
494 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
495 #define INCR_LBRT_OFF 5
496 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
497 #define USR_DATA_BLOCK_SZ_OFF 20
498 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
499 #define T10_CHK_MSK_OFF 16
500 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
501 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
503 #define BASE_VECTORS_V3_HW 16
504 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
506 #define CHNL_INT_STS_MSK 0xeeeeeeee
507 #define CHNL_INT_STS_PHY_MSK 0xe
508 #define CHNL_INT_STS_INT0_MSK BIT(1)
509 #define CHNL_INT_STS_INT1_MSK BIT(2)
510 #define CHNL_INT_STS_INT2_MSK BIT(3)
514 DSM_FUNC_ERR_HANDLE_MSI = 0,
517 static bool hisi_sas_intr_conv;
518 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
520 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
521 static int prot_mask;
522 module_param(prot_mask, int, 0444);
523 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
525 static bool auto_affine_msi_experimental;
526 module_param(auto_affine_msi_experimental, bool, 0444);
527 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n"
530 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
532 void __iomem *regs = hisi_hba->regs + off;
537 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
539 void __iomem *regs = hisi_hba->regs + off;
544 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
547 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
552 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
555 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
560 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
563 void __iomem *regs = hisi_hba->regs + off; \
564 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
567 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
570 void __iomem *regs = hisi_hba->regs + off; \
571 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
574 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
578 /* Global registers init */
579 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
580 (u32)((1ULL << hisi_hba->queue_count) - 1));
581 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
582 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
583 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
584 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
585 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
586 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
587 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
588 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
590 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
591 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
592 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
593 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
594 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
595 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
596 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
597 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
598 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
599 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
600 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
601 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
602 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
603 for (i = 0; i < hisi_hba->queue_count; i++)
604 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
606 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
608 for (i = 0; i < hisi_hba->n_phy; i++) {
609 enum sas_linkrate max;
610 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
611 struct asd_sas_phy *sas_phy = &phy->sas_phy;
612 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
615 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
616 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
617 SAS_LINK_RATE_1_5_GBPS))
618 max = SAS_LINK_RATE_12_0_GBPS;
620 max = sas_phy->phy->maximum_linkrate;
621 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
622 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
624 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
625 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
626 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
627 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
628 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
629 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
630 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
631 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
632 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
633 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
634 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
635 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
636 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
637 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
638 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
639 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
640 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
641 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
643 /* used for 12G negotiate */
644 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
645 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
647 /* get default FFE configuration for BIST */
648 for (j = 0; j < FFE_CFG_MAX; j++) {
649 u32 val = hisi_sas_phy_read32(hisi_hba, i,
650 TXDEEMPH_G1 + (j * 0x4));
651 hisi_hba->debugfs_bist_ffe[i][j] = val;
655 for (i = 0; i < hisi_hba->queue_count; i++) {
657 hisi_sas_write32(hisi_hba,
658 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
659 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
661 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
662 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
664 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
665 HISI_SAS_QUEUE_SLOTS);
667 /* Completion queue */
668 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
669 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
671 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
672 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
674 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
675 HISI_SAS_QUEUE_SLOTS);
679 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
680 lower_32_bits(hisi_hba->itct_dma));
682 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
683 upper_32_bits(hisi_hba->itct_dma));
686 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
687 lower_32_bits(hisi_hba->iost_dma));
689 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
690 upper_32_bits(hisi_hba->iost_dma));
693 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
694 lower_32_bits(hisi_hba->breakpoint_dma));
696 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
697 upper_32_bits(hisi_hba->breakpoint_dma));
699 /* SATA broken msg */
700 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
701 lower_32_bits(hisi_hba->sata_breakpoint_dma));
703 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
704 upper_32_bits(hisi_hba->sata_breakpoint_dma));
706 /* SATA initial fis */
707 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
708 lower_32_bits(hisi_hba->initial_fis_dma));
710 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
711 upper_32_bits(hisi_hba->initial_fis_dma));
713 /* RAS registers init */
714 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
715 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
716 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
717 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
719 /* LED registers init */
720 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
721 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
722 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
723 /* Configure blink generator rate A to 1Hz and B to 4Hz */
724 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
725 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
728 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
730 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
732 cfg &= ~PHY_CFG_DC_OPT_MSK;
733 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
734 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
737 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
739 struct sas_identify_frame identify_frame;
740 u32 *identify_buffer;
742 memset(&identify_frame, 0, sizeof(identify_frame));
743 identify_frame.dev_type = SAS_END_DEVICE;
744 identify_frame.frame_type = 0;
745 identify_frame._un1 = 1;
746 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
747 identify_frame.target_bits = SAS_PROTOCOL_NONE;
748 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
749 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
750 identify_frame.phy_id = phy_no;
751 identify_buffer = (u32 *)(&identify_frame);
753 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
754 __swab32(identify_buffer[0]));
755 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
756 __swab32(identify_buffer[1]));
757 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
758 __swab32(identify_buffer[2]));
759 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
760 __swab32(identify_buffer[3]));
761 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
762 __swab32(identify_buffer[4]));
763 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
764 __swab32(identify_buffer[5]));
767 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
768 struct hisi_sas_device *sas_dev)
770 struct domain_device *device = sas_dev->sas_device;
771 struct device *dev = hisi_hba->dev;
772 u64 qw0, device_id = sas_dev->device_id;
773 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
774 struct domain_device *parent_dev = device->parent;
775 struct asd_sas_port *sas_port = device->port;
776 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
779 memset(itct, 0, sizeof(*itct));
783 switch (sas_dev->dev_type) {
785 case SAS_EDGE_EXPANDER_DEVICE:
786 case SAS_FANOUT_EXPANDER_DEVICE:
787 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
790 case SAS_SATA_PENDING:
791 if (parent_dev && dev_is_expander(parent_dev->dev_type))
792 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
794 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
797 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
801 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
802 (device->linkrate << ITCT_HDR_MCR_OFF) |
803 (1 << ITCT_HDR_VLN_OFF) |
804 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
805 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
806 (port->id << ITCT_HDR_PORT_ID_OFF));
807 itct->qw0 = cpu_to_le64(qw0);
810 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
811 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
814 if (!dev_is_sata(device))
815 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
816 (0x1ULL << ITCT_HDR_RTOLT_OFF));
819 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
820 struct hisi_sas_device *sas_dev)
822 DECLARE_COMPLETION_ONSTACK(completion);
823 u64 dev_id = sas_dev->device_id;
824 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
825 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
826 struct device *dev = hisi_hba->dev;
828 sas_dev->completion = &completion;
830 /* clear the itct interrupt state */
831 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
832 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
833 ENT_INT_SRC3_ITC_INT_MSK);
835 /* clear the itct table */
836 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
837 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
839 if (!wait_for_completion_timeout(sas_dev->completion,
840 CLEAR_ITCT_TIMEOUT * HZ)) {
841 dev_warn(dev, "failed to clear ITCT\n");
845 memset(itct, 0, sizeof(struct hisi_sas_itct));
849 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
850 struct domain_device *device)
852 struct hisi_sas_slot *slot, *slot2;
853 struct hisi_sas_device *sas_dev = device->lldd_dev;
854 u32 cfg_abt_set_query_iptt;
856 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
857 CFG_ABT_SET_QUERY_IPTT);
858 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
859 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
860 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
861 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
862 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
863 cfg_abt_set_query_iptt);
865 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
866 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
867 cfg_abt_set_query_iptt);
868 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
869 1 << CFG_ABT_SET_IPTT_DONE_OFF);
872 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
874 struct device *dev = hisi_hba->dev;
878 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
880 /* Disable all of the PHYs */
881 hisi_sas_stop_phys(hisi_hba);
884 /* Ensure axi bus idle */
885 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
888 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
892 if (ACPI_HANDLE(dev)) {
895 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
896 if (ACPI_FAILURE(s)) {
897 dev_err(dev, "Reset failed\n");
901 dev_err(dev, "no reset method!\n");
908 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
910 struct device *dev = hisi_hba->dev;
911 struct acpi_device *acpi_dev;
912 union acpi_object *obj;
916 rc = reset_hw_v3_hw(hisi_hba);
918 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
923 init_reg_v3_hw(hisi_hba);
925 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
926 dev_err(dev, "Parse GUID failed\n");
931 * This DSM handles some hardware-related configurations:
932 * 1. Switch over to MSI error handling in kernel
933 * 2. BIOS *may* reset some register values through this method
935 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
936 DSM_FUNC_ERR_HANDLE_MSI, NULL);
938 dev_warn(dev, "can not find DSM method, ignore\n");
942 acpi_dev = ACPI_COMPANION(dev);
943 if (!acpi_device_power_manageable(acpi_dev))
944 dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
948 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
950 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
952 cfg |= PHY_CFG_ENA_MSK;
953 cfg &= ~PHY_CFG_PHY_RST_MSK;
954 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
957 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
959 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
960 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
961 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
962 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
963 BIT(CHL_INT2_RX_INVLD_DW_OFF);
966 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
968 cfg &= ~PHY_CFG_ENA_MSK;
969 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
973 state = hisi_sas_read32(hisi_hba, PHY_STATE);
974 if (state & BIT(phy_no)) {
975 cfg |= PHY_CFG_PHY_RST_MSK;
976 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
981 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
982 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
983 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
985 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
986 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
989 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
991 config_id_frame_v3_hw(hisi_hba, phy_no);
992 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
993 enable_phy_v3_hw(hisi_hba, phy_no);
996 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
998 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1001 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1002 if (phy->identify.device_type == SAS_END_DEVICE) {
1003 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1004 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1005 txid_auto | TX_HARDRST_MSK);
1008 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1011 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1013 return SAS_LINK_RATE_12_0_GBPS;
1016 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1020 for (i = 0; i < hisi_hba->n_phy; i++) {
1021 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1022 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1024 if (!sas_phy->phy->enabled)
1027 hisi_sas_phy_enable(hisi_hba, i, 1);
1031 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1035 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1036 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1037 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1039 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1040 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1041 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1044 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1047 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1048 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1050 for (i = 0; i < hisi_hba->n_phy; i++)
1051 if (phy_state & BIT(i))
1052 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1058 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1060 struct hisi_hba *hisi_hba = dq->hisi_hba;
1061 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1062 int dlvry_queue = dq->id;
1065 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1069 list_del(&s->delivery);
1076 * Ensure that memories for slots built on other CPUs is observed.
1079 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1081 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1084 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1085 struct hisi_sas_slot *slot,
1086 struct hisi_sas_cmd_hdr *hdr,
1087 struct scatterlist *scatter,
1090 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1091 struct scatterlist *sg;
1094 for_each_sg(scatter, sg, n_elem, i) {
1095 struct hisi_sas_sge *entry = &sge_page->sge[i];
1097 entry->addr = cpu_to_le64(sg_dma_address(sg));
1098 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1099 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1100 entry->data_off = 0;
1103 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1105 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1108 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1109 struct hisi_sas_slot *slot,
1110 struct hisi_sas_cmd_hdr *hdr,
1111 struct scatterlist *scatter,
1114 struct hisi_sas_sge_dif_page *sge_dif_page;
1115 struct scatterlist *sg;
1118 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1120 for_each_sg(scatter, sg, n_elem, i) {
1121 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1123 entry->addr = cpu_to_le64(sg_dma_address(sg));
1124 entry->page_ctrl_0 = 0;
1125 entry->page_ctrl_1 = 0;
1126 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1127 entry->data_off = 0;
1130 hdr->dif_prd_table_addr =
1131 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1133 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1136 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1138 unsigned char prot_flags = scsi_cmnd->prot_flags;
1140 if (prot_flags & SCSI_PROT_REF_CHECK)
1141 return T10_CHK_APP_TAG_MSK;
1142 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1145 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1146 struct hisi_sas_protect_iu_v3_hw *prot)
1148 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1149 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1150 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
1153 case SCSI_PROT_READ_INSERT:
1154 prot->dw0 |= T10_INSRT_EN_MSK;
1155 prot->lbrtgv = lbrt_chk_val;
1157 case SCSI_PROT_READ_STRIP:
1158 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1159 prot->lbrtcv = lbrt_chk_val;
1160 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1162 case SCSI_PROT_READ_PASS:
1163 prot->dw0 |= T10_CHK_EN_MSK;
1164 prot->lbrtcv = lbrt_chk_val;
1165 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1167 case SCSI_PROT_WRITE_INSERT:
1168 prot->dw0 |= T10_INSRT_EN_MSK;
1169 prot->lbrtgv = lbrt_chk_val;
1171 case SCSI_PROT_WRITE_STRIP:
1172 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1173 prot->lbrtcv = lbrt_chk_val;
1175 case SCSI_PROT_WRITE_PASS:
1176 prot->dw0 |= T10_CHK_EN_MSK;
1177 prot->lbrtcv = lbrt_chk_val;
1178 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1181 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1189 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1192 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1195 WARN(1, "protection interval (0x%x) invalid\n",
1200 prot->dw0 |= INCR_LBRT_MSK;
1203 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1204 struct hisi_sas_slot *slot)
1206 struct sas_task *task = slot->task;
1207 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1208 struct domain_device *device = task->dev;
1209 struct hisi_sas_device *sas_dev = device->lldd_dev;
1210 struct hisi_sas_port *port = slot->port;
1211 struct sas_ssp_task *ssp_task = &task->ssp_task;
1212 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1213 struct hisi_sas_tmf_task *tmf = slot->tmf;
1214 int has_data = 0, priority = !!tmf;
1215 unsigned char prot_op;
1217 u32 dw1 = 0, dw2 = 0, len = 0;
1219 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1220 (2 << CMD_HDR_TLR_CTRL_OFF) |
1221 (port->id << CMD_HDR_PORT_OFF) |
1222 (priority << CMD_HDR_PRIORITY_OFF) |
1223 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1225 dw1 = 1 << CMD_HDR_VDTL_OFF;
1227 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1228 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1230 prot_op = scsi_get_prot_op(scsi_cmnd);
1231 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1232 switch (scsi_cmnd->sc_data_direction) {
1235 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1237 case DMA_FROM_DEVICE:
1239 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1242 dw1 &= ~CMD_HDR_DIR_MSK;
1246 /* map itct entry */
1247 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1249 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1250 + 3) / 4) << CMD_HDR_CFL_OFF) |
1251 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1252 (2 << CMD_HDR_SG_MOD_OFF);
1253 hdr->dw2 = cpu_to_le32(dw2);
1254 hdr->transfer_tags = cpu_to_le32(slot->idx);
1257 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1260 if (scsi_prot_sg_count(scsi_cmnd))
1261 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1262 scsi_prot_sglist(scsi_cmnd),
1266 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1267 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1269 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1270 sizeof(struct ssp_frame_hdr);
1272 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1274 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1275 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1277 buf_cmd[10] = tmf->tmf;
1279 case TMF_ABORT_TASK:
1280 case TMF_QUERY_TASK:
1282 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1284 tmf->tag_of_task_to_be_managed & 0xff;
1291 if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1292 struct hisi_sas_protect_iu_v3_hw prot;
1295 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1296 dw1 |= CMD_HDR_PIR_MSK;
1297 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1298 sizeof(struct ssp_frame_hdr) +
1299 sizeof(struct ssp_command_iu);
1301 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1302 fill_prot_v3_hw(scsi_cmnd, &prot);
1303 memcpy(buf_cmd_prot, &prot,
1304 sizeof(struct hisi_sas_protect_iu_v3_hw));
1306 * For READ, we need length of info read to memory, while for
1307 * WRITE we need length of data written to the disk.
1309 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1310 prot_op == SCSI_PROT_READ_INSERT ||
1311 prot_op == SCSI_PROT_WRITE_PASS ||
1312 prot_op == SCSI_PROT_READ_PASS) {
1313 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1314 unsigned int ilog2_interval = ilog2(interval);
1316 len = (task->total_xfer_len >> ilog2_interval) * 8;
1320 hdr->dw1 = cpu_to_le32(dw1);
1322 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1325 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1326 struct hisi_sas_slot *slot)
1328 struct sas_task *task = slot->task;
1329 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1330 struct domain_device *device = task->dev;
1331 struct hisi_sas_port *port = slot->port;
1332 struct scatterlist *sg_req;
1333 struct hisi_sas_device *sas_dev = device->lldd_dev;
1334 dma_addr_t req_dma_addr;
1335 unsigned int req_len;
1338 sg_req = &task->smp_task.smp_req;
1339 req_len = sg_dma_len(sg_req);
1340 req_dma_addr = sg_dma_address(sg_req);
1344 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1345 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1346 (2 << CMD_HDR_CMD_OFF)); /* smp */
1348 /* map itct entry */
1349 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1350 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1351 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1354 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1355 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1358 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1360 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1361 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1364 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1365 struct hisi_sas_slot *slot)
1367 struct sas_task *task = slot->task;
1368 struct domain_device *device = task->dev;
1369 struct domain_device *parent_dev = device->parent;
1370 struct hisi_sas_device *sas_dev = device->lldd_dev;
1371 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1372 struct asd_sas_port *sas_port = device->port;
1373 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1375 int has_data = 0, hdr_tag = 0;
1376 u32 dw1 = 0, dw2 = 0;
1378 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1379 if (parent_dev && dev_is_expander(parent_dev->dev_type))
1380 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1382 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1384 switch (task->data_dir) {
1387 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1389 case DMA_FROM_DEVICE:
1391 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1394 dw1 &= ~CMD_HDR_DIR_MSK;
1397 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1398 (task->ata_task.fis.control & ATA_SRST))
1399 dw1 |= 1 << CMD_HDR_RESET_OFF;
1401 dw1 |= (hisi_sas_get_ata_protocol(
1402 &task->ata_task.fis, task->data_dir))
1403 << CMD_HDR_FRAME_TYPE_OFF;
1404 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1406 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1407 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1409 hdr->dw1 = cpu_to_le32(dw1);
1412 if (task->ata_task.use_ncq) {
1413 struct ata_queued_cmd *qc = task->uldd_task;
1416 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1417 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1420 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1421 2 << CMD_HDR_SG_MOD_OFF;
1422 hdr->dw2 = cpu_to_le32(dw2);
1425 hdr->transfer_tags = cpu_to_le32(slot->idx);
1428 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1431 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1432 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1433 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1435 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1437 if (likely(!task->ata_task.device_control_reg_update))
1438 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1439 /* fill in command FIS */
1440 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1443 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1444 struct hisi_sas_slot *slot,
1445 int device_id, int abort_flag, int tag_to_abort)
1447 struct sas_task *task = slot->task;
1448 struct domain_device *dev = task->dev;
1449 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1450 struct hisi_sas_port *port = slot->port;
1453 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/
1454 (port->id << CMD_HDR_PORT_OFF) |
1456 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1458 << CMD_HDR_ABORT_FLAG_OFF));
1461 hdr->dw1 = cpu_to_le32(device_id
1462 << CMD_HDR_DEV_ID_OFF);
1465 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1466 hdr->transfer_tags = cpu_to_le32(slot->idx);
1469 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1473 u32 context, port_id, link_rate;
1474 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1475 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1476 struct device *dev = hisi_hba->dev;
1477 unsigned long flags;
1479 del_timer(&phy->timer);
1480 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1482 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1483 port_id = (port_id >> (4 * phy_no)) & 0xf;
1484 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1485 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1487 if (port_id == 0xf) {
1488 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1492 sas_phy->linkrate = link_rate;
1493 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1495 /* Check for SATA dev */
1496 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1497 if (context & (1 << phy_no)) {
1498 struct hisi_sas_initial_fis *initial_fis;
1499 struct dev_to_host_fis *fis;
1500 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1501 struct Scsi_Host *shost = hisi_hba->shost;
1503 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1504 initial_fis = &hisi_hba->initial_fis[phy_no];
1505 fis = &initial_fis->fis;
1507 /* check ERR bit of Status Register */
1508 if (fis->status & ATA_ERR) {
1509 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1510 phy_no, fis->status);
1511 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1516 sas_phy->oob_mode = SATA_OOB_MODE;
1517 attached_sas_addr[0] = 0x50;
1518 attached_sas_addr[6] = shost->host_no;
1519 attached_sas_addr[7] = phy_no;
1520 memcpy(sas_phy->attached_sas_addr,
1523 memcpy(sas_phy->frame_rcvd, fis,
1524 sizeof(struct dev_to_host_fis));
1525 phy->phy_type |= PORT_TYPE_SATA;
1526 phy->identify.device_type = SAS_SATA_DEV;
1527 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1528 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1530 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1531 struct sas_identify_frame *id =
1532 (struct sas_identify_frame *)frame_rcvd;
1534 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1535 for (i = 0; i < 6; i++) {
1536 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1537 RX_IDAF_DWORD0 + (i * 4));
1538 frame_rcvd[i] = __swab32(idaf);
1540 sas_phy->oob_mode = SAS_OOB_MODE;
1541 memcpy(sas_phy->attached_sas_addr,
1544 phy->phy_type |= PORT_TYPE_SAS;
1545 phy->identify.device_type = id->dev_type;
1546 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1547 if (phy->identify.device_type == SAS_END_DEVICE)
1548 phy->identify.target_port_protocols =
1550 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1551 phy->identify.target_port_protocols =
1555 phy->port_id = port_id;
1556 phy->phy_attached = 1;
1557 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1559 spin_lock_irqsave(&phy->lock, flags);
1560 if (phy->reset_completion) {
1562 complete(phy->reset_completion);
1564 spin_unlock_irqrestore(&phy->lock, flags);
1566 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1567 CHL_INT0_SL_PHY_ENABLE_MSK);
1568 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1573 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1575 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1576 u32 phy_state, sl_ctrl, txid_auto;
1577 struct device *dev = hisi_hba->dev;
1579 atomic_inc(&phy->down_cnt);
1581 del_timer(&phy->timer);
1582 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1584 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1585 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1586 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1588 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1589 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1590 sl_ctrl&(~SL_CTA_MSK));
1592 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1593 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1594 txid_auto | CT3_MSK);
1596 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1597 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1602 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1604 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1605 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1608 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1609 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1610 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1611 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1612 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1613 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1614 CHL_INT0_SL_RX_BCST_ACK_MSK);
1615 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1620 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1622 struct hisi_hba *hisi_hba = p;
1625 irqreturn_t res = IRQ_NONE;
1627 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1631 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1633 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1634 int rdy = phy_state & (1 << phy_no);
1637 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1639 if (phy_up_v3_hw(phy_no, hisi_hba)
1642 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1644 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1648 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1650 if (phy_down_v3_hw(phy_no, hisi_hba)
1662 static const struct hisi_sas_hw_error port_axi_error[] = {
1664 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1665 .msg = "dmac_tx_ecc_bad_err",
1668 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1669 .msg = "dmac_rx_ecc_bad_err",
1672 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1673 .msg = "dma_tx_axi_wr_err",
1676 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1677 .msg = "dma_tx_axi_rd_err",
1680 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1681 .msg = "dma_rx_axi_wr_err",
1684 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1685 .msg = "dma_rx_axi_rd_err",
1688 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1689 .msg = "dma_tx_fifo_err",
1692 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1693 .msg = "dma_rx_fifo_err",
1696 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1697 .msg = "dma_tx_axi_ruser_err",
1700 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1701 .msg = "dma_rx_axi_ruser_err",
1705 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1707 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1708 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1709 struct device *dev = hisi_hba->dev;
1712 irq_value &= ~irq_msk;
1716 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1717 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1719 if (!(irq_value & error->irq_msk))
1722 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1723 error->msg, phy_no, irq_value);
1724 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1727 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1730 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1732 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1733 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1734 struct sas_phy *sphy = sas_phy->phy;
1735 unsigned long flags;
1738 spin_lock_irqsave(&phy->lock, flags);
1740 /* loss dword sync */
1741 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1742 sphy->loss_of_dword_sync_count += reg_value;
1744 /* phy reset problem */
1745 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1746 sphy->phy_reset_problem_count += reg_value;
1749 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1750 sphy->invalid_dword_count += reg_value;
1753 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1754 sphy->running_disparity_error_count += reg_value;
1756 /* code violation error */
1757 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1758 phy->code_violation_err_count += reg_value;
1760 spin_unlock_irqrestore(&phy->lock, flags);
1763 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1765 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1766 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1767 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1768 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1769 struct device *dev = hisi_hba->dev;
1770 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1771 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1772 BIT(CHL_INT2_RX_INVLD_DW_OFF);
1774 irq_value &= ~irq_msk;
1778 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1779 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1780 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1783 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1784 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1785 STP_LINK_TIMEOUT_STATE);
1787 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1789 if (reg_value & BIT(4))
1790 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1793 if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1794 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1795 struct sas_phy *sphy = sas_phy->phy;
1797 phy_get_events_v3_hw(hisi_hba, phy_no);
1799 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1800 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
1801 sphy->invalid_dword_count);
1803 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1804 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
1805 phy->code_violation_err_count);
1807 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1808 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1809 sphy->running_disparity_error_count);
1812 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1813 (pci_dev->revision == 0x20)) {
1817 rc = hisi_sas_read32_poll_timeout_atomic(
1818 HILINK_ERR_DFX, reg_value,
1819 !((reg_value >> 8) & BIT(phy_no)),
1822 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1825 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1828 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1830 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1832 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1833 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1835 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1836 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1837 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1838 & (~CHL_INT0_NOT_RDY_MSK));
1841 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1843 struct hisi_hba *hisi_hba = p;
1847 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1851 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1852 handle_chl_int0_v3_hw(hisi_hba, phy_no);
1854 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1855 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1857 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1858 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1860 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1867 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1869 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1870 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
1871 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
1872 .msg = "hgc_dqe_eccbad_intr",
1873 .reg = HGC_DQE_ECC_ADDR,
1876 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1877 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
1878 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
1879 .msg = "hgc_iost_eccbad_intr",
1880 .reg = HGC_IOST_ECC_ADDR,
1883 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1884 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1885 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1886 .msg = "hgc_itct_eccbad_intr",
1887 .reg = HGC_ITCT_ECC_ADDR,
1890 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1891 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1892 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1893 .msg = "hgc_iostl_eccbad_intr",
1894 .reg = HGC_LM_DFX_STATUS2,
1897 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1898 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1899 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1900 .msg = "hgc_itctl_eccbad_intr",
1901 .reg = HGC_LM_DFX_STATUS2,
1904 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1905 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
1906 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
1907 .msg = "hgc_cqe_eccbad_intr",
1908 .reg = HGC_CQE_ECC_ADDR,
1911 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1912 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1913 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1914 .msg = "rxm_mem0_eccbad_intr",
1915 .reg = HGC_RXM_DFX_STATUS14,
1918 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1919 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1920 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1921 .msg = "rxm_mem1_eccbad_intr",
1922 .reg = HGC_RXM_DFX_STATUS14,
1925 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1926 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1927 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1928 .msg = "rxm_mem2_eccbad_intr",
1929 .reg = HGC_RXM_DFX_STATUS14,
1932 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1933 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1934 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1935 .msg = "rxm_mem3_eccbad_intr",
1936 .reg = HGC_RXM_DFX_STATUS15,
1939 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1940 .msk = AM_ROB_ECC_ERR_ADDR_MSK,
1941 .shift = AM_ROB_ECC_ERR_ADDR_OFF,
1942 .msg = "ooo_ram_eccbad_intr",
1943 .reg = AM_ROB_ECC_ERR_ADDR,
1947 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1950 struct device *dev = hisi_hba->dev;
1951 const struct hisi_sas_hw_error *ecc_error;
1955 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1956 ecc_error = &multi_bit_ecc_errors[i];
1957 if (irq_value & ecc_error->irq_msk) {
1958 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1959 val &= ecc_error->msk;
1960 val >>= ecc_error->shift;
1961 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1962 ecc_error->msg, irq_value, val);
1963 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1968 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
1970 u32 irq_value, irq_msk;
1972 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
1973 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1975 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1977 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
1979 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
1980 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
1983 static const struct hisi_sas_hw_error axi_error[] = {
1984 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1985 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1986 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1987 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1988 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1989 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1990 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1991 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1995 static const struct hisi_sas_hw_error fifo_error[] = {
1996 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1997 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1998 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1999 { .msk = BIT(11), .msg = "CMDP_FIFO" },
2000 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2004 static const struct hisi_sas_hw_error fatal_axi_error[] = {
2006 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2007 .msg = "write pointer and depth",
2010 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2011 .msg = "iptt no match slot",
2014 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2015 .msg = "read pointer and depth",
2018 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2019 .reg = HGC_AXI_FIFO_ERR_INFO,
2023 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2024 .reg = HGC_AXI_FIFO_ERR_INFO,
2028 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2029 .msg = "LM add/fetch list",
2032 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2033 .msg = "SAS_HGC_ABT fetch LM list",
2036 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2037 .msg = "read dqe poison",
2040 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2041 .msg = "read iost poison",
2044 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2045 .msg = "read itct poison",
2048 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2049 .msg = "read itct ncq poison",
2054 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2056 u32 irq_value, irq_msk;
2057 struct hisi_hba *hisi_hba = p;
2058 struct device *dev = hisi_hba->dev;
2059 struct pci_dev *pdev = hisi_hba->pci_dev;
2062 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2063 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2065 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2066 irq_value &= ~irq_msk;
2068 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2069 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2071 if (!(irq_value & error->irq_msk))
2075 const struct hisi_sas_hw_error *sub = error->sub;
2076 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2078 for (; sub->msk || sub->msg; sub++) {
2079 if (!(err_value & sub->msk))
2082 dev_err(dev, "%s error (0x%x) found!\n",
2083 sub->msg, irq_value);
2084 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2087 dev_err(dev, "%s error (0x%x) found!\n",
2088 error->msg, irq_value);
2089 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2092 if (pdev->revision < 0x21) {
2095 reg_val = hisi_sas_read32(hisi_hba,
2096 AXI_MASTER_CFG_BASE +
2098 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2099 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2100 AM_CTRL_GLOBAL, reg_val);
2104 fatal_ecc_int_v3_hw(hisi_hba);
2106 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2107 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2108 u32 dev_id = reg_val & ITCT_DEV_MSK;
2109 struct hisi_sas_device *sas_dev =
2110 &hisi_hba->devices[dev_id];
2112 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2113 dev_dbg(dev, "clear ITCT ok\n");
2114 complete(sas_dev->completion);
2117 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2118 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2124 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2125 struct hisi_sas_slot *slot)
2127 struct task_status_struct *ts = &task->task_status;
2128 struct hisi_sas_complete_v3_hdr *complete_queue =
2129 hisi_hba->complete_hdr[slot->cmplt_queue];
2130 struct hisi_sas_complete_v3_hdr *complete_hdr =
2131 &complete_queue[slot->cmplt_queue_slot];
2132 struct hisi_sas_err_record_v3 *record =
2133 hisi_sas_status_buf_addr_mem(slot);
2134 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2135 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2136 u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
2137 u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2138 u32 dw0 = le32_to_cpu(complete_hdr->dw0);
2140 switch (task->task_proto) {
2141 case SAS_PROTOCOL_SSP:
2142 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2144 * If returned response frame is incorrect because of data underflow,
2145 * but I/O information has been written to the host memory, we examine
2148 if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2149 (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2152 ts->residual = trans_tx_fail_type;
2153 ts->stat = SAS_DATA_UNDERRUN;
2154 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2155 ts->stat = SAS_QUEUE_FULL;
2158 ts->stat = SAS_OPEN_REJECT;
2159 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2162 case SAS_PROTOCOL_SATA:
2163 case SAS_PROTOCOL_STP:
2164 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2165 if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2166 (sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
2167 ts->stat = SAS_PROTO_RESPONSE;
2168 } else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2169 ts->residual = trans_tx_fail_type;
2170 ts->stat = SAS_DATA_UNDERRUN;
2171 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2172 ts->stat = SAS_PHY_DOWN;
2175 ts->stat = SAS_OPEN_REJECT;
2176 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2178 if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2179 hisi_sas_sata_done(task, slot);
2181 case SAS_PROTOCOL_SMP:
2182 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2190 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2191 struct hisi_sas_slot *slot)
2193 struct sas_task *task = slot->task;
2194 struct hisi_sas_device *sas_dev;
2195 struct device *dev = hisi_hba->dev;
2196 struct task_status_struct *ts;
2197 struct domain_device *device;
2198 struct sas_ha_struct *ha;
2199 struct hisi_sas_complete_v3_hdr *complete_queue =
2200 hisi_hba->complete_hdr[slot->cmplt_queue];
2201 struct hisi_sas_complete_v3_hdr *complete_hdr =
2202 &complete_queue[slot->cmplt_queue_slot];
2203 unsigned long flags;
2204 bool is_internal = slot->is_internal;
2207 if (unlikely(!task || !task->lldd_task || !task->dev))
2210 ts = &task->task_status;
2212 ha = device->port->ha;
2213 sas_dev = device->lldd_dev;
2215 spin_lock_irqsave(&task->task_state_lock, flags);
2216 task->task_state_flags &=
2217 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2218 spin_unlock_irqrestore(&task->task_state_lock, flags);
2220 memset(ts, 0, sizeof(*ts));
2221 ts->resp = SAS_TASK_COMPLETE;
2223 if (unlikely(!sas_dev)) {
2224 dev_dbg(dev, "slot complete: port has not device\n");
2225 ts->stat = SAS_PHY_DOWN;
2229 dw0 = le32_to_cpu(complete_hdr->dw0);
2230 dw1 = le32_to_cpu(complete_hdr->dw1);
2231 dw3 = le32_to_cpu(complete_hdr->dw3);
2234 * Use SAS+TMF status codes
2236 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2237 case STAT_IO_ABORTED:
2238 /* this IO has been aborted by abort command */
2239 ts->stat = SAS_ABORTED_TASK;
2241 case STAT_IO_COMPLETE:
2242 /* internal abort command complete */
2243 ts->stat = TMF_RESP_FUNC_SUCC;
2245 case STAT_IO_NO_DEVICE:
2246 ts->stat = TMF_RESP_FUNC_COMPLETE;
2248 case STAT_IO_NOT_VALID:
2250 * abort single IO, the controller can't find the IO
2252 ts->stat = TMF_RESP_FUNC_FAILED;
2258 /* check for erroneous completion */
2259 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2260 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2262 if (slot_err_v3_hw(hisi_hba, task, slot)) {
2263 if (ts->stat != SAS_DATA_UNDERRUN)
2264 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2265 slot->idx, task, sas_dev->device_id,
2266 SAS_ADDR(device->sas_addr),
2267 dw0, dw1, complete_hdr->act, dw3,
2268 error_info[0], error_info[1],
2269 error_info[2], error_info[3]);
2270 if (unlikely(slot->abort)) {
2271 sas_task_abort(task);
2278 switch (task->task_proto) {
2279 case SAS_PROTOCOL_SSP: {
2280 struct ssp_response_iu *iu =
2281 hisi_sas_status_buf_addr_mem(slot) +
2282 sizeof(struct hisi_sas_err_record);
2284 sas_ssp_task_response(dev, task, iu);
2287 case SAS_PROTOCOL_SMP: {
2288 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2289 void *to = page_address(sg_page(sg_resp));
2291 ts->stat = SAS_SAM_STAT_GOOD;
2293 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2295 memcpy(to + sg_resp->offset,
2296 hisi_sas_status_buf_addr_mem(slot) +
2297 sizeof(struct hisi_sas_err_record),
2301 case SAS_PROTOCOL_SATA:
2302 case SAS_PROTOCOL_STP:
2303 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2304 ts->stat = SAS_SAM_STAT_GOOD;
2305 if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2306 hisi_sas_sata_done(task, slot);
2309 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2313 if (!slot->port->port_attached) {
2314 dev_warn(dev, "slot complete: port %d has removed\n",
2315 slot->port->sas_port.id);
2316 ts->stat = SAS_PHY_DOWN;
2320 spin_lock_irqsave(&task->task_state_lock, flags);
2321 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2322 spin_unlock_irqrestore(&task->task_state_lock, flags);
2323 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2326 task->task_state_flags |= SAS_TASK_STATE_DONE;
2327 spin_unlock_irqrestore(&task->task_state_lock, flags);
2328 hisi_sas_slot_task_free(hisi_hba, task, slot);
2330 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2331 spin_lock_irqsave(&device->done_lock, flags);
2332 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2333 spin_unlock_irqrestore(&device->done_lock, flags);
2334 dev_info(dev, "slot complete: task(%pK) ignored\n ",
2338 spin_unlock_irqrestore(&device->done_lock, flags);
2341 if (task->task_done)
2342 task->task_done(task);
2345 static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2347 struct hisi_sas_cq *cq = p;
2348 struct hisi_hba *hisi_hba = cq->hisi_hba;
2349 struct hisi_sas_slot *slot;
2350 struct hisi_sas_complete_v3_hdr *complete_queue;
2351 u32 rd_point = cq->rd_point, wr_point;
2354 complete_queue = hisi_hba->complete_hdr[queue];
2356 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2359 while (rd_point != wr_point) {
2360 struct hisi_sas_complete_v3_hdr *complete_hdr;
2361 struct device *dev = hisi_hba->dev;
2365 complete_hdr = &complete_queue[rd_point];
2366 dw1 = le32_to_cpu(complete_hdr->dw1);
2368 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2369 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2370 slot = &hisi_hba->slot_info[iptt];
2371 slot->cmplt_queue_slot = rd_point;
2372 slot->cmplt_queue = queue;
2373 slot_complete_v3_hw(hisi_hba, slot);
2375 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2377 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2381 /* update rd_point */
2382 cq->rd_point = rd_point;
2383 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2388 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2390 struct hisi_sas_cq *cq = p;
2391 struct hisi_hba *hisi_hba = cq->hisi_hba;
2394 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2396 return IRQ_WAKE_THREAD;
2399 static void hisi_sas_v3_free_vectors(void *data)
2401 struct pci_dev *pdev = data;
2403 pci_free_irq_vectors(pdev);
2406 static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2409 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2410 struct Scsi_Host *shost = hisi_hba->shost;
2411 struct pci_dev *pdev = hisi_hba->pci_dev;
2412 struct irq_affinity desc = {
2413 .pre_vectors = BASE_VECTORS_V3_HW,
2416 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2417 vectors = pci_alloc_irq_vectors_affinity(pdev,
2426 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2427 shost->nr_hw_queues = hisi_hba->cq_nvecs;
2429 return devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2432 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2434 struct device *dev = hisi_hba->dev;
2435 struct pci_dev *pdev = hisi_hba->pci_dev;
2438 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2439 int_phy_up_down_bcast_v3_hw, 0,
2440 DRV_NAME " phy", hisi_hba);
2442 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2446 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2447 int_chnl_int_v3_hw, 0,
2448 DRV_NAME " channel", hisi_hba);
2450 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2454 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2455 fatal_axi_int_v3_hw, 0,
2456 DRV_NAME " fatal", hisi_hba);
2458 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2462 if (hisi_sas_intr_conv)
2463 dev_info(dev, "Enable interrupt converge\n");
2465 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2466 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2467 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2468 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2471 cq->irq_no = pci_irq_vector(pdev, nr);
2472 rc = devm_request_threaded_irq(dev, cq->irq_no,
2476 DRV_NAME " cq", cq);
2478 dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2482 cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2483 if (!cq->irq_mask) {
2484 dev_err(dev, "could not get cq%d irq affinity!\n", i);
2492 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2496 rc = hw_init_v3_hw(hisi_hba);
2500 rc = interrupt_init_v3_hw(hisi_hba);
2507 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2508 struct sas_phy_linkrates *r)
2510 enum sas_linkrate max = r->maximum_linkrate;
2511 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2512 PROG_PHY_LINK_RATE);
2514 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2515 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2516 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2517 prog_phy_link_rate);
2520 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2522 struct pci_dev *pdev = hisi_hba->pci_dev;
2525 synchronize_irq(pci_irq_vector(pdev, 1));
2526 synchronize_irq(pci_irq_vector(pdev, 2));
2527 synchronize_irq(pci_irq_vector(pdev, 11));
2528 for (i = 0; i < hisi_hba->queue_count; i++)
2529 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2531 for (i = 0; i < hisi_hba->cq_nvecs; i++)
2532 synchronize_irq(pci_irq_vector(pdev, i + 16));
2534 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2535 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2536 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2537 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2539 for (i = 0; i < hisi_hba->n_phy; i++) {
2540 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2541 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2542 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2543 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2544 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2548 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2550 return hisi_sas_read32(hisi_hba, PHY_STATE);
2553 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2555 struct device *dev = hisi_hba->dev;
2556 u32 status, reg_val;
2559 interrupt_disable_v3_hw(hisi_hba);
2560 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2562 hisi_sas_stop_phys(hisi_hba);
2566 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2568 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2569 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2570 AM_CTRL_GLOBAL, reg_val);
2572 /* wait until bus idle */
2573 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2574 AM_CURR_TRANS_RETURN, status,
2575 status == 0x3, 10, 100);
2577 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2584 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2586 struct device *dev = hisi_hba->dev;
2589 rc = disable_host_v3_hw(hisi_hba);
2591 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2595 hisi_sas_init_mem(hisi_hba);
2597 return hw_init_v3_hw(hisi_hba);
2600 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2601 u8 reg_index, u8 reg_count, u8 *write_data)
2603 struct device *dev = hisi_hba->dev;
2604 u32 *data = (u32 *)write_data;
2608 case SAS_GPIO_REG_TX:
2609 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2610 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2611 reg_index, reg_index + reg_count - 1);
2615 for (i = 0; i < reg_count; i++)
2616 hisi_sas_write32(hisi_hba,
2617 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2621 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2629 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2630 int delay_ms, int timeout_ms)
2632 struct device *dev = hisi_hba->dev;
2633 int entries, entries_old = 0, time;
2635 for (time = 0; time < timeout_ms; time += delay_ms) {
2636 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2637 if (entries == entries_old)
2640 entries_old = entries;
2644 if (time >= timeout_ms) {
2645 dev_dbg(dev, "Wait commands complete timeout!\n");
2649 dev_dbg(dev, "wait commands complete %dms\n", time);
2652 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2653 struct device_attribute *attr, char *buf)
2655 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2657 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2659 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2661 /* config those registers between enable and disable PHYs */
2662 hisi_sas_stop_phys(hisi_hba);
2664 if (hisi_hba->intr_coal_ticks == 0 ||
2665 hisi_hba->intr_coal_count == 0) {
2666 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2667 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2668 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2670 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2671 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2672 hisi_hba->intr_coal_ticks);
2673 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2674 hisi_hba->intr_coal_count);
2676 phys_init_v3_hw(hisi_hba);
2679 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2680 struct device_attribute *attr,
2683 struct Scsi_Host *shost = class_to_shost(dev);
2684 struct hisi_hba *hisi_hba = shost_priv(shost);
2686 return scnprintf(buf, PAGE_SIZE, "%u\n",
2687 hisi_hba->intr_coal_ticks);
2690 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2691 struct device_attribute *attr,
2692 const char *buf, size_t count)
2694 struct Scsi_Host *shost = class_to_shost(dev);
2695 struct hisi_hba *hisi_hba = shost_priv(shost);
2696 u32 intr_coal_ticks;
2699 ret = kstrtou32(buf, 10, &intr_coal_ticks);
2701 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2705 if (intr_coal_ticks >= BIT(24)) {
2706 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2710 hisi_hba->intr_coal_ticks = intr_coal_ticks;
2712 config_intr_coal_v3_hw(hisi_hba);
2716 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2718 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2719 struct device_attribute
2722 struct Scsi_Host *shost = class_to_shost(dev);
2723 struct hisi_hba *hisi_hba = shost_priv(shost);
2725 return scnprintf(buf, PAGE_SIZE, "%u\n",
2726 hisi_hba->intr_coal_count);
2729 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2730 struct device_attribute
2731 *attr, const char *buf, size_t count)
2733 struct Scsi_Host *shost = class_to_shost(dev);
2734 struct hisi_hba *hisi_hba = shost_priv(shost);
2735 u32 intr_coal_count;
2738 ret = kstrtou32(buf, 10, &intr_coal_count);
2740 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2744 if (intr_coal_count >= BIT(8)) {
2745 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2749 hisi_hba->intr_coal_count = intr_coal_count;
2751 config_intr_coal_v3_hw(hisi_hba);
2755 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2757 static int slave_configure_v3_hw(struct scsi_device *sdev)
2759 struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2760 struct domain_device *ddev = sdev_to_domain_dev(sdev);
2761 struct hisi_hba *hisi_hba = shost_priv(shost);
2762 struct device *dev = hisi_hba->dev;
2763 int ret = sas_slave_configure(sdev);
2767 if (!dev_is_sata(ddev))
2768 sas_change_queue_depth(sdev, 64);
2770 if (sdev->type == TYPE_ENCLOSURE)
2773 if (!device_link_add(&sdev->sdev_gendev, dev,
2774 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2775 if (pm_runtime_enabled(dev)) {
2776 dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2777 pm_runtime_disable(dev);
2784 static struct device_attribute *host_attrs_v3_hw[] = {
2785 &dev_attr_phy_event_threshold,
2786 &dev_attr_intr_conv_v3_hw,
2787 &dev_attr_intr_coal_ticks_v3_hw,
2788 &dev_attr_intr_coal_count_v3_hw,
2792 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2793 HISI_SAS_DEBUGFS_REG(PHY_CFG),
2794 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2795 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2796 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2797 HISI_SAS_DEBUGFS_REG(SL_CFG),
2798 HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2799 HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2800 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2801 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2802 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2803 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2804 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2805 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2806 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2807 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2808 HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2809 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2810 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2811 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2812 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2813 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2814 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2815 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2816 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2817 HISI_SAS_DEBUGFS_REG(CHL_INT0),
2818 HISI_SAS_DEBUGFS_REG(CHL_INT1),
2819 HISI_SAS_DEBUGFS_REG(CHL_INT2),
2820 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2821 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2822 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2823 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2824 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2825 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2826 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2827 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2828 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2829 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2830 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2831 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2832 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2833 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2834 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2835 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2836 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2837 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2838 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2839 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2843 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2844 .lu = debugfs_port_reg_lu,
2846 .base_off = PORT_BASE,
2847 .read_port_reg = hisi_sas_phy_read32,
2850 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2851 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2852 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2853 HISI_SAS_DEBUGFS_REG(PHY_STATE),
2854 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2855 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2856 HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2857 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2858 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2859 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2860 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2861 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2862 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2863 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2864 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2865 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2866 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2867 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2868 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2869 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2870 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2871 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2872 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2873 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2874 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2875 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2876 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2877 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2878 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2879 HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2880 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2881 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2882 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2883 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2884 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2885 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2886 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2887 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2888 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2889 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2890 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2891 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2892 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2893 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2894 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2895 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2896 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2897 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2898 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2899 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2900 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2901 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2902 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2903 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2904 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2905 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2906 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2907 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2908 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2909 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2910 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2911 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2912 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2913 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2917 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2918 .lu = debugfs_global_reg_lu,
2920 .read_global_reg = hisi_sas_read32,
2923 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2924 HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2925 HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2926 HISI_SAS_DEBUGFS_REG(AXI_CFG),
2927 HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2931 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2932 .lu = debugfs_axi_reg_lu,
2934 .base_off = AXI_MASTER_CFG_BASE,
2935 .read_global_reg = hisi_sas_read32,
2938 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2939 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2940 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2941 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2942 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2943 HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2944 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2945 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2949 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2950 .lu = debugfs_ras_reg_lu,
2952 .base_off = RAS_BASE,
2953 .read_global_reg = hisi_sas_read32,
2956 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2958 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2960 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
2962 wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
2964 hisi_sas_sync_irqs(hisi_hba);
2967 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
2969 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
2970 (u32)((1ULL << hisi_hba->queue_count) - 1));
2972 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2975 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
2976 enum hisi_sas_debugfs_cache_type type,
2979 u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
2980 HISI_SAS_IOST_ITCT_CACHE_NUM;
2981 struct device *dev = hisi_hba->dev;
2985 hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
2987 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
2988 val = hisi_sas_read32(hisi_hba, TAB_DFX);
2989 if (val == 0xffffffff)
2993 if (val != 0xffffffff) {
2994 dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
2998 memset(buf, 0, cache_dw_size * 4);
3001 for (i = 1; i < cache_dw_size; i++)
3002 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3005 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3008 int phy_no = hisi_hba->debugfs_bist_phy_no;
3012 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3015 for (i = 0; i < FFE_CFG_MAX; i++)
3016 hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3017 hisi_hba->debugfs_bist_ffe[phy_no][i]);
3020 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3021 reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3022 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3025 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3028 int phy_no = hisi_hba->debugfs_bist_phy_no;
3030 /* disable loopback */
3031 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3032 reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3034 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3037 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3038 reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3039 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3041 /* restore the linkrate */
3042 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3043 /* init OOB link rate as 1.5 Gbits */
3044 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3045 reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3046 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3049 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3052 #define SAS_PHY_BIST_CODE_INIT 0x1
3053 #define SAS_PHY_BIST_CODE1_INIT 0X80
3054 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3056 u32 reg_val, mode_tmp;
3057 u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3058 u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3059 u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3060 u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3061 u32 path_mode = hisi_hba->debugfs_bist_mode;
3062 u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3063 struct device *dev = hisi_hba->dev;
3065 dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3066 phy_no, linkrate, code_mode, path_mode,
3067 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3068 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3069 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3070 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3071 fix_code[FIXED_CODE_1]);
3072 mode_tmp = path_mode ? 2 : 1;
3074 /* some preparations before bist test */
3075 hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3077 /* set linkrate of bit test*/
3078 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3079 PROG_PHY_LINK_RATE);
3080 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3081 reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3082 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3085 /* set code mode of bit test */
3086 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3088 reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3089 CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3091 reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3092 (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3094 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3097 /* set the bist init value */
3098 if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3099 reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3100 hisi_sas_phy_write32(hisi_hba, phy_no,
3101 SAS_PHY_BIST_CODE, reg_val);
3103 reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3104 hisi_sas_phy_write32(hisi_hba, phy_no,
3105 SAS_PHY_BIST_CODE1, reg_val);
3107 hisi_sas_phy_write32(hisi_hba, phy_no,
3109 SAS_PHY_BIST_CODE_INIT);
3110 hisi_sas_phy_write32(hisi_hba, phy_no,
3112 SAS_PHY_BIST_CODE1_INIT);
3116 reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3117 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3120 /* clear error bit */
3122 hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3124 /* disable bist test and recover it */
3125 hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3126 phy_no, SAS_BIST_ERR_CNT);
3127 hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3133 static int hisi_sas_map_queues(struct Scsi_Host *shost)
3135 struct hisi_hba *hisi_hba = shost_priv(shost);
3136 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
3138 return blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
3139 BASE_VECTORS_V3_HW);
3142 static struct scsi_host_template sht_v3_hw = {
3144 .proc_name = DRV_NAME,
3145 .module = THIS_MODULE,
3146 .queuecommand = sas_queuecommand,
3147 .dma_need_drain = ata_scsi_dma_need_drain,
3148 .target_alloc = sas_target_alloc,
3149 .slave_configure = slave_configure_v3_hw,
3150 .scan_finished = hisi_sas_scan_finished,
3151 .scan_start = hisi_sas_scan_start,
3152 .map_queues = hisi_sas_map_queues,
3153 .change_queue_depth = sas_change_queue_depth,
3154 .bios_param = sas_bios_param,
3156 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3157 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
3158 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3159 .eh_device_reset_handler = sas_eh_device_reset_handler,
3160 .eh_target_reset_handler = sas_eh_target_reset_handler,
3161 .slave_alloc = sas_slave_alloc,
3162 .target_destroy = sas_target_destroy,
3164 #ifdef CONFIG_COMPAT
3165 .compat_ioctl = sas_ioctl,
3167 .shost_attrs = host_attrs_v3_hw,
3168 .tag_alloc_policy = BLK_TAG_ALLOC_RR,
3169 .host_reset = hisi_sas_host_reset,
3173 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3174 .hw_init = hisi_sas_v3_init,
3175 .setup_itct = setup_itct_v3_hw,
3176 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3177 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3178 .clear_itct = clear_itct_v3_hw,
3179 .sl_notify_ssp = sl_notify_ssp_v3_hw,
3180 .prep_ssp = prep_ssp_v3_hw,
3181 .prep_smp = prep_smp_v3_hw,
3182 .prep_stp = prep_ata_v3_hw,
3183 .prep_abort = prep_abort_v3_hw,
3184 .start_delivery = start_delivery_v3_hw,
3185 .phys_init = phys_init_v3_hw,
3186 .phy_start = start_phy_v3_hw,
3187 .phy_disable = disable_phy_v3_hw,
3188 .phy_hard_reset = phy_hard_reset_v3_hw,
3189 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3190 .phy_set_linkrate = phy_set_linkrate_v3_hw,
3191 .dereg_device = dereg_device_v3_hw,
3192 .soft_reset = soft_reset_v3_hw,
3193 .get_phys_state = get_phys_state_v3_hw,
3194 .get_events = phy_get_events_v3_hw,
3195 .write_gpio = write_gpio_v3_hw,
3196 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3197 .debugfs_reg_array[DEBUGFS_GLOBAL] = &debugfs_global_reg,
3198 .debugfs_reg_array[DEBUGFS_AXI] = &debugfs_axi_reg,
3199 .debugfs_reg_array[DEBUGFS_RAS] = &debugfs_ras_reg,
3200 .debugfs_reg_port = &debugfs_port_reg,
3201 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw,
3202 .snapshot_restore = debugfs_snapshot_restore_v3_hw,
3203 .read_iost_itct_cache = read_iost_itct_cache_v3_hw,
3204 .set_bist = debugfs_set_bist_v3_hw,
3207 static struct Scsi_Host *
3208 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3210 struct Scsi_Host *shost;
3211 struct hisi_hba *hisi_hba;
3212 struct device *dev = &pdev->dev;
3214 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3216 dev_err(dev, "shost alloc failed\n");
3219 hisi_hba = shost_priv(shost);
3221 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3222 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler);
3223 hisi_hba->hw = &hisi_sas_v3_hw;
3224 hisi_hba->pci_dev = pdev;
3225 hisi_hba->dev = dev;
3226 hisi_hba->shost = shost;
3227 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3229 if (prot_mask & ~HISI_SAS_PROT_MASK)
3230 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3233 hisi_hba->prot_mask = prot_mask;
3235 if (hisi_sas_get_fw_info(hisi_hba) < 0)
3238 if (hisi_sas_alloc(hisi_hba)) {
3239 hisi_sas_free(hisi_hba);
3245 scsi_host_put(shost);
3246 dev_err(dev, "shost alloc failed\n");
3251 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3253 struct Scsi_Host *shost;
3254 struct hisi_hba *hisi_hba;
3255 struct device *dev = &pdev->dev;
3256 struct asd_sas_phy **arr_phy;
3257 struct asd_sas_port **arr_port;
3258 struct sas_ha_struct *sha;
3259 int rc, phy_nr, port_nr, i;
3261 rc = pci_enable_device(pdev);
3265 pci_set_master(pdev);
3267 rc = pci_request_regions(pdev, DRV_NAME);
3269 goto err_out_disable_device;
3271 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3273 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3275 dev_err(dev, "No usable DMA addressing method\n");
3277 goto err_out_regions;
3280 shost = hisi_sas_shost_alloc_pci(pdev);
3283 goto err_out_regions;
3286 sha = SHOST_TO_SAS_HA(shost);
3287 hisi_hba = shost_priv(shost);
3288 dev_set_drvdata(dev, sha);
3290 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
3291 if (!hisi_hba->regs) {
3292 dev_err(dev, "cannot map register\n");
3297 phy_nr = port_nr = hisi_hba->n_phy;
3299 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
3300 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
3301 if (!arr_phy || !arr_port) {
3306 sha->sas_phy = arr_phy;
3307 sha->sas_port = arr_port;
3308 sha->core.shost = shost;
3309 sha->lldd_ha = hisi_hba;
3311 shost->transportt = hisi_sas_stt;
3312 shost->max_id = HISI_SAS_MAX_DEVICES;
3313 shost->max_lun = ~0;
3314 shost->max_channel = 1;
3315 shost->max_cmd_len = 16;
3316 shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
3317 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
3319 sha->sas_ha_name = DRV_NAME;
3321 sha->lldd_module = THIS_MODULE;
3322 sha->sas_addr = &hisi_hba->sas_addr[0];
3323 sha->num_phys = hisi_hba->n_phy;
3325 for (i = 0; i < hisi_hba->n_phy; i++) {
3326 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
3327 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
3330 if (hisi_hba->prot_mask) {
3331 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
3333 scsi_host_set_prot(hisi_hba->shost, prot_mask);
3334 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
3335 scsi_host_set_guard(hisi_hba->shost,
3336 SHOST_DIX_GUARD_CRC);
3339 if (hisi_sas_debugfs_enable)
3340 hisi_sas_debugfs_init(hisi_hba);
3342 rc = interrupt_preinit_v3_hw(hisi_hba);
3344 goto err_out_debugfs;
3345 dev_err(dev, "%d hw queues\n", shost->nr_hw_queues);
3346 rc = scsi_add_host(shost, dev);
3348 goto err_out_debugfs;
3350 rc = sas_register_ha(sha);
3352 goto err_out_register_ha;
3354 rc = hisi_hba->hw->hw_init(hisi_hba);
3356 goto err_out_register_ha;
3358 scsi_scan_host(shost);
3361 * For the situation that there are ATA disks connected with SAS
3362 * controller, it additionally creates ata_port which will affect the
3363 * child_count of hisi_hba->dev. Even if suspended all the disks,
3364 * ata_port is still and the child_count of hisi_hba->dev is not 0.
3365 * So use pm_suspend_ignore_children() to ignore the effect to
3368 pm_suspend_ignore_children(dev, true);
3369 pm_runtime_put_noidle(&pdev->dev);
3373 err_out_register_ha:
3374 scsi_remove_host(shost);
3376 hisi_sas_debugfs_exit(hisi_hba);
3378 hisi_sas_free(hisi_hba);
3379 scsi_host_put(shost);
3381 pci_release_regions(pdev);
3382 err_out_disable_device:
3383 pci_disable_device(pdev);
3389 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
3393 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
3394 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
3395 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
3396 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
3397 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
3398 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
3400 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
3404 static void hisi_sas_v3_remove(struct pci_dev *pdev)
3406 struct device *dev = &pdev->dev;
3407 struct sas_ha_struct *sha = dev_get_drvdata(dev);
3408 struct hisi_hba *hisi_hba = sha->lldd_ha;
3409 struct Scsi_Host *shost = sha->core.shost;
3411 pm_runtime_get_noresume(dev);
3412 if (timer_pending(&hisi_hba->timer))
3413 del_timer(&hisi_hba->timer);
3415 sas_unregister_ha(sha);
3416 sas_remove_host(sha->core.shost);
3418 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
3419 pci_release_regions(pdev);
3420 pci_disable_device(pdev);
3421 hisi_sas_free(hisi_hba);
3422 hisi_sas_debugfs_exit(hisi_hba);
3423 scsi_host_put(shost);
3426 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
3428 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3429 struct hisi_hba *hisi_hba = sha->lldd_ha;
3430 struct device *dev = hisi_hba->dev;
3433 dev_info(dev, "FLR prepare\n");
3434 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3435 hisi_sas_controller_reset_prepare(hisi_hba);
3437 rc = disable_host_v3_hw(hisi_hba);
3439 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
3442 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
3444 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3445 struct hisi_hba *hisi_hba = sha->lldd_ha;
3446 struct device *dev = hisi_hba->dev;
3449 hisi_sas_init_mem(hisi_hba);
3451 rc = hw_init_v3_hw(hisi_hba);
3453 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
3457 hisi_sas_controller_reset_done(hisi_hba);
3458 dev_info(dev, "FLR done\n");
3462 /* instances of the controller */
3466 static int _suspend_v3_hw(struct device *device)
3468 struct pci_dev *pdev = to_pci_dev(device);
3469 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3470 struct hisi_hba *hisi_hba = sha->lldd_ha;
3471 struct device *dev = hisi_hba->dev;
3472 struct Scsi_Host *shost = hisi_hba->shost;
3473 pci_power_t device_state;
3476 if (!pdev->pm_cap) {
3477 dev_err(dev, "PCI PM not supported\n");
3481 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
3484 scsi_block_requests(shost);
3485 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3486 flush_workqueue(hisi_hba->wq);
3488 rc = disable_host_v3_hw(hisi_hba);
3490 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
3491 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3492 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3493 scsi_unblock_requests(shost);
3497 hisi_sas_init_mem(hisi_hba);
3499 device_state = pci_choose_state(pdev, PMSG_SUSPEND);
3500 dev_warn(dev, "entering operating state [D%d]\n",
3502 pci_save_state(pdev);
3503 pci_disable_device(pdev);
3504 pci_set_power_state(pdev, device_state);
3506 hisi_sas_release_tasks(hisi_hba);
3508 sas_suspend_ha(sha);
3512 static int _resume_v3_hw(struct device *device)
3514 struct pci_dev *pdev = to_pci_dev(device);
3515 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3516 struct hisi_hba *hisi_hba = sha->lldd_ha;
3517 struct Scsi_Host *shost = hisi_hba->shost;
3518 struct device *dev = hisi_hba->dev;
3520 pci_power_t device_state = pdev->current_state;
3522 dev_warn(dev, "resuming from operating state [D%d]\n",
3524 pci_set_power_state(pdev, PCI_D0);
3525 pci_enable_wake(pdev, PCI_D0, 0);
3526 pci_restore_state(pdev);
3527 rc = pci_enable_device(pdev);
3529 dev_err(dev, "enable device failed during resume (%d)\n", rc);
3533 pci_set_master(pdev);
3534 scsi_unblock_requests(shost);
3535 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3537 sas_prep_resume_ha(sha);
3538 rc = hw_init_v3_hw(hisi_hba);
3540 scsi_remove_host(shost);
3541 pci_disable_device(pdev);
3544 hisi_hba->hw->phys_init(hisi_hba);
3546 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3551 static int suspend_v3_hw(struct device *device)
3553 struct pci_dev *pdev = to_pci_dev(device);
3554 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3555 struct hisi_hba *hisi_hba = sha->lldd_ha;
3558 set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
3560 rc = _suspend_v3_hw(device);
3562 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
3567 static int resume_v3_hw(struct device *device)
3569 struct pci_dev *pdev = to_pci_dev(device);
3570 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3571 struct hisi_hba *hisi_hba = sha->lldd_ha;
3572 int rc = _resume_v3_hw(device);
3574 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
3579 static const struct pci_device_id sas_v3_pci_table[] = {
3580 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
3583 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
3585 static const struct pci_error_handlers hisi_sas_err_handler = {
3586 .reset_prepare = hisi_sas_reset_prepare_v3_hw,
3587 .reset_done = hisi_sas_reset_done_v3_hw,
3590 static int runtime_suspend_v3_hw(struct device *dev)
3592 return suspend_v3_hw(dev);
3595 static int runtime_resume_v3_hw(struct device *dev)
3597 return resume_v3_hw(dev);
3600 static const struct dev_pm_ops hisi_sas_v3_pm_ops = {
3601 SET_SYSTEM_SLEEP_PM_OPS(suspend_v3_hw, resume_v3_hw)
3602 SET_RUNTIME_PM_OPS(runtime_suspend_v3_hw,
3603 runtime_resume_v3_hw, NULL)
3606 static struct pci_driver sas_v3_pci_driver = {
3608 .id_table = sas_v3_pci_table,
3609 .probe = hisi_sas_v3_probe,
3610 .remove = hisi_sas_v3_remove,
3611 .err_handler = &hisi_sas_err_handler,
3612 .driver.pm = &hisi_sas_v3_pm_ops,
3615 module_pci_driver(sas_v3_pci_driver);
3616 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
3618 MODULE_LICENSE("GPL");
3619 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3620 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
3621 MODULE_ALIAS("pci:" DRV_NAME);