drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2015 Linaro Ltd.
   4  * Copyright (c) 2015 Hisilicon Limited.
   5  */
   6
   7 #include "hisi_sas.h"
   8 #define DRV_NAME "hisi_sas_v1_hw"
   9
  10 /* global registers need init*/
  11 #define DLVRY_QUEUE_ENABLE              0x0
  12 #define IOST_BASE_ADDR_LO               0x8
  13 #define IOST_BASE_ADDR_HI               0xc
  14 #define ITCT_BASE_ADDR_LO               0x10
  15 #define ITCT_BASE_ADDR_HI               0x14
  16 #define BROKEN_MSG_ADDR_LO              0x18
  17 #define BROKEN_MSG_ADDR_HI              0x1c
  18 #define PHY_CONTEXT                     0x20
  19 #define PHY_STATE                       0x24
  20 #define PHY_PORT_NUM_MA                 0x28
  21 #define PORT_STATE                      0x2c
  22 #define PHY_CONN_RATE                   0x30
  23 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  24 #define AXI_AHB_CLK_CFG                 0x3c
  25 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x84
  26 #define HGC_GET_ITV_TIME                0x90
  27 #define DEVICE_MSG_WORK_MODE            0x94
  28 #define I_T_NEXUS_LOSS_TIME             0xa0
  29 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  30 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  31 #define CFG_AGING_TIME                  0xbc
  32 #define CFG_AGING_TIME_ITCT_REL_OFF     0
  33 #define CFG_AGING_TIME_ITCT_REL_MSK     (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
  34 #define HGC_DFX_CFG2                    0xc0
  35 #define FIS_LIST_BADDR_L                0xc4
  36 #define CFG_1US_TIMER_TRSH              0xcc
  37 #define CFG_SAS_CONFIG                  0xd4
  38 #define HGC_IOST_ECC_ADDR               0x140
  39 #define HGC_IOST_ECC_ADDR_BAD_OFF       16
  40 #define HGC_IOST_ECC_ADDR_BAD_MSK       (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
  41 #define HGC_DQ_ECC_ADDR                 0x144
  42 #define HGC_DQ_ECC_ADDR_BAD_OFF         16
  43 #define HGC_DQ_ECC_ADDR_BAD_MSK         (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
  44 #define HGC_INVLD_DQE_INFO              0x148
  45 #define HGC_INVLD_DQE_INFO_DQ_OFF       0
  46 #define HGC_INVLD_DQE_INFO_DQ_MSK       (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
  47 #define HGC_INVLD_DQE_INFO_TYPE_OFF     16
  48 #define HGC_INVLD_DQE_INFO_TYPE_MSK     (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
  49 #define HGC_INVLD_DQE_INFO_FORCE_OFF    17
  50 #define HGC_INVLD_DQE_INFO_FORCE_MSK    (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
  51 #define HGC_INVLD_DQE_INFO_PHY_OFF      18
  52 #define HGC_INVLD_DQE_INFO_PHY_MSK      (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
  53 #define HGC_INVLD_DQE_INFO_ABORT_OFF    19
  54 #define HGC_INVLD_DQE_INFO_ABORT_MSK    (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
  55 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF  20
  56 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK  (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
  57 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF  21
  58 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK  (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
  59 #define HGC_INVLD_DQE_INFO_OFL_OFF      22
  60 #define HGC_INVLD_DQE_INFO_OFL_MSK      (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
  61 #define HGC_ITCT_ECC_ADDR               0x150
  62 #define HGC_ITCT_ECC_ADDR_BAD_OFF       16
  63 #define HGC_ITCT_ECC_ADDR_BAD_MSK       (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
  64 #define HGC_AXI_FIFO_ERR_INFO           0x154
  65 #define INT_COAL_EN                     0x1bc
  66 #define OQ_INT_COAL_TIME                0x1c0
  67 #define OQ_INT_COAL_CNT                 0x1c4
  68 #define ENT_INT_COAL_TIME               0x1c8
  69 #define ENT_INT_COAL_CNT                0x1cc
  70 #define OQ_INT_SRC                      0x1d0
  71 #define OQ_INT_SRC_MSK                  0x1d4
  72 #define ENT_INT_SRC1                    0x1d8
  73 #define ENT_INT_SRC2                    0x1dc
  74 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF     25
  75 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK     (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
  76 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF     27
  77 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK     (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
  78 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF  28
  79 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK  (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
  80 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
  81 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
  82 #define ENT_INT_SRC_MSK1                0x1e0
  83 #define ENT_INT_SRC_MSK2                0x1e4
  84 #define SAS_ECC_INTR                    0x1e8
  85 #define SAS_ECC_INTR_DQ_ECC1B_OFF       0
  86 #define SAS_ECC_INTR_DQ_ECC1B_MSK       (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
  87 #define SAS_ECC_INTR_DQ_ECCBAD_OFF      1
  88 #define SAS_ECC_INTR_DQ_ECCBAD_MSK      (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
  89 #define SAS_ECC_INTR_IOST_ECC1B_OFF     2
  90 #define SAS_ECC_INTR_IOST_ECC1B_MSK     (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
  91 #define SAS_ECC_INTR_IOST_ECCBAD_OFF    3
  92 #define SAS_ECC_INTR_IOST_ECCBAD_MSK    (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
  93 #define SAS_ECC_INTR_ITCT_ECC1B_OFF     4
  94 #define SAS_ECC_INTR_ITCT_ECC1B_MSK     (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
  95 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF    5
  96 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK    (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
  97 #define SAS_ECC_INTR_MSK                0x1ec
  98 #define HGC_ERR_STAT_EN                 0x238
  99 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 100 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 101 #define DLVRY_Q_0_DEPTH                 0x268
 102 #define DLVRY_Q_0_WR_PTR                0x26c
 103 #define DLVRY_Q_0_RD_PTR                0x270
 104 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 105 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 106 #define COMPL_Q_0_DEPTH                 0x4e8
 107 #define COMPL_Q_0_WR_PTR                0x4ec
 108 #define COMPL_Q_0_RD_PTR                0x4f0
 109 #define HGC_ECC_ERR                     0x7d0
 110
 111 /* phy registers need init */
 112 #define PORT_BASE                       (0x800)
 113
 114 #define PHY_CFG                         (PORT_BASE + 0x0)
 115 #define PHY_CFG_ENA_OFF                 0
 116 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 117 #define PHY_CFG_DC_OPT_OFF              2
 118 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 119 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0xc)
 120 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 121 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
 122 #define PROG_PHY_LINK_RATE_MIN_OFF      4
 123 #define PROG_PHY_LINK_RATE_MIN_MSK      (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
 124 #define PROG_PHY_LINK_RATE_OOB_OFF      8
 125 #define PROG_PHY_LINK_RATE_OOB_MSK      (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
 126 #define PHY_CTRL                        (PORT_BASE + 0x14)
 127 #define PHY_CTRL_RESET_OFF              0
 128 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 129 #define PHY_RATE_NEGO                   (PORT_BASE + 0x30)
 130 #define PHY_PCN                         (PORT_BASE + 0x44)
 131 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 132 #define SL_CONTROL                      (PORT_BASE + 0x94)
 133 #define SL_CONTROL_NOTIFY_EN_OFF        0
 134 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 135 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 136 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 137 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 138 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 139 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 140 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 141 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 142 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 143 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 144 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 145 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 146 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 147 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 148 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 149 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 150 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x12c)
 151 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
 152 #define PHY_CONFIG2                     (PORT_BASE + 0x1a8)
 153 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF  3
 154 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK  (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
 155 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF   24
 156 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK   (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
 157 #define CHL_INT0                        (PORT_BASE + 0x1b0)
 158 #define CHL_INT0_PHYCTRL_NOTRDY_OFF     0
 159 #define CHL_INT0_PHYCTRL_NOTRDY_MSK     (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
 160 #define CHL_INT0_SN_FAIL_NGR_OFF        2
 161 #define CHL_INT0_SN_FAIL_NGR_MSK        (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
 162 #define CHL_INT0_DWS_LOST_OFF           4
 163 #define CHL_INT0_DWS_LOST_MSK           (0x1 << CHL_INT0_DWS_LOST_OFF)
 164 #define CHL_INT0_SL_IDAF_FAIL_OFF       10
 165 #define CHL_INT0_SL_IDAF_FAIL_MSK       (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
 166 #define CHL_INT0_ID_TIMEOUT_OFF         11
 167 #define CHL_INT0_ID_TIMEOUT_MSK         (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
 168 #define CHL_INT0_SL_OPAF_FAIL_OFF       12
 169 #define CHL_INT0_SL_OPAF_FAIL_MSK       (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
 170 #define CHL_INT0_SL_PS_FAIL_OFF         21
 171 #define CHL_INT0_SL_PS_FAIL_MSK         (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
 172 #define CHL_INT1                        (PORT_BASE + 0x1b4)
 173 #define CHL_INT2                        (PORT_BASE + 0x1b8)
 174 #define CHL_INT2_SL_RX_BC_ACK_OFF       2
 175 #define CHL_INT2_SL_RX_BC_ACK_MSK       (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
 176 #define CHL_INT2_SL_PHY_ENA_OFF         6
 177 #define CHL_INT2_SL_PHY_ENA_MSK         (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
 178 #define CHL_INT0_MSK                    (PORT_BASE + 0x1bc)
 179 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
 180 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
 181 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c0)
 182 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c4)
 183 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 184 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 185 #define DMA_TX_STATUS_BUSY_OFF          0
 186 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 187 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 188 #define DMA_RX_STATUS_BUSY_OFF          0
 189 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 190
 191 #define AXI_CFG                         0x5100
 192 #define RESET_VALUE                     0x7ffff
 193
 194 /* HW dma structures */
 195 /* Delivery queue header */
 196 /* dw0 */
 197 #define CMD_HDR_RESP_REPORT_OFF         5
 198 #define CMD_HDR_RESP_REPORT_MSK         0x20
 199 #define CMD_HDR_TLR_CTRL_OFF            6
 200 #define CMD_HDR_TLR_CTRL_MSK            0xc0
 201 #define CMD_HDR_PORT_OFF                17
 202 #define CMD_HDR_PORT_MSK                0xe0000
 203 #define CMD_HDR_PRIORITY_OFF            27
 204 #define CMD_HDR_PRIORITY_MSK            0x8000000
 205 #define CMD_HDR_MODE_OFF                28
 206 #define CMD_HDR_MODE_MSK                0x10000000
 207 #define CMD_HDR_CMD_OFF                 29
 208 #define CMD_HDR_CMD_MSK                 0xe0000000
 209 /* dw1 */
 210 #define CMD_HDR_VERIFY_DTL_OFF          10
 211 #define CMD_HDR_VERIFY_DTL_MSK          0x400
 212 #define CMD_HDR_SSP_FRAME_TYPE_OFF      13
 213 #define CMD_HDR_SSP_FRAME_TYPE_MSK      0xe000
 214 #define CMD_HDR_DEVICE_ID_OFF           16
 215 #define CMD_HDR_DEVICE_ID_MSK           0xffff0000
 216 /* dw2 */
 217 #define CMD_HDR_CFL_OFF                 0
 218 #define CMD_HDR_CFL_MSK                 0x1ff
 219 #define CMD_HDR_MRFL_OFF                15
 220 #define CMD_HDR_MRFL_MSK                0xff8000
 221 #define CMD_HDR_FIRST_BURST_OFF         25
 222 #define CMD_HDR_FIRST_BURST_MSK         0x2000000
 223 /* dw3 */
 224 #define CMD_HDR_IPTT_OFF                0
 225 #define CMD_HDR_IPTT_MSK                0xffff
 226 /* dw6 */
 227 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 228 #define CMD_HDR_DATA_SGL_LEN_MSK        0xffff0000
 229
 230 /* Completion header */
 231 #define CMPLT_HDR_IPTT_OFF              0
 232 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 233 #define CMPLT_HDR_CMD_CMPLT_OFF         17
 234 #define CMPLT_HDR_CMD_CMPLT_MSK         (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
 235 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF     18
 236 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK     (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
 237 #define CMPLT_HDR_RSPNS_XFRD_OFF        19
 238 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 239 #define CMPLT_HDR_IO_CFG_ERR_OFF        27
 240 #define CMPLT_HDR_IO_CFG_ERR_MSK        (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
 241
 242 /* ITCT header */
 243 /* qw0 */
 244 #define ITCT_HDR_DEV_TYPE_OFF           0
 245 #define ITCT_HDR_DEV_TYPE_MSK           (0x3ULL << ITCT_HDR_DEV_TYPE_OFF)
 246 #define ITCT_HDR_VALID_OFF              2
 247 #define ITCT_HDR_VALID_MSK              (0x1ULL << ITCT_HDR_VALID_OFF)
 248 #define ITCT_HDR_AWT_CONTROL_OFF        4
 249 #define ITCT_HDR_AWT_CONTROL_MSK        (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)
 250 #define ITCT_HDR_MAX_CONN_RATE_OFF      5
 251 #define ITCT_HDR_MAX_CONN_RATE_MSK      (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)
 252 #define ITCT_HDR_VALID_LINK_NUM_OFF     9
 253 #define ITCT_HDR_VALID_LINK_NUM_MSK     (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)
 254 #define ITCT_HDR_PORT_ID_OFF            13
 255 #define ITCT_HDR_PORT_ID_MSK            (0x7ULL << ITCT_HDR_PORT_ID_OFF)
 256 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 257 #define ITCT_HDR_SMP_TIMEOUT_MSK        (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)
 258 /* qw1 */
 259 #define ITCT_HDR_MAX_SAS_ADDR_OFF       0
 260 #define ITCT_HDR_MAX_SAS_ADDR_MSK       (0xffffffffffffffff << \
 261                                         ITCT_HDR_MAX_SAS_ADDR_OFF)
 262 /* qw2 */
 263 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF   0
 264 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK   (0xffffULL << \
 265                                         ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
 266 #define ITCT_HDR_BUS_INACTIVE_TL_OFF    16
 267 #define ITCT_HDR_BUS_INACTIVE_TL_MSK    (0xffffULL << \
 268                                         ITCT_HDR_BUS_INACTIVE_TL_OFF)
 269 #define ITCT_HDR_MAX_CONN_TL_OFF        32
 270 #define ITCT_HDR_MAX_CONN_TL_MSK        (0xffffULL << \
 271                                         ITCT_HDR_MAX_CONN_TL_OFF)
 272 #define ITCT_HDR_REJ_OPEN_TL_OFF        48
 273 #define ITCT_HDR_REJ_OPEN_TL_MSK        (0xffffULL << \
 274                                         ITCT_HDR_REJ_OPEN_TL_OFF)
 275
 276 /* Err record header */
 277 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF     0
 278 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK     (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
 279 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF     16
 280 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK     (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
 281
 282 struct hisi_sas_complete_v1_hdr {
 283         __le32 data;
 284 };
 285
 286 struct hisi_sas_err_record_v1 {
 287         /* dw0 */
 288         __le32 dma_err_type;
 289
 290         /* dw1 */
 291         __le32 trans_tx_fail_type;
 292
 293         /* dw2 */
 294         __le32 trans_rx_fail_type;
 295
 296         /* dw3 */
 297         u32 rsvd;
 298 };
 299
 300 enum {
 301         HISI_SAS_PHY_BCAST_ACK = 0,
 302         HISI_SAS_PHY_SL_PHY_ENABLED,
 303         HISI_SAS_PHY_INT_ABNORMAL,
 304         HISI_SAS_PHY_INT_NR
 305 };
 306
 307 enum {
 308         DMA_TX_ERR_BASE = 0x0,
 309         DMA_RX_ERR_BASE = 0x100,
 310         TRANS_TX_FAIL_BASE = 0x200,
 311         TRANS_RX_FAIL_BASE = 0x300,
 312
 313         /* dma tx */
 314         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
 315         DMA_TX_DIF_APP_ERR, /* 0x1 */
 316         DMA_TX_DIF_RPP_ERR, /* 0x2 */
 317         DMA_TX_AXI_BUS_ERR, /* 0x3 */
 318         DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
 319         DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
 320         DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
 321         DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
 322         DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
 323         DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
 324
 325         /* dma rx */
 326         DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
 327         DMA_RX_DIF_CRC_ERR, /* 0x101 */
 328         DMA_RX_DIF_APP_ERR, /* 0x102 */
 329         DMA_RX_DIF_RPP_ERR, /* 0x103 */
 330         DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
 331         DMA_RX_AXI_BUS_ERR, /* 0x105 */
 332         DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
 333         DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
 334         DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
 335         DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
 336         DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
 337         DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
 338         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
 339
 340         /* trans tx */
 341         TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
 342         TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
 343         TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
 344         TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
 345         TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
 346         TRANS_TX_RSVD1_ERR, /* 0x205 */
 347         TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
 348         TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
 349         TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
 350         TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
 351         TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
 352         TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
 353         TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
 354         TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
 355         TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
 356         TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
 357         TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
 358         TRANS_TX_RSVD2_ERR, /* 0x211 */
 359         TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
 360         TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
 361         TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
 362         TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
 363         TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
 364         TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
 365         TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
 366         TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
 367         TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
 368         TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
 369         TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
 370         TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
 371         TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
 372         TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
 373
 374         /* trans rx */
 375         TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
 376         TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
 377         TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
 378         TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
 379         TRANS_RX_RSVD0_ERR, /* 0x304 */
 380         TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
 381         TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
 382         TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
 383         TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
 384         TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
 385         TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
 386         TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
 387         TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
 388         TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
 389         TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
 390         TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
 391         TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
 392         TRANS_RX_BAD_HASH_ERR, /* 0x311 */
 393         TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
 394         TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
 395         TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
 396         TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
 397         TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
 398         TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
 399         TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
 400         TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
 401         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
 402 };
 403
 404 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
 405 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
 406 #define HISI_SAS_FATAL_INT_NR (2)
 407
 408 #define HISI_SAS_MAX_INT_NR \
 409         (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
 410         HISI_SAS_FATAL_INT_NR)
 411
 412 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 413 {
 414         void __iomem *regs = hisi_hba->regs + off;
 415
 416         return readl(regs);
 417 }
 418
 419 static void hisi_sas_write32(struct hisi_hba *hisi_hba,
 420                                     u32 off, u32 val)
 421 {
 422         void __iomem *regs = hisi_hba->regs + off;
 423
 424         writel(val, regs);
 425 }
 426
 427 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
 428                                         int phy_no, u32 off, u32 val)
 429 {
 430         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 431
 432         writel(val, regs);
 433 }
 434
 435 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 436                                       int phy_no, u32 off)
 437 {
 438         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 439
 440         return readl(regs);
 441 }
 442
 443 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 444 {
 445         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 446
 447         cfg &= ~PHY_CFG_DC_OPT_MSK;
 448         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 449         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 450 }
 451
 452 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 453 {
 454         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
 455
 456         cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
 457         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
 458 }
 459
 460 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 461 {
 462         struct sas_identify_frame identify_frame;
 463         u32 *identify_buffer;
 464
 465         memset(&identify_frame, 0, sizeof(identify_frame));
 466         identify_frame.dev_type = SAS_END_DEVICE;
 467         identify_frame.frame_type = 0;
 468         identify_frame._un1 = 1;
 469         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 470         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 471         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 472         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 473         identify_frame.phy_id = phy_no;
 474         identify_buffer = (u32 *)(&identify_frame);
 475
 476         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 477                         __swab32(identify_buffer[0]));
 478         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 479                         __swab32(identify_buffer[1]));
 480         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 481                         __swab32(identify_buffer[2]));
 482         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 483                         __swab32(identify_buffer[3]));
 484         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 485                         __swab32(identify_buffer[4]));
 486         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 487                         __swab32(identify_buffer[5]));
 488 }
 489
 490 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
 491                              struct hisi_sas_device *sas_dev)
 492 {
 493         struct domain_device *device = sas_dev->sas_device;
 494         struct device *dev = hisi_hba->dev;
 495         u64 qw0, device_id = sas_dev->device_id;
 496         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 497         struct asd_sas_port *sas_port = device->port;
 498         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 499         u64 sas_addr;
 500
 501         memset(itct, 0, sizeof(*itct));
 502
 503         /* qw0 */
 504         qw0 = 0;
 505         switch (sas_dev->dev_type) {
 506         case SAS_END_DEVICE:
 507         case SAS_EDGE_EXPANDER_DEVICE:
 508         case SAS_FANOUT_EXPANDER_DEVICE:
 509                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 510                 break;
 511         default:
 512                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 513                          sas_dev->dev_type);
 514         }
 515
 516         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 517                 (1 << ITCT_HDR_AWT_CONTROL_OFF) |
 518                 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
 519                 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
 520                 (port->id << ITCT_HDR_PORT_ID_OFF));
 521         itct->qw0 = cpu_to_le64(qw0);
 522
 523         /* qw1 */
 524         memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 525         itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 526
 527         /* qw2 */
 528         itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
 529                                 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) |
 530                                 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) |
 531                                 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
 532 }
 533
 534 static void clear_itct_v1_hw(struct hisi_hba *hisi_hba,
 535                               struct hisi_sas_device *sas_dev)
 536 {
 537         u64 dev_id = sas_dev->device_id;
 538         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 539         u64 qw0;
 540         u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
 541
 542         reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
 543         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 544
 545         /* free itct */
 546         udelay(1);
 547         reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
 548         reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
 549         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 550
 551         qw0 = le64_to_cpu(itct->qw0);
 552         qw0 &= ~ITCT_HDR_VALID_MSK;
 553         itct->qw0 = cpu_to_le64(qw0);
 554 }
 555
 556 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
 557 {
 558         int i;
 559         unsigned long end_time;
 560         u32 val;
 561         struct device *dev = hisi_hba->dev;
 562
 563         for (i = 0; i < hisi_hba->n_phy; i++) {
 564                 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
 565
 566                 phy_ctrl |= PHY_CTRL_RESET_MSK;
 567                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
 568         }
 569         msleep(1); /* It is safe to wait for 50us */
 570
 571         /* Ensure DMA tx & rx idle */
 572         for (i = 0; i < hisi_hba->n_phy; i++) {
 573                 u32 dma_tx_status, dma_rx_status;
 574
 575                 end_time = jiffies + msecs_to_jiffies(1000);
 576
 577                 while (1) {
 578                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 579                                                             DMA_TX_STATUS);
 580                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 581                                                             DMA_RX_STATUS);
 582
 583                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 584                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 585                                 break;
 586
 587                         msleep(20);
 588                         if (time_after(jiffies, end_time))
 589                                 return -EIO;
 590                 }
 591         }
 592
 593         /* Ensure axi bus idle */
 594         end_time = jiffies + msecs_to_jiffies(1000);
 595         while (1) {
 596                 u32 axi_status =
 597                         hisi_sas_read32(hisi_hba, AXI_CFG);
 598
 599                 if (axi_status == 0)
 600                         break;
 601
 602                 msleep(20);
 603                 if (time_after(jiffies, end_time))
 604                         return -EIO;
 605         }
 606
 607         if (ACPI_HANDLE(dev)) {
 608                 acpi_status s;
 609
 610                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 611                 if (ACPI_FAILURE(s)) {
 612                         dev_err(dev, "Reset failed\n");
 613                         return -EIO;
 614                 }
 615         } else if (hisi_hba->ctrl) {
 616                 /* Apply reset and disable clock */
 617                 /* clk disable reg is offset by +4 bytes from clk enable reg */
 618                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 619                              RESET_VALUE);
 620                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 621                              RESET_VALUE);
 622                 msleep(1);
 623                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 624                 if (RESET_VALUE != (val & RESET_VALUE)) {
 625                         dev_err(dev, "Reset failed\n");
 626                         return -EIO;
 627                 }
 628
 629                 /* De-reset and enable clock */
 630                 /* deassert rst reg is offset by +4 bytes from assert reg */
 631                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 632                              RESET_VALUE);
 633                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 634                              RESET_VALUE);
 635                 msleep(1);
 636                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 637                 if (val & RESET_VALUE) {
 638                         dev_err(dev, "De-reset failed\n");
 639                         return -EIO;
 640                 }
 641         } else {
 642                 dev_warn(dev, "no reset method\n");
 643                 return -EINVAL;
 644         }
 645
 646         return 0;
 647 }
 648
 649 static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
 650 {
 651         int i;
 652
 653         /* Global registers init*/
 654         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 655                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 656         hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
 657         hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
 658         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
 659         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
 660         hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
 661         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 662         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
 663         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
 664         hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
 665         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
 666         hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
 667         hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
 668         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
 669         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
 670         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
 671         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 672         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 673         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
 674         hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
 675         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 676         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
 677         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 678         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
 679         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
 680         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
 681         hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
 682
 683         for (i = 0; i < hisi_hba->n_phy; i++) {
 684                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
 685                 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
 686                 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
 687                 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
 688                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 689                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
 690                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 691                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
 692                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
 693                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
 694                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
 695         }
 696
 697         for (i = 0; i < hisi_hba->queue_count; i++) {
 698                 /* Delivery queue */
 699                 hisi_sas_write32(hisi_hba,
 700                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 701                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 702
 703                 hisi_sas_write32(hisi_hba,
 704                                  DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 705                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 706
 707                 hisi_sas_write32(hisi_hba,
 708                                  DLVRY_Q_0_DEPTH + (i * 0x14),
 709                                  HISI_SAS_QUEUE_SLOTS);
 710
 711                 /* Completion queue */
 712                 hisi_sas_write32(hisi_hba,
 713                                  COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 714                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 715
 716                 hisi_sas_write32(hisi_hba,
 717                                  COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 718                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 719
 720                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 721                                  HISI_SAS_QUEUE_SLOTS);
 722         }
 723
 724         /* itct */
 725         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 726                          lower_32_bits(hisi_hba->itct_dma));
 727
 728         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 729                          upper_32_bits(hisi_hba->itct_dma));
 730
 731         /* iost */
 732         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 733                          lower_32_bits(hisi_hba->iost_dma));
 734
 735         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 736                          upper_32_bits(hisi_hba->iost_dma));
 737
 738         /* breakpoint */
 739         hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
 740                          lower_32_bits(hisi_hba->breakpoint_dma));
 741
 742         hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
 743                          upper_32_bits(hisi_hba->breakpoint_dma));
 744 }
 745
 746 static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
 747 {
 748         struct device *dev = hisi_hba->dev;
 749         int rc;
 750
 751         rc = reset_hw_v1_hw(hisi_hba);
 752         if (rc) {
 753                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 754                 return rc;
 755         }
 756
 757         msleep(100);
 758         init_reg_v1_hw(hisi_hba);
 759
 760         return 0;
 761 }
 762
 763 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 764 {
 765         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 766
 767         cfg |= PHY_CFG_ENA_MSK;
 768         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 769 }
 770
 771 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 772 {
 773         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 774
 775         cfg &= ~PHY_CFG_ENA_MSK;
 776         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 777 }
 778
 779 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 780 {
 781         config_id_frame_v1_hw(hisi_hba, phy_no);
 782         config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
 783         config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
 784         enable_phy_v1_hw(hisi_hba, phy_no);
 785 }
 786
 787 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 788 {
 789         hisi_sas_phy_enable(hisi_hba, phy_no, 0);
 790         msleep(100);
 791         hisi_sas_phy_enable(hisi_hba, phy_no, 1);
 792 }
 793
 794 static void start_phys_v1_hw(struct timer_list *t)
 795 {
 796         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
 797         int i;
 798
 799         for (i = 0; i < hisi_hba->n_phy; i++) {
 800                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
 801                 hisi_sas_phy_enable(hisi_hba, i, 1);
 802         }
 803 }
 804
 805 static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
 806 {
 807         int i;
 808         struct timer_list *timer = &hisi_hba->timer;
 809
 810         for (i = 0; i < hisi_hba->n_phy; i++) {
 811                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
 812                 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
 813         }
 814
 815         timer_setup(timer, start_phys_v1_hw, 0);
 816         mod_timer(timer, jiffies + HZ);
 817 }
 818
 819 static void sl_notify_ssp_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 820 {
 821         u32 sl_control;
 822
 823         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 824         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 825         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 826         msleep(1);
 827         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 828         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 829         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 830 }
 831
 832 static enum sas_linkrate phy_get_max_linkrate_v1_hw(void)
 833 {
 834         return SAS_LINK_RATE_6_0_GBPS;
 835 }
 836
 837 static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no,
 838                 struct sas_phy_linkrates *r)
 839 {
 840         enum sas_linkrate max = r->maximum_linkrate;
 841         u32 prog_phy_link_rate = 0x800;
 842
 843         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
 844         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
 845                              prog_phy_link_rate);
 846 }
 847
 848 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
 849 {
 850         int i, bitmap = 0;
 851         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 852
 853         for (i = 0; i < hisi_hba->n_phy; i++)
 854                 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 855                         bitmap |= 1 << i;
 856
 857         return bitmap;
 858 }
 859
 860 /* DQ lock must be taken here */
 861 static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
 862 {
 863         struct hisi_hba *hisi_hba = dq->hisi_hba;
 864         struct hisi_sas_slot *s, *s1, *s2 = NULL;
 865         int dlvry_queue = dq->id;
 866         int wp;
 867
 868         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
 869                 if (!s->ready)
 870                         break;
 871                 s2 = s;
 872                 list_del(&s->delivery);
 873         }
 874
 875         if (!s2)
 876                 return;
 877
 878         /*
 879          * Ensure that memories for slots built on other CPUs is observed.
 880          */
 881         smp_rmb();
 882         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
 883
 884         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
 885 }
 886
 887 static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
 888                               struct hisi_sas_slot *slot,
 889                               struct hisi_sas_cmd_hdr *hdr,
 890                               struct scatterlist *scatter,
 891                               int n_elem)
 892 {
 893         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
 894         struct scatterlist *sg;
 895         int i;
 896
 897         for_each_sg(scatter, sg, n_elem, i) {
 898                 struct hisi_sas_sge *entry = &sge_page->sge[i];
 899
 900                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 901                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 902                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 903                 entry->data_off = 0;
 904         }
 905
 906         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
 907
 908         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 909 }
 910
 911 static void prep_smp_v1_hw(struct hisi_hba *hisi_hba,
 912                           struct hisi_sas_slot *slot)
 913 {
 914         struct sas_task *task = slot->task;
 915         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 916         struct domain_device *device = task->dev;
 917         struct hisi_sas_port *port = slot->port;
 918         struct scatterlist *sg_req;
 919         struct hisi_sas_device *sas_dev = device->lldd_dev;
 920         dma_addr_t req_dma_addr;
 921         unsigned int req_len;
 922
 923         /* req */
 924         sg_req = &task->smp_task.smp_req;
 925         req_len = sg_dma_len(sg_req);
 926         req_dma_addr = sg_dma_address(sg_req);
 927
 928         /* create header */
 929         /* dw0 */
 930         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
 931                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
 932                                (1 << CMD_HDR_MODE_OFF) | /* ini mode */
 933                                (2 << CMD_HDR_CMD_OFF)); /* smp */
 934
 935         /* map itct entry */
 936         hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
 937
 938         /* dw2 */
 939         hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
 940                                (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
 941                                CMD_HDR_MRFL_OFF));
 942
 943         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
 944
 945         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
 946         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
 947 }
 948
 949 static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 950                           struct hisi_sas_slot *slot)
 951 {
 952         struct sas_task *task = slot->task;
 953         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 954         struct domain_device *device = task->dev;
 955         struct hisi_sas_device *sas_dev = device->lldd_dev;
 956         struct hisi_sas_port *port = slot->port;
 957         struct sas_ssp_task *ssp_task = &task->ssp_task;
 958         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
 959         struct hisi_sas_tmf_task *tmf = slot->tmf;
 960         int has_data = 0, priority = !!tmf;
 961         u8 *buf_cmd, fburst = 0;
 962         u32 dw1, dw2;
 963
 964         /* create header */
 965         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
 966                                (0x2 << CMD_HDR_TLR_CTRL_OFF) |
 967                                (port->id << CMD_HDR_PORT_OFF) |
 968                                (priority << CMD_HDR_PRIORITY_OFF) |
 969                                (1 << CMD_HDR_MODE_OFF) | /* ini mode */
 970                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
 971
 972         dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
 973
 974         if (tmf) {
 975                 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
 976         } else {
 977                 switch (scsi_cmnd->sc_data_direction) {
 978                 case DMA_TO_DEVICE:
 979                         dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
 980                         has_data = 1;
 981                         break;
 982                 case DMA_FROM_DEVICE:
 983                         dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
 984                         has_data = 1;
 985                         break;
 986                 default:
 987                         dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
 988                 }
 989         }
 990
 991         /* map itct entry */
 992         dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
 993         hdr->dw1 = cpu_to_le32(dw1);
 994
 995         if (tmf) {
 996                 dw2 = ((sizeof(struct ssp_tmf_iu) +
 997                         sizeof(struct ssp_frame_hdr)+3)/4) <<
 998                         CMD_HDR_CFL_OFF;
 999         } else {
1000                 dw2 = ((sizeof(struct ssp_command_iu) +
1001                         sizeof(struct ssp_frame_hdr)+3)/4) <<
1002                         CMD_HDR_CFL_OFF;
1003         }
1004
1005         dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
1006
1007         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1008
1009         if (has_data)
1010                 prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
1011                                         slot->n_elem);
1012
1013         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1014         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1015         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1016
1017         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1018                 sizeof(struct ssp_frame_hdr);
1019         if (task->ssp_task.enable_first_burst) {
1020                 fburst = (1 << 7);
1021                 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
1022         }
1023         hdr->dw2 = cpu_to_le32(dw2);
1024
1025         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1026         if (!tmf) {
1027                 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1028                                 (task->ssp_task.task_prio << 3);
1029                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1030                                 task->ssp_task.cmd->cmd_len);
1031         } else {
1032                 buf_cmd[10] = tmf->tmf;
1033                 switch (tmf->tmf) {
1034                 case TMF_ABORT_TASK:
1035                 case TMF_QUERY_TASK:
1036                         buf_cmd[12] =
1037                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1038                         buf_cmd[13] =
1039                                 tmf->tag_of_task_to_be_managed & 0xff;
1040                         break;
1041                 default:
1042                         break;
1043                 }
1044         }
1045 }
1046
1047 /* by default, task resp is complete */
1048 static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
1049                            struct sas_task *task,
1050                            struct hisi_sas_slot *slot)
1051 {
1052         struct task_status_struct *ts = &task->task_status;
1053         struct hisi_sas_err_record_v1 *err_record =
1054                         hisi_sas_status_buf_addr_mem(slot);
1055         struct device *dev = hisi_hba->dev;
1056
1057         switch (task->task_proto) {
1058         case SAS_PROTOCOL_SSP:
1059         {
1060                 int error = -1;
1061                 u32 dma_err_type = le32_to_cpu(err_record->dma_err_type);
1062                 u32 dma_tx_err_type = ((dma_err_type &
1063                                         ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
1064                                         ERR_HDR_DMA_TX_ERR_TYPE_OFF;
1065                 u32 dma_rx_err_type = ((dma_err_type &
1066                                         ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
1067                                         ERR_HDR_DMA_RX_ERR_TYPE_OFF;
1068                 u32 trans_tx_fail_type =
1069                                 le32_to_cpu(err_record->trans_tx_fail_type);
1070                 u32 trans_rx_fail_type =
1071                                 le32_to_cpu(err_record->trans_rx_fail_type);
1072
1073                 if (dma_tx_err_type) {
1074                         /* dma tx err */
1075                         error = ffs(dma_tx_err_type)
1076                                 - 1 + DMA_TX_ERR_BASE;
1077                 } else if (dma_rx_err_type) {
1078                         /* dma rx err */
1079                         error = ffs(dma_rx_err_type)
1080                                 - 1 + DMA_RX_ERR_BASE;
1081                 } else if (trans_tx_fail_type) {
1082                         /* trans tx err */
1083                         error = ffs(trans_tx_fail_type)
1084                                 - 1 + TRANS_TX_FAIL_BASE;
1085                 } else if (trans_rx_fail_type) {
1086                         /* trans rx err */
1087                         error = ffs(trans_rx_fail_type)
1088                                 - 1 + TRANS_RX_FAIL_BASE;
1089                 }
1090
1091                 switch (error) {
1092                 case DMA_TX_DATA_UNDERFLOW_ERR:
1093                 case DMA_RX_DATA_UNDERFLOW_ERR:
1094                 {
1095                         ts->residual = 0;
1096                         ts->stat = SAS_DATA_UNDERRUN;
1097                         break;
1098                 }
1099                 case DMA_TX_DATA_SGL_OVERFLOW_ERR:
1100                 case DMA_TX_DIF_SGL_OVERFLOW_ERR:
1101                 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
1102                 case DMA_RX_DATA_OVERFLOW_ERR:
1103                 case TRANS_RX_FRAME_OVERRUN_ERR:
1104                 case TRANS_RX_LINK_BUF_OVERRUN_ERR:
1105                 {
1106                         ts->stat = SAS_DATA_OVERRUN;
1107                         ts->residual = 0;
1108                         break;
1109                 }
1110                 case TRANS_TX_PHY_NOT_ENABLE_ERR:
1111                 {
1112                         ts->stat = SAS_PHY_DOWN;
1113                         break;
1114                 }
1115                 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
1116                 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
1117                 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
1118                 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
1119                 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
1120                 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
1121                 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
1122                 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
1123                 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
1124                 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
1125                 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
1126                 case TRANS_TX_OPEN_RETRY_ERR:
1127                 {
1128                         ts->stat = SAS_OPEN_REJECT;
1129                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1130                         break;
1131                 }
1132                 case TRANS_TX_OPEN_TIMEOUT_ERR:
1133                 {
1134                         ts->stat = SAS_OPEN_TO;
1135                         break;
1136                 }
1137                 case TRANS_TX_NAK_RECEIVE_ERR:
1138                 case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
1139                 {
1140                         ts->stat = SAS_NAK_R_ERR;
1141                         break;
1142                 }
1143                 case TRANS_TX_CREDIT_TIMEOUT_ERR:
1144                 case TRANS_TX_CLOSE_NORMAL_ERR:
1145                 {
1146                         /* This will request a retry */
1147                         ts->stat = SAS_QUEUE_FULL;
1148                         slot->abort = 1;
1149                         break;
1150                 }
1151                 default:
1152                 {
1153                         ts->stat = SAM_STAT_CHECK_CONDITION;
1154                         break;
1155                 }
1156                 }
1157         }
1158                 break;
1159         case SAS_PROTOCOL_SMP:
1160                 ts->stat = SAM_STAT_CHECK_CONDITION;
1161                 break;
1162
1163         case SAS_PROTOCOL_SATA:
1164         case SAS_PROTOCOL_STP:
1165         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1166         {
1167                 dev_err(dev, "slot err: SATA/STP not supported");
1168         }
1169                 break;
1170         default:
1171                 break;
1172         }
1173
1174 }
1175
1176 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1177                                struct hisi_sas_slot *slot)
1178 {
1179         struct sas_task *task = slot->task;
1180         struct hisi_sas_device *sas_dev;
1181         struct device *dev = hisi_hba->dev;
1182         struct task_status_struct *ts;
1183         struct domain_device *device;
1184         enum exec_status sts;
1185         struct hisi_sas_complete_v1_hdr *complete_queue =
1186                         hisi_hba->complete_hdr[slot->cmplt_queue];
1187         struct hisi_sas_complete_v1_hdr *complete_hdr;
1188         unsigned long flags;
1189         u32 cmplt_hdr_data;
1190
1191         complete_hdr = &complete_queue[slot->cmplt_queue_slot];
1192         cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1193
1194         if (unlikely(!task || !task->lldd_task || !task->dev))
1195                 return -EINVAL;
1196
1197         ts = &task->task_status;
1198         device = task->dev;
1199         sas_dev = device->lldd_dev;
1200
1201         spin_lock_irqsave(&task->task_state_lock, flags);
1202         task->task_state_flags &=
1203                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1204         task->task_state_flags |= SAS_TASK_STATE_DONE;
1205         spin_unlock_irqrestore(&task->task_state_lock, flags);
1206
1207         memset(ts, 0, sizeof(*ts));
1208         ts->resp = SAS_TASK_COMPLETE;
1209
1210         if (unlikely(!sas_dev)) {
1211                 dev_dbg(dev, "slot complete: port has no device\n");
1212                 ts->stat = SAS_PHY_DOWN;
1213                 goto out;
1214         }
1215
1216         if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
1217                 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
1218
1219                 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
1220                         dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
1221                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1222
1223                 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
1224                         dev_err(dev, "slot complete: [%d:%d] has dq type err",
1225                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1226
1227                 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
1228                         dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
1229                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1230
1231                 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
1232                         dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
1233                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1234
1235                 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
1236                         dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
1237                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1238
1239                 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
1240                         dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
1241                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1242
1243                 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
1244                         dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
1245                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1246
1247                 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
1248                         dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
1249                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1250
1251                 ts->stat = SAS_OPEN_REJECT;
1252                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1253                 goto out;
1254         }
1255
1256         if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK &&
1257                 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
1258
1259                 slot_err_v1_hw(hisi_hba, task, slot);
1260                 if (unlikely(slot->abort))
1261                         return ts->stat;
1262                 goto out;
1263         }
1264
1265         switch (task->task_proto) {
1266         case SAS_PROTOCOL_SSP:
1267         {
1268                 struct hisi_sas_status_buffer *status_buffer =
1269                                 hisi_sas_status_buf_addr_mem(slot);
1270                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
1271                                 &status_buffer->iu[0];
1272
1273                 sas_ssp_task_response(dev, task, iu);
1274                 break;
1275         }
1276         case SAS_PROTOCOL_SMP:
1277         {
1278                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1279                 void *to = page_address(sg_page(sg_resp));
1280
1281                 ts->stat = SAM_STAT_GOOD;
1282
1283                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1284                              DMA_TO_DEVICE);
1285                 memcpy(to + sg_resp->offset,
1286                        hisi_sas_status_buf_addr_mem(slot) +
1287                        sizeof(struct hisi_sas_err_record),
1288                        sg_resp->length);
1289                 break;
1290         }
1291         case SAS_PROTOCOL_SATA:
1292         case SAS_PROTOCOL_STP:
1293         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1294                 dev_err(dev, "slot complete: SATA/STP not supported");
1295                 break;
1296
1297         default:
1298                 ts->stat = SAM_STAT_CHECK_CONDITION;
1299                 break;
1300         }
1301
1302         if (!slot->port->port_attached) {
1303                 dev_err(dev, "slot complete: port %d has removed\n",
1304                         slot->port->sas_port.id);
1305                 ts->stat = SAS_PHY_DOWN;
1306         }
1307
1308 out:
1309         hisi_sas_slot_task_free(hisi_hba, task, slot);
1310         sts = ts->stat;
1311
1312         if (task->task_done)
1313                 task->task_done(task);
1314
1315         return sts;
1316 }
1317
1318 /* Interrupts */
1319 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
1320 {
1321         struct hisi_sas_phy *phy = p;
1322         struct hisi_hba *hisi_hba = phy->hisi_hba;
1323         struct device *dev = hisi_hba->dev;
1324         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1325         int i, phy_no = sas_phy->id;
1326         u32 irq_value, context, port_id, link_rate;
1327         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1328         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1329         irqreturn_t res = IRQ_HANDLED;
1330         unsigned long flags;
1331
1332         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1333         if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
1334                 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
1335                         irq_value);
1336                 res = IRQ_NONE;
1337                 goto end;
1338         }
1339
1340         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1341         if (context & 1 << phy_no) {
1342                 dev_err(dev, "phyup: phy%d SATA attached equipment\n",
1343                         phy_no);
1344                 goto end;
1345         }
1346
1347         port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
1348                   & 0xf;
1349         if (port_id == 0xf) {
1350                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1351                 res = IRQ_NONE;
1352                 goto end;
1353         }
1354
1355         for (i = 0; i < 6; i++) {
1356                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1357                                         RX_IDAF_DWORD0 + (i * 4));
1358                 frame_rcvd[i] = __swab32(idaf);
1359         }
1360
1361         /* Get the linkrate */
1362         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1363         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1364         sas_phy->linkrate = link_rate;
1365         sas_phy->oob_mode = SAS_OOB_MODE;
1366         memcpy(sas_phy->attached_sas_addr,
1367                 &id->sas_addr, SAS_ADDR_SIZE);
1368         dev_info(dev, "phyup: phy%d link_rate=%d\n",
1369                  phy_no, link_rate);
1370         phy->port_id = port_id;
1371         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1372         phy->phy_type |= PORT_TYPE_SAS;
1373         phy->phy_attached = 1;
1374         phy->identify.device_type = id->dev_type;
1375         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
1376         if (phy->identify.device_type == SAS_END_DEVICE)
1377                 phy->identify.target_port_protocols =
1378                         SAS_PROTOCOL_SSP;
1379         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1380                 phy->identify.target_port_protocols =
1381                         SAS_PROTOCOL_SMP;
1382         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1383
1384         spin_lock_irqsave(&phy->lock, flags);
1385         if (phy->reset_completion) {
1386                 phy->in_reset = 0;
1387                 complete(phy->reset_completion);
1388         }
1389         spin_unlock_irqrestore(&phy->lock, flags);
1390
1391 end:
1392         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1393                              CHL_INT2_SL_PHY_ENA_MSK);
1394
1395         if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
1396                 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1397
1398                 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
1399                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
1400                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
1401         }
1402
1403         return res;
1404 }
1405
1406 static irqreturn_t int_bcast_v1_hw(int irq, void *p)
1407 {
1408         struct hisi_sas_phy *phy = p;
1409         struct hisi_hba *hisi_hba = phy->hisi_hba;
1410         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1411         struct sas_ha_struct *sha = &hisi_hba->sha;
1412         struct device *dev = hisi_hba->dev;
1413         int phy_no = sas_phy->id;
1414         u32 irq_value;
1415         irqreturn_t res = IRQ_HANDLED;
1416
1417         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1418
1419         if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1420                 dev_err(dev, "bcast: irq_value = %x not set enable bit",
1421                         irq_value);
1422                 res = IRQ_NONE;
1423                 goto end;
1424         }
1425
1426         if (!test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1427                 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1428
1429 end:
1430         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1431                              CHL_INT2_SL_RX_BC_ACK_MSK);
1432
1433         return res;
1434 }
1435
1436 static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
1437 {
1438         struct hisi_sas_phy *phy = p;
1439         struct hisi_hba *hisi_hba = phy->hisi_hba;
1440         struct device *dev = hisi_hba->dev;
1441         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1442         u32 irq_value, irq_mask_old;
1443         int phy_no = sas_phy->id;
1444
1445         /* mask_int0 */
1446         irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
1447         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
1448
1449         /* read int0 */
1450         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1451
1452         if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
1453                 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1454
1455                 hisi_sas_phy_down(hisi_hba, phy_no,
1456                                   (phy_state & 1 << phy_no) ? 1 : 0);
1457         }
1458
1459         if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
1460                 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
1461                         phy_no);
1462
1463         if (irq_value & CHL_INT0_DWS_LOST_MSK)
1464                 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
1465
1466         if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
1467                 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
1468                         phy_no);
1469
1470         if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
1471                 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
1472                 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
1473                         phy_no);
1474
1475         if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
1476                 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
1477
1478         /* write to zero */
1479         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
1480
1481         if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
1482                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1483                                 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1484         else
1485                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1486                                 irq_mask_old);
1487
1488         return IRQ_HANDLED;
1489 }
1490
1491 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
1492 {
1493         struct hisi_sas_cq *cq = p;
1494         struct hisi_hba *hisi_hba = cq->hisi_hba;
1495         struct hisi_sas_slot *slot;
1496         int queue = cq->id;
1497         struct hisi_sas_complete_v1_hdr *complete_queue =
1498                         (struct hisi_sas_complete_v1_hdr *)
1499                         hisi_hba->complete_hdr[queue];
1500         u32 rd_point = cq->rd_point, wr_point;
1501
1502         spin_lock(&hisi_hba->lock);
1503         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1504         wr_point = hisi_sas_read32(hisi_hba,
1505                         COMPL_Q_0_WR_PTR + (0x14 * queue));
1506
1507         while (rd_point != wr_point) {
1508                 struct hisi_sas_complete_v1_hdr *complete_hdr;
1509                 int idx;
1510                 u32 cmplt_hdr_data;
1511
1512                 complete_hdr = &complete_queue[rd_point];
1513                 cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1514                 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
1515                       CMPLT_HDR_IPTT_OFF;
1516                 slot = &hisi_hba->slot_info[idx];
1517
1518                 /* The completion queue and queue slot index are not
1519                  * necessarily the same as the delivery queue and
1520                  * queue slot index.
1521                  */
1522                 slot->cmplt_queue_slot = rd_point;
1523                 slot->cmplt_queue = queue;
1524                 slot_complete_v1_hw(hisi_hba, slot);
1525
1526                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1527                         rd_point = 0;
1528         }
1529
1530         /* update rd_point */
1531         cq->rd_point = rd_point;
1532         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1533         spin_unlock(&hisi_hba->lock);
1534
1535         return IRQ_HANDLED;
1536 }
1537
1538 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
1539 {
1540         struct hisi_hba *hisi_hba = p;
1541         struct device *dev = hisi_hba->dev;
1542         u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1543
1544         if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
1545                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1546
1547                 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
1548                       dev_name(dev), ecc_err);
1549         }
1550
1551         if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
1552                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
1553                                 HGC_DQ_ECC_ADDR_BAD_MSK) >>
1554                                 HGC_DQ_ECC_ADDR_BAD_OFF;
1555
1556                 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
1557                       dev_name(dev), addr);
1558         }
1559
1560         if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
1561                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1562
1563                 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
1564                       dev_name(dev), ecc_err);
1565         }
1566
1567         if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
1568                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
1569                                 HGC_IOST_ECC_ADDR_BAD_MSK) >>
1570                                 HGC_IOST_ECC_ADDR_BAD_OFF;
1571
1572                 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
1573                       dev_name(dev), addr);
1574         }
1575
1576         if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
1577                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
1578                                 HGC_ITCT_ECC_ADDR_BAD_MSK) >>
1579                                 HGC_ITCT_ECC_ADDR_BAD_OFF;
1580
1581                 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
1582                       dev_name(dev), addr);
1583         }
1584
1585         if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
1586                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1587
1588                 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
1589                       dev_name(dev), ecc_err);
1590         }
1591
1592         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
1593
1594         return IRQ_HANDLED;
1595 }
1596
1597 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
1598 {
1599         struct hisi_hba *hisi_hba = p;
1600         struct device *dev = hisi_hba->dev;
1601         u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
1602         u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
1603
1604         if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
1605                 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
1606                       dev_name(dev), axi_info);
1607
1608         if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
1609                 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
1610                       dev_name(dev), axi_info);
1611
1612         if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
1613                 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
1614                       dev_name(dev), axi_info);
1615
1616         if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
1617                 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
1618                       dev_name(dev), axi_info);
1619
1620         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
1621
1622         return IRQ_HANDLED;
1623 }
1624
1625 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1626         int_bcast_v1_hw,
1627         int_phyup_v1_hw,
1628         int_abnormal_v1_hw
1629 };
1630
1631 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
1632         fatal_ecc_int_v1_hw,
1633         fatal_axi_int_v1_hw
1634 };
1635
1636 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
1637 {
1638         struct platform_device *pdev = hisi_hba->platform_dev;
1639         struct device *dev = &pdev->dev;
1640         int i, j, irq, rc, idx;
1641
1642         for (i = 0; i < hisi_hba->n_phy; i++) {
1643                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1644
1645                 idx = i * HISI_SAS_PHY_INT_NR;
1646                 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
1647                         irq = platform_get_irq(pdev, idx);
1648                         if (irq < 0) {
1649                                 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1650                                         idx);
1651                                 return irq;
1652                         }
1653
1654                         rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
1655                                               DRV_NAME " phy", phy);
1656                         if (rc) {
1657                                 dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
1658                                         irq, rc);
1659                                 return rc;
1660                         }
1661                 }
1662         }
1663
1664         idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
1665         for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
1666                 irq = platform_get_irq(pdev, idx);
1667                 if (irq < 0) {
1668                         dev_err(dev, "irq init: could not map cq interrupt %d\n",
1669                                 idx);
1670                         return irq;
1671                 }
1672
1673                 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
1674                                       DRV_NAME " cq", &hisi_hba->cq[i]);
1675                 if (rc) {
1676                         dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
1677                                 irq, rc);
1678                         return rc;
1679                 }
1680         }
1681
1682         idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
1683         for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
1684                 irq = platform_get_irq(pdev, idx);
1685                 if (irq < 0) {
1686                         dev_err(dev, "irq init: could not map fatal interrupt %d\n",
1687                                 idx);
1688                         return irq;
1689                 }
1690
1691                 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
1692                                       DRV_NAME " fatal", hisi_hba);
1693                 if (rc) {
1694                         dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
1695                                 irq, rc);
1696                         return rc;
1697                 }
1698         }
1699
1700         hisi_hba->cq_nvecs = hisi_hba->queue_count;
1701
1702         return 0;
1703 }
1704
1705 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
1706 {
1707         int i;
1708         u32 val;
1709
1710         for (i = 0; i < hisi_hba->n_phy; i++) {
1711                 /* Clear interrupt status */
1712                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
1713                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
1714                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
1715                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
1716                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
1717                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
1718
1719                 /* Unmask interrupt */
1720                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
1721                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
1722                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
1723
1724                 /* bypass chip bug mask abnormal intr */
1725                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK,
1726                                 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1727         }
1728
1729         return 0;
1730 }
1731
1732 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
1733 {
1734         int rc;
1735
1736         rc = hw_init_v1_hw(hisi_hba);
1737         if (rc)
1738                 return rc;
1739
1740         rc = interrupt_init_v1_hw(hisi_hba);
1741         if (rc)
1742                 return rc;
1743
1744         rc = interrupt_openall_v1_hw(hisi_hba);
1745         if (rc)
1746                 return rc;
1747
1748         return 0;
1749 }
1750
1751 static struct device_attribute *host_attrs_v1_hw[] = {
1752         &dev_attr_phy_event_threshold,
1753         NULL
1754 };
1755
1756 static struct scsi_host_template sht_v1_hw = {
1757         .name                   = DRV_NAME,
1758         .module                 = THIS_MODULE,
1759         .queuecommand           = sas_queuecommand,
1760         .target_alloc           = sas_target_alloc,
1761         .slave_configure        = hisi_sas_slave_configure,
1762         .scan_finished          = hisi_sas_scan_finished,
1763         .scan_start             = hisi_sas_scan_start,
1764         .change_queue_depth     = sas_change_queue_depth,
1765         .bios_param             = sas_bios_param,
1766         .this_id                = -1,
1767         .sg_tablesize           = HISI_SAS_SGE_PAGE_CNT,
1768         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
1769         .eh_device_reset_handler = sas_eh_device_reset_handler,
1770         .eh_target_reset_handler = sas_eh_target_reset_handler,
1771         .slave_alloc            = sas_slave_alloc,
1772         .target_destroy         = sas_target_destroy,
1773         .ioctl                  = sas_ioctl,
1774         .shost_attrs            = host_attrs_v1_hw,
1775         .host_reset             = hisi_sas_host_reset,
1776 };
1777
1778 static const struct hisi_sas_hw hisi_sas_v1_hw = {
1779         .hw_init = hisi_sas_v1_init,
1780         .setup_itct = setup_itct_v1_hw,
1781         .sl_notify_ssp = sl_notify_ssp_v1_hw,
1782         .clear_itct = clear_itct_v1_hw,
1783         .prep_smp = prep_smp_v1_hw,
1784         .prep_ssp = prep_ssp_v1_hw,
1785         .start_delivery = start_delivery_v1_hw,
1786         .phys_init = phys_init_v1_hw,
1787         .phy_start = start_phy_v1_hw,
1788         .phy_disable = disable_phy_v1_hw,
1789         .phy_hard_reset = phy_hard_reset_v1_hw,
1790         .phy_set_linkrate = phy_set_linkrate_v1_hw,
1791         .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw,
1792         .get_wideport_bitmap = get_wideport_bitmap_v1_hw,
1793         .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
1794         .sht = &sht_v1_hw,
1795 };
1796
1797 static int hisi_sas_v1_probe(struct platform_device *pdev)
1798 {
1799         return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
1800 }
1801
1802 static int hisi_sas_v1_remove(struct platform_device *pdev)
1803 {
1804         return hisi_sas_remove(pdev);
1805 }
1806
1807 static const struct of_device_id sas_v1_of_match[] = {
1808         { .compatible = "hisilicon,hip05-sas-v1",},
1809         {},
1810 };
1811 MODULE_DEVICE_TABLE(of, sas_v1_of_match);
1812
1813 static const struct acpi_device_id sas_v1_acpi_match[] = {
1814         { "HISI0161", 0 },
1815         { }
1816 };
1817
1818 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match);
1819
1820 static struct platform_driver hisi_sas_v1_driver = {
1821         .probe = hisi_sas_v1_probe,
1822         .remove = hisi_sas_v1_remove,
1823         .driver = {
1824                 .name = DRV_NAME,
1825                 .of_match_table = sas_v1_of_match,
1826                 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match),
1827         },
1828 };
1829
1830 module_platform_driver(hisi_sas_v1_driver);
1831
1832 MODULE_LICENSE("GPL");
1833 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1834 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
1835 MODULE_ALIAS("platform:" DRV_NAME);