2 * Copyright 2017 Broadcom. All Rights Reserved.
3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@broadcom.com
15 #ifndef _BEISCSI_MAIN_
16 #define _BEISCSI_MAIN_
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/if_ether.h>
22 #include <linux/ctype.h>
23 #include <linux/module.h>
24 #include <linux/aer.h>
25 #include <scsi/scsi.h>
26 #include <scsi/scsi_cmnd.h>
27 #include <scsi/scsi_device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/iscsi_proto.h>
30 #include <scsi/libiscsi.h>
31 #include <scsi/scsi_transport_iscsi.h>
33 #define DRV_NAME "be2iscsi"
34 #define BUILD_STR "11.4.0.0"
35 #define BE_NAME "Emulex OneConnect" \
36 "Open-iSCSI Driver version" BUILD_STR
37 #define DRV_DESC BE_NAME " " "Driver"
39 #define BE_VENDOR_ID 0x19A2
40 #define ELX_VENDOR_ID 0x10DF
41 /* DEVICE ID's for BE2 */
42 #define BE_DEVICE_ID1 0x212
43 #define OC_DEVICE_ID1 0x702
44 #define OC_DEVICE_ID2 0x703
46 /* DEVICE ID's for BE3 */
47 #define BE_DEVICE_ID2 0x222
48 #define OC_DEVICE_ID3 0x712
50 /* DEVICE ID for SKH */
51 #define OC_SKH_ID1 0x722
53 #define BE2_IO_DEPTH 1024
54 #define BE2_MAX_SESSIONS 256
56 #define BE2_NOPOUT_REQ 16
58 #define BE2_DEFPDU_HDR_SZ 64
59 #define BE2_DEFPDU_DATA_SZ 8192
60 #define BE2_MAX_NUM_CQ_PROC 512
63 #define BEISCSI_MAX_NUM_CPUS 7
65 #define BEISCSI_VER_STRLEN 32
67 #define BEISCSI_SGLIST_ELEMENTS 30
70 * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
71 * be invalidated at a time, consider it before changing the value of
72 * BEISCSI_CMD_PER_LUN.
74 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
75 #define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
76 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
78 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
79 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
80 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
81 #define BEISCSI_MAX_FRAGS_INIT 192
82 #define BE_NUM_MSIX_ENTRIES 1
84 #define BE_SENSE_INFO_SIZE 258
85 #define BE_ISCSI_PDU_HEADER_SIZE 64
86 #define BE_MIN_MEM_SIZE 16384
87 #define MAX_CMD_SZ 65536
88 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
91 * hardware needs the async PDU buffers to be posted in multiples of 8
92 * So have atleast 8 of them by default
95 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
96 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
98 /********* Memory BAR register ************/
99 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
101 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
102 * Disable" may still globally block interrupts in addition to individual
103 * interrupt masks; a mechanism for the device driver to block all interrupts
104 * atomically without having to arbitrate for the PCI Interrupt Disable bit
107 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
109 /********* ISR0 Register offset **********/
110 #define CEV_ISR0_OFFSET 0xC18
111 #define CEV_ISR_SIZE 4
114 * Macros for reading/writing a protection domain or CSR registers
118 #define DB_TXULP0_OFFSET 0x40
119 #define DB_RXULP0_OFFSET 0xA0
120 /********* Event Q door bell *************/
121 #define DB_EQ_OFFSET DB_CQ_OFFSET
122 #define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
123 /* Clear the interrupt for this eq */
124 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
126 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
127 /* Higher Order EQ_ID bit */
128 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
129 #define DB_EQ_HIGH_SET_SHIFT 11
130 #define DB_EQ_HIGH_FEILD_SHIFT 9
131 /* Number of event entries processed */
132 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
134 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
136 /********* Compl Q door bell *************/
137 #define DB_CQ_OFFSET 0x120
138 #define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
139 /* Higher Order CQ_ID bit */
140 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
141 #define DB_CQ_HIGH_SET_SHIFT 11
142 #define DB_CQ_HIGH_FEILD_SHIFT 10
144 /* Number of event entries processed */
145 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
147 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
149 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
150 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
151 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
152 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
153 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
155 #define PAGES_REQUIRED(x) \
156 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
158 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
160 #define MEM_DESCR_OFFSET 8
161 #define BEISCSI_DEFQ_HDR 1
162 #define BEISCSI_DEFQ_DATA 0
164 HWI_MEM_ADDN_CONTEXT,
169 HWI_MEM_TEMPLATE_HDR_ULP0,
170 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
171 HWI_MEM_ASYNC_DATA_BUF_ULP0,
172 HWI_MEM_ASYNC_HEADER_RING_ULP0,
173 HWI_MEM_ASYNC_DATA_RING_ULP0,
174 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
175 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
176 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
177 HWI_MEM_TEMPLATE_HDR_ULP1,
178 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
179 HWI_MEM_ASYNC_DATA_BUF_ULP1,
180 HWI_MEM_ASYNC_HEADER_RING_ULP1,
181 HWI_MEM_ASYNC_DATA_RING_ULP1,
182 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
183 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
184 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
185 ISCSI_MEM_GLOBAL_HEADER,
189 struct be_bus_address32 {
190 unsigned int address_lo;
191 unsigned int address_hi;
194 struct be_bus_address64 {
195 unsigned long long address;
198 struct be_bus_address {
200 struct be_bus_address32 a32;
201 struct be_bus_address64 a64;
206 struct be_bus_address bus_address; /* Bus address of location */
207 void *virtual_address; /* virtual address to the location */
208 unsigned int size; /* Size required by memory block */
211 struct be_mem_descriptor {
212 unsigned int index; /* Index of this memory parameter */
213 unsigned int category; /* type indicates cached/non-cached */
214 unsigned int num_elements; /* number of elements in this
217 unsigned int alignment_mask; /* Alignment mask for this block */
218 unsigned int size_in_bytes; /* Size required by memory block */
219 struct mem_array *mem_array;
223 unsigned int sgl_index;
226 struct iscsi_task *task;
227 struct iscsi_sge *pfrag;
230 struct hba_parameters {
231 unsigned int ios_per_ctrl;
232 unsigned int cxns_per_ctrl;
233 unsigned int icds_per_ctrl;
234 unsigned int num_sge_per_io;
235 unsigned int defpdu_hdr_sz;
236 unsigned int defpdu_data_sz;
237 unsigned int num_cq_entries;
238 unsigned int num_eq_entries;
239 unsigned int wrbs_per_cxn;
240 unsigned int hwi_ws_sz;
242 * These are calculated from other params. They're here
245 unsigned int num_mcc_pages;
246 unsigned int num_mcc_cq_pages;
247 unsigned int num_cq_pages;
248 unsigned int num_eq_pages;
250 unsigned int num_async_pdu_buf_pages;
251 unsigned int num_async_pdu_buf_sgl_pages;
252 unsigned int num_async_pdu_buf_cq_pages;
254 unsigned int num_async_pdu_hdr_pages;
255 unsigned int num_async_pdu_hdr_sgl_pages;
256 unsigned int num_async_pdu_hdr_cq_pages;
258 unsigned int num_sge;
261 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
262 (phwi_ctrlr->wrb_context[cri].ulp_num)
263 struct hwi_wrb_context {
265 struct list_head wrb_handle_list;
266 struct list_head wrb_handle_drvr_list;
267 struct wrb_handle **pwrb_handle_base;
268 struct wrb_handle **pwrb_handle_basestd;
269 struct iscsi_wrb *plast_wrb;
270 unsigned short alloc_index;
271 unsigned short free_index;
272 unsigned short wrb_handles_available;
274 uint8_t ulp_num; /* ULP to which CID binded */
275 uint16_t register_set;
276 uint16_t doorbell_format;
277 uint32_t doorbell_offset;
280 struct ulp_cid_info {
281 unsigned short *cid_array;
282 unsigned short avlbl_cids;
283 unsigned short cid_alloc;
284 unsigned short cid_free;
288 #define chip_be2(phba) (phba->generation == BE_GEN2)
289 #define chip_be3_r(phba) (phba->generation == BE_GEN3)
290 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
292 #define BEISCSI_ULP0 0
293 #define BEISCSI_ULP1 1
294 #define BEISCSI_ULP_COUNT 2
295 #define BEISCSI_ULP0_LOADED 0x01
296 #define BEISCSI_ULP1_LOADED 0x02
298 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
299 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
300 #define BEISCSI_ULP0_AVLBL_CID(phba) \
301 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
302 #define BEISCSI_ULP1_AVLBL_CID(phba) \
303 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
306 struct hba_parameters params;
307 struct hwi_controller *phwi_ctrlr;
308 unsigned int mem_req[SE_MEM_MAX];
309 /* PCI BAR mapped addresses */
310 u8 __iomem *csr_va; /* CSR */
311 u8 __iomem *db_va; /* Door Bell */
312 u8 __iomem *pci_va; /* PCI Config */
313 struct be_bus_address csr_pa; /* CSR */
314 struct be_bus_address db_pa; /* CSR */
315 struct be_bus_address pci_pa; /* CSR */
316 /* PCI representation of our HBA */
317 struct pci_dev *pcidev;
318 unsigned int num_cpus;
319 unsigned int nxt_cqid;
320 char *msi_name[MAX_CPUS];
321 struct be_mem_descriptor *init_mem;
323 unsigned short io_sgl_alloc_index;
324 unsigned short io_sgl_free_index;
325 unsigned short io_sgl_hndl_avbl;
326 struct sgl_handle **io_sgl_hndl_base;
327 struct sgl_handle **sgl_hndl_array;
329 unsigned short eh_sgl_alloc_index;
330 unsigned short eh_sgl_free_index;
331 unsigned short eh_sgl_hndl_avbl;
332 struct sgl_handle **eh_sgl_hndl_base;
333 spinlock_t io_sgl_lock;
334 spinlock_t mgmt_sgl_lock;
335 spinlock_t async_pdu_lock;
336 struct list_head hba_queue;
337 #define BE_MAX_SESSION 2048
338 #define BE_INVALID_CID 0xffff
339 #define BE_SET_CID_TO_CRI(cri_index, cid) \
340 (phba->cid_to_cri_map[cid] = cri_index)
341 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
342 unsigned short cid_to_cri_map[BE_MAX_SESSION];
343 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
344 struct iscsi_endpoint **ep_array;
345 struct beiscsi_conn **conn_table;
346 struct Scsi_Host *shost;
347 struct iscsi_iface *ipv4_iface;
348 struct iscsi_iface *ipv6_iface;
351 * group together since they are used most frequently
352 * for cid to cri conversion
354 #define BEISCSI_PHYS_PORT_MAX 4
355 unsigned int phys_port;
356 /* valid values of phys_port id are 0, 1, 2, 3 */
357 unsigned int eqid_count;
358 unsigned int cqid_count;
359 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
360 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
361 (phba->fw_config.iscsi_cid_count[ulp_num])
362 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
363 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
364 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
365 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
366 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
368 unsigned short iscsi_features;
369 uint16_t dual_ulp_aware;
370 unsigned long ulp_supported;
374 #define BEISCSI_HBA_ONLINE 0
375 #define BEISCSI_HBA_LINK_UP 1
376 #define BEISCSI_HBA_BOOT_FOUND 2
377 #define BEISCSI_HBA_BOOT_WORK 3
378 #define BEISCSI_HBA_UER_SUPP 4
379 #define BEISCSI_HBA_PCI_ERR 5
380 #define BEISCSI_HBA_FW_TIMEOUT 6
381 #define BEISCSI_HBA_IN_UE 7
382 #define BEISCSI_HBA_IN_TPE 8
385 #define BEISCSI_HBA_IN_ERR ((1 << BEISCSI_HBA_PCI_ERR) | \
386 (1 << BEISCSI_HBA_FW_TIMEOUT) | \
387 (1 << BEISCSI_HBA_IN_UE) | \
388 (1 << BEISCSI_HBA_IN_TPE))
391 struct delayed_work eqd_update;
392 /* update EQ delay timer every 1000ms */
393 #define BEISCSI_EQD_UPDATE_INTERVAL 1000
394 struct timer_list hw_check;
395 /* check for UE every 1000ms */
396 #define BEISCSI_UE_DETECT_INTERVAL 1000
398 struct delayed_work recover_port;
399 struct work_struct sess_work;
402 u8 mac_address[ETH_ALEN];
405 char fw_ver_str[BEISCSI_VER_STRLEN];
406 struct workqueue_struct *wq; /* The actuak work queue */
407 struct be_ctrl_info ctrl;
408 unsigned int generation;
409 unsigned int interface_handle;
411 struct be_aic_obj aic_obj[MAX_CPUS];
412 unsigned int attr_log_enable;
413 int (*iotask_fn)(struct iscsi_task *,
414 struct scatterlist *sg,
415 uint32_t num_sg, uint32_t xferlen,
420 unsigned int s_handle;
421 struct be_dma_mem nonemb_cmd;
423 BEISCSI_BOOT_REOPEN_SESS = 1,
424 BEISCSI_BOOT_GET_SHANDLE,
425 BEISCSI_BOOT_GET_SINFO,
426 BEISCSI_BOOT_LOGOUT_SESS,
427 BEISCSI_BOOT_CREATE_KSET,
429 struct mgmt_session_info boot_sess;
430 struct iscsi_boot_kset *boot_kset;
432 struct work_struct boot_work;
435 #define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
436 #define beiscsi_hba_is_online(phba) \
437 (!beiscsi_hba_in_error((phba)) && \
438 test_bit(BEISCSI_HBA_ONLINE, &phba->state))
440 struct beiscsi_session {
441 struct dma_pool *bhs_pool;
445 * struct beiscsi_conn - iscsi connection structure
447 struct beiscsi_conn {
448 struct iscsi_conn *conn;
449 struct beiscsi_hba *phba;
452 u32 beiscsi_conn_cid;
453 struct beiscsi_endpoint *ep;
454 unsigned short login_in_progress;
455 struct wrb_handle *plogin_wrb_handle;
456 struct sgl_handle *plogin_sgl_handle;
457 struct beiscsi_session *beiscsi_sess;
458 struct iscsi_task *task;
461 /* This structure is used by the chip */
462 struct pdu_data_out {
466 * Pseudo amap definition in which each bit of the actual structure is defined
467 * as a byte: used to calculate offset/shift/mask of each field
469 struct amap_pdu_data_out {
470 u8 opcode[6]; /* opcode */
471 u8 rsvd0[2]; /* should be 0 */
473 u8 final_bit; /* F bit */
475 u8 ahs_length[8]; /* no AHS */
477 u8 data_len_lo[16]; /* DataSegmentLength */
479 u8 itt[32]; /* ITT; initiator task tag */
480 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
485 u8 buffer_offset[32];
490 struct iscsi_scsi_req iscsi_hdr;
491 unsigned char pad1[16];
492 struct pdu_data_out iscsi_data_pdu;
493 unsigned char pad2[BE_SENSE_INFO_SIZE -
494 sizeof(struct pdu_data_out)];
497 struct beiscsi_io_task {
498 struct wrb_handle *pwrb_handle;
499 struct sgl_handle *psgl_handle;
500 struct beiscsi_conn *conn;
501 struct scsi_cmnd *scsi_cmnd;
503 struct hwi_wrb_context *pwrb_context;
505 struct be_cmd_bhs *cmd_bhs;
506 struct be_bus_address bhs_pa;
507 unsigned short bhs_len;
508 dma_addr_t mtask_addr;
509 uint32_t mtask_data_count;
513 struct be_nonio_bhs {
514 struct iscsi_hdr iscsi_hdr;
515 unsigned char pad1[16];
516 struct pdu_data_out iscsi_data_pdu;
517 unsigned char pad2[BE_SENSE_INFO_SIZE -
518 sizeof(struct pdu_data_out)];
521 struct be_status_bhs {
522 struct iscsi_scsi_req iscsi_hdr;
523 unsigned char pad1[16];
525 * The plus 2 below is to hold the sense info length that gets
528 unsigned char sense_info[BE_SENSE_INFO_SIZE];
536 * Pseudo amap definition in which each bit of the actual structure is defined
537 * as a byte: used to calculate offset/shift/mask of each field
539 struct amap_iscsi_sge {
542 u8 sge_offset[22]; /* DWORD 2 */
543 u8 rsvd0[9]; /* DWORD 2 */
544 u8 last_sge; /* DWORD 2 */
545 u8 len[17]; /* DWORD 3 */
546 u8 rsvd1[15]; /* DWORD 3 */
549 struct beiscsi_offload_params {
553 #define OFFLD_PARAMS_ERL 0x00000003
554 #define OFFLD_PARAMS_DDE 0x00000004
555 #define OFFLD_PARAMS_HDE 0x00000008
556 #define OFFLD_PARAMS_IR2T 0x00000010
557 #define OFFLD_PARAMS_IMD 0x00000020
558 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
559 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
560 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
563 * Pseudo amap definition in which each bit of the actual structure is defined
564 * as a byte: used to calculate offset/shift/mask of each field
566 struct amap_beiscsi_offload_params {
567 u8 max_burst_length[32];
568 u8 max_send_data_segment_length[32];
569 u8 first_burst_length[32];
575 u8 data_seq_inorder[1];
576 u8 pdu_seq_inorder[1];
580 u8 max_recv_data_segment_length[32];
583 struct hd_async_handle {
584 struct list_head link;
585 struct be_bus_address pa;
595 #define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) \
596 (BEISCSI_GET_CID_COUNT((phba), (ulp)) * 2)
599 * This has list of async PDUs that are waiting to be processed.
600 * Buffers live in this list for a brief duration before they get
601 * processed and posted back to hardware.
602 * Note that we don't really need one cri_wait_queue per async_entry.
603 * We need one cri_wait_queue per CRI. Its easier to manage if this
604 * is tagged along with the async_entry.
606 struct hd_async_entry {
607 struct cri_wait_queue {
608 unsigned short hdr_len;
609 unsigned int bytes_received;
610 unsigned int bytes_needed;
611 struct list_head list;
613 /* handles posted to FW resides here */
614 struct hd_async_handle *header;
615 struct hd_async_handle *data;
618 struct hd_async_buf_context {
619 struct be_bus_address pa_base;
622 struct hd_async_handle *handle_base;
628 * hd_async_context is declared for each ULP supporting iSCSI function.
630 struct hd_async_context {
631 struct hd_async_buf_context async_header;
632 struct hd_async_buf_context async_data;
635 * When unsol PDU is in, it needs to be chained till all the bytes are
636 * received and then processing is done. hd_async_entry is created
637 * based on the cid_count for each ULP. When unsol PDU comes in based
638 * on the conn_id it needs to be added to the correct async_entry wq.
639 * Below defined cid_to_async_cri_map is used to reterive the
640 * async_cri_map for a particular connection.
642 * This array is initialized after beiscsi_create_wrb_rings returns.
644 * - this method takes more memory space, fixed to 2K
645 * - any support for connections greater than this the array size needs
648 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
649 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
651 * This is a variable size array. Don`t add anything after this field!!
653 struct hd_async_entry *async_entry;
656 struct i_t_dpdu_cqe {
661 * Pseudo amap definition in which each bit of the actual structure is defined
662 * as a byte: used to calculate offset/shift/mask of each field
664 struct amap_i_t_dpdu_cqe {
677 struct amap_i_t_dpdu_cqe_v2 {
678 u8 db_addr_hi[32]; /* DWORD 0 */
679 u8 db_addr_lo[32]; /* DWORD 1 */
680 u8 code[6]; /* DWORD 2 */
681 u8 num_cons; /* DWORD 2*/
682 u8 rsvd0[8]; /* DWORD 2 */
683 u8 dpl[17]; /* DWORD 2 */
684 u8 index[16]; /* DWORD 3 */
685 u8 cid[13]; /* DWORD 3 */
686 u8 rsvd1; /* DWORD 3 */
687 u8 final; /* DWORD 3 */
688 u8 valid; /* DWORD 3 */
691 #define CQE_VALID_MASK 0x80000000
692 #define CQE_CODE_MASK 0x0000003F
693 #define CQE_CID_MASK 0x0000FFC0
695 #define EQE_VALID_MASK 0x00000001
696 #define EQE_MAJORCODE_MASK 0x0000000E
697 #define EQE_RESID_MASK 0xFFFF0000
704 * Pseudo amap definition in which each bit of the actual structure is defined
705 * as a byte: used to calculate offset/shift/mask of each field
707 struct amap_eq_entry {
708 u8 valid; /* DWORD 0 */
709 u8 major_code[3]; /* DWORD 0 */
710 u8 minor_code[12]; /* DWORD 0 */
711 u8 resource_id[16]; /* DWORD 0 */
720 * Pseudo amap definition in which each bit of the actual structure is defined
721 * as a byte: used to calculate offset/shift/mask of each field
732 void beiscsi_process_eq(struct beiscsi_hba *phba);
738 #define WRB_TYPE_MASK 0xF0000000
739 #define SKH_WRB_TYPE_OFFSET 27
740 #define BE_WRB_TYPE_OFFSET 28
742 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
743 (pwrb->dw[0] |= (wrb_type << type_offset))
746 * Pseudo amap definition in which each bit of the actual structure is defined
747 * as a byte: used to calculate offset/shift/mask of each field
749 struct amap_iscsi_wrb {
750 u8 lun[14]; /* DWORD 0 */
752 u8 invld; /* DWORD 0 */
753 u8 wrb_idx[8]; /* DWORD 0 */
754 u8 dsp; /* DWORD 0 */
755 u8 dmsg; /* DWORD 0 */
756 u8 undr_run; /* DWORD 0 */
757 u8 over_run; /* DWORD 0 */
758 u8 type[4]; /* DWORD 0 */
759 u8 ptr2nextwrb[8]; /* DWORD 1 */
760 u8 r2t_exp_dtl[24]; /* DWORD 1 */
761 u8 sgl_icd_idx[12]; /* DWORD 2 */
762 u8 rsvd0[20]; /* DWORD 2 */
763 u8 exp_data_sn[32]; /* DWORD 3 */
764 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
765 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
766 u8 cmdsn_itt[32]; /* DWORD 6 */
767 u8 dif_ref_tag[32]; /* DWORD 7 */
768 u8 sge0_addr_hi[32]; /* DWORD 8 */
769 u8 sge0_addr_lo[32]; /* DWORD 9 */
770 u8 sge0_offset[22]; /* DWORD 10 */
771 u8 pbs; /* DWORD 10 */
772 u8 dif_mode[2]; /* DWORD 10 */
773 u8 rsvd1[6]; /* DWORD 10 */
774 u8 sge0_last; /* DWORD 10 */
775 u8 sge0_len[17]; /* DWORD 11 */
776 u8 dif_meta_tag[14]; /* DWORD 11 */
777 u8 sge0_in_ddr; /* DWORD 11 */
778 u8 sge1_addr_hi[32]; /* DWORD 12 */
779 u8 sge1_addr_lo[32]; /* DWORD 13 */
780 u8 sge1_r2t_offset[22]; /* DWORD 14 */
781 u8 rsvd2[9]; /* DWORD 14 */
782 u8 sge1_last; /* DWORD 14 */
783 u8 sge1_len[17]; /* DWORD 15 */
784 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
785 u8 rsvd3[2]; /* DWORD 15 */
786 u8 sge1_in_ddr; /* DWORD 15 */
790 struct amap_iscsi_wrb_v2 {
791 u8 r2t_exp_dtl[25]; /* DWORD 0 */
792 u8 rsvd0[2]; /* DWORD 0*/
793 u8 type[5]; /* DWORD 0 */
794 u8 ptr2nextwrb[8]; /* DWORD 1 */
795 u8 wrb_idx[8]; /* DWORD 1 */
796 u8 lun[16]; /* DWORD 1 */
797 u8 sgl_idx[16]; /* DWORD 2 */
798 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
799 u8 exp_data_sn[32]; /* DWORD 3 */
800 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
801 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
802 u8 cq_id[16]; /* DWORD 6 */
803 u8 rsvd1[16]; /* DWORD 6 */
804 u8 cmdsn_itt[32]; /* DWORD 7 */
805 u8 sge0_addr_hi[32]; /* DWORD 8 */
806 u8 sge0_addr_lo[32]; /* DWORD 9 */
807 u8 sge0_offset[24]; /* DWORD 10 */
808 u8 rsvd2[7]; /* DWORD 10 */
809 u8 sge0_last; /* DWORD 10 */
810 u8 sge0_len[17]; /* DWORD 11 */
811 u8 rsvd3[7]; /* DWORD 11 */
812 u8 diff_enbl; /* DWORD 11 */
813 u8 u_run; /* DWORD 11 */
814 u8 o_run; /* DWORD 11 */
815 u8 invld; /* DWORD 11 */
816 u8 dsp; /* DWORD 11 */
817 u8 dmsg; /* DWORD 11 */
818 u8 rsvd4; /* DWORD 11 */
819 u8 lt; /* DWORD 11 */
820 u8 sge1_addr_hi[32]; /* DWORD 12 */
821 u8 sge1_addr_lo[32]; /* DWORD 13 */
822 u8 sge1_r2t_offset[24]; /* DWORD 14 */
823 u8 rsvd5[7]; /* DWORD 14 */
824 u8 sge1_last; /* DWORD 14 */
825 u8 sge1_len[17]; /* DWORD 15 */
826 u8 rsvd6[15]; /* DWORD 15 */
830 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
831 struct hwi_wrb_context **pcontext);
833 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
835 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
836 struct iscsi_task *task);
838 void hwi_ring_cq_db(struct beiscsi_hba *phba,
839 unsigned int id, unsigned int num_processed,
840 unsigned char rearm);
842 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
843 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
850 * Pseudo amap definition in which each bit of the actual structure is defined
851 * as a byte: used to calculate offset/shift/mask of each field
853 struct amap_pdu_nop_out {
854 u8 opcode[6]; /* opcode 0x00 */
855 u8 i_bit; /* I Bit */
856 u8 x_bit; /* reserved; should be 0 */
857 u8 fp_bit_filler1[7];
858 u8 f_bit; /* always 1 */
860 u8 ahs_length[8]; /* no AHS */
862 u8 data_len_lo[16]; /* DataSegmentLength */
864 u8 itt[32]; /* initiator id for ping or 0xffffffff */
865 u8 ttt[32]; /* target id for ping or 0xffffffff */
871 #define PDUBASE_OPCODE_MASK 0x0000003F
872 #define PDUBASE_DATALENHI_MASK 0x0000FF00
873 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
880 * Pseudo amap definition in which each bit of the actual structure is defined
881 * as a byte: used to calculate offset/shift/mask of each field
883 struct amap_pdu_base {
885 u8 i_bit; /* immediate bit */
886 u8 x_bit; /* reserved, always 0 */
887 u8 reserved1[24]; /* opcode-specific fields */
888 u8 ahs_length[8]; /* length units is 4 byte words */
890 u8 data_len_lo[16]; /* DatasegmentLength */
891 u8 lun[64]; /* lun or opcode-specific fields */
892 u8 itt[32]; /* initiator task tag */
896 struct iscsi_target_context_update_wrb {
901 * Pseudo amap definition in which each bit of the actual structure is defined
902 * as a byte: used to calculate offset/shift/mask of each field
904 #define BE_TGT_CTX_UPDT_CMD 0x07
905 struct amap_iscsi_target_context_update_wrb {
906 u8 lun[14]; /* DWORD 0 */
908 u8 invld; /* DWORD 0 */
909 u8 wrb_idx[8]; /* DWORD 0 */
910 u8 dsp; /* DWORD 0 */
911 u8 dmsg; /* DWORD 0 */
912 u8 undr_run; /* DWORD 0 */
913 u8 over_run; /* DWORD 0 */
914 u8 type[4]; /* DWORD 0 */
915 u8 ptr2nextwrb[8]; /* DWORD 1 */
916 u8 max_burst_length[19]; /* DWORD 1 */
917 u8 rsvd0[5]; /* DWORD 1 */
918 u8 rsvd1[15]; /* DWORD 2 */
919 u8 max_send_data_segment_length[17]; /* DWORD 2 */
920 u8 first_burst_length[14]; /* DWORD 3 */
921 u8 rsvd2[2]; /* DWORD 3 */
922 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
923 u8 rsvd3[5]; /* DWORD 3 */
924 u8 session_state[3]; /* DWORD 3 */
925 u8 rsvd4[16]; /* DWORD 4 */
926 u8 tx_jumbo; /* DWORD 4 */
927 u8 hde; /* DWORD 4 */
928 u8 dde; /* DWORD 4 */
929 u8 erl[2]; /* DWORD 4 */
930 u8 domain_id[5]; /* DWORD 4 */
931 u8 mode; /* DWORD 4 */
932 u8 imd; /* DWORD 4 */
933 u8 ir2t; /* DWORD 4 */
934 u8 notpredblq[2]; /* DWORD 4 */
935 u8 compltonack; /* DWORD 4 */
936 u8 stat_sn[32]; /* DWORD 5 */
937 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
938 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
939 u8 pad_addr_hi[32]; /* DWORD 8 */
940 u8 pad_addr_lo[32]; /* DWORD 9 */
941 u8 rsvd5[32]; /* DWORD 10 */
942 u8 rsvd6[32]; /* DWORD 11 */
943 u8 rsvd7[32]; /* DWORD 12 */
944 u8 rsvd8[32]; /* DWORD 13 */
945 u8 rsvd9[32]; /* DWORD 14 */
946 u8 rsvd10[32]; /* DWORD 15 */
950 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
951 #define BEISCSI_MAX_CXNS 1
952 struct amap_iscsi_target_context_update_wrb_v2 {
953 u8 max_burst_length[24]; /* DWORD 0 */
954 u8 rsvd0[3]; /* DWORD 0 */
955 u8 type[5]; /* DWORD 0 */
956 u8 ptr2nextwrb[8]; /* DWORD 1 */
957 u8 wrb_idx[8]; /* DWORD 1 */
958 u8 rsvd1[16]; /* DWORD 1 */
959 u8 max_send_data_segment_length[24]; /* DWORD 2 */
960 u8 rsvd2[8]; /* DWORD 2 */
961 u8 first_burst_length[24]; /* DWORD 3 */
962 u8 rsvd3[8]; /* DOWRD 3 */
963 u8 max_r2t[16]; /* DWORD 4 */
964 u8 rsvd4; /* DWORD 4 */
965 u8 hde; /* DWORD 4 */
966 u8 dde; /* DWORD 4 */
967 u8 erl[2]; /* DWORD 4 */
968 u8 rsvd5[6]; /* DWORD 4 */
969 u8 imd; /* DWORD 4 */
970 u8 ir2t; /* DWORD 4 */
971 u8 rsvd6[3]; /* DWORD 4 */
972 u8 stat_sn[32]; /* DWORD 5 */
973 u8 rsvd7[32]; /* DWORD 6 */
974 u8 rsvd8[32]; /* DWORD 7 */
975 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
976 u8 rsvd9[8]; /* DWORD 8 */
977 u8 rsvd10[32]; /* DWORD 9 */
978 u8 rsvd11[32]; /* DWORD 10 */
979 u8 max_cxns[16]; /* DWORD 11 */
980 u8 rsvd12[11]; /* DWORD 11*/
981 u8 invld; /* DWORD 11 */
982 u8 rsvd13;/* DWORD 11*/
983 u8 dmsg; /* DWORD 11 */
984 u8 data_seq_inorder; /* DWORD 11 */
985 u8 pdu_seq_inorder; /* DWORD 11 */
986 u8 rsvd14[32]; /*DWORD 12 */
987 u8 rsvd15[32]; /* DWORD 13 */
988 u8 rsvd16[32]; /* DWORD 14 */
989 u8 rsvd17[32]; /* DWORD 15 */
994 u32 pages; /* queue size in pages */
995 u32 id; /* queue id assigned by beklib */
996 u32 num; /* number of elements in queue */
997 u32 cidx; /* consumer index */
998 u32 pidx; /* producer index -- not used by most rings */
999 u32 item_size; /* size in bytes of one object */
1000 u8 ulp_num; /* ULP to which CID binded */
1002 u16 doorbell_format;
1003 u32 doorbell_offset;
1005 void *va; /* The virtual address of the ring. This
1006 * should be last to allow 32 & 64 bit debugger
1007 * extensions to work.
1011 struct hwi_controller {
1012 struct list_head io_sgl_list;
1013 struct list_head eh_sgl_list;
1014 struct sgl_handle *psgl_handle_base;
1016 struct hwi_wrb_context *wrb_context;
1017 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1018 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1019 struct hwi_context_memory *phwi_ctxt;
1022 enum hwh_type_enum {
1024 HWH_TYPE_LOGOUT = 2,
1028 HWH_TYPE_LOGIN = 11,
1029 HWH_TYPE_INVALID = 0xFFFFFFFF
1033 unsigned short wrb_index;
1034 struct iscsi_task *pio_handle;
1035 struct iscsi_wrb *pwrb;
1038 struct hwi_context_memory {
1039 /* Adaptive interrupt coalescing (AIC) info */
1040 u16 min_eqd; /* in usecs */
1041 u16 max_eqd; /* in usecs */
1042 u16 cur_eqd; /* in usecs */
1043 struct be_eq_obj be_eq[MAX_CPUS];
1044 struct be_queue_info be_cq[MAX_CPUS - 1];
1046 struct be_queue_info *be_wrbq;
1048 * Create array of ULP number for below entries as DEFQ
1049 * will be created for both ULP if iSCSI Protocol is
1050 * loaded on both ULP.
1052 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1053 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1054 struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT];
1057 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
1059 /* Logging related definitions */
1060 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1061 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1062 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1063 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1064 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1065 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
1066 #define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
1068 #define __beiscsi_log(phba, level, fmt, arg...) \
1069 shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1071 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1073 uint32_t log_value = phba->attr_log_enable; \
1074 if (((mask) & log_value) || (level[1] <= '3')) \
1075 __beiscsi_log(phba, level, fmt, ##arg); \