2 *******************************************************************************
4 ** FILE NAME : arcmsr.h
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA RAID Host adapter
8 *******************************************************************************
9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
11 ** Web site: www.areca.com.tw
12 ** E-mail: support@areca.com.tw
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License version 2 as
16 ** published by the Free Software Foundation.
17 ** This program is distributed in the hope that it will be useful,
18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ** GNU General Public License for more details.
21 *******************************************************************************
22 ** Redistribution and use in source and binary forms, with or without
23 ** modification, are permitted provided that the following conditions
25 ** 1. Redistributions of source code must retain the above copyright
26 ** notice, this list of conditions and the following disclaimer.
27 ** 2. Redistributions in binary form must reproduce the above copyright
28 ** notice, this list of conditions and the following disclaimer in the
29 ** documentation and/or other materials provided with the distribution.
30 ** 3. The name of the author may not be used to endorse or promote products
31 ** derived from this software without specific prior written permission.
33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *******************************************************************************
45 #include <linux/interrupt.h>
46 struct device_attribute;
47 /*The limit of outstanding scsi command that firmware can handle*/
48 #define ARCMSR_MAX_FREECCB_NUM 1024
49 #define ARCMSR_MAX_OUTSTANDING_CMD 1024
50 #define ARCMSR_DEFAULT_OUTSTANDING_CMD 128
51 #define ARCMSR_MIN_OUTSTANDING_CMD 32
52 #define ARCMSR_DRIVER_VERSION "v1.50.00.02-20200819"
53 #define ARCMSR_SCSI_INITIATOR_ID 255
54 #define ARCMSR_MAX_XFER_SECTORS 512
55 #define ARCMSR_MAX_XFER_SECTORS_B 4096
56 #define ARCMSR_MAX_XFER_SECTORS_C 304
57 #define ARCMSR_MAX_TARGETID 17
58 #define ARCMSR_MAX_TARGETLUN 8
59 #define ARCMSR_MAX_CMD_PERLUN 128
60 #define ARCMSR_DEFAULT_CMD_PERLUN 32
61 #define ARCMSR_MIN_CMD_PERLUN 1
62 #define ARCMSR_MAX_QBUFFER 4096
63 #define ARCMSR_DEFAULT_SG_ENTRIES 38
64 #define ARCMSR_MAX_HBB_POSTQUEUE 264
65 #define ARCMSR_MAX_ARC1214_POSTQUEUE 256
66 #define ARCMSR_MAX_ARC1214_DONEQUEUE 257
67 #define ARCMSR_MAX_HBE_DONEQUEUE 512
68 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
69 #define ARCMSR_CDB_SG_PAGE_LENGTH 256
70 #define ARCMST_NUM_MSIX_VECTORS 4
71 #ifndef PCI_DEVICE_ID_ARECA_1880
72 #define PCI_DEVICE_ID_ARECA_1880 0x1880
74 #ifndef PCI_DEVICE_ID_ARECA_1214
75 #define PCI_DEVICE_ID_ARECA_1214 0x1214
77 #ifndef PCI_DEVICE_ID_ARECA_1203
78 #define PCI_DEVICE_ID_ARECA_1203 0x1203
80 #ifndef PCI_DEVICE_ID_ARECA_1884
81 #define PCI_DEVICE_ID_ARECA_1884 0x1884
83 #define PCI_DEVICE_ID_ARECA_1886 0x188A
84 #define ARCMSR_HOURS (1000 * 60 * 60 * 4)
85 #define ARCMSR_MINUTES (1000 * 60 * 60)
87 **********************************************************************************
89 **********************************************************************************
94 *******************************************************************************
95 ** split 64bits dma addressing
96 *******************************************************************************
98 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
99 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
101 *******************************************************************************
102 ** MESSAGE CONTROL CODE
103 *******************************************************************************
107 uint32_t HeaderLength;
108 uint8_t Signature[8];
110 uint32_t ControlCode;
115 *******************************************************************************
116 ** IOP Message Transfer Data for user space
117 *******************************************************************************
119 #define ARCMSR_API_DATA_BUFLEN 1032
120 struct CMD_MESSAGE_FIELD
122 struct CMD_MESSAGE cmdmessage;
123 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN];
125 /* IOP message transfer */
126 #define ARCMSR_MESSAGE_FAIL 0x0001
128 #define ARECA_SATA_RAID 0x90000000
130 #define FUNCTION_READ_RQBUFFER 0x0801
131 #define FUNCTION_WRITE_WQBUFFER 0x0802
132 #define FUNCTION_CLEAR_RQBUFFER 0x0803
133 #define FUNCTION_CLEAR_WQBUFFER 0x0804
134 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
135 #define FUNCTION_RETURN_CODE_3F 0x0806
136 #define FUNCTION_SAY_HELLO 0x0807
137 #define FUNCTION_SAY_GOODBYE 0x0808
138 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
139 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A
140 #define FUNCTION_HARDWARE_RESET 0x080B
141 /* ARECA IO CONTROL CODE*/
142 #define ARCMSR_MESSAGE_READ_RQBUFFER \
143 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
144 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \
145 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
146 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
147 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
148 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
149 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
150 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
151 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
152 #define ARCMSR_MESSAGE_RETURN_CODE_3F \
153 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
154 #define ARCMSR_MESSAGE_SAY_HELLO \
155 ARECA_SATA_RAID | FUNCTION_SAY_HELLO
156 #define ARCMSR_MESSAGE_SAY_GOODBYE \
157 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
158 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
159 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
160 /* ARECA IOCTL ReturnCode */
161 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
162 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
163 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
164 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
166 *************************************************************
167 ** structure for holding DMA address data
168 *************************************************************
170 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
171 #define IS_SG64_ADDR 0x01000000 /* bit24 */
176 }__attribute__ ((packed));
182 }__attribute__ ((packed));
184 ********************************************************************
185 ** Q Buffer of IOP Message Transfer
186 ********************************************************************
194 *******************************************************************************
195 ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
196 *******************************************************************************
200 uint32_t signature; /*0, 00-03*/
201 uint32_t request_len; /*1, 04-07*/
202 uint32_t numbers_queue; /*2, 08-11*/
203 uint32_t sdram_size; /*3, 12-15*/
204 uint32_t ide_channels; /*4, 16-19*/
205 char vendor[40]; /*5, 20-59*/
206 char model[8]; /*15, 60-67*/
207 char firmware_ver[16]; /*17, 68-83*/
208 char device_map[16]; /*21, 84-99*/
209 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
210 uint8_t cfgSerial[16]; /*26,104-119*/
211 uint32_t cfgPicStatus; /*30,120-123*/
213 /* signature of set and get firmware config */
214 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
215 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
216 /* message code of inbound message register */
217 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
218 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
219 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
220 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
221 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
222 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
223 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
224 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
225 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
226 /* doorbell interrupt generator */
227 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
228 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
229 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
230 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
231 /* ccb areca cdb flag */
232 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
233 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
234 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
235 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
236 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
237 /* outbound firmware ok */
238 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
239 /* ARC-1680 Bus Reset*/
240 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
241 /* ARC-1880 Bus Reset*/
242 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
243 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
246 ************************************************************************
247 ** SPEC. for Areca Type B adapter
248 ************************************************************************
250 /* ARECA HBB COMMAND for its FIRMWARE */
251 /* window of "instruction flags" from driver to iop */
252 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400
253 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
254 /* window of "instruction flags" from iop to driver */
255 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408
256 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
257 /* window of "instruction flags" from iop to driver */
258 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870
259 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
260 /* window of "instruction flags" from driver to iop */
261 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878
262 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
263 /* ARECA FLAG LANGUAGE */
265 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
267 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
268 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
269 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
271 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
272 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
273 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
274 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
275 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
276 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
277 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
278 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
279 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
280 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
281 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
282 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
283 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
284 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
285 #define ARCMSR_MESSAGE_START_BGRB 0x00060008
286 #define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
287 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
288 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
289 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
290 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
291 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
293 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
295 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
296 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
297 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
298 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
300 /* data tunnel buffer between user space program and its firmware */
301 /* user space data to iop 128bytes */
302 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
303 /* iop data to user space 128bytes */
304 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
305 /* iop message_rwbuffer for message command */
306 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
308 #define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x)
309 #define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x)
311 ************************************************************************
312 ** SPEC. for Areca HBC adapter
313 ************************************************************************
315 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
316 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
317 /* Host Interrupt Mask */
318 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
319 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
320 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
321 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
322 /* Host Interrupt Status */
323 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
325 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
326 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
328 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
330 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
331 ** value. This bit clears only when Outbound Doorbell bits
332 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
333 ** Clear register clears bits in the Outbound Doorbell register.
335 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
337 ** Set whenever the Outbound Post List Producer/Consumer
338 ** Register (FIFO) is not empty. It clears when the Outbound
339 ** Post List FIFO is empty.
341 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
343 ** This bit indicates a SAS interrupt from a source external to
344 ** the PCIe core. This bit is not maskable.
347 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
348 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
349 /*inbound message 0 ready*/
350 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
351 /*more than 12 request completed in a time*/
352 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
353 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
354 /*outbound DATA WRITE isr door bell clear*/
355 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
356 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
357 /*outbound DATA READ isr door bell clear*/
358 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
359 /*outbound message 0 ready*/
360 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
361 /*outbound message cmd isr door bell clear*/
362 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
363 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
364 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
366 *******************************************************************************
367 ** SPEC. for Areca Type D adapter
368 *******************************************************************************
370 #define ARCMSR_ARC1214_CHIP_ID 0x00004
371 #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
372 #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
373 #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
374 #define ARCMSR_ARC1214_RESET_REQUEST 0x00108
375 #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
376 #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
377 #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
378 #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
379 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
380 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
381 #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
382 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
383 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
384 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
385 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
386 #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
387 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
388 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
389 #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
390 #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
391 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
392 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
393 #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
394 #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
395 #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
396 /* Host Interrupt Mask */
397 #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
398 #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
399 /* Host Interrupt Status */
400 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
401 #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
403 #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
404 #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
405 /*inbound message 0 ready*/
406 #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
407 /*outbound DATA WRITE isr door bell clear*/
408 #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
409 /*outbound message 0 ready*/
410 #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
411 /*outbound message cmd isr door bell clear*/
412 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
413 #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
414 #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
416 *******************************************************************************
417 ** SPEC. for Areca Type E adapter
418 *******************************************************************************
420 #define ARCMSR_SIGNATURE_1884 0x188417D3
422 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
423 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
424 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
426 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
427 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
428 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
430 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000
432 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
433 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
434 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009
436 /* ARC-1884 doorbell sync */
437 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
438 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
439 #define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080
442 *******************************************************************************
443 ** SPEC. for Areca Type F adapter
444 *******************************************************************************
446 #define ARCMSR_SIGNATURE_1886 0x188617D3
447 // Doorbell and interrupt definition are same as Type E adapter
448 /* ARC-1886 doorbell sync */
449 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
450 //set host rw buffer physical address at inbound message 0, 1 (low,high)
451 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
452 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
453 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
456 *******************************************************************************
457 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
458 *******************************************************************************
469 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
470 #define ARCMSR_CDB_FLAG_BIOS 0x02
471 #define ARCMSR_CDB_FLAG_WRITE 0x04
472 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
473 #define ARCMSR_CDB_FLAG_HEADQ 0x08
474 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
480 uint8_t DeviceStatus;
481 #define ARCMSR_DEV_CHECK_CONDITION 0x02
482 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
483 #define ARCMSR_DEV_ABORTED 0xF1
484 #define ARCMSR_DEV_INIT_FAIL 0xF2
486 uint8_t SenseData[15];
489 struct SG32ENTRY sg32entry[1];
490 struct SG64ENTRY sg64entry[1];
494 *******************************************************************************
495 ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
496 *******************************************************************************
500 uint32_t resrved0[4]; /*0000 000F*/
501 uint32_t inbound_msgaddr0; /*0010 0013*/
502 uint32_t inbound_msgaddr1; /*0014 0017*/
503 uint32_t outbound_msgaddr0; /*0018 001B*/
504 uint32_t outbound_msgaddr1; /*001C 001F*/
505 uint32_t inbound_doorbell; /*0020 0023*/
506 uint32_t inbound_intstatus; /*0024 0027*/
507 uint32_t inbound_intmask; /*0028 002B*/
508 uint32_t outbound_doorbell; /*002C 002F*/
509 uint32_t outbound_intstatus; /*0030 0033*/
510 uint32_t outbound_intmask; /*0034 0037*/
511 uint32_t reserved1[2]; /*0038 003F*/
512 uint32_t inbound_queueport; /*0040 0043*/
513 uint32_t outbound_queueport; /*0044 0047*/
514 uint32_t reserved2[2]; /*0048 004F*/
515 uint32_t reserved3[492]; /*0050 07FF 492*/
516 uint32_t reserved4[128]; /*0800 09FF 128*/
517 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
518 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
519 uint32_t reserved5[32]; /*0E80 0EFF 32*/
520 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
521 uint32_t reserved6[32]; /*0F80 0FFF 32*/
526 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
527 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
528 uint32_t postq_index;
529 uint32_t doneq_index;
530 uint32_t __iomem *drv2iop_doorbell;
531 uint32_t __iomem *drv2iop_doorbell_mask;
532 uint32_t __iomem *iop2drv_doorbell;
533 uint32_t __iomem *iop2drv_doorbell_mask;
534 uint32_t __iomem *message_rwbuffer;
535 uint32_t __iomem *message_wbuffer;
536 uint32_t __iomem *message_rbuffer;
539 *********************************************************************
541 *********************************************************************
543 struct MessageUnit_C{
544 uint32_t message_unit_status; /*0000 0003*/
545 uint32_t slave_error_attribute; /*0004 0007*/
546 uint32_t slave_error_address; /*0008 000B*/
547 uint32_t posted_outbound_doorbell; /*000C 000F*/
548 uint32_t master_error_attribute; /*0010 0013*/
549 uint32_t master_error_address_low; /*0014 0017*/
550 uint32_t master_error_address_high; /*0018 001B*/
551 uint32_t hcb_size; /*001C 001F*/
552 uint32_t inbound_doorbell; /*0020 0023*/
553 uint32_t diagnostic_rw_data; /*0024 0027*/
554 uint32_t diagnostic_rw_address_low; /*0028 002B*/
555 uint32_t diagnostic_rw_address_high; /*002C 002F*/
556 uint32_t host_int_status; /*0030 0033*/
557 uint32_t host_int_mask; /*0034 0037*/
558 uint32_t dcr_data; /*0038 003B*/
559 uint32_t dcr_address; /*003C 003F*/
560 uint32_t inbound_queueport; /*0040 0043*/
561 uint32_t outbound_queueport; /*0044 0047*/
562 uint32_t hcb_pci_address_low; /*0048 004B*/
563 uint32_t hcb_pci_address_high; /*004C 004F*/
564 uint32_t iop_int_status; /*0050 0053*/
565 uint32_t iop_int_mask; /*0054 0057*/
566 uint32_t iop_inbound_queue_port; /*0058 005B*/
567 uint32_t iop_outbound_queue_port; /*005C 005F*/
568 uint32_t inbound_free_list_index; /*0060 0063*/
569 uint32_t inbound_post_list_index; /*0064 0067*/
570 uint32_t outbound_free_list_index; /*0068 006B*/
571 uint32_t outbound_post_list_index; /*006C 006F*/
572 uint32_t inbound_doorbell_clear; /*0070 0073*/
573 uint32_t i2o_message_unit_control; /*0074 0077*/
574 uint32_t last_used_message_source_address_low; /*0078 007B*/
575 uint32_t last_used_message_source_address_high; /*007C 007F*/
576 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
577 uint32_t message_dest_address_index; /*0090 0093*/
578 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
579 uint32_t utility_A_int_counter_timer; /*0098 009B*/
580 uint32_t outbound_doorbell; /*009C 009F*/
581 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
582 uint32_t message_source_address_index; /*00A4 00A7*/
583 uint32_t message_done_queue_index; /*00A8 00AB*/
584 uint32_t reserved0; /*00AC 00AF*/
585 uint32_t inbound_msgaddr0; /*00B0 00B3*/
586 uint32_t inbound_msgaddr1; /*00B4 00B7*/
587 uint32_t outbound_msgaddr0; /*00B8 00BB*/
588 uint32_t outbound_msgaddr1; /*00BC 00BF*/
589 uint32_t inbound_queueport_low; /*00C0 00C3*/
590 uint32_t inbound_queueport_high; /*00C4 00C7*/
591 uint32_t outbound_queueport_low; /*00C8 00CB*/
592 uint32_t outbound_queueport_high; /*00CC 00CF*/
593 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
594 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
595 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
596 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
597 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
598 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
599 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
600 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
601 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
602 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
603 uint32_t host_diagnostic; /*00F8 00FB*/
604 uint32_t write_sequence; /*00FC 00FF*/
605 uint32_t reserved1[34]; /*0100 0187*/
606 uint32_t reserved2[1950]; /*0188 1FFF*/
607 uint32_t message_wbuffer[32]; /*2000 207F*/
608 uint32_t reserved3[32]; /*2080 20FF*/
609 uint32_t message_rbuffer[32]; /*2100 217F*/
610 uint32_t reserved4[32]; /*2180 21FF*/
611 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
614 *********************************************************************
615 ** Messaging Unit (MU) of Type D processor
616 *********************************************************************
619 uint32_t addressLow; /* pointer to SRB block */
620 uint32_t addressHigh;
621 uint32_t length; /* in DWORDs */
625 struct OutBound_SRB {
626 uint32_t addressLow; /* pointer to SRB block */
627 uint32_t addressHigh;
630 struct MessageUnit_D {
631 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
632 volatile struct OutBound_SRB
633 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
635 volatile u16 doneq_index;
636 u32 __iomem *chip_id; /* 0x00004 */
637 u32 __iomem *cpu_mem_config; /* 0x00008 */
638 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
639 u32 __iomem *sample_at_reset; /* 0x00100 */
640 u32 __iomem *reset_request; /* 0x00108 */
641 u32 __iomem *host_int_status; /* 0x00200 */
642 u32 __iomem *pcief0_int_enable; /* 0x0020C */
643 u32 __iomem *inbound_msgaddr0; /* 0x00400 */
644 u32 __iomem *inbound_msgaddr1; /* 0x00404 */
645 u32 __iomem *outbound_msgaddr0; /* 0x00420 */
646 u32 __iomem *outbound_msgaddr1; /* 0x00424 */
647 u32 __iomem *inbound_doorbell; /* 0x00460 */
648 u32 __iomem *outbound_doorbell; /* 0x00480 */
649 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
650 u32 __iomem *inboundlist_base_low; /* 0x01000 */
651 u32 __iomem *inboundlist_base_high; /* 0x01004 */
652 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
653 u32 __iomem *outboundlist_base_low; /* 0x01060 */
654 u32 __iomem *outboundlist_base_high; /* 0x01064 */
655 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
656 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
657 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
658 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
659 u32 __iomem *message_wbuffer; /* 0x2000 */
660 u32 __iomem *message_rbuffer; /* 0x2100 */
661 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
664 *********************************************************************
665 ** Messaging Unit (MU) of Type E processor(LSI)
666 *********************************************************************
668 struct MessageUnit_E{
669 uint32_t iobound_doorbell; /*0000 0003*/
670 uint32_t write_sequence_3xxx; /*0004 0007*/
671 uint32_t host_diagnostic_3xxx; /*0008 000B*/
672 uint32_t posted_outbound_doorbell; /*000C 000F*/
673 uint32_t master_error_attribute; /*0010 0013*/
674 uint32_t master_error_address_low; /*0014 0017*/
675 uint32_t master_error_address_high; /*0018 001B*/
676 uint32_t hcb_size; /*001C 001F*/
677 uint32_t inbound_doorbell; /*0020 0023*/
678 uint32_t diagnostic_rw_data; /*0024 0027*/
679 uint32_t diagnostic_rw_address_low; /*0028 002B*/
680 uint32_t diagnostic_rw_address_high; /*002C 002F*/
681 uint32_t host_int_status; /*0030 0033*/
682 uint32_t host_int_mask; /*0034 0037*/
683 uint32_t dcr_data; /*0038 003B*/
684 uint32_t dcr_address; /*003C 003F*/
685 uint32_t inbound_queueport; /*0040 0043*/
686 uint32_t outbound_queueport; /*0044 0047*/
687 uint32_t hcb_pci_address_low; /*0048 004B*/
688 uint32_t hcb_pci_address_high; /*004C 004F*/
689 uint32_t iop_int_status; /*0050 0053*/
690 uint32_t iop_int_mask; /*0054 0057*/
691 uint32_t iop_inbound_queue_port; /*0058 005B*/
692 uint32_t iop_outbound_queue_port; /*005C 005F*/
693 uint32_t inbound_free_list_index; /*0060 0063*/
694 uint32_t inbound_post_list_index; /*0064 0067*/
695 uint32_t reply_post_producer_index; /*0068 006B*/
696 uint32_t reply_post_consumer_index; /*006C 006F*/
697 uint32_t inbound_doorbell_clear; /*0070 0073*/
698 uint32_t i2o_message_unit_control; /*0074 0077*/
699 uint32_t last_used_message_source_address_low; /*0078 007B*/
700 uint32_t last_used_message_source_address_high; /*007C 007F*/
701 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
702 uint32_t message_dest_address_index; /*0090 0093*/
703 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
704 uint32_t utility_A_int_counter_timer; /*0098 009B*/
705 uint32_t outbound_doorbell; /*009C 009F*/
706 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
707 uint32_t message_source_address_index; /*00A4 00A7*/
708 uint32_t message_done_queue_index; /*00A8 00AB*/
709 uint32_t reserved0; /*00AC 00AF*/
710 uint32_t inbound_msgaddr0; /*00B0 00B3*/
711 uint32_t inbound_msgaddr1; /*00B4 00B7*/
712 uint32_t outbound_msgaddr0; /*00B8 00BB*/
713 uint32_t outbound_msgaddr1; /*00BC 00BF*/
714 uint32_t inbound_queueport_low; /*00C0 00C3*/
715 uint32_t inbound_queueport_high; /*00C4 00C7*/
716 uint32_t outbound_queueport_low; /*00C8 00CB*/
717 uint32_t outbound_queueport_high; /*00CC 00CF*/
718 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
719 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
720 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
721 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
722 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
723 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
724 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
725 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
726 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
727 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
728 uint32_t host_diagnostic; /*00F8 00FB*/
729 uint32_t write_sequence; /*00FC 00FF*/
730 uint32_t reserved1[34]; /*0100 0187*/
731 uint32_t reserved2[1950]; /*0188 1FFF*/
732 uint32_t message_wbuffer[32]; /*2000 207F*/
733 uint32_t reserved3[32]; /*2080 20FF*/
734 uint32_t message_rbuffer[32]; /*2100 217F*/
735 uint32_t reserved4[32]; /*2180 21FF*/
736 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
740 *********************************************************************
741 ** Messaging Unit (MU) of Type F processor(LSI)
742 *********************************************************************
744 struct MessageUnit_F {
745 uint32_t iobound_doorbell; /*0000 0003*/
746 uint32_t write_sequence_3xxx; /*0004 0007*/
747 uint32_t host_diagnostic_3xxx; /*0008 000B*/
748 uint32_t posted_outbound_doorbell; /*000C 000F*/
749 uint32_t master_error_attribute; /*0010 0013*/
750 uint32_t master_error_address_low; /*0014 0017*/
751 uint32_t master_error_address_high; /*0018 001B*/
752 uint32_t hcb_size; /*001C 001F*/
753 uint32_t inbound_doorbell; /*0020 0023*/
754 uint32_t diagnostic_rw_data; /*0024 0027*/
755 uint32_t diagnostic_rw_address_low; /*0028 002B*/
756 uint32_t diagnostic_rw_address_high; /*002C 002F*/
757 uint32_t host_int_status; /*0030 0033*/
758 uint32_t host_int_mask; /*0034 0037*/
759 uint32_t dcr_data; /*0038 003B*/
760 uint32_t dcr_address; /*003C 003F*/
761 uint32_t inbound_queueport; /*0040 0043*/
762 uint32_t outbound_queueport; /*0044 0047*/
763 uint32_t hcb_pci_address_low; /*0048 004B*/
764 uint32_t hcb_pci_address_high; /*004C 004F*/
765 uint32_t iop_int_status; /*0050 0053*/
766 uint32_t iop_int_mask; /*0054 0057*/
767 uint32_t iop_inbound_queue_port; /*0058 005B*/
768 uint32_t iop_outbound_queue_port; /*005C 005F*/
769 uint32_t inbound_free_list_index; /*0060 0063*/
770 uint32_t inbound_post_list_index; /*0064 0067*/
771 uint32_t reply_post_producer_index; /*0068 006B*/
772 uint32_t reply_post_consumer_index; /*006C 006F*/
773 uint32_t inbound_doorbell_clear; /*0070 0073*/
774 uint32_t i2o_message_unit_control; /*0074 0077*/
775 uint32_t last_used_message_source_address_low; /*0078 007B*/
776 uint32_t last_used_message_source_address_high; /*007C 007F*/
777 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
778 uint32_t message_dest_address_index; /*0090 0093*/
779 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
780 uint32_t utility_A_int_counter_timer; /*0098 009B*/
781 uint32_t outbound_doorbell; /*009C 009F*/
782 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
783 uint32_t message_source_address_index; /*00A4 00A7*/
784 uint32_t message_done_queue_index; /*00A8 00AB*/
785 uint32_t reserved0; /*00AC 00AF*/
786 uint32_t inbound_msgaddr0; /*00B0 00B3*/
787 uint32_t inbound_msgaddr1; /*00B4 00B7*/
788 uint32_t outbound_msgaddr0; /*00B8 00BB*/
789 uint32_t outbound_msgaddr1; /*00BC 00BF*/
790 uint32_t inbound_queueport_low; /*00C0 00C3*/
791 uint32_t inbound_queueport_high; /*00C4 00C7*/
792 uint32_t outbound_queueport_low; /*00C8 00CB*/
793 uint32_t outbound_queueport_high; /*00CC 00CF*/
794 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
795 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
796 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
797 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
798 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
799 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
800 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
801 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
802 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
803 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
804 uint32_t host_diagnostic; /*00F8 00FB*/
805 uint32_t write_sequence; /*00FC 00FF*/
806 uint32_t reserved1[46]; /*0100 01B7*/
807 uint32_t reply_post_producer_index1; /*01B8 01BB*/
808 uint32_t reply_post_consumer_index1; /*01BC 01BF*/
811 #define MESG_RW_BUFFER_SIZE (256 * 3)
813 typedef struct deliver_completeQ {
816 uint16_t cmdLMID; // reserved (0)
817 uint16_t cmdFlag2; // reserved (0)
818 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
820 *******************************************************************************
821 ** Adapter Control Block
822 *******************************************************************************
824 struct AdapterControlBlock
826 uint32_t adapter_type; /* adapter A,B..... */
827 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
828 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
829 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
830 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
831 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
832 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */
834 struct pci_dev * pdev;
835 struct Scsi_Host * host;
836 unsigned long vir2phy_offset;
837 /* Offset is used in making arc cdb physical to virtual calculations */
838 uint32_t outbound_int_enable;
839 uint32_t cdb_phyaddr_hi32;
840 uint32_t reg_mu_acc_handle0;
841 uint64_t cdb_phyadd_hipart;
843 spinlock_t ccblist_lock;
844 spinlock_t postq_lock;
845 spinlock_t doneq_lock;
846 spinlock_t rqbuffer_lock;
847 spinlock_t wqbuffer_lock;
849 struct MessageUnit_A __iomem *pmuA;
850 struct MessageUnit_B *pmuB;
851 struct MessageUnit_C __iomem *pmuC;
852 struct MessageUnit_D *pmuD;
853 struct MessageUnit_E __iomem *pmuE;
854 struct MessageUnit_F __iomem *pmuF;
856 /* message unit ATU inbound base address0 */
857 void __iomem *mem_base0;
858 void __iomem *mem_base1;
859 //0x000 - COMPORT_IN (Host sent to ROC)
860 uint32_t *message_wbuffer;
861 //0x100 - COMPORT_OUT (ROC sent to Host)
862 uint32_t *message_rbuffer;
863 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
866 uint8_t adapter_index;
867 #define ACB_F_SCSISTOPADAPTER 0x0001
868 #define ACB_F_MSG_STOP_BGRB 0x0002
869 /* stop RAID background rebuild */
870 #define ACB_F_MSG_START_BGRB 0x0004
871 /* stop RAID background rebuild */
872 #define ACB_F_IOPDATA_OVERFLOW 0x0008
873 /* iop message data rqbuffer overflow */
874 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
875 /* message clear wqbuffer */
876 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
877 /* message clear rqbuffer */
878 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
879 #define ACB_F_BUS_RESET 0x0080
881 #define ACB_F_IOP_INITED 0x0100
883 #define ACB_F_ABORT 0x0200
884 #define ACB_F_FIRMWARE_TRAP 0x0400
885 #define ACB_F_ADAPTER_REMOVED 0x0800
886 #define ACB_F_MSG_GET_CONFIG 0x1000
887 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
888 /* used for memory free */
889 struct list_head ccb_free_list;
890 /* head of free ccb list */
892 atomic_t ccboutstandingcount;
893 /*The present outstanding command number that in the IOP that
894 waiting for being handled by FW*/
897 /* dma_coherent used for memory free */
898 dma_addr_t dma_coherent_handle;
899 /* dma_coherent_handle used for memory free */
900 dma_addr_t dma_coherent_handle2;
902 unsigned int uncache_size;
903 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
904 /* data collection buffer for read from 80331 */
905 int32_t rqbuf_getIndex;
906 /* first of read buffer */
907 int32_t rqbuf_putIndex;
908 /* last of read buffer */
909 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
910 /* data collection buffer for write to 80331 */
911 int32_t wqbuf_getIndex;
912 /* first of write buffer */
913 int32_t wqbuf_putIndex;
914 /* last of write buffer */
915 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
916 /* id0 ..... id15, lun0...lun7 */
917 #define ARECA_RAID_GONE 0x55
918 #define ARECA_RAID_GOOD 0xaa
922 uint32_t firm_request_len;
923 uint32_t firm_numbers_queue;
924 uint32_t firm_sdram_size;
925 uint32_t firm_hd_channels;
926 uint32_t firm_cfg_version;
928 char firm_version[20];
929 char device_map[20]; /*21,84-99*/
930 struct work_struct arcmsr_do_message_isr_bh;
931 struct timer_list eternal_timer;
932 unsigned short fw_flag;
933 #define FW_NORMAL 0x0000
934 #define FW_BOG 0x0001
935 #define FW_DEADLOCK 0x0010
936 uint32_t maxOutstanding;
939 struct timer_list refresh_timer;
940 uint32_t doneq_index;
942 uint32_t in_doorbell;
943 uint32_t out_doorbell;
944 uint32_t completionQ_entry;
945 pCompletion_Q pCompletionQ;
946 uint32_t completeQ_size;
947 };/* HW_DEVICE_EXTENSION */
949 *******************************************************************************
950 ** Command Control Block
951 ** this CCB length must be 32 bytes boundary
952 *******************************************************************************
954 struct CommandControlBlock{
955 /*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
956 struct list_head list; /*x32: 8byte, x64: 16byte*/
957 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
958 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
959 unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/
960 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
961 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
962 #define CCB_FLAG_READ 0x0000
963 #define CCB_FLAG_WRITE 0x0001
964 #define CCB_FLAG_ERROR 0x0002
965 #define CCB_FLAG_FLUSHCACHE 0x0004
966 #define CCB_FLAG_MASTER_ABORTED 0x0008
967 uint16_t startdone; /*x32:2byte,x32:2byte*/
968 #define ARCMSR_CCB_DONE 0x0000
969 #define ARCMSR_CCB_START 0x55AA
970 #define ARCMSR_CCB_ABORTED 0xAA55
971 #define ARCMSR_CCB_ILLEGAL 0xFFFF
973 #if BITS_PER_LONG == 64
974 /* ======================512+64 bytes======================== */
975 uint32_t reserved[3]; /*12 byte*/
977 /* ======================512+32 bytes======================== */
978 uint32_t reserved[8]; /*32 byte*/
980 /* ======================================================= */
981 struct ARCMSR_CDB arcmsr_cdb;
984 *******************************************************************************
985 ** ARECA SCSI sense data
986 *******************************************************************************
991 #define SCSI_SENSE_CURRENT_ERRORS 0x70
992 #define SCSI_SENSE_DEFERRED_ERRORS 0x71
994 uint8_t SegmentNumber;
997 uint8_t IncorrectLength:1;
998 uint8_t EndOfMedia:1;
1000 uint8_t Information[4];
1001 uint8_t AdditionalSenseLength;
1002 uint8_t CommandSpecificInformation[4];
1003 uint8_t AdditionalSenseCode;
1004 uint8_t AdditionalSenseCodeQualifier;
1005 uint8_t FieldReplaceableUnitCode;
1006 uint8_t SenseKeySpecific[3];
1009 *******************************************************************************
1010 ** Outbound Interrupt Status Register - OISR
1011 *******************************************************************************
1013 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
1014 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
1015 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
1016 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
1017 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
1018 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
1019 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \
1020 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
1021 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
1022 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \
1023 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
1024 |ARCMSR_MU_OUTBOUND_PCI_INT)
1026 *******************************************************************************
1027 ** Outbound Interrupt Mask Register - OIMR
1028 *******************************************************************************
1030 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
1031 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
1032 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
1033 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
1034 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
1035 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
1036 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
1038 extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
1039 extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
1040 struct QBUFFER __iomem *);
1041 extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *);
1042 extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
1043 extern struct device_attribute *arcmsr_host_attrs[];
1044 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
1045 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);