2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
43 #include "aic7xxx_osm.h"
44 #include "aic7xxx_inline.h"
45 #include "aicasm/aicasm_insformat.h"
47 /***************************** Lookup Tables **********************************/
48 static const char *const ahc_chip_names[] = {
66 * Hardware error codes.
68 struct ahc_hard_error_entry {
73 static const struct ahc_hard_error_entry ahc_hard_errors[] = {
74 { ILLHADDR, "Illegal Host Access" },
75 { ILLSADDR, "Illegal Sequencer Address referenced" },
76 { ILLOPCODE, "Illegal Opcode in sequencer program" },
77 { SQPARERR, "Sequencer Parity Error" },
78 { DPARERR, "Data-path Parity Error" },
79 { MPARERR, "Scratch or SCB Memory Parity Error" },
80 { PCIERRSTAT, "PCI Error detected" },
81 { CIOPARERR, "CIOBUS Parity Error" },
83 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
85 static const struct ahc_phase_table_entry ahc_phase_table[] =
87 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
88 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
89 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
90 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
91 { P_COMMAND, MSG_NOOP, "in Command phase" },
92 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
93 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
94 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
95 { P_BUSFREE, MSG_NOOP, "while idle" },
96 { 0, MSG_NOOP, "in unknown phase" }
100 * In most cases we only wish to itterate over real phases, so
101 * exclude the last element from the count.
103 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
106 * Valid SCSIRATE values. (p. 3-17)
107 * Provides a mapping of tranfer periods in ns to the proper value to
108 * stick in the scsixfer reg.
110 static const struct ahc_syncrate ahc_syncrates[] =
112 /* ultra2 fast/ultra period rate */
113 { 0x42, 0x000, 9, "80.0" },
114 { 0x03, 0x000, 10, "40.0" },
115 { 0x04, 0x000, 11, "33.0" },
116 { 0x05, 0x100, 12, "20.0" },
117 { 0x06, 0x110, 15, "16.0" },
118 { 0x07, 0x120, 18, "13.4" },
119 { 0x08, 0x000, 25, "10.0" },
120 { 0x19, 0x010, 31, "8.0" },
121 { 0x1a, 0x020, 37, "6.67" },
122 { 0x1b, 0x030, 43, "5.7" },
123 { 0x1c, 0x040, 50, "5.0" },
124 { 0x00, 0x050, 56, "4.4" },
125 { 0x00, 0x060, 62, "4.0" },
126 { 0x00, 0x070, 68, "3.6" },
127 { 0x00, 0x000, 0, NULL }
130 /* Our Sequencer Program */
131 #include "aic7xxx_seq.h"
133 /**************************** Function Declarations ***************************/
134 static void ahc_force_renegotiation(struct ahc_softc *ahc,
135 struct ahc_devinfo *devinfo);
136 static struct ahc_tmode_tstate*
137 ahc_alloc_tstate(struct ahc_softc *ahc,
138 u_int scsi_id, char channel);
139 #ifdef AHC_TARGET_MODE
140 static void ahc_free_tstate(struct ahc_softc *ahc,
141 u_int scsi_id, char channel, int force);
143 static const struct ahc_syncrate*
144 ahc_devlimited_syncrate(struct ahc_softc *ahc,
145 struct ahc_initiator_tinfo *,
149 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
150 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
151 struct ahc_devinfo *devinfo);
152 static void ahc_scb_devinfo(struct ahc_softc *ahc,
153 struct ahc_devinfo *devinfo,
155 static void ahc_assert_atn(struct ahc_softc *ahc);
156 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
157 struct ahc_devinfo *devinfo,
159 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
160 struct ahc_devinfo *devinfo);
161 static void ahc_construct_sdtr(struct ahc_softc *ahc,
162 struct ahc_devinfo *devinfo,
163 u_int period, u_int offset);
164 static void ahc_construct_wdtr(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
167 static void ahc_construct_ppr(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo,
169 u_int period, u_int offset,
170 u_int bus_width, u_int ppr_options);
171 static void ahc_clear_msg_state(struct ahc_softc *ahc);
172 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
173 static void ahc_handle_message_phase(struct ahc_softc *ahc);
179 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
180 u_int msgval, int full);
181 static int ahc_parse_msg(struct ahc_softc *ahc,
182 struct ahc_devinfo *devinfo);
183 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
184 struct ahc_devinfo *devinfo);
185 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
186 struct ahc_devinfo *devinfo);
187 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
188 static void ahc_handle_devreset(struct ahc_softc *ahc,
189 struct ahc_devinfo *devinfo,
190 cam_status status, char *message,
192 #ifdef AHC_TARGET_MODE
193 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo,
198 static bus_dmamap_callback_t ahc_dmamap_cb;
199 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
200 static int ahc_init_scbdata(struct ahc_softc *ahc);
201 static void ahc_fini_scbdata(struct ahc_softc *ahc);
202 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
203 struct scb *prev_scb,
205 static int ahc_qinfifo_count(struct ahc_softc *ahc);
206 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
207 u_int prev, u_int scbptr);
208 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
209 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
210 u_int scbpos, u_int prev);
211 static void ahc_reset_current_bus(struct ahc_softc *ahc);
213 static void ahc_dumpseq(struct ahc_softc *ahc);
215 static int ahc_loadseq(struct ahc_softc *ahc);
216 static int ahc_check_patch(struct ahc_softc *ahc,
217 const struct patch **start_patch,
218 u_int start_instr, u_int *skip_addr);
219 static void ahc_download_instr(struct ahc_softc *ahc,
220 u_int instrptr, uint8_t *dconsts);
221 #ifdef AHC_TARGET_MODE
222 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
223 struct ahc_tmode_lstate *lstate,
227 static void ahc_update_scsiid(struct ahc_softc *ahc,
229 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
230 struct target_cmd *cmd);
233 static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
234 static void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
235 static void ahc_busy_tcl(struct ahc_softc *ahc,
236 u_int tcl, u_int busyid);
238 /************************** SCB and SCB queue management **********************/
239 static void ahc_run_untagged_queues(struct ahc_softc *ahc);
240 static void ahc_run_untagged_queue(struct ahc_softc *ahc,
241 struct scb_tailq *queue);
243 /****************************** Initialization ********************************/
244 static void ahc_alloc_scbs(struct ahc_softc *ahc);
245 static void ahc_shutdown(void *arg);
247 /*************************** Interrupt Services *******************************/
248 static void ahc_clear_intstat(struct ahc_softc *ahc);
249 static void ahc_run_qoutfifo(struct ahc_softc *ahc);
250 #ifdef AHC_TARGET_MODE
251 static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
253 static void ahc_handle_brkadrint(struct ahc_softc *ahc);
254 static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
255 static void ahc_handle_scsiint(struct ahc_softc *ahc,
257 static void ahc_clear_critical_section(struct ahc_softc *ahc);
259 /***************************** Error Recovery *********************************/
260 static void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
261 static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
262 char channel, int lun, u_int tag,
263 role_t role, uint32_t status);
264 static void ahc_calc_residual(struct ahc_softc *ahc,
267 /*********************** Untagged Transaction Routines ************************/
268 static inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
269 static inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
272 * Block our completion routine from starting the next untagged
273 * transaction for this target or target lun.
276 ahc_freeze_untagged_queues(struct ahc_softc *ahc)
278 if ((ahc->flags & AHC_SCB_BTT) == 0)
279 ahc->untagged_queue_lock++;
283 * Allow the next untagged transaction for this target or target lun
284 * to be executed. We use a counting semaphore to allow the lock
285 * to be acquired recursively. Once the count drops to zero, the
286 * transaction queues will be run.
289 ahc_release_untagged_queues(struct ahc_softc *ahc)
291 if ((ahc->flags & AHC_SCB_BTT) == 0) {
292 ahc->untagged_queue_lock--;
293 if (ahc->untagged_queue_lock == 0)
294 ahc_run_untagged_queues(ahc);
298 /************************* Sequencer Execution Control ************************/
300 * Work around any chip bugs related to halting sequencer execution.
301 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
302 * reading a register that will set this signal and deassert it.
303 * Without this workaround, if the chip is paused, by an interrupt or
304 * manual pause while accessing scb ram, accesses to certain registers
305 * will hang the system (infinite pci retries).
308 ahc_pause_bug_fix(struct ahc_softc *ahc)
310 if ((ahc->features & AHC_ULTRA2) != 0)
311 (void)ahc_inb(ahc, CCSCBCTL);
315 * Determine whether the sequencer has halted code execution.
316 * Returns non-zero status if the sequencer is stopped.
319 ahc_is_paused(struct ahc_softc *ahc)
321 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
325 * Request that the sequencer stop and wait, indefinitely, for it
326 * to stop. The sequencer will only acknowledge that it is paused
327 * once it has reached an instruction boundary and PAUSEDIS is
328 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
329 * for critical sections.
332 ahc_pause(struct ahc_softc *ahc)
334 ahc_outb(ahc, HCNTRL, ahc->pause);
337 * Since the sequencer can disable pausing in a critical section, we
338 * must loop until it actually stops.
340 while (ahc_is_paused(ahc) == 0)
343 ahc_pause_bug_fix(ahc);
347 * Allow the sequencer to continue program execution.
348 * We check here to ensure that no additional interrupt
349 * sources that would cause the sequencer to halt have been
350 * asserted. If, for example, a SCSI bus reset is detected
351 * while we are fielding a different, pausing, interrupt type,
352 * we don't want to release the sequencer before going back
353 * into our interrupt handler and dealing with this new
357 ahc_unpause(struct ahc_softc *ahc)
359 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
360 ahc_outb(ahc, HCNTRL, ahc->unpause);
363 /************************** Memory mapping routines ***************************/
364 static struct ahc_dma_seg *
365 ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
369 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
370 /* sg_list_phys points to entry 1, not 0 */
373 return (&scb->sg_list[sg_index]);
377 ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
381 /* sg_list_phys points to entry 1, not 0 */
382 sg_index = sg - &scb->sg_list[1];
384 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
388 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
390 return (ahc->scb_data->hscb_busaddr
391 + (sizeof(struct hardware_scb) * index));
395 ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
397 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
398 ahc->scb_data->hscb_dmamap,
399 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
400 /*len*/sizeof(*scb->hscb), op);
404 ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
406 if (scb->sg_count == 0)
409 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
410 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
411 * sizeof(struct ahc_dma_seg),
412 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
415 #ifdef AHC_TARGET_MODE
417 ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
419 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
423 /*********************** Miscellaneous Support Functions ***********************/
425 * Determine whether the sequencer reported a residual
426 * for this SCB/transaction.
429 ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
433 sgptr = ahc_le32toh(scb->hscb->sgptr);
434 if ((sgptr & SG_RESID_VALID) != 0)
435 ahc_calc_residual(ahc, scb);
439 * Return pointers to the transfer negotiation information
440 * for the specified our_id/remote_id pair.
442 struct ahc_initiator_tinfo *
443 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
444 u_int remote_id, struct ahc_tmode_tstate **tstate)
447 * Transfer data structures are stored from the perspective
448 * of the target role. Since the parameters for a connection
449 * in the initiator role to a given target are the same as
450 * when the roles are reversed, we pretend we are the target.
454 *tstate = ahc->enabled_targets[our_id];
455 return (&(*tstate)->transinfo[remote_id]);
459 ahc_inw(struct ahc_softc *ahc, u_int port)
461 uint16_t r = ahc_inb(ahc, port+1) << 8;
462 return r | ahc_inb(ahc, port);
466 ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
468 ahc_outb(ahc, port, value & 0xFF);
469 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
473 ahc_inl(struct ahc_softc *ahc, u_int port)
475 return ((ahc_inb(ahc, port))
476 | (ahc_inb(ahc, port+1) << 8)
477 | (ahc_inb(ahc, port+2) << 16)
478 | (ahc_inb(ahc, port+3) << 24));
482 ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
484 ahc_outb(ahc, port, (value) & 0xFF);
485 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
486 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
487 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
491 ahc_inq(struct ahc_softc *ahc, u_int port)
493 return ((ahc_inb(ahc, port))
494 | (ahc_inb(ahc, port+1) << 8)
495 | (ahc_inb(ahc, port+2) << 16)
496 | (((uint64_t)ahc_inb(ahc, port+3)) << 24)
497 | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
498 | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
499 | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
500 | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
504 ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
506 ahc_outb(ahc, port, value & 0xFF);
507 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
508 ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
509 ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
510 ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
511 ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
512 ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
513 ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
517 * Get a free scb. If there are none, see if we can allocate a new SCB.
520 ahc_get_scb(struct ahc_softc *ahc)
524 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
526 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
530 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
535 * Return an SCB resource to the free list.
538 ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
540 struct hardware_scb *hscb;
543 /* Clean up for the next user */
544 ahc->scb_data->scbindex[hscb->tag] = NULL;
545 scb->flags = SCB_FREE;
548 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
550 /* Notify the OSM that a resource is now available. */
551 ahc_platform_scb_free(ahc, scb);
555 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
559 scb = ahc->scb_data->scbindex[tag];
561 ahc_sync_scb(ahc, scb,
562 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
567 ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
569 struct hardware_scb *q_hscb;
573 * Our queuing method is a bit tricky. The card
574 * knows in advance which HSCB to download, and we
575 * can't disappoint it. To achieve this, the next
576 * SCB to download is saved off in ahc->next_queued_scb.
577 * When we are called to queue "an arbitrary scb",
578 * we copy the contents of the incoming HSCB to the one
579 * the sequencer knows about, swap HSCB pointers and
580 * finally assign the SCB to the tag indexed location
581 * in the scb_array. This makes sure that we can still
582 * locate the correct SCB by SCB_TAG.
584 q_hscb = ahc->next_queued_scb->hscb;
585 saved_tag = q_hscb->tag;
586 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
587 if ((scb->flags & SCB_CDB32_PTR) != 0) {
588 q_hscb->shared_data.cdb_ptr =
589 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
590 + offsetof(struct hardware_scb, cdb32));
592 q_hscb->tag = saved_tag;
593 q_hscb->next = scb->hscb->tag;
595 /* Now swap HSCB pointers. */
596 ahc->next_queued_scb->hscb = scb->hscb;
599 /* Now define the mapping from tag to SCB in the scbindex */
600 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
604 * Tell the sequencer about a new transaction to execute.
607 ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
609 ahc_swap_with_next_hscb(ahc, scb);
611 if (scb->hscb->tag == SCB_LIST_NULL
612 || scb->hscb->next == SCB_LIST_NULL)
613 panic("Attempt to queue invalid SCB tag %x:%x\n",
614 scb->hscb->tag, scb->hscb->next);
617 * Setup data "oddness".
619 scb->hscb->lun &= LID;
620 if (ahc_get_transfer_length(scb) & 0x1)
621 scb->hscb->lun |= SCB_XFERLEN_ODD;
624 * Keep a history of SCBs we've downloaded in the qinfifo.
626 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
629 * Make sure our data is consistent from the
630 * perspective of the adapter.
632 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
634 /* Tell the adapter about the newly queued SCB */
635 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
636 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
638 if ((ahc->features & AHC_AUTOPAUSE) == 0)
640 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
641 if ((ahc->features & AHC_AUTOPAUSE) == 0)
646 struct scsi_sense_data *
647 ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
651 offset = scb - ahc->scb_data->scbarray;
652 return (&ahc->scb_data->sense[offset]);
656 ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
660 offset = scb - ahc->scb_data->scbarray;
661 return (ahc->scb_data->sense_busaddr
662 + (offset * sizeof(struct scsi_sense_data)));
665 /************************** Interrupt Processing ******************************/
667 ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
669 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
670 /*offset*/0, /*len*/256, op);
674 ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
676 #ifdef AHC_TARGET_MODE
677 if ((ahc->flags & AHC_TARGETROLE) != 0) {
678 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
679 ahc->shared_data_dmamap,
680 ahc_targetcmd_offset(ahc, 0),
681 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
688 * See if the firmware has posted any completed commands
689 * into our in-core command complete fifos.
691 #define AHC_RUN_QOUTFIFO 0x1
692 #define AHC_RUN_TQINFIFO 0x2
694 ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
699 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
700 /*offset*/ahc->qoutfifonext, /*len*/1,
701 BUS_DMASYNC_POSTREAD);
702 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
703 retval |= AHC_RUN_QOUTFIFO;
704 #ifdef AHC_TARGET_MODE
705 if ((ahc->flags & AHC_TARGETROLE) != 0
706 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
707 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
708 ahc->shared_data_dmamap,
709 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
710 /*len*/sizeof(struct target_cmd),
711 BUS_DMASYNC_POSTREAD);
712 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
713 retval |= AHC_RUN_TQINFIFO;
720 * Catch an interrupt from the adapter
723 ahc_intr(struct ahc_softc *ahc)
727 if ((ahc->pause & INTEN) == 0) {
729 * Our interrupt is not enabled on the chip
730 * and may be disabled for re-entrancy reasons,
731 * so just return. This is likely just a shared
737 * Instead of directly reading the interrupt status register,
738 * infer the cause of the interrupt by checking our in-core
739 * completion queues. This avoids a costly PCI bus read in
742 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
743 && (ahc_check_cmdcmpltqueues(ahc) != 0))
746 intstat = ahc_inb(ahc, INTSTAT);
749 if ((intstat & INT_PEND) == 0) {
750 #if AHC_PCI_CONFIG > 0
751 if (ahc->unsolicited_ints > 500) {
752 ahc->unsolicited_ints = 0;
753 if ((ahc->chip & AHC_PCI) != 0
754 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
758 ahc->unsolicited_ints++;
761 ahc->unsolicited_ints = 0;
763 if (intstat & CMDCMPLT) {
764 ahc_outb(ahc, CLRINT, CLRCMDINT);
767 * Ensure that the chip sees that we've cleared
768 * this interrupt before we walk the output fifo.
769 * Otherwise, we may, due to posted bus writes,
770 * clear the interrupt after we finish the scan,
771 * and after the sequencer has added new entries
772 * and asserted the interrupt again.
774 ahc_flush_device_writes(ahc);
775 ahc_run_qoutfifo(ahc);
776 #ifdef AHC_TARGET_MODE
777 if ((ahc->flags & AHC_TARGETROLE) != 0)
778 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
783 * Handle statuses that may invalidate our cached
784 * copy of INTSTAT separately.
786 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
787 /* Hot eject. Do nothing */
788 } else if (intstat & BRKADRINT) {
789 ahc_handle_brkadrint(ahc);
790 } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
792 ahc_pause_bug_fix(ahc);
794 if ((intstat & SEQINT) != 0)
795 ahc_handle_seqint(ahc, intstat);
797 if ((intstat & SCSIINT) != 0)
798 ahc_handle_scsiint(ahc, intstat);
803 /************************* Sequencer Execution Control ************************/
805 * Restart the sequencer program from address zero
808 ahc_restart(struct ahc_softc *ahc)
814 /* No more pending messages. */
815 ahc_clear_msg_state(ahc);
817 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
818 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
819 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
820 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
821 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
822 ahc_outb(ahc, SAVED_LUN, 0xFF);
825 * Ensure that the sequencer's idea of TQINPOS
826 * matches our own. The sequencer increments TQINPOS
827 * only after it sees a DMA complete and a reset could
828 * occur before the increment leaving the kernel to believe
829 * the command arrived but the sequencer to not.
831 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
833 /* Always allow reselection */
834 ahc_outb(ahc, SCSISEQ,
835 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
836 if ((ahc->features & AHC_CMD_CHAN) != 0) {
837 /* Ensure that no DMA operations are in progress */
838 ahc_outb(ahc, CCSCBCNT, 0);
839 ahc_outb(ahc, CCSGCTL, 0);
840 ahc_outb(ahc, CCSCBCTL, 0);
843 * If we were in the process of DMA'ing SCB data into
844 * an SCB, replace that SCB on the free list. This prevents
847 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
848 ahc_add_curscb_to_free_list(ahc);
849 ahc_outb(ahc, SEQ_FLAGS2,
850 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
854 * Clear any pending sequencer interrupt. It is no
855 * longer relevant since we're resetting the Program
858 ahc_outb(ahc, CLRINT, CLRSEQINT);
860 ahc_outb(ahc, MWI_RESIDUAL, 0);
861 ahc_outb(ahc, SEQCTL, ahc->seqctl);
862 ahc_outb(ahc, SEQADDR0, 0);
863 ahc_outb(ahc, SEQADDR1, 0);
866 * Take the LED out of diagnostic mode on PM resume, too
868 sblkctl = ahc_inb(ahc, SBLKCTL);
869 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
874 /************************* Input/Output Queues ********************************/
876 ahc_run_qoutfifo(struct ahc_softc *ahc)
881 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
882 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
884 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
885 if ((ahc->qoutfifonext & 0x03) == 0x03) {
889 * Clear 32bits of QOUTFIFO at a time
890 * so that we don't clobber an incoming
891 * byte DMA to the array on architectures
892 * that only support 32bit load and store
895 modnext = ahc->qoutfifonext & ~0x3;
896 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
897 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
898 ahc->shared_data_dmamap,
899 /*offset*/modnext, /*len*/4,
900 BUS_DMASYNC_PREREAD);
904 scb = ahc_lookup_scb(ahc, scb_index);
906 printk("%s: WARNING no command for scb %d "
907 "(cmdcmplt)\nQOUTPOS = %d\n",
908 ahc_name(ahc), scb_index,
909 (ahc->qoutfifonext - 1) & 0xFF);
914 * Save off the residual
917 ahc_update_residual(ahc, scb);
923 ahc_run_untagged_queues(struct ahc_softc *ahc)
927 for (i = 0; i < 16; i++)
928 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
932 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
936 if (ahc->untagged_queue_lock != 0)
939 if ((scb = TAILQ_FIRST(queue)) != NULL
940 && (scb->flags & SCB_ACTIVE) == 0) {
941 scb->flags |= SCB_ACTIVE;
942 ahc_queue_scb(ahc, scb);
946 /************************* Interrupt Handling *********************************/
948 ahc_handle_brkadrint(struct ahc_softc *ahc)
951 * We upset the sequencer :-(
952 * Lookup the error message
957 error = ahc_inb(ahc, ERROR);
958 for (i = 0; error != 1 && i < num_errors; i++)
960 printk("%s: brkadrint, %s at seqaddr = 0x%x\n",
961 ahc_name(ahc), ahc_hard_errors[i].errmesg,
962 ahc_inb(ahc, SEQADDR0) |
963 (ahc_inb(ahc, SEQADDR1) << 8));
965 ahc_dump_card_state(ahc);
967 /* Tell everyone that this HBA is no longer available */
968 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
969 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
972 /* Disable all interrupt sources by resetting the controller */
977 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
980 struct ahc_devinfo devinfo;
982 ahc_fetch_devinfo(ahc, &devinfo);
985 * Clear the upper byte that holds SEQINT status
986 * codes and clear the SEQINT bit. We will unpause
987 * the sequencer, if appropriate, after servicing
990 ahc_outb(ahc, CLRINT, CLRSEQINT);
991 switch (intstat & SEQINT_MASK) {
995 struct hardware_scb *hscb;
998 * Set the default return value to 0 (don't
999 * send sense). The sense code will change
1002 ahc_outb(ahc, RETURN_1, 0);
1005 * The sequencer will notify us when a command
1006 * has an error that would be of interest to
1007 * the kernel. This allows us to leave the sequencer
1008 * running in the common case of command completes
1009 * without error. The sequencer will already have
1010 * dma'd the SCB back up to us, so we can reference
1011 * the in kernel copy directly.
1013 scb_index = ahc_inb(ahc, SCB_TAG);
1014 scb = ahc_lookup_scb(ahc, scb_index);
1016 ahc_print_devinfo(ahc, &devinfo);
1017 printk("ahc_intr - referenced scb "
1018 "not valid during seqint 0x%x scb(%d)\n",
1019 intstat, scb_index);
1020 ahc_dump_card_state(ahc);
1021 panic("for safety");
1027 /* Don't want to clobber the original sense code */
1028 if ((scb->flags & SCB_SENSE) != 0) {
1030 * Clear the SCB_SENSE Flag and have
1031 * the sequencer do a normal command
1034 scb->flags &= ~SCB_SENSE;
1035 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1038 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
1039 /* Freeze the queue until the client sees the error. */
1040 ahc_freeze_devq(ahc, scb);
1041 ahc_freeze_scb(scb);
1042 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
1043 switch (hscb->shared_data.status.scsi_status) {
1044 case SCSI_STATUS_OK:
1045 printk("%s: Interrupted for status of 0???\n",
1048 case SCSI_STATUS_CMD_TERMINATED:
1049 case SCSI_STATUS_CHECK_COND:
1051 struct ahc_dma_seg *sg;
1052 struct scsi_sense *sc;
1053 struct ahc_initiator_tinfo *targ_info;
1054 struct ahc_tmode_tstate *tstate;
1055 struct ahc_transinfo *tinfo;
1057 if (ahc_debug & AHC_SHOW_SENSE) {
1058 ahc_print_path(ahc, scb);
1059 printk("SCB %d: requests Check Status\n",
1064 if (ahc_perform_autosense(scb) == 0)
1067 targ_info = ahc_fetch_transinfo(ahc,
1072 tinfo = &targ_info->curr;
1074 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
1076 * Save off the residual if there is one.
1078 ahc_update_residual(ahc, scb);
1080 if (ahc_debug & AHC_SHOW_SENSE) {
1081 ahc_print_path(ahc, scb);
1082 printk("Sending Sense\n");
1085 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
1086 sg->len = ahc_get_sense_bufsize(ahc, scb);
1087 sg->len |= AHC_DMA_LAST_SEG;
1089 /* Fixup byte order */
1090 sg->addr = ahc_htole32(sg->addr);
1091 sg->len = ahc_htole32(sg->len);
1093 sc->opcode = REQUEST_SENSE;
1095 if (tinfo->protocol_version <= SCSI_REV_2
1096 && SCB_GET_LUN(scb) < 8)
1097 sc->byte2 = SCB_GET_LUN(scb) << 5;
1100 sc->length = sg->len;
1104 * We can't allow the target to disconnect.
1105 * This will be an untagged transaction and
1106 * having the target disconnect will make this
1107 * transaction indestinguishable from outstanding
1108 * tagged transactions.
1113 * This request sense could be because the
1114 * the device lost power or in some other
1115 * way has lost our transfer negotiations.
1116 * Renegotiate if appropriate. Unit attention
1117 * errors will be reported before any data
1120 if (ahc_get_residual(scb)
1121 == ahc_get_transfer_length(scb)) {
1122 ahc_update_neg_request(ahc, &devinfo,
1124 AHC_NEG_IF_NON_ASYNC);
1126 if (tstate->auto_negotiate & devinfo.target_mask) {
1127 hscb->control |= MK_MESSAGE;
1128 scb->flags &= ~SCB_NEGOTIATE;
1129 scb->flags |= SCB_AUTO_NEGOTIATE;
1131 hscb->cdb_len = sizeof(*sc);
1132 hscb->dataptr = sg->addr;
1133 hscb->datacnt = sg->len;
1134 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
1135 hscb->sgptr = ahc_htole32(hscb->sgptr);
1137 scb->flags |= SCB_SENSE;
1138 ahc_qinfifo_requeue_tail(ahc, scb);
1139 ahc_outb(ahc, RETURN_1, SEND_SENSE);
1141 * Ensure we have enough time to actually
1142 * retrieve the sense.
1144 ahc_scb_timer_reset(scb, 5 * 1000000);
1154 /* Ensure we don't leave the selection hardware on */
1155 ahc_outb(ahc, SCSISEQ,
1156 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1158 printk("%s:%c:%d: no active SCB for reconnecting "
1159 "target - issuing BUS DEVICE RESET\n",
1160 ahc_name(ahc), devinfo.channel, devinfo.target);
1161 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1162 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1163 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1164 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
1165 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1167 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1168 ahc_index_busy_tcl(ahc,
1169 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1170 ahc_inb(ahc, SAVED_LUN))),
1171 ahc_inb(ahc, SINDEX));
1172 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1173 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1174 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1175 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1176 ahc_inb(ahc, SCB_CONTROL));
1177 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1178 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1179 printk("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
1180 printk("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
1181 ahc_dump_card_state(ahc);
1182 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
1183 ahc->msgout_len = 1;
1184 ahc->msgout_index = 0;
1185 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1186 ahc_outb(ahc, MSG_OUT, HOST_MSG);
1187 ahc_assert_atn(ahc);
1192 u_int rejbyte = ahc_inb(ahc, ACCUM);
1193 printk("%s:%c:%d: Warning - unknown message received from "
1194 "target (0x%x). Rejecting\n",
1195 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
1198 case PROTO_VIOLATION:
1200 ahc_handle_proto_violation(ahc);
1204 ahc_handle_ign_wide_residue(ahc, &devinfo);
1207 ahc_reinitialize_dataptrs(ahc);
1213 lastphase = ahc_inb(ahc, LASTPHASE);
1214 printk("%s:%c:%d: unknown scsi bus phase %x, "
1215 "lastphase = 0x%x. Attempting to continue\n",
1216 ahc_name(ahc), devinfo.channel, devinfo.target,
1217 lastphase, ahc_inb(ahc, SCSISIGI));
1220 case MISSED_BUSFREE:
1224 lastphase = ahc_inb(ahc, LASTPHASE);
1225 printk("%s:%c:%d: Missed busfree. "
1226 "Lastphase = 0x%x, Curphase = 0x%x\n",
1227 ahc_name(ahc), devinfo.channel, devinfo.target,
1228 lastphase, ahc_inb(ahc, SCSISIGI));
1235 * The sequencer has encountered a message phase
1236 * that requires host assistance for completion.
1237 * While handling the message phase(s), we will be
1238 * notified by the sequencer after each byte is
1239 * transferred so we can track bus phase changes.
1241 * If this is the first time we've seen a HOST_MSG_LOOP
1242 * interrupt, initialize the state of the host message
1245 if (ahc->msg_type == MSG_TYPE_NONE) {
1250 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1251 if (bus_phase != P_MESGIN
1252 && bus_phase != P_MESGOUT) {
1253 printk("ahc_intr: HOST_MSG_LOOP bad "
1257 * Probably transitioned to bus free before
1258 * we got here. Just punt the message.
1260 ahc_clear_intstat(ahc);
1265 scb_index = ahc_inb(ahc, SCB_TAG);
1266 scb = ahc_lookup_scb(ahc, scb_index);
1267 if (devinfo.role == ROLE_INITIATOR) {
1268 if (bus_phase == P_MESGOUT) {
1270 panic("HOST_MSG_LOOP with "
1274 ahc_setup_initiator_msgout(ahc,
1279 MSG_TYPE_INITIATOR_MSGIN;
1280 ahc->msgin_index = 0;
1283 #ifdef AHC_TARGET_MODE
1285 if (bus_phase == P_MESGOUT) {
1287 MSG_TYPE_TARGET_MSGOUT;
1288 ahc->msgin_index = 0;
1291 ahc_setup_target_msgin(ahc,
1298 ahc_handle_message_phase(ahc);
1304 * If we've cleared the parity error interrupt
1305 * but the sequencer still believes that SCSIPERR
1306 * is true, it must be that the parity error is
1307 * for the currently presented byte on the bus,
1308 * and we are not in a phase (data-in) where we will
1309 * eventually ack this byte. Ack the byte and
1310 * throw it away in the hope that the target will
1311 * take us to message out to deliver the appropriate
1314 if ((intstat & SCSIINT) == 0
1315 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
1317 if ((ahc->features & AHC_DT) == 0) {
1321 * The hardware will only let you ack bytes
1322 * if the expected phase in SCSISIGO matches
1323 * the current phase. Make sure this is
1324 * currently the case.
1326 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1327 ahc_outb(ahc, LASTPHASE, curphase);
1328 ahc_outb(ahc, SCSISIGO, curphase);
1330 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
1334 * In a data phase. Faster to bitbucket
1335 * the data than to individually ack each
1336 * byte. This is also the only strategy
1337 * that will work with AUTOACK enabled.
1339 ahc_outb(ahc, SXFRCTL1,
1340 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
1342 while (--wait != 0) {
1343 if ((ahc_inb(ahc, SCSISIGI)
1348 ahc_outb(ahc, SXFRCTL1,
1349 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
1354 ahc_print_devinfo(ahc, &devinfo);
1355 printk("Unable to clear parity error. "
1356 "Resetting bus.\n");
1357 scb_index = ahc_inb(ahc, SCB_TAG);
1358 scb = ahc_lookup_scb(ahc, scb_index);
1360 ahc_set_transaction_status(scb,
1362 ahc_reset_channel(ahc, devinfo.channel,
1363 /*init reset*/TRUE);
1366 ahc_inb(ahc, SCSIDATL);
1374 * When the sequencer detects an overrun, it
1375 * places the controller in "BITBUCKET" mode
1376 * and allows the target to complete its transfer.
1377 * Unfortunately, none of the counters get updated
1378 * when the controller is in this mode, so we have
1379 * no way of knowing how large the overrun was.
1381 u_int scbindex = ahc_inb(ahc, SCB_TAG);
1382 u_int lastphase = ahc_inb(ahc, LASTPHASE);
1385 scb = ahc_lookup_scb(ahc, scbindex);
1386 for (i = 0; i < num_phases; i++) {
1387 if (lastphase == ahc_phase_table[i].phase)
1390 ahc_print_path(ahc, scb);
1391 printk("data overrun detected %s."
1393 ahc_phase_table[i].phasemsg,
1395 ahc_print_path(ahc, scb);
1396 printk("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
1397 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
1398 ahc_get_transfer_length(scb), scb->sg_count);
1399 if (scb->sg_count > 0) {
1400 for (i = 0; i < scb->sg_count; i++) {
1402 printk("sg[%d] - Addr 0x%x%x : Length %d\n",
1404 (ahc_le32toh(scb->sg_list[i].len) >> 24
1405 & SG_HIGH_ADDR_BITS),
1406 ahc_le32toh(scb->sg_list[i].addr),
1407 ahc_le32toh(scb->sg_list[i].len)
1412 * Set this and it will take effect when the
1413 * target does a command complete.
1415 ahc_freeze_devq(ahc, scb);
1416 if ((scb->flags & SCB_SENSE) == 0) {
1417 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1419 scb->flags &= ~SCB_SENSE;
1420 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1422 ahc_freeze_scb(scb);
1424 if ((ahc->features & AHC_ULTRA2) != 0) {
1426 * Clear the channel in case we return
1427 * to data phase later.
1429 ahc_outb(ahc, SXFRCTL0,
1430 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1431 ahc_outb(ahc, SXFRCTL0,
1432 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1434 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1437 /* Ensure HHADDR is 0 for future DMA operations. */
1438 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
1439 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
1440 ahc_outb(ahc, HADDR, 0);
1441 ahc_outb(ahc, DSCOMMAND1, dscommand1);
1449 printk("%s:%c:%d:%d: Attempt to issue message failed\n",
1450 ahc_name(ahc), devinfo.channel, devinfo.target,
1452 scbindex = ahc_inb(ahc, SCB_TAG);
1453 scb = ahc_lookup_scb(ahc, scbindex);
1455 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1457 * Ensure that we didn't put a second instance of this
1458 * SCB into the QINFIFO.
1460 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
1461 SCB_GET_CHANNEL(ahc, scb),
1462 SCB_GET_LUN(scb), scb->hscb->tag,
1463 ROLE_INITIATOR, /*status*/0,
1469 printk("%s: No free or disconnected SCBs\n", ahc_name(ahc));
1470 ahc_dump_card_state(ahc);
1471 panic("for safety");
1478 scbptr = ahc_inb(ahc, SCBPTR);
1479 printk("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
1480 scbptr, ahc_inb(ahc, ARG_1),
1481 ahc->scb_data->hscbs[scbptr].tag);
1482 ahc_dump_card_state(ahc);
1483 panic("for safety");
1488 printk("%s: BTT calculation out of range\n", ahc_name(ahc));
1489 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1490 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1491 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1492 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
1493 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1494 "SINDEX == 0x%x\n, A == 0x%x\n",
1495 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1496 ahc_index_busy_tcl(ahc,
1497 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1498 ahc_inb(ahc, SAVED_LUN))),
1499 ahc_inb(ahc, SINDEX),
1500 ahc_inb(ahc, ACCUM));
1501 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1502 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1503 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1504 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1505 ahc_inb(ahc, SCB_CONTROL));
1506 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1507 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1508 ahc_dump_card_state(ahc);
1509 panic("for safety");
1513 printk("ahc_intr: seqint, "
1514 "intstat == 0x%x, scsisigi = 0x%x\n",
1515 intstat, ahc_inb(ahc, SCSISIGI));
1520 * The sequencer is paused immediately on
1521 * a SEQINT, so we should restart it when
1528 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
1537 if ((ahc->features & AHC_TWIN) != 0
1538 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
1542 intr_channel = cur_channel;
1544 if ((ahc->features & AHC_ULTRA2) != 0)
1545 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
1548 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1549 if (status == 0 && status0 == 0) {
1550 if ((ahc->features & AHC_TWIN) != 0) {
1551 /* Try the other channel */
1552 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1553 status = ahc_inb(ahc, SSTAT1)
1554 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1555 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1558 printk("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1559 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1565 /* Make sure the sequencer is in a safe location. */
1566 ahc_clear_critical_section(ahc);
1568 scb_index = ahc_inb(ahc, SCB_TAG);
1569 scb = ahc_lookup_scb(ahc, scb_index);
1571 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1574 if ((ahc->features & AHC_ULTRA2) != 0
1575 && (status0 & IOERR) != 0) {
1578 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1579 printk("%s: Transceiver State Has Changed to %s mode\n",
1580 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1581 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1583 * When transitioning to SE mode, the reset line
1584 * glitches, triggering an arbitration bug in some
1585 * Ultra2 controllers. This bug is cleared when we
1586 * assert the reset line. Since a reset glitch has
1587 * already occurred with this transition and a
1588 * transceiver state change is handled just like
1589 * a bus reset anyway, asserting the reset line
1590 * ourselves is safe.
1592 ahc_reset_channel(ahc, intr_channel,
1593 /*Initiate Reset*/now_lvd == 0);
1594 } else if ((status & SCSIRSTI) != 0) {
1595 printk("%s: Someone reset channel %c\n",
1596 ahc_name(ahc), intr_channel);
1597 if (intr_channel != cur_channel)
1598 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1599 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1600 } else if ((status & SCSIPERR) != 0) {
1602 * Determine the bus phase and queue an appropriate message.
1603 * SCSIPERR is latched true as soon as a parity error
1604 * occurs. If the sequencer acked the transfer that
1605 * caused the parity error and the currently presented
1606 * transfer on the bus has correct parity, SCSIPERR will
1607 * be cleared by CLRSCSIPERR. Use this to determine if
1608 * we should look at the last phase the sequencer recorded,
1609 * or the current phase presented on the bus.
1611 struct ahc_devinfo devinfo;
1621 lastphase = ahc_inb(ahc, LASTPHASE);
1622 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1623 sstat2 = ahc_inb(ahc, SSTAT2);
1624 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1626 * For all phases save DATA, the sequencer won't
1627 * automatically ack a byte that has a parity error
1628 * in it. So the only way that the current phase
1629 * could be 'data-in' is if the parity error is for
1630 * an already acked byte in the data phase. During
1631 * synchronous data-in transfers, we may actually
1632 * ack bytes before latching the current phase in
1633 * LASTPHASE, leading to the discrepancy between
1634 * curphase and lastphase.
1636 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1637 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1638 errorphase = curphase;
1640 errorphase = lastphase;
1642 for (i = 0; i < num_phases; i++) {
1643 if (errorphase == ahc_phase_table[i].phase)
1646 mesg_out = ahc_phase_table[i].mesg_out;
1649 if (SCB_IS_SILENT(scb))
1652 ahc_print_path(ahc, scb);
1653 scb->flags |= SCB_TRANSMISSION_ERROR;
1655 printk("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1656 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1657 scsirate = ahc_inb(ahc, SCSIRATE);
1658 if (silent == FALSE) {
1659 printk("parity error detected %s. "
1660 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1661 ahc_phase_table[i].phasemsg,
1662 ahc_inw(ahc, SEQADDR0),
1664 if ((ahc->features & AHC_DT) != 0) {
1665 if ((sstat2 & CRCVALERR) != 0)
1666 printk("\tCRC Value Mismatch\n");
1667 if ((sstat2 & CRCENDERR) != 0)
1668 printk("\tNo terminal CRC packet "
1670 if ((sstat2 & CRCREQERR) != 0)
1671 printk("\tIllegal CRC packet "
1673 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1674 printk("\tUnexpected %sDT Data Phase\n",
1675 (scsirate & SINGLE_EDGE)
1680 if ((ahc->features & AHC_DT) != 0
1681 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1683 * This error applies regardless of
1684 * data direction, so ignore the value
1685 * in the phase table.
1687 mesg_out = MSG_INITIATOR_DET_ERR;
1691 * We've set the hardware to assert ATN if we
1692 * get a parity error on "in" phases, so all we
1693 * need to do is stuff the message buffer with
1694 * the appropriate message. "In" phases have set
1695 * mesg_out to something other than MSG_NOP.
1697 if (mesg_out != MSG_NOOP) {
1698 if (ahc->msg_type != MSG_TYPE_NONE)
1699 ahc->send_msg_perror = TRUE;
1701 ahc_outb(ahc, MSG_OUT, mesg_out);
1704 * Force a renegotiation with this target just in
1705 * case we are out of sync for some external reason
1706 * unknown (or unreported) by the target.
1708 ahc_fetch_devinfo(ahc, &devinfo);
1709 ahc_force_renegotiation(ahc, &devinfo);
1711 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1713 } else if ((status & SELTO) != 0) {
1716 /* Stop the selection */
1717 ahc_outb(ahc, SCSISEQ, 0);
1719 /* No more pending messages */
1720 ahc_clear_msg_state(ahc);
1722 /* Clear interrupt state */
1723 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1724 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1727 * Although the driver does not care about the
1728 * 'Selection in Progress' status bit, the busy
1729 * LED does. SELINGO is only cleared by a successful
1730 * selection, so we must manually clear it to insure
1731 * the LED turns off just incase no future successful
1732 * selections occur (e.g. no devices on the bus).
1734 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1736 scbptr = ahc_inb(ahc, WAITING_SCBH);
1737 ahc_outb(ahc, SCBPTR, scbptr);
1738 scb_index = ahc_inb(ahc, SCB_TAG);
1740 scb = ahc_lookup_scb(ahc, scb_index);
1742 printk("%s: ahc_intr - referenced scb not "
1743 "valid during SELTO scb(%d, %d)\n",
1744 ahc_name(ahc), scbptr, scb_index);
1745 ahc_dump_card_state(ahc);
1747 struct ahc_devinfo devinfo;
1749 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1750 ahc_print_path(ahc, scb);
1751 printk("Saw Selection Timeout for SCB 0x%x\n",
1755 ahc_scb_devinfo(ahc, &devinfo, scb);
1756 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1757 ahc_freeze_devq(ahc, scb);
1760 * Cancel any pending transactions on the device
1761 * now that it seems to be missing. This will
1762 * also revert us to async/narrow transfers until
1763 * we can renegotiate with the device.
1765 ahc_handle_devreset(ahc, &devinfo,
1767 "Selection Timeout",
1768 /*verbose_level*/1);
1770 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1772 } else if ((status & BUSFREE) != 0
1773 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1774 struct ahc_devinfo devinfo;
1779 u_int initiator_role_id;
1784 * Clear our selection hardware as soon as possible.
1785 * We may have an entry in the waiting Q for this target,
1786 * that is affected by this busfree and we don't want to
1787 * go about selecting the target while we handle the event.
1789 ahc_outb(ahc, SCSISEQ,
1790 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1793 * Disable busfree interrupts and clear the busfree
1794 * interrupt status. We do this here so that several
1795 * bus transactions occur prior to clearing the SCSIINT
1796 * latch. It can take a bit for the clearing to take effect.
1798 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1799 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1802 * Look at what phase we were last in.
1803 * If its message out, chances are pretty good
1804 * that the busfree was in response to one of
1805 * our abort requests.
1807 lastphase = ahc_inb(ahc, LASTPHASE);
1808 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1809 saved_lun = ahc_inb(ahc, SAVED_LUN);
1810 target = SCSIID_TARGET(ahc, saved_scsiid);
1811 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1812 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1813 ahc_compile_devinfo(&devinfo, initiator_role_id,
1814 target, saved_lun, channel, ROLE_INITIATOR);
1817 if (lastphase == P_MESGOUT) {
1820 tag = SCB_LIST_NULL;
1821 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1822 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1823 if (ahc->msgout_buf[ahc->msgout_index - 1]
1825 tag = scb->hscb->tag;
1826 ahc_print_path(ahc, scb);
1827 printk("SCB %d - Abort%s Completed.\n",
1828 scb->hscb->tag, tag == SCB_LIST_NULL ?
1830 ahc_abort_scbs(ahc, target, channel,
1835 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1836 MSG_BUS_DEV_RESET, TRUE)) {
1837 ahc_compile_devinfo(&devinfo,
1843 ahc_handle_devreset(ahc, &devinfo,
1846 /*verbose_level*/0);
1848 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1849 MSG_EXT_PPR, FALSE)) {
1850 struct ahc_initiator_tinfo *tinfo;
1851 struct ahc_tmode_tstate *tstate;
1854 * PPR Rejected. Try non-ppr negotiation
1855 * and retry command.
1857 tinfo = ahc_fetch_transinfo(ahc,
1862 tinfo->curr.transport_version = 2;
1863 tinfo->goal.transport_version = 2;
1864 tinfo->goal.ppr_options = 0;
1865 ahc_qinfifo_requeue_tail(ahc, scb);
1867 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1868 MSG_EXT_WDTR, FALSE)) {
1870 * Negotiation Rejected. Go-narrow and
1873 ahc_set_width(ahc, &devinfo,
1874 MSG_EXT_WDTR_BUS_8_BIT,
1875 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1877 ahc_qinfifo_requeue_tail(ahc, scb);
1879 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1880 MSG_EXT_SDTR, FALSE)) {
1882 * Negotiation Rejected. Go-async and
1885 ahc_set_syncrate(ahc, &devinfo,
1887 /*period*/0, /*offset*/0,
1889 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1891 ahc_qinfifo_requeue_tail(ahc, scb);
1895 if (printerror != 0) {
1901 if ((scb->hscb->control & TAG_ENB) != 0)
1902 tag = scb->hscb->tag;
1904 tag = SCB_LIST_NULL;
1905 ahc_print_path(ahc, scb);
1906 ahc_abort_scbs(ahc, target, channel,
1907 SCB_GET_LUN(scb), tag,
1912 * We had not fully identified this connection,
1913 * so we cannot abort anything.
1915 printk("%s: ", ahc_name(ahc));
1917 for (i = 0; i < num_phases; i++) {
1918 if (lastphase == ahc_phase_table[i].phase)
1921 if (lastphase != P_BUSFREE) {
1923 * Renegotiate with this device at the
1924 * next opportunity just in case this busfree
1925 * is due to a negotiation mismatch with the
1928 ahc_force_renegotiation(ahc, &devinfo);
1930 printk("Unexpected busfree %s\n"
1931 "SEQADDR == 0x%x\n",
1932 ahc_phase_table[i].phasemsg,
1933 ahc_inb(ahc, SEQADDR0)
1934 | (ahc_inb(ahc, SEQADDR1) << 8));
1936 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1939 printk("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1940 ahc_name(ahc), status);
1941 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1946 * Force renegotiation to occur the next time we initiate
1947 * a command to the current device.
1950 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1952 struct ahc_initiator_tinfo *targ_info;
1953 struct ahc_tmode_tstate *tstate;
1955 targ_info = ahc_fetch_transinfo(ahc,
1957 devinfo->our_scsiid,
1960 ahc_update_neg_request(ahc, devinfo, tstate,
1961 targ_info, AHC_NEG_IF_NON_ASYNC);
1964 #define AHC_MAX_STEPS 2000
1966 ahc_clear_critical_section(struct ahc_softc *ahc)
1973 if (ahc->num_critical_sections == 0)
1985 seqaddr = ahc_inb(ahc, SEQADDR0)
1986 | (ahc_inb(ahc, SEQADDR1) << 8);
1989 * Seqaddr represents the next instruction to execute,
1990 * so we are really executing the instruction just
1995 cs = ahc->critical_sections;
1996 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1998 if (cs->begin < seqaddr && cs->end >= seqaddr)
2002 if (i == ahc->num_critical_sections)
2005 if (steps > AHC_MAX_STEPS) {
2006 printk("%s: Infinite loop in critical section\n",
2008 ahc_dump_card_state(ahc);
2009 panic("critical section loop");
2013 if (stepping == FALSE) {
2016 * Disable all interrupt sources so that the
2017 * sequencer will not be stuck by a pausing
2018 * interrupt condition while we attempt to
2019 * leave a critical section.
2021 simode0 = ahc_inb(ahc, SIMODE0);
2022 ahc_outb(ahc, SIMODE0, 0);
2023 simode1 = ahc_inb(ahc, SIMODE1);
2024 if ((ahc->features & AHC_DT) != 0)
2026 * On DT class controllers, we
2027 * use the enhanced busfree logic.
2028 * Unfortunately we cannot re-enable
2029 * busfree detection within the
2030 * current connection, so we must
2031 * leave it on while single stepping.
2033 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
2035 ahc_outb(ahc, SIMODE1, 0);
2036 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2037 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
2040 if ((ahc->features & AHC_DT) != 0) {
2041 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
2042 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2044 ahc_outb(ahc, HCNTRL, ahc->unpause);
2045 while (!ahc_is_paused(ahc))
2049 ahc_outb(ahc, SIMODE0, simode0);
2050 ahc_outb(ahc, SIMODE1, simode1);
2051 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2056 * Clear any pending interrupt status.
2059 ahc_clear_intstat(struct ahc_softc *ahc)
2061 /* Clear any interrupt conditions this may have caused */
2062 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2063 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
2065 ahc_flush_device_writes(ahc);
2066 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
2067 ahc_flush_device_writes(ahc);
2068 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2069 ahc_flush_device_writes(ahc);
2072 /**************************** Debugging Routines ******************************/
2074 uint32_t ahc_debug = AHC_DEBUG_OPTS;
2079 ahc_print_scb(struct scb *scb)
2083 struct hardware_scb *hscb = scb->hscb;
2085 printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2091 printk("Shared Data: ");
2092 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
2093 printk("%#02x", hscb->shared_data.cdb[i]);
2094 printk(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
2095 ahc_le32toh(hscb->dataptr),
2096 ahc_le32toh(hscb->datacnt),
2097 ahc_le32toh(hscb->sgptr),
2099 if (scb->sg_count > 0) {
2100 for (i = 0; i < scb->sg_count; i++) {
2101 printk("sg[%d] - Addr 0x%x%x : Length %d\n",
2103 (ahc_le32toh(scb->sg_list[i].len) >> 24
2104 & SG_HIGH_ADDR_BITS),
2105 ahc_le32toh(scb->sg_list[i].addr),
2106 ahc_le32toh(scb->sg_list[i].len));
2112 /************************* Transfer Negotiation *******************************/
2114 * Allocate per target mode instance (ID we respond to as a target)
2115 * transfer negotiation data structures.
2117 static struct ahc_tmode_tstate *
2118 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
2120 struct ahc_tmode_tstate *master_tstate;
2121 struct ahc_tmode_tstate *tstate;
2124 master_tstate = ahc->enabled_targets[ahc->our_id];
2125 if (channel == 'B') {
2127 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
2129 if (ahc->enabled_targets[scsi_id] != NULL
2130 && ahc->enabled_targets[scsi_id] != master_tstate)
2131 panic("%s: ahc_alloc_tstate - Target already allocated",
2133 tstate = kmalloc(sizeof(*tstate), GFP_ATOMIC);
2138 * If we have allocated a master tstate, copy user settings from
2139 * the master tstate (taken from SRAM or the EEPROM) for this
2140 * channel, but reset our current and goal settings to async/narrow
2141 * until an initiator talks to us.
2143 if (master_tstate != NULL) {
2144 memcpy(tstate, master_tstate, sizeof(*tstate));
2145 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2146 tstate->ultraenb = 0;
2147 for (i = 0; i < AHC_NUM_TARGETS; i++) {
2148 memset(&tstate->transinfo[i].curr, 0,
2149 sizeof(tstate->transinfo[i].curr));
2150 memset(&tstate->transinfo[i].goal, 0,
2151 sizeof(tstate->transinfo[i].goal));
2154 memset(tstate, 0, sizeof(*tstate));
2155 ahc->enabled_targets[scsi_id] = tstate;
2159 #ifdef AHC_TARGET_MODE
2161 * Free per target mode instance (ID we respond to as a target)
2162 * transfer negotiation data structures.
2165 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
2167 struct ahc_tmode_tstate *tstate;
2170 * Don't clean up our "master" tstate.
2171 * It has our default user settings.
2173 if (((channel == 'B' && scsi_id == ahc->our_id_b)
2174 || (channel == 'A' && scsi_id == ahc->our_id))
2180 tstate = ahc->enabled_targets[scsi_id];
2182 ahc->enabled_targets[scsi_id] = NULL;
2187 * Called when we have an active connection to a target on the bus,
2188 * this function finds the nearest syncrate to the input period limited
2189 * by the capabilities of the bus connectivity of and sync settings for
2192 static const struct ahc_syncrate *
2193 ahc_devlimited_syncrate(struct ahc_softc *ahc,
2194 struct ahc_initiator_tinfo *tinfo,
2195 u_int *period, u_int *ppr_options, role_t role)
2197 struct ahc_transinfo *transinfo;
2200 if ((ahc->features & AHC_ULTRA2) != 0) {
2201 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
2202 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
2203 maxsync = AHC_SYNCRATE_DT;
2205 maxsync = AHC_SYNCRATE_ULTRA;
2206 /* Can't do DT on an SE bus */
2207 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2209 } else if ((ahc->features & AHC_ULTRA) != 0) {
2210 maxsync = AHC_SYNCRATE_ULTRA;
2212 maxsync = AHC_SYNCRATE_FAST;
2215 * Never allow a value higher than our current goal
2216 * period otherwise we may allow a target initiated
2217 * negotiation to go above the limit as set by the
2218 * user. In the case of an initiator initiated
2219 * sync negotiation, we limit based on the user
2220 * setting. This allows the system to still accept
2221 * incoming negotiations even if target initiated
2222 * negotiation is not performed.
2224 if (role == ROLE_TARGET)
2225 transinfo = &tinfo->user;
2227 transinfo = &tinfo->goal;
2228 *ppr_options &= transinfo->ppr_options;
2229 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2230 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
2231 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2233 if (transinfo->period == 0) {
2238 *period = max(*period, (u_int)transinfo->period);
2239 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
2243 * Look up the valid period to SCSIRATE conversion in our table.
2244 * Return the period and offset that should be sent to the target
2245 * if this was the beginning of an SDTR.
2247 const struct ahc_syncrate *
2248 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
2249 u_int *ppr_options, u_int maxsync)
2251 const struct ahc_syncrate *syncrate;
2253 if ((ahc->features & AHC_DT) == 0)
2254 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2256 /* Skip all DT only entries if DT is not available */
2257 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2258 && maxsync < AHC_SYNCRATE_ULTRA2)
2259 maxsync = AHC_SYNCRATE_ULTRA2;
2261 /* Now set the maxsync based on the card capabilities
2262 * DT is already done above */
2263 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2264 && maxsync < AHC_SYNCRATE_ULTRA)
2265 maxsync = AHC_SYNCRATE_ULTRA;
2266 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2267 && maxsync < AHC_SYNCRATE_FAST)
2268 maxsync = AHC_SYNCRATE_FAST;
2270 for (syncrate = &ahc_syncrates[maxsync];
2271 syncrate->rate != NULL;
2275 * The Ultra2 table doesn't go as low
2276 * as for the Fast/Ultra cards.
2278 if ((ahc->features & AHC_ULTRA2) != 0
2279 && (syncrate->sxfr_u2 == 0))
2282 if (*period <= syncrate->period) {
2284 * When responding to a target that requests
2285 * sync, the requested rate may fall between
2286 * two rates that we can output, but still be
2287 * a rate that we can receive. Because of this,
2288 * we want to respond to the target with
2289 * the same rate that it sent to us even
2290 * if the period we use to send data to it
2291 * is lower. Only lower the response period
2294 if (syncrate == &ahc_syncrates[maxsync])
2295 *period = syncrate->period;
2298 * At some speeds, we only support
2301 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
2302 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2308 || (syncrate->rate == NULL)
2309 || ((ahc->features & AHC_ULTRA2) != 0
2310 && (syncrate->sxfr_u2 == 0))) {
2311 /* Use asynchronous transfers. */
2314 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2320 * Convert from an entry in our syncrate table to the SCSI equivalent
2321 * sync "period" factor.
2324 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
2326 const struct ahc_syncrate *syncrate;
2328 if ((ahc->features & AHC_ULTRA2) != 0)
2329 scsirate &= SXFR_ULTRA2;
2333 /* now set maxsync based on card capabilities */
2334 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
2335 maxsync = AHC_SYNCRATE_ULTRA2;
2336 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2337 && maxsync < AHC_SYNCRATE_ULTRA)
2338 maxsync = AHC_SYNCRATE_ULTRA;
2339 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2340 && maxsync < AHC_SYNCRATE_FAST)
2341 maxsync = AHC_SYNCRATE_FAST;
2344 syncrate = &ahc_syncrates[maxsync];
2345 while (syncrate->rate != NULL) {
2347 if ((ahc->features & AHC_ULTRA2) != 0) {
2348 if (syncrate->sxfr_u2 == 0)
2350 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
2351 return (syncrate->period);
2352 } else if (scsirate == (syncrate->sxfr & SXFR)) {
2353 return (syncrate->period);
2357 return (0); /* async */
2361 * Truncate the given synchronous offset to a value the
2362 * current adapter type and syncrate are capable of.
2365 ahc_validate_offset(struct ahc_softc *ahc,
2366 struct ahc_initiator_tinfo *tinfo,
2367 const struct ahc_syncrate *syncrate,
2368 u_int *offset, int wide, role_t role)
2372 /* Limit offset to what we can do */
2373 if (syncrate == NULL) {
2375 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2376 maxoffset = MAX_OFFSET_ULTRA2;
2379 maxoffset = MAX_OFFSET_16BIT;
2381 maxoffset = MAX_OFFSET_8BIT;
2383 *offset = min(*offset, maxoffset);
2384 if (tinfo != NULL) {
2385 if (role == ROLE_TARGET)
2386 *offset = min(*offset, (u_int)tinfo->user.offset);
2388 *offset = min(*offset, (u_int)tinfo->goal.offset);
2393 * Truncate the given transfer width parameter to a value the
2394 * current adapter type is capable of.
2397 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
2398 u_int *bus_width, role_t role)
2400 switch (*bus_width) {
2402 if (ahc->features & AHC_WIDE) {
2404 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2408 case MSG_EXT_WDTR_BUS_8_BIT:
2409 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2412 if (tinfo != NULL) {
2413 if (role == ROLE_TARGET)
2414 *bus_width = min((u_int)tinfo->user.width, *bus_width);
2416 *bus_width = min((u_int)tinfo->goal.width, *bus_width);
2421 * Update the bitmask of targets for which the controller should
2422 * negotiate with at the next convenient opportunity. This currently
2423 * means the next time we send the initial identify messages for
2424 * a new transaction.
2427 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2428 struct ahc_tmode_tstate *tstate,
2429 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
2431 u_int auto_negotiate_orig;
2433 auto_negotiate_orig = tstate->auto_negotiate;
2434 if (neg_type == AHC_NEG_ALWAYS) {
2436 * Force our "current" settings to be
2437 * unknown so that unless a bus reset
2438 * occurs the need to renegotiate is
2439 * recorded persistently.
2441 if ((ahc->features & AHC_WIDE) != 0)
2442 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
2443 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
2444 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
2446 if (tinfo->curr.period != tinfo->goal.period
2447 || tinfo->curr.width != tinfo->goal.width
2448 || tinfo->curr.offset != tinfo->goal.offset
2449 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
2450 || (neg_type == AHC_NEG_IF_NON_ASYNC
2451 && (tinfo->goal.offset != 0
2452 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
2453 || tinfo->goal.ppr_options != 0)))
2454 tstate->auto_negotiate |= devinfo->target_mask;
2456 tstate->auto_negotiate &= ~devinfo->target_mask;
2458 return (auto_negotiate_orig != tstate->auto_negotiate);
2462 * Update the user/goal/curr tables of synchronous negotiation
2463 * parameters as well as, in the case of a current or active update,
2464 * any data structures on the host controller. In the case of an
2465 * active update, the specified target is currently talking to us on
2466 * the bus, so the transfer parameter update must take effect
2470 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2471 const struct ahc_syncrate *syncrate, u_int period,
2472 u_int offset, u_int ppr_options, u_int type, int paused)
2474 struct ahc_initiator_tinfo *tinfo;
2475 struct ahc_tmode_tstate *tstate;
2482 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2485 if (syncrate == NULL) {
2490 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2491 devinfo->target, &tstate);
2493 if ((type & AHC_TRANS_USER) != 0) {
2494 tinfo->user.period = period;
2495 tinfo->user.offset = offset;
2496 tinfo->user.ppr_options = ppr_options;
2499 if ((type & AHC_TRANS_GOAL) != 0) {
2500 tinfo->goal.period = period;
2501 tinfo->goal.offset = offset;
2502 tinfo->goal.ppr_options = ppr_options;
2505 old_period = tinfo->curr.period;
2506 old_offset = tinfo->curr.offset;
2507 old_ppr = tinfo->curr.ppr_options;
2509 if ((type & AHC_TRANS_CUR) != 0
2510 && (old_period != period
2511 || old_offset != offset
2512 || old_ppr != ppr_options)) {
2516 scsirate = tinfo->scsirate;
2517 if ((ahc->features & AHC_ULTRA2) != 0) {
2519 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
2520 if (syncrate != NULL) {
2521 scsirate |= syncrate->sxfr_u2;
2522 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
2523 scsirate |= ENABLE_CRC;
2525 scsirate |= SINGLE_EDGE;
2529 scsirate &= ~(SXFR|SOFS);
2531 * Ensure Ultra mode is set properly for
2534 tstate->ultraenb &= ~devinfo->target_mask;
2535 if (syncrate != NULL) {
2536 if (syncrate->sxfr & ULTRA_SXFR) {
2538 devinfo->target_mask;
2540 scsirate |= syncrate->sxfr & SXFR;
2541 scsirate |= offset & SOFS;
2546 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
2547 sxfrctl0 &= ~FAST20;
2548 if (tstate->ultraenb & devinfo->target_mask)
2550 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
2554 ahc_outb(ahc, SCSIRATE, scsirate);
2555 if ((ahc->features & AHC_ULTRA2) != 0)
2556 ahc_outb(ahc, SCSIOFFSET, offset);
2559 tinfo->scsirate = scsirate;
2560 tinfo->curr.period = period;
2561 tinfo->curr.offset = offset;
2562 tinfo->curr.ppr_options = ppr_options;
2564 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2565 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2568 printk("%s: target %d synchronous at %sMHz%s, "
2569 "offset = 0x%x\n", ahc_name(ahc),
2570 devinfo->target, syncrate->rate,
2571 (ppr_options & MSG_EXT_PPR_DT_REQ)
2572 ? " DT" : "", offset);
2574 printk("%s: target %d using "
2575 "asynchronous transfers\n",
2576 ahc_name(ahc), devinfo->target);
2581 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2582 tinfo, AHC_NEG_TO_GOAL);
2585 ahc_update_pending_scbs(ahc);
2589 * Update the user/goal/curr tables of wide negotiation
2590 * parameters as well as, in the case of a current or active update,
2591 * any data structures on the host controller. In the case of an
2592 * active update, the specified target is currently talking to us on
2593 * the bus, so the transfer parameter update must take effect
2597 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2598 u_int width, u_int type, int paused)
2600 struct ahc_initiator_tinfo *tinfo;
2601 struct ahc_tmode_tstate *tstate;
2606 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2608 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2609 devinfo->target, &tstate);
2611 if ((type & AHC_TRANS_USER) != 0)
2612 tinfo->user.width = width;
2614 if ((type & AHC_TRANS_GOAL) != 0)
2615 tinfo->goal.width = width;
2617 oldwidth = tinfo->curr.width;
2618 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2622 scsirate = tinfo->scsirate;
2623 scsirate &= ~WIDEXFER;
2624 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2625 scsirate |= WIDEXFER;
2627 tinfo->scsirate = scsirate;
2630 ahc_outb(ahc, SCSIRATE, scsirate);
2632 tinfo->curr.width = width;
2634 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2635 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2637 printk("%s: target %d using %dbit transfers\n",
2638 ahc_name(ahc), devinfo->target,
2639 8 * (0x01 << width));
2643 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2644 tinfo, AHC_NEG_TO_GOAL);
2646 ahc_update_pending_scbs(ahc);
2650 * Update the current state of tagged queuing for a given target.
2653 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
2654 struct ahc_devinfo *devinfo, ahc_queue_alg alg)
2656 struct scsi_device *sdev = cmd->device;
2658 ahc_platform_set_tags(ahc, sdev, devinfo, alg);
2659 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2660 devinfo->lun, AC_TRANSFER_NEG);
2664 * When the transfer settings for a connection change, update any
2665 * in-transit SCBs to contain the new data so the hardware will
2666 * be set correctly during future (re)selections.
2669 ahc_update_pending_scbs(struct ahc_softc *ahc)
2671 struct scb *pending_scb;
2672 int pending_scb_count;
2678 * Traverse the pending SCB list and ensure that all of the
2679 * SCBs there have the proper settings.
2681 pending_scb_count = 0;
2682 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2683 struct ahc_devinfo devinfo;
2684 struct hardware_scb *pending_hscb;
2685 struct ahc_initiator_tinfo *tinfo;
2686 struct ahc_tmode_tstate *tstate;
2688 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2689 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2691 devinfo.target, &tstate);
2692 pending_hscb = pending_scb->hscb;
2693 pending_hscb->control &= ~ULTRAENB;
2694 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2695 pending_hscb->control |= ULTRAENB;
2696 pending_hscb->scsirate = tinfo->scsirate;
2697 pending_hscb->scsioffset = tinfo->curr.offset;
2698 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2699 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2700 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2701 pending_hscb->control &= ~MK_MESSAGE;
2703 ahc_sync_scb(ahc, pending_scb,
2704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2705 pending_scb_count++;
2708 if (pending_scb_count == 0)
2711 if (ahc_is_paused(ahc)) {
2718 saved_scbptr = ahc_inb(ahc, SCBPTR);
2719 /* Ensure that the hscbs down on the card match the new information */
2720 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2721 struct hardware_scb *pending_hscb;
2725 ahc_outb(ahc, SCBPTR, i);
2726 scb_tag = ahc_inb(ahc, SCB_TAG);
2727 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2728 if (pending_scb == NULL)
2731 pending_hscb = pending_scb->hscb;
2732 control = ahc_inb(ahc, SCB_CONTROL);
2733 control &= ~(ULTRAENB|MK_MESSAGE);
2734 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2735 ahc_outb(ahc, SCB_CONTROL, control);
2736 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2737 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2739 ahc_outb(ahc, SCBPTR, saved_scbptr);
2745 /**************************** Pathing Information *****************************/
2747 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2753 if (ahc_inb(ahc, SSTAT0) & TARGET)
2756 role = ROLE_INITIATOR;
2758 if (role == ROLE_TARGET
2759 && (ahc->features & AHC_MULTI_TID) != 0
2760 && (ahc_inb(ahc, SEQ_FLAGS)
2761 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2762 /* We were selected, so pull our id from TARGIDIN */
2763 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2764 } else if ((ahc->features & AHC_ULTRA2) != 0)
2765 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2767 our_id = ahc_inb(ahc, SCSIID) & OID;
2769 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2770 ahc_compile_devinfo(devinfo,
2772 SCSIID_TARGET(ahc, saved_scsiid),
2773 ahc_inb(ahc, SAVED_LUN),
2774 SCSIID_CHANNEL(ahc, saved_scsiid),
2778 static const struct ahc_phase_table_entry*
2779 ahc_lookup_phase_entry(int phase)
2781 const struct ahc_phase_table_entry *entry;
2782 const struct ahc_phase_table_entry *last_entry;
2785 * num_phases doesn't include the default entry which
2786 * will be returned if the phase doesn't match.
2788 last_entry = &ahc_phase_table[num_phases];
2789 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2790 if (phase == entry->phase)
2797 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2798 u_int lun, char channel, role_t role)
2800 devinfo->our_scsiid = our_id;
2801 devinfo->target = target;
2803 devinfo->target_offset = target;
2804 devinfo->channel = channel;
2805 devinfo->role = role;
2807 devinfo->target_offset += 8;
2808 devinfo->target_mask = (0x01 << devinfo->target_offset);
2812 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2814 printk("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2815 devinfo->target, devinfo->lun);
2819 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2825 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2826 role = ROLE_INITIATOR;
2827 if ((scb->flags & SCB_TARGET_SCB) != 0)
2829 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2830 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2834 /************************ Message Phase Processing ****************************/
2836 ahc_assert_atn(struct ahc_softc *ahc)
2841 if ((ahc->features & AHC_DT) == 0)
2842 scsisigo |= ahc_inb(ahc, SCSISIGI);
2843 ahc_outb(ahc, SCSISIGO, scsisigo);
2847 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2848 * or enters the initial message out phase, we are interrupted. Fill our
2849 * outgoing message buffer with the appropriate message and beging handing
2850 * the message phase(s) manually.
2853 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2857 * To facilitate adding multiple messages together,
2858 * each routine should increment the index and len
2859 * variables instead of setting them explicitly.
2861 ahc->msgout_index = 0;
2862 ahc->msgout_len = 0;
2864 if ((scb->flags & SCB_DEVICE_RESET) == 0
2865 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2868 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2869 if ((scb->hscb->control & DISCENB) != 0)
2870 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2871 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2874 if ((scb->hscb->control & TAG_ENB) != 0) {
2875 ahc->msgout_buf[ahc->msgout_index++] =
2876 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2877 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2878 ahc->msgout_len += 2;
2882 if (scb->flags & SCB_DEVICE_RESET) {
2883 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2885 ahc_print_path(ahc, scb);
2886 printk("Bus Device Reset Message Sent\n");
2888 * Clear our selection hardware in advance of
2889 * the busfree. We may have an entry in the waiting
2890 * Q for this target, and we don't want to go about
2891 * selecting while we handle the busfree and blow it
2894 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2895 } else if ((scb->flags & SCB_ABORT) != 0) {
2896 if ((scb->hscb->control & TAG_ENB) != 0)
2897 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2899 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2901 ahc_print_path(ahc, scb);
2902 printk("Abort%s Message Sent\n",
2903 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2905 * Clear our selection hardware in advance of
2906 * the busfree. We may have an entry in the waiting
2907 * Q for this target, and we don't want to go about
2908 * selecting while we handle the busfree and blow it
2911 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2912 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2913 ahc_build_transfer_msg(ahc, devinfo);
2915 printk("ahc_intr: AWAITING_MSG for an SCB that "
2916 "does not have a waiting message\n");
2917 printk("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2918 devinfo->target_mask);
2919 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2920 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2921 ahc_inb(ahc, MSG_OUT), scb->flags);
2925 * Clear the MK_MESSAGE flag from the SCB so we aren't
2926 * asked to send this message again.
2928 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2929 scb->hscb->control &= ~MK_MESSAGE;
2930 ahc->msgout_index = 0;
2931 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2935 * Build an appropriate transfer negotiation message for the
2936 * currently active target.
2939 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2942 * We need to initiate transfer negotiations.
2943 * If our current and goal settings are identical,
2944 * we want to renegotiate due to a check condition.
2946 struct ahc_initiator_tinfo *tinfo;
2947 struct ahc_tmode_tstate *tstate;
2948 const struct ahc_syncrate *rate;
2956 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2957 devinfo->target, &tstate);
2959 * Filter our period based on the current connection.
2960 * If we can't perform DT transfers on this segment (not in LVD
2961 * mode for instance), then our decision to issue a PPR message
2964 period = tinfo->goal.period;
2965 offset = tinfo->goal.offset;
2966 ppr_options = tinfo->goal.ppr_options;
2967 /* Target initiated PPR is not allowed in the SCSI spec */
2968 if (devinfo->role == ROLE_TARGET)
2970 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2971 &ppr_options, devinfo->role);
2972 dowide = tinfo->curr.width != tinfo->goal.width;
2973 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2975 * Only use PPR if we have options that need it, even if the device
2976 * claims to support it. There might be an expander in the way
2979 doppr = ppr_options != 0;
2981 if (!dowide && !dosync && !doppr) {
2982 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2983 dosync = tinfo->goal.offset != 0;
2986 if (!dowide && !dosync && !doppr) {
2988 * Force async with a WDTR message if we have a wide bus,
2989 * or just issue an SDTR with a 0 offset.
2991 if ((ahc->features & AHC_WIDE) != 0)
2997 ahc_print_devinfo(ahc, devinfo);
2998 printk("Ensuring async\n");
3002 /* Target initiated PPR is not allowed in the SCSI spec */
3003 if (devinfo->role == ROLE_TARGET)
3007 * Both the PPR message and SDTR message require the
3008 * goal syncrate to be limited to what the target device
3009 * is capable of handling (based on whether an LVD->SE
3010 * expander is on the bus), so combine these two cases.
3011 * Regardless, guarantee that if we are using WDTR and SDTR
3012 * messages that WDTR comes first.
3014 if (doppr || (dosync && !dowide)) {
3016 offset = tinfo->goal.offset;
3017 ahc_validate_offset(ahc, tinfo, rate, &offset,
3018 doppr ? tinfo->goal.width
3019 : tinfo->curr.width,
3022 ahc_construct_ppr(ahc, devinfo, period, offset,
3023 tinfo->goal.width, ppr_options);
3025 ahc_construct_sdtr(ahc, devinfo, period, offset);
3028 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
3033 * Build a synchronous negotiation message in our message
3034 * buffer based on the input parameters.
3037 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3038 u_int period, u_int offset)
3041 period = AHC_ASYNC_XFER_PERIOD;
3042 ahc->msgout_index += spi_populate_sync_msg(
3043 ahc->msgout_buf + ahc->msgout_index, period, offset);
3044 ahc->msgout_len += 5;
3046 printk("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3047 ahc_name(ahc), devinfo->channel, devinfo->target,
3048 devinfo->lun, period, offset);
3053 * Build a wide negotiation message in our message
3054 * buffer based on the input parameters.
3057 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3060 ahc->msgout_index += spi_populate_width_msg(
3061 ahc->msgout_buf + ahc->msgout_index, bus_width);
3062 ahc->msgout_len += 4;
3064 printk("(%s:%c:%d:%d): Sending WDTR %x\n",
3065 ahc_name(ahc), devinfo->channel, devinfo->target,
3066 devinfo->lun, bus_width);
3071 * Build a parallel protocol request message in our message
3072 * buffer based on the input parameters.
3075 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3076 u_int period, u_int offset, u_int bus_width,
3080 period = AHC_ASYNC_XFER_PERIOD;
3081 ahc->msgout_index += spi_populate_ppr_msg(
3082 ahc->msgout_buf + ahc->msgout_index, period, offset,
3083 bus_width, ppr_options);
3084 ahc->msgout_len += 8;
3086 printk("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3087 "offset %x, ppr_options %x\n", ahc_name(ahc),
3088 devinfo->channel, devinfo->target, devinfo->lun,
3089 bus_width, period, offset, ppr_options);
3094 * Clear any active message state.
3097 ahc_clear_msg_state(struct ahc_softc *ahc)
3099 ahc->msgout_len = 0;
3100 ahc->msgin_index = 0;
3101 ahc->msg_type = MSG_TYPE_NONE;
3102 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
3104 * The target didn't care to respond to our
3105 * message request, so clear ATN.
3107 ahc_outb(ahc, CLRSINT1, CLRATNO);
3109 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
3110 ahc_outb(ahc, SEQ_FLAGS2,
3111 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3115 ahc_handle_proto_violation(struct ahc_softc *ahc)
3117 struct ahc_devinfo devinfo;
3125 ahc_fetch_devinfo(ahc, &devinfo);
3126 scbid = ahc_inb(ahc, SCB_TAG);
3127 scb = ahc_lookup_scb(ahc, scbid);
3128 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
3129 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3130 lastphase = ahc_inb(ahc, LASTPHASE);
3131 if ((seq_flags & NOT_IDENTIFIED) != 0) {
3134 * The reconnecting target either did not send an
3135 * identify message, or did, but we didn't find an SCB
3138 ahc_print_devinfo(ahc, &devinfo);
3139 printk("Target did not send an IDENTIFY message. "
3140 "LASTPHASE = 0x%x.\n", lastphase);
3142 } else if (scb == NULL) {
3144 * We don't seem to have an SCB active for this
3145 * transaction. Print an error and reset the bus.
3147 ahc_print_devinfo(ahc, &devinfo);
3148 printk("No SCB found during protocol violation\n");
3149 goto proto_violation_reset;
3151 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
3152 if ((seq_flags & NO_CDB_SENT) != 0) {
3153 ahc_print_path(ahc, scb);
3154 printk("No or incomplete CDB sent to device.\n");
3155 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
3157 * The target never bothered to provide status to
3158 * us prior to completing the command. Since we don't
3159 * know the disposition of this command, we must attempt
3160 * to abort it. Assert ATN and prepare to send an abort
3163 ahc_print_path(ahc, scb);
3164 printk("Completed command without status.\n");
3166 ahc_print_path(ahc, scb);
3167 printk("Unknown protocol violation.\n");
3168 ahc_dump_card_state(ahc);
3171 if ((lastphase & ~P_DATAIN_DT) == 0
3172 || lastphase == P_COMMAND) {
3173 proto_violation_reset:
3175 * Target either went directly to data/command
3176 * phase or didn't respond to our ATN.
3177 * The only safe thing to do is to blow
3178 * it away with a bus reset.
3180 found = ahc_reset_channel(ahc, 'A', TRUE);
3181 printk("%s: Issued Channel %c Bus Reset. "
3182 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
3185 * Leave the selection hardware off in case
3186 * this abort attempt will affect yet to
3189 ahc_outb(ahc, SCSISEQ,
3190 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
3191 ahc_assert_atn(ahc);
3192 ahc_outb(ahc, MSG_OUT, HOST_MSG);
3194 ahc_print_devinfo(ahc, &devinfo);
3195 ahc->msgout_buf[0] = MSG_ABORT_TASK;
3196 ahc->msgout_len = 1;
3197 ahc->msgout_index = 0;
3198 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3200 ahc_print_path(ahc, scb);
3201 scb->flags |= SCB_ABORT;
3203 printk("Protocol violation %s. Attempting to abort.\n",
3204 ahc_lookup_phase_entry(curphase)->phasemsg);
3209 * Manual message loop handler.
3212 ahc_handle_message_phase(struct ahc_softc *ahc)
3214 struct ahc_devinfo devinfo;
3218 ahc_fetch_devinfo(ahc, &devinfo);
3219 end_session = FALSE;
3220 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3223 switch (ahc->msg_type) {
3224 case MSG_TYPE_INITIATOR_MSGOUT:
3230 if (ahc->msgout_len == 0)
3231 panic("HOST_MSG_LOOP interrupt with no active message");
3234 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3235 ahc_print_devinfo(ahc, &devinfo);
3236 printk("INITIATOR_MSG_OUT");
3239 phasemis = bus_phase != P_MESGOUT;
3242 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3243 printk(" PHASEMIS %s\n",
3244 ahc_lookup_phase_entry(bus_phase)
3248 if (bus_phase == P_MESGIN) {
3250 * Change gears and see if
3251 * this messages is of interest to
3252 * us or should be passed back to
3255 ahc_outb(ahc, CLRSINT1, CLRATNO);
3256 ahc->send_msg_perror = FALSE;
3257 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3258 ahc->msgin_index = 0;
3265 if (ahc->send_msg_perror) {
3266 ahc_outb(ahc, CLRSINT1, CLRATNO);
3267 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3269 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3270 printk(" byte 0x%x\n", ahc->send_msg_perror);
3272 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
3276 msgdone = ahc->msgout_index == ahc->msgout_len;
3279 * The target has requested a retry.
3280 * Re-assert ATN, reset our message index to
3283 ahc->msgout_index = 0;
3284 ahc_assert_atn(ahc);
3287 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
3289 /* Last byte is signified by dropping ATN */
3290 ahc_outb(ahc, CLRSINT1, CLRATNO);
3294 * Clear our interrupt status and present
3295 * the next byte on the bus.
3297 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3299 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3300 printk(" byte 0x%x\n",
3301 ahc->msgout_buf[ahc->msgout_index]);
3303 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3306 case MSG_TYPE_INITIATOR_MSGIN:
3312 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3313 ahc_print_devinfo(ahc, &devinfo);
3314 printk("INITIATOR_MSG_IN");
3317 phasemis = bus_phase != P_MESGIN;
3320 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3321 printk(" PHASEMIS %s\n",
3322 ahc_lookup_phase_entry(bus_phase)
3326 ahc->msgin_index = 0;
3327 if (bus_phase == P_MESGOUT
3328 && (ahc->send_msg_perror == TRUE
3329 || (ahc->msgout_len != 0
3330 && ahc->msgout_index == 0))) {
3331 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3338 /* Pull the byte in without acking it */
3339 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
3341 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3342 printk(" byte 0x%x\n",
3343 ahc->msgin_buf[ahc->msgin_index]);
3346 message_done = ahc_parse_msg(ahc, &devinfo);
3350 * Clear our incoming message buffer in case there
3351 * is another message following this one.
3353 ahc->msgin_index = 0;
3356 * If this message illicited a response,
3357 * assert ATN so the target takes us to the
3358 * message out phase.
3360 if (ahc->msgout_len != 0) {
3362 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3363 ahc_print_devinfo(ahc, &devinfo);
3364 printk("Asserting ATN for response\n");
3367 ahc_assert_atn(ahc);
3372 if (message_done == MSGLOOP_TERMINATED) {
3376 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3377 ahc_inb(ahc, SCSIDATL);
3381 case MSG_TYPE_TARGET_MSGIN:
3386 if (ahc->msgout_len == 0)
3387 panic("Target MSGIN with no active message");
3390 * If we interrupted a mesgout session, the initiator
3391 * will not know this until our first REQ. So, we
3392 * only honor mesgout requests after we've sent our
3395 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
3396 && ahc->msgout_index > 0)
3397 msgout_request = TRUE;
3399 msgout_request = FALSE;
3401 if (msgout_request) {
3404 * Change gears and see if
3405 * this messages is of interest to
3406 * us or should be passed back to
3409 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
3410 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
3411 ahc->msgin_index = 0;
3412 /* Dummy read to REQ for first byte */
3413 ahc_inb(ahc, SCSIDATL);
3414 ahc_outb(ahc, SXFRCTL0,
3415 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3419 msgdone = ahc->msgout_index == ahc->msgout_len;
3421 ahc_outb(ahc, SXFRCTL0,
3422 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3428 * Present the next byte on the bus.
3430 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3431 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3434 case MSG_TYPE_TARGET_MSGOUT:
3440 * The initiator signals that this is
3441 * the last byte by dropping ATN.
3443 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
3446 * Read the latched byte, but turn off SPIOEN first
3447 * so that we don't inadvertently cause a REQ for the
3450 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3451 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
3452 msgdone = ahc_parse_msg(ahc, &devinfo);
3453 if (msgdone == MSGLOOP_TERMINATED) {
3455 * The message is *really* done in that it caused
3456 * us to go to bus free. The sequencer has already
3457 * been reset at this point, so pull the ejection
3466 * XXX Read spec about initiator dropping ATN too soon
3467 * and use msgdone to detect it.
3469 if (msgdone == MSGLOOP_MSGCOMPLETE) {
3470 ahc->msgin_index = 0;
3473 * If this message illicited a response, transition
3474 * to the Message in phase and send it.
3476 if (ahc->msgout_len != 0) {
3477 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
3478 ahc_outb(ahc, SXFRCTL0,
3479 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3480 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3481 ahc->msgin_index = 0;
3489 /* Ask for the next byte. */
3490 ahc_outb(ahc, SXFRCTL0,
3491 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3497 panic("Unknown REQINIT message type");
3501 ahc_clear_msg_state(ahc);
3502 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3504 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3508 * See if we sent a particular extended message to the target.
3509 * If "full" is true, return true only if the target saw the full
3510 * message. If "full" is false, return true if the target saw at
3511 * least the first byte of the message.
3514 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3522 while (index < ahc->msgout_len) {
3523 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3526 end_index = index + 1 + ahc->msgout_buf[index + 1];
3527 if (ahc->msgout_buf[index+2] == msgval
3528 && type == AHCMSG_EXT) {
3531 if (ahc->msgout_index > end_index)
3533 } else if (ahc->msgout_index > index)
3537 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3538 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3540 /* Skip tag type and tag id or residue param*/
3543 /* Single byte message */
3544 if (type == AHCMSG_1B
3545 && ahc->msgout_buf[index] == msgval
3546 && ahc->msgout_index > index)
3558 * Wait for a complete incoming message, parse it, and respond accordingly.
3561 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3563 struct ahc_initiator_tinfo *tinfo;
3564 struct ahc_tmode_tstate *tstate;
3568 u_int targ_scsirate;
3570 done = MSGLOOP_IN_PROG;
3573 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3574 devinfo->target, &tstate);
3575 targ_scsirate = tinfo->scsirate;
3578 * Parse as much of the message as is available,
3579 * rejecting it if we don't support it. When
3580 * the entire message is available and has been
3581 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3582 * that we have parsed an entire message.
3584 * In the case of extended messages, we accept the length
3585 * byte outright and perform more checking once we know the
3586 * extended message type.
3588 switch (ahc->msgin_buf[0]) {
3589 case MSG_DISCONNECT:
3590 case MSG_SAVEDATAPOINTER:
3591 case MSG_CMDCOMPLETE:
3592 case MSG_RESTOREPOINTERS:
3593 case MSG_IGN_WIDE_RESIDUE:
3595 * End our message loop as these are messages
3596 * the sequencer handles on its own.
3598 done = MSGLOOP_TERMINATED;
3600 case MSG_MESSAGE_REJECT:
3601 response = ahc_handle_msg_reject(ahc, devinfo);
3604 done = MSGLOOP_MSGCOMPLETE;
3608 /* Wait for enough of the message to begin validation */
3609 if (ahc->msgin_index < 2)
3611 switch (ahc->msgin_buf[2]) {
3614 const struct ahc_syncrate *syncrate;
3620 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3626 * Wait until we have both args before validating
3627 * and acting on this message.
3629 * Add one to MSG_EXT_SDTR_LEN to account for
3630 * the extended message preamble.
3632 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3635 period = ahc->msgin_buf[3];
3637 saved_offset = offset = ahc->msgin_buf[4];
3638 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3641 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3642 targ_scsirate & WIDEXFER,
3645 printk("(%s:%c:%d:%d): Received "
3646 "SDTR period %x, offset %x\n\t"
3647 "Filtered to period %x, offset %x\n",
3648 ahc_name(ahc), devinfo->channel,
3649 devinfo->target, devinfo->lun,
3650 ahc->msgin_buf[3], saved_offset,
3653 ahc_set_syncrate(ahc, devinfo,
3655 offset, ppr_options,
3656 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3660 * See if we initiated Sync Negotiation
3661 * and didn't have to fall down to async
3664 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3666 if (saved_offset != offset) {
3667 /* Went too low - force async */
3672 * Send our own SDTR in reply
3675 && devinfo->role == ROLE_INITIATOR) {
3676 printk("(%s:%c:%d:%d): Target "
3678 ahc_name(ahc), devinfo->channel,
3679 devinfo->target, devinfo->lun);
3681 ahc->msgout_index = 0;
3682 ahc->msgout_len = 0;
3683 ahc_construct_sdtr(ahc, devinfo,
3685 ahc->msgout_index = 0;
3688 done = MSGLOOP_MSGCOMPLETE;
3695 u_int sending_reply;
3697 sending_reply = FALSE;
3698 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3704 * Wait until we have our arg before validating
3705 * and acting on this message.
3707 * Add one to MSG_EXT_WDTR_LEN to account for
3708 * the extended message preamble.
3710 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3713 bus_width = ahc->msgin_buf[3];
3714 saved_width = bus_width;
3715 ahc_validate_width(ahc, tinfo, &bus_width,
3718 printk("(%s:%c:%d:%d): Received WDTR "
3719 "%x filtered to %x\n",
3720 ahc_name(ahc), devinfo->channel,
3721 devinfo->target, devinfo->lun,
3722 saved_width, bus_width);
3725 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3727 * Don't send a WDTR back to the
3728 * target, since we asked first.
3729 * If the width went higher than our
3730 * request, reject it.
3732 if (saved_width > bus_width) {
3734 printk("(%s:%c:%d:%d): requested %dBit "
3735 "transfers. Rejecting...\n",
3736 ahc_name(ahc), devinfo->channel,
3737 devinfo->target, devinfo->lun,
3738 8 * (0x01 << bus_width));
3743 * Send our own WDTR in reply
3746 && devinfo->role == ROLE_INITIATOR) {
3747 printk("(%s:%c:%d:%d): Target "
3749 ahc_name(ahc), devinfo->channel,
3750 devinfo->target, devinfo->lun);
3752 ahc->msgout_index = 0;
3753 ahc->msgout_len = 0;
3754 ahc_construct_wdtr(ahc, devinfo, bus_width);
3755 ahc->msgout_index = 0;
3757 sending_reply = TRUE;
3760 * After a wide message, we are async, but
3761 * some devices don't seem to honor this portion
3762 * of the spec. Force a renegotiation of the
3763 * sync component of our transfer agreement even
3764 * if our goal is async. By updating our width
3765 * after forcing the negotiation, we avoid
3766 * renegotiating for width.
3768 ahc_update_neg_request(ahc, devinfo, tstate,
3769 tinfo, AHC_NEG_ALWAYS);
3770 ahc_set_width(ahc, devinfo, bus_width,
3771 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3773 if (sending_reply == FALSE && reject == FALSE) {
3776 * We will always have an SDTR to send.
3778 ahc->msgout_index = 0;
3779 ahc->msgout_len = 0;
3780 ahc_build_transfer_msg(ahc, devinfo);
3781 ahc->msgout_index = 0;
3784 done = MSGLOOP_MSGCOMPLETE;
3789 const struct ahc_syncrate *syncrate;
3796 u_int saved_ppr_options;
3798 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3804 * Wait until we have all args before validating
3805 * and acting on this message.
3807 * Add one to MSG_EXT_PPR_LEN to account for
3808 * the extended message preamble.
3810 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3813 period = ahc->msgin_buf[3];
3814 offset = ahc->msgin_buf[5];
3815 bus_width = ahc->msgin_buf[6];
3816 saved_width = bus_width;
3817 ppr_options = ahc->msgin_buf[7];
3819 * According to the spec, a DT only
3820 * period factor with no DT option
3821 * set implies async.
3823 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3826 saved_ppr_options = ppr_options;
3827 saved_offset = offset;
3830 * Mask out any options we don't support
3831 * on any controller. Transfer options are
3832 * only available if we are negotiating wide.
3834 ppr_options &= MSG_EXT_PPR_DT_REQ;
3838 ahc_validate_width(ahc, tinfo, &bus_width,
3840 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3843 ahc_validate_offset(ahc, tinfo, syncrate,
3847 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3849 * If we are unable to do any of the
3850 * requested options (we went too low),
3851 * then we'll have to reject the message.
3853 if (saved_width > bus_width
3854 || saved_offset != offset
3855 || saved_ppr_options != ppr_options) {
3864 if (devinfo->role != ROLE_TARGET)
3865 printk("(%s:%c:%d:%d): Target "
3867 ahc_name(ahc), devinfo->channel,
3868 devinfo->target, devinfo->lun);
3870 printk("(%s:%c:%d:%d): Initiator "
3872 ahc_name(ahc), devinfo->channel,
3873 devinfo->target, devinfo->lun);
3874 ahc->msgout_index = 0;
3875 ahc->msgout_len = 0;
3876 ahc_construct_ppr(ahc, devinfo, period, offset,
3877 bus_width, ppr_options);
3878 ahc->msgout_index = 0;
3882 printk("(%s:%c:%d:%d): Received PPR width %x, "
3883 "period %x, offset %x,options %x\n"
3884 "\tFiltered to width %x, period %x, "
3885 "offset %x, options %x\n",
3886 ahc_name(ahc), devinfo->channel,
3887 devinfo->target, devinfo->lun,
3888 saved_width, ahc->msgin_buf[3],
3889 saved_offset, saved_ppr_options,
3890 bus_width, period, offset, ppr_options);
3892 ahc_set_width(ahc, devinfo, bus_width,
3893 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3895 ahc_set_syncrate(ahc, devinfo,
3897 offset, ppr_options,
3898 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3900 done = MSGLOOP_MSGCOMPLETE;
3904 /* Unknown extended message. Reject it. */
3910 #ifdef AHC_TARGET_MODE
3911 case MSG_BUS_DEV_RESET:
3912 ahc_handle_devreset(ahc, devinfo,
3914 "Bus Device Reset Received",
3915 /*verbose_level*/0);
3917 done = MSGLOOP_TERMINATED;
3921 case MSG_CLEAR_QUEUE:
3925 /* Target mode messages */
3926 if (devinfo->role != ROLE_TARGET) {
3930 tag = SCB_LIST_NULL;
3931 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3932 tag = ahc_inb(ahc, INITIATOR_TAG);
3933 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3934 devinfo->lun, tag, ROLE_TARGET,
3937 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3938 if (tstate != NULL) {
3939 struct ahc_tmode_lstate* lstate;
3941 lstate = tstate->enabled_luns[devinfo->lun];
3942 if (lstate != NULL) {
3943 ahc_queue_lstate_event(ahc, lstate,
3944 devinfo->our_scsiid,
3947 ahc_send_lstate_events(ahc, lstate);
3951 done = MSGLOOP_TERMINATED;
3955 case MSG_TERM_IO_PROC:
3963 * Setup to reject the message.
3965 ahc->msgout_index = 0;
3966 ahc->msgout_len = 1;
3967 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3968 done = MSGLOOP_MSGCOMPLETE;
3972 if (done != MSGLOOP_IN_PROG && !response)
3973 /* Clear the outgoing message buffer */
3974 ahc->msgout_len = 0;
3980 * Process a message reject message.
3983 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3986 * What we care about here is if we had an
3987 * outstanding SDTR or WDTR message for this
3988 * target. If we did, this is a signal that
3989 * the target is refusing negotiation.
3992 struct ahc_initiator_tinfo *tinfo;
3993 struct ahc_tmode_tstate *tstate;
3998 scb_index = ahc_inb(ahc, SCB_TAG);
3999 scb = ahc_lookup_scb(ahc, scb_index);
4000 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
4001 devinfo->our_scsiid,
4002 devinfo->target, &tstate);
4003 /* Might be necessary */
4004 last_msg = ahc_inb(ahc, LAST_MSG);
4006 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4008 * Target does not support the PPR message.
4009 * Attempt to negotiate SPI-2 style.
4012 printk("(%s:%c:%d:%d): PPR Rejected. "
4013 "Trying WDTR/SDTR\n",
4014 ahc_name(ahc), devinfo->channel,
4015 devinfo->target, devinfo->lun);
4017 tinfo->goal.ppr_options = 0;
4018 tinfo->curr.transport_version = 2;
4019 tinfo->goal.transport_version = 2;
4020 ahc->msgout_index = 0;
4021 ahc->msgout_len = 0;
4022 ahc_build_transfer_msg(ahc, devinfo);
4023 ahc->msgout_index = 0;
4025 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4027 /* note 8bit xfers */
4028 printk("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4029 "8bit transfers\n", ahc_name(ahc),
4030 devinfo->channel, devinfo->target, devinfo->lun);
4031 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4032 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4035 * No need to clear the sync rate. If the target
4036 * did not accept the command, our syncrate is
4037 * unaffected. If the target started the negotiation,
4038 * but rejected our response, we already cleared the
4039 * sync rate before sending our WDTR.
4041 if (tinfo->goal.offset != tinfo->curr.offset) {
4043 /* Start the sync negotiation */
4044 ahc->msgout_index = 0;
4045 ahc->msgout_len = 0;
4046 ahc_build_transfer_msg(ahc, devinfo);
4047 ahc->msgout_index = 0;
4050 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4051 /* note asynch xfers and clear flag */
4052 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
4053 /*offset*/0, /*ppr_options*/0,
4054 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4056 printk("(%s:%c:%d:%d): refuses synchronous negotiation. "
4057 "Using asynchronous transfers\n",
4058 ahc_name(ahc), devinfo->channel,
4059 devinfo->target, devinfo->lun);
4060 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4064 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4066 if (tag_type == MSG_SIMPLE_TASK) {
4067 printk("(%s:%c:%d:%d): refuses tagged commands. "
4068 "Performing non-tagged I/O\n", ahc_name(ahc),
4069 devinfo->channel, devinfo->target, devinfo->lun);
4070 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
4073 printk("(%s:%c:%d:%d): refuses %s tagged commands. "
4074 "Performing simple queue tagged I/O only\n",
4075 ahc_name(ahc), devinfo->channel, devinfo->target,
4076 devinfo->lun, tag_type == MSG_ORDERED_TASK
4077 ? "ordered" : "head of queue");
4078 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
4083 * Resend the identify for this CCB as the target
4084 * may believe that the selection is invalid otherwise.
4086 ahc_outb(ahc, SCB_CONTROL,
4087 ahc_inb(ahc, SCB_CONTROL) & mask);
4088 scb->hscb->control &= mask;
4089 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
4090 /*type*/MSG_SIMPLE_TASK);
4091 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
4092 ahc_assert_atn(ahc);
4095 * This transaction is now at the head of
4096 * the untagged queue for this target.
4098 if ((ahc->flags & AHC_SCB_BTT) == 0) {
4099 struct scb_tailq *untagged_q;
4102 &(ahc->untagged_queues[devinfo->target_offset]);
4103 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
4104 scb->flags |= SCB_UNTAGGEDQ;
4106 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4110 * Requeue all tagged commands for this target
4111 * currently in our possession so they can be
4112 * converted to untagged commands.
4114 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
4115 SCB_GET_CHANNEL(ahc, scb),
4116 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4117 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4121 * Otherwise, we ignore it.
4123 printk("%s:%c:%d: Message reject for %x -- ignored\n",
4124 ahc_name(ahc), devinfo->channel, devinfo->target,
4131 * Process an ingnore wide residue message.
4134 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
4139 scb_index = ahc_inb(ahc, SCB_TAG);
4140 scb = ahc_lookup_scb(ahc, scb_index);
4142 * XXX Actually check data direction in the sequencer?
4143 * Perhaps add datadir to some spare bits in the hscb?
4145 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
4146 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
4148 * Ignore the message if we haven't
4149 * seen an appropriate data phase yet.
4153 * If the residual occurred on the last
4154 * transfer and the transfer request was
4155 * expected to end on an odd count, do
4156 * nothing. Otherwise, subtract a byte
4157 * and update the residual count accordingly.
4161 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4162 if ((sgptr & SG_LIST_NULL) != 0
4163 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
4165 * If the residual occurred on the last
4166 * transfer and the transfer request was
4167 * expected to end on an odd count, do
4171 struct ahc_dma_seg *sg;
4176 /* Pull in all of the sgptr */
4177 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
4178 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
4180 if ((sgptr & SG_LIST_NULL) != 0) {
4182 * The residual data count is not updated
4183 * for the command run to completion case.
4184 * Explicitly zero the count.
4186 data_cnt &= ~AHC_SG_LEN_MASK;
4189 data_addr = ahc_inl(ahc, SHADDR);
4193 sgptr &= SG_PTR_MASK;
4195 sg = ahc_sg_bus_to_virt(scb, sgptr);
4198 * The residual sg ptr points to the next S/G
4199 * to load so we must go back one.
4202 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
4203 if (sg != scb->sg_list
4204 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
4207 sglen = ahc_le32toh(sg->len);
4209 * Preserve High Address and SG_LIST bits
4210 * while setting the count to 1.
4212 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
4213 data_addr = ahc_le32toh(sg->addr)
4214 + (sglen & AHC_SG_LEN_MASK) - 1;
4217 * Increment sg so it points to the
4221 sgptr = ahc_sg_virt_to_bus(scb, sg);
4223 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
4224 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
4226 * Toggle the "oddness" of the transfer length
4227 * to handle this mid-transfer ignore wide
4228 * residue. This ensures that the oddness is
4229 * correct for subsequent data transfers.
4231 ahc_outb(ahc, SCB_LUN,
4232 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
4239 * Reinitialize the data pointers for the active transfer
4240 * based on its current residual.
4243 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
4246 struct ahc_dma_seg *sg;
4252 scb_index = ahc_inb(ahc, SCB_TAG);
4253 scb = ahc_lookup_scb(ahc, scb_index);
4254 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
4255 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
4256 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
4257 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4259 sgptr &= SG_PTR_MASK;
4260 sg = ahc_sg_bus_to_virt(scb, sgptr);
4262 /* The residual sg_ptr always points to the next sg */
4265 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
4266 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
4267 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
4269 dataptr = ahc_le32toh(sg->addr)
4270 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
4272 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
4275 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
4276 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
4277 ahc_outb(ahc, HADDR,
4278 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
4279 ahc_outb(ahc, DSCOMMAND1, dscommand1);
4281 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
4282 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
4283 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
4284 ahc_outb(ahc, HADDR, dataptr);
4285 ahc_outb(ahc, HCNT + 2, resid >> 16);
4286 ahc_outb(ahc, HCNT + 1, resid >> 8);
4287 ahc_outb(ahc, HCNT, resid);
4288 if ((ahc->features & AHC_ULTRA2) == 0) {
4289 ahc_outb(ahc, STCNT + 2, resid >> 16);
4290 ahc_outb(ahc, STCNT + 1, resid >> 8);
4291 ahc_outb(ahc, STCNT, resid);
4296 * Handle the effects of issuing a bus device reset message.
4299 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4300 cam_status status, char *message, int verbose_level)
4302 #ifdef AHC_TARGET_MODE
4303 struct ahc_tmode_tstate* tstate;
4308 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
4309 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
4312 #ifdef AHC_TARGET_MODE
4314 * Send an immediate notify ccb to all target mord peripheral
4315 * drivers affected by this action.
4317 tstate = ahc->enabled_targets[devinfo->our_scsiid];
4318 if (tstate != NULL) {
4319 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
4320 struct ahc_tmode_lstate* lstate;
4322 lstate = tstate->enabled_luns[lun];
4326 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
4327 MSG_BUS_DEV_RESET, /*arg*/0);
4328 ahc_send_lstate_events(ahc, lstate);
4334 * Go back to async/narrow transfers and renegotiate.
4336 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4337 AHC_TRANS_CUR, /*paused*/TRUE);
4338 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
4339 /*period*/0, /*offset*/0, /*ppr_options*/0,
4340 AHC_TRANS_CUR, /*paused*/TRUE);
4342 if (status != CAM_SEL_TIMEOUT)
4343 ahc_send_async(ahc, devinfo->channel, devinfo->target,
4344 CAM_LUN_WILDCARD, AC_SENT_BDR);
4347 && (verbose_level <= bootverbose))
4348 printk("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
4349 message, devinfo->channel, devinfo->target, found);
4352 #ifdef AHC_TARGET_MODE
4354 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4359 * To facilitate adding multiple messages together,
4360 * each routine should increment the index and len
4361 * variables instead of setting them explicitly.
4363 ahc->msgout_index = 0;
4364 ahc->msgout_len = 0;
4366 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
4367 ahc_build_transfer_msg(ahc, devinfo);
4369 panic("ahc_intr: AWAITING target message with no message");
4371 ahc->msgout_index = 0;
4372 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
4375 /**************************** Initialization **********************************/
4377 * Allocate a controller structure for a new device
4378 * and perform initial initializion.
4381 ahc_alloc(void *platform_arg, char *name)
4383 struct ahc_softc *ahc;
4386 ahc = kzalloc(sizeof(*ahc), GFP_ATOMIC);
4388 printk("aic7xxx: cannot malloc softc!\n");
4393 ahc->seep_config = kmalloc(sizeof(*ahc->seep_config), GFP_ATOMIC);
4394 if (ahc->seep_config == NULL) {
4399 LIST_INIT(&ahc->pending_scbs);
4400 /* We don't know our unit number until the OSM sets it */
4403 ahc->description = NULL;
4405 ahc->channel_b = 'B';
4406 ahc->chip = AHC_NONE;
4407 ahc->features = AHC_FENONE;
4408 ahc->bugs = AHC_BUGNONE;
4409 ahc->flags = AHC_FNONE;
4411 * Default to all error reporting enabled with the
4412 * sequencer operating at its fastest speed.
4413 * The bus attach code may modify this.
4415 ahc->seqctl = FASTMODE;
4417 for (i = 0; i < AHC_NUM_TARGETS; i++)
4418 TAILQ_INIT(&ahc->untagged_queues[i]);
4419 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
4427 ahc_softc_init(struct ahc_softc *ahc)
4430 /* The IRQMS bit is only valid on VL and EISA chips */
4431 if ((ahc->chip & AHC_PCI) == 0)
4432 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
4435 ahc->pause = ahc->unpause | PAUSE;
4436 /* XXX The shared scb data stuff should be deprecated */
4437 if (ahc->scb_data == NULL) {
4438 ahc->scb_data = kzalloc(sizeof(*ahc->scb_data), GFP_ATOMIC);
4439 if (ahc->scb_data == NULL)
4447 ahc_set_unit(struct ahc_softc *ahc, int unit)
4453 ahc_set_name(struct ahc_softc *ahc, char *name)
4460 ahc_free(struct ahc_softc *ahc)
4464 switch (ahc->init_level) {
4470 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
4471 ahc->shared_data_dmamap);
4474 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4475 ahc->shared_data_dmamap);
4476 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
4477 ahc->shared_data_dmamap);
4480 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4487 ahc_platform_free(ahc);
4488 ahc_fini_scbdata(ahc);
4489 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4490 struct ahc_tmode_tstate *tstate;
4492 tstate = ahc->enabled_targets[i];
4493 if (tstate != NULL) {
4494 #ifdef AHC_TARGET_MODE
4497 for (j = 0; j < AHC_NUM_LUNS; j++) {
4498 struct ahc_tmode_lstate *lstate;
4500 lstate = tstate->enabled_luns[j];
4501 if (lstate != NULL) {
4502 xpt_free_path(lstate->path);
4510 #ifdef AHC_TARGET_MODE
4511 if (ahc->black_hole != NULL) {
4512 xpt_free_path(ahc->black_hole->path);
4513 kfree(ahc->black_hole);
4517 kfree(ahc->seep_config);
4523 ahc_shutdown(void *arg)
4525 struct ahc_softc *ahc;
4528 ahc = (struct ahc_softc *)arg;
4530 /* This will reset most registers to 0, but not all */
4531 ahc_reset(ahc, /*reinit*/FALSE);
4532 ahc_outb(ahc, SCSISEQ, 0);
4533 ahc_outb(ahc, SXFRCTL0, 0);
4534 ahc_outb(ahc, DSPCISTATUS, 0);
4536 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4537 ahc_outb(ahc, i, 0);
4541 * Reset the controller and record some information about it
4542 * that is only available just after a reset. If "reinit" is
4543 * non-zero, this reset occurred after initial configuration
4544 * and the caller requests that the chip be fully reinitialized
4545 * to a runable state. Chip interrupts are *not* enabled after
4546 * a reinitialization. The caller must enable interrupts via
4547 * ahc_intr_enable().
4550 ahc_reset(struct ahc_softc *ahc, int reinit)
4553 u_int sxfrctl1_a, sxfrctl1_b;
4558 * Preserve the value of the SXFRCTL1 register for all channels.
4559 * It contains settings that affect termination and we don't want
4560 * to disturb the integrity of the bus.
4564 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4568 * Save channel B's settings in case this chip
4569 * is setup for TWIN channel operation.
4571 sblkctl = ahc_inb(ahc, SBLKCTL);
4572 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4573 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4574 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4576 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4578 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4581 * Ensure that the reset has finished. We delay 1000us
4582 * prior to reading the register to make sure the chip
4583 * has sufficiently completed its reset to handle register
4589 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4592 printk("%s: WARNING - Failed chip reset! "
4593 "Trying to initialize anyway.\n", ahc_name(ahc));
4595 ahc_outb(ahc, HCNTRL, ahc->pause);
4597 /* Determine channel configuration */
4598 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4599 /* No Twin Channel PCI cards */
4600 if ((ahc->chip & AHC_PCI) != 0)
4601 sblkctl &= ~SELBUSB;
4604 /* Single Narrow Channel */
4608 ahc->features |= AHC_WIDE;
4612 ahc->features |= AHC_TWIN;
4615 printk(" Unsupported adapter type. Ignoring\n");
4622 * We must always initialize STPWEN to 1 before we
4623 * restore the saved values. STPWEN is initialized
4624 * to a tri-state condition which can only be cleared
4627 if ((ahc->features & AHC_TWIN) != 0) {
4630 sblkctl = ahc_inb(ahc, SBLKCTL);
4631 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4632 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4633 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4635 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4640 * If a recovery action has forced a chip reset,
4641 * re-initialize the chip to our liking.
4643 error = ahc->bus_chip_init(ahc);
4653 * Determine the number of SCBs available on the controller
4656 ahc_probe_scbs(struct ahc_softc *ahc) {
4659 for (i = 0; i < AHC_SCB_MAX; i++) {
4661 ahc_outb(ahc, SCBPTR, i);
4662 ahc_outb(ahc, SCB_BASE, i);
4663 if (ahc_inb(ahc, SCB_BASE) != i)
4665 ahc_outb(ahc, SCBPTR, 0);
4666 if (ahc_inb(ahc, SCB_BASE) != 0)
4673 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4677 baddr = (dma_addr_t *)arg;
4678 *baddr = segs->ds_addr;
4682 ahc_build_free_scb_list(struct ahc_softc *ahc)
4688 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4691 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4694 ahc_outb(ahc, SCBPTR, i);
4697 * Touch all SCB bytes to avoid parity errors
4698 * should one of our debugging routines read
4699 * an otherwise uninitiatlized byte.
4701 for (j = 0; j < scbsize; j++)
4702 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4704 /* Clear the control byte. */
4705 ahc_outb(ahc, SCB_CONTROL, 0);
4707 /* Set the next pointer */
4708 if ((ahc->flags & AHC_PAGESCBS) != 0)
4709 ahc_outb(ahc, SCB_NEXT, i+1);
4711 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4713 /* Make the tag number, SCSIID, and lun invalid */
4714 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4715 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4716 ahc_outb(ahc, SCB_LUN, 0xFF);
4719 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4720 /* SCB 0 heads the free list. */
4721 ahc_outb(ahc, FREE_SCBH, 0);
4724 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4727 /* Make sure that the last SCB terminates the free list */
4728 ahc_outb(ahc, SCBPTR, i-1);
4729 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4733 ahc_init_scbdata(struct ahc_softc *ahc)
4735 struct scb_data *scb_data;
4737 scb_data = ahc->scb_data;
4738 SLIST_INIT(&scb_data->free_scbs);
4739 SLIST_INIT(&scb_data->sg_maps);
4741 /* Allocate SCB resources */
4742 scb_data->scbarray = kcalloc(AHC_SCB_MAX_ALLOC, sizeof(struct scb),
4744 if (scb_data->scbarray == NULL)
4747 /* Determine the number of hardware SCBs and initialize them */
4749 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4750 if (ahc->scb_data->maxhscbs == 0) {
4751 printk("%s: No SCB space found\n", ahc_name(ahc));
4756 * Create our DMA tags. These tags define the kinds of device
4757 * accessible memory allocations and memory mappings we will
4758 * need to perform during normal operation.
4760 * Unless we need to further restrict the allocation, we rely
4761 * on the restrictions of the parent dmat, hence the common
4762 * use of MAXADDR and MAXSIZE.
4765 /* DMA tag for our hardware scb structures */
4766 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4767 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4768 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4769 /*highaddr*/BUS_SPACE_MAXADDR,
4770 /*filter*/NULL, /*filterarg*/NULL,
4771 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4773 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4774 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4778 scb_data->init_level++;
4780 /* Allocation for our hscbs */
4781 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4782 (void **)&scb_data->hscbs,
4783 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4787 scb_data->init_level++;
4789 /* And permanently map them */
4790 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4792 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4793 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4795 scb_data->init_level++;
4797 /* DMA tag for our sense buffers */
4798 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4799 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4800 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4801 /*highaddr*/BUS_SPACE_MAXADDR,
4802 /*filter*/NULL, /*filterarg*/NULL,
4803 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4805 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4806 /*flags*/0, &scb_data->sense_dmat) != 0) {
4810 scb_data->init_level++;
4813 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4814 (void **)&scb_data->sense,
4815 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4819 scb_data->init_level++;
4821 /* And permanently map them */
4822 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4824 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4825 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4827 scb_data->init_level++;
4829 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4830 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4831 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4832 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4833 /*highaddr*/BUS_SPACE_MAXADDR,
4834 /*filter*/NULL, /*filterarg*/NULL,
4835 PAGE_SIZE, /*nsegments*/1,
4836 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4837 /*flags*/0, &scb_data->sg_dmat) != 0) {
4841 scb_data->init_level++;
4843 /* Perform initial CCB allocation */
4844 memset(scb_data->hscbs, 0,
4845 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4846 ahc_alloc_scbs(ahc);
4848 if (scb_data->numscbs == 0) {
4849 printk("%s: ahc_init_scbdata - "
4850 "Unable to allocate initial scbs\n",
4856 * Reserve the next queued SCB.
4858 ahc->next_queued_scb = ahc_get_scb(ahc);
4861 * Note that we were successful
4871 ahc_fini_scbdata(struct ahc_softc *ahc)
4873 struct scb_data *scb_data;
4875 scb_data = ahc->scb_data;
4876 if (scb_data == NULL)
4879 switch (scb_data->init_level) {
4883 struct sg_map_node *sg_map;
4885 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4886 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4887 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4889 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4894 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4898 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4899 scb_data->sense_dmamap);
4902 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4903 scb_data->sense_dmamap);
4904 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4905 scb_data->sense_dmamap);
4908 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4911 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4912 scb_data->hscb_dmamap);
4915 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4916 scb_data->hscb_dmamap);
4917 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4918 scb_data->hscb_dmamap);
4921 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4926 kfree(scb_data->scbarray);
4930 ahc_alloc_scbs(struct ahc_softc *ahc)
4932 struct scb_data *scb_data;
4933 struct scb *next_scb;
4934 struct sg_map_node *sg_map;
4935 dma_addr_t physaddr;
4936 struct ahc_dma_seg *segs;
4940 scb_data = ahc->scb_data;
4941 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4942 /* Can't allocate any more */
4945 next_scb = &scb_data->scbarray[scb_data->numscbs];
4947 sg_map = kmalloc(sizeof(*sg_map), GFP_ATOMIC);
4952 /* Allocate S/G space for the next batch of SCBS */
4953 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4954 (void **)&sg_map->sg_vaddr,
4955 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4960 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4962 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4963 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4964 &sg_map->sg_physaddr, /*flags*/0);
4966 segs = sg_map->sg_vaddr;
4967 physaddr = sg_map->sg_physaddr;
4969 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4970 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4971 for (i = 0; i < newcount; i++) {
4972 struct scb_platform_data *pdata;
4974 pdata = kmalloc(sizeof(*pdata), GFP_ATOMIC);
4977 next_scb->platform_data = pdata;
4978 next_scb->sg_map = sg_map;
4979 next_scb->sg_list = segs;
4981 * The sequencer always starts with the second entry.
4982 * The first entry is embedded in the scb.
4984 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4985 next_scb->ahc_softc = ahc;
4986 next_scb->flags = SCB_FREE;
4987 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4988 next_scb->hscb->tag = ahc->scb_data->numscbs;
4989 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4990 next_scb, links.sle);
4992 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4994 ahc->scb_data->numscbs++;
4999 ahc_controller_info(struct ahc_softc *ahc, char *buf)
5003 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
5005 if ((ahc->features & AHC_TWIN) != 0)
5006 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
5007 "B SCSI Id=%d, primary %c, ",
5008 ahc->our_id, ahc->our_id_b,
5009 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
5015 if ((ahc->features & AHC_ULTRA) != 0) {
5017 } else if ((ahc->features & AHC_DT) != 0) {
5018 speed = "Ultra160 ";
5019 } else if ((ahc->features & AHC_ULTRA2) != 0) {
5022 if ((ahc->features & AHC_WIDE) != 0) {
5027 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
5028 speed, type, ahc->channel, ahc->our_id);
5032 if ((ahc->flags & AHC_PAGESCBS) != 0)
5033 sprintf(buf, "%d/%d SCBs",
5034 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
5036 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
5040 ahc_chip_init(struct ahc_softc *ahc)
5046 u_int scsiseq_template;
5049 ahc_outb(ahc, SEQ_FLAGS, 0);
5050 ahc_outb(ahc, SEQ_FLAGS2, 0);
5052 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
5053 if (ahc->features & AHC_TWIN) {
5056 * Setup Channel B first.
5058 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
5059 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
5060 ahc_outb(ahc, SCSIID, ahc->our_id_b);
5061 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5062 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5063 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
5064 if ((ahc->features & AHC_ULTRA2) != 0)
5065 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5066 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5067 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5069 /* Select Channel A */
5070 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
5072 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
5073 if ((ahc->features & AHC_ULTRA2) != 0)
5074 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
5076 ahc_outb(ahc, SCSIID, ahc->our_id);
5077 scsi_conf = ahc_inb(ahc, SCSICONF);
5078 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5080 |ENSTIMER|ACTNEGEN);
5081 if ((ahc->features & AHC_ULTRA2) != 0)
5082 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5083 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5084 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5086 /* There are no untagged SCBs active yet. */
5087 for (i = 0; i < 16; i++) {
5088 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
5089 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5093 * The SCB based BTT allows an entry per
5094 * target and lun pair.
5096 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
5097 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
5101 /* All of our queues are empty */
5102 for (i = 0; i < 256; i++)
5103 ahc->qoutfifo[i] = SCB_LIST_NULL;
5104 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
5106 for (i = 0; i < 256; i++)
5107 ahc->qinfifo[i] = SCB_LIST_NULL;
5109 if ((ahc->features & AHC_MULTI_TID) != 0) {
5110 ahc_outb(ahc, TARGID, 0);
5111 ahc_outb(ahc, TARGID + 1, 0);
5115 * Tell the sequencer where it can find our arrays in memory.
5117 physaddr = ahc->scb_data->hscb_busaddr;
5118 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
5119 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
5120 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
5121 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
5123 physaddr = ahc->shared_data_busaddr;
5124 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
5125 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
5126 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
5127 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
5130 * Initialize the group code to command length table.
5131 * This overrides the values in TARG_SCSIRATE, so only
5132 * setup the table after we have processed that information.
5134 ahc_outb(ahc, CMDSIZE_TABLE, 5);
5135 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
5136 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
5137 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
5138 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
5139 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
5140 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
5141 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
5143 if ((ahc->features & AHC_HS_MAILBOX) != 0)
5144 ahc_outb(ahc, HS_MAILBOX, 0);
5146 /* Tell the sequencer of our initial queue positions */
5147 if ((ahc->features & AHC_TARGETMODE) != 0) {
5148 ahc->tqinfifonext = 1;
5149 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
5150 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
5152 ahc->qinfifonext = 0;
5153 ahc->qoutfifonext = 0;
5154 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5155 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
5156 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5157 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
5158 ahc_outb(ahc, SDSCB_QOFF, 0);
5160 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5161 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
5162 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
5165 /* We don't have any waiting selections */
5166 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
5168 /* Our disconnection list is empty too */
5169 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
5171 /* Message out buffer starts empty */
5172 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
5175 * Setup the allowed SCSI Sequences based on operational mode.
5176 * If we are a target, we'll enable select in operations once
5177 * we've had a lun enabled.
5179 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
5180 if ((ahc->flags & AHC_INITIATORROLE) != 0)
5181 scsiseq_template |= ENRSELI;
5182 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
5184 /* Initialize our list of free SCBs. */
5185 ahc_build_free_scb_list(ahc);
5188 * Tell the sequencer which SCB will be the next one it receives.
5190 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5193 * Load the Sequencer program and Enable the adapter
5197 printk("%s: Downloading Sequencer Program...",
5200 error = ahc_loadseq(ahc);
5204 if ((ahc->features & AHC_ULTRA2) != 0) {
5208 * Wait for up to 500ms for our transceivers
5209 * to settle. If the adapter does not have
5210 * a cable attached, the transceivers may
5211 * never settle, so don't complain if we
5215 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
5224 * Start the board, ready for normal operation
5227 ahc_init(struct ahc_softc *ahc)
5235 size_t driver_data_size;
5238 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
5239 ahc->flags |= AHC_SEQUENCER_DEBUG;
5242 #ifdef AHC_PRINT_SRAM
5243 printk("Scratch Ram:");
5244 for (i = 0x20; i < 0x5f; i++) {
5245 if (((i % 8) == 0) && (i != 0)) {
5248 printk (" 0x%x", ahc_inb(ahc, i));
5250 if ((ahc->features & AHC_MORE_SRAM) != 0) {
5251 for (i = 0x70; i < 0x7f; i++) {
5252 if (((i % 8) == 0) && (i != 0)) {
5255 printk (" 0x%x", ahc_inb(ahc, i));
5260 * Reading uninitialized scratch ram may
5261 * generate parity errors.
5263 ahc_outb(ahc, CLRINT, CLRPARERR);
5264 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
5269 * Assume we have a board at this stage and it has been reset.
5271 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
5272 ahc->our_id = ahc->our_id_b = 7;
5275 * Default to allowing initiator operations.
5277 ahc->flags |= AHC_INITIATORROLE;
5280 * Only allow target mode features if this unit has them enabled.
5282 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
5283 ahc->features &= ~AHC_TARGETMODE;
5288 * DMA tag for our command fifos and other data in system memory
5289 * the card's sequencer must be able to access. For initiator
5290 * roles, we need to allocate space for the qinfifo and qoutfifo.
5291 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
5292 * When providing for the target mode role, we must additionally
5293 * provide space for the incoming target command fifo and an extra
5294 * byte to deal with a dma bug in some chip versions.
5296 driver_data_size = 2 * 256 * sizeof(uint8_t);
5297 if ((ahc->features & AHC_TARGETMODE) != 0)
5298 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
5299 + /*DMA WideOdd Bug Buffer*/1;
5300 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
5301 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5302 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5303 /*highaddr*/BUS_SPACE_MAXADDR,
5304 /*filter*/NULL, /*filterarg*/NULL,
5307 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5308 /*flags*/0, &ahc->shared_data_dmat) != 0) {
5314 /* Allocation of driver data */
5315 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
5316 (void **)&ahc->qoutfifo,
5317 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
5323 /* And permanently map it in */
5324 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
5325 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
5326 &ahc->shared_data_busaddr, /*flags*/0);
5328 if ((ahc->features & AHC_TARGETMODE) != 0) {
5329 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
5330 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
5331 ahc->dma_bug_buf = ahc->shared_data_busaddr
5332 + driver_data_size - 1;
5333 /* All target command blocks start out invalid. */
5334 for (i = 0; i < AHC_TMODE_CMDS; i++)
5335 ahc->targetcmds[i].cmd_valid = 0;
5336 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
5337 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
5339 ahc->qinfifo = &ahc->qoutfifo[256];
5343 /* Allocate SCB data now that buffer_dmat is initialized */
5344 if (ahc->scb_data->maxhscbs == 0)
5345 if (ahc_init_scbdata(ahc) != 0)
5349 * Allocate a tstate to house information for our
5350 * initiator presence on the bus as well as the user
5351 * data for any target mode initiator.
5353 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
5354 printk("%s: unable to allocate ahc_tmode_tstate. "
5355 "Failing attach\n", ahc_name(ahc));
5359 if ((ahc->features & AHC_TWIN) != 0) {
5360 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
5361 printk("%s: unable to allocate ahc_tmode_tstate. "
5362 "Failing attach\n", ahc_name(ahc));
5367 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
5368 ahc->flags |= AHC_PAGESCBS;
5370 ahc->flags &= ~AHC_PAGESCBS;
5374 if (ahc_debug & AHC_SHOW_MISC) {
5375 printk("%s: hardware scb %u bytes; kernel scb %u bytes; "
5376 "ahc_dma %u bytes\n",
5378 (u_int)sizeof(struct hardware_scb),
5379 (u_int)sizeof(struct scb),
5380 (u_int)sizeof(struct ahc_dma_seg));
5382 #endif /* AHC_DEBUG */
5385 * Look at the information that board initialization or
5386 * the board bios has left us.
5388 if (ahc->features & AHC_TWIN) {
5389 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5390 if ((scsi_conf & RESET_SCSI) != 0
5391 && (ahc->flags & AHC_INITIATORROLE) != 0)
5392 ahc->flags |= AHC_RESET_BUS_B;
5395 scsi_conf = ahc_inb(ahc, SCSICONF);
5396 if ((scsi_conf & RESET_SCSI) != 0
5397 && (ahc->flags & AHC_INITIATORROLE) != 0)
5398 ahc->flags |= AHC_RESET_BUS_A;
5401 tagenable = ALL_TARGETS_MASK;
5403 /* Grab the disconnection disable table and invert it for our needs */
5404 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5405 printk("%s: Host Adapter Bios disabled. Using default SCSI "
5406 "device parameters\n", ahc_name(ahc));
5407 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5408 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5409 discenable = ALL_TARGETS_MASK;
5410 if ((ahc->features & AHC_ULTRA) != 0)
5411 ultraenb = ALL_TARGETS_MASK;
5413 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5414 | ahc_inb(ahc, DISC_DSB));
5415 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5416 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5417 | ahc_inb(ahc, ULTRA_ENB);
5420 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5423 for (i = 0; i <= max_targ; i++) {
5424 struct ahc_initiator_tinfo *tinfo;
5425 struct ahc_tmode_tstate *tstate;
5431 our_id = ahc->our_id;
5433 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5435 our_id = ahc->our_id_b;
5438 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5439 target_id, &tstate);
5440 /* Default to async narrow across the board */
5441 memset(tinfo, 0, sizeof(*tinfo));
5442 if (ahc->flags & AHC_USEDEFAULTS) {
5443 if ((ahc->features & AHC_WIDE) != 0)
5444 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5447 * These will be truncated when we determine the
5448 * connection type we have with the target.
5450 tinfo->user.period = ahc_syncrates->period;
5451 tinfo->user.offset = MAX_OFFSET;
5456 /* Take the settings leftover in scratch RAM. */
5457 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5459 if ((ahc->features & AHC_ULTRA2) != 0) {
5463 if ((scsirate & SOFS) == 0x0F) {
5465 * Haven't negotiated yet,
5466 * so the format is different.
5468 scsirate = (scsirate & SXFR) >> 4
5471 | (scsirate & WIDEXFER);
5472 offset = MAX_OFFSET_ULTRA2;
5474 offset = ahc_inb(ahc, TARG_OFFSET + i);
5475 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5476 /* Set to the lowest sync rate, 5MHz */
5478 maxsync = AHC_SYNCRATE_ULTRA2;
5479 if ((ahc->features & AHC_DT) != 0)
5480 maxsync = AHC_SYNCRATE_DT;
5481 tinfo->user.period =
5482 ahc_find_period(ahc, scsirate, maxsync);
5484 tinfo->user.period = 0;
5486 tinfo->user.offset = MAX_OFFSET;
5487 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5488 && (ahc->features & AHC_DT) != 0)
5489 tinfo->user.ppr_options =
5491 } else if ((scsirate & SOFS) != 0) {
5492 if ((scsirate & SXFR) == 0x40
5493 && (ultraenb & mask) != 0) {
5494 /* Treat 10MHz as a non-ultra speed */
5498 tinfo->user.period =
5499 ahc_find_period(ahc, scsirate,
5501 ? AHC_SYNCRATE_ULTRA
5502 : AHC_SYNCRATE_FAST);
5503 if (tinfo->user.period != 0)
5504 tinfo->user.offset = MAX_OFFSET;
5506 if (tinfo->user.period == 0)
5507 tinfo->user.offset = 0;
5508 if ((scsirate & WIDEXFER) != 0
5509 && (ahc->features & AHC_WIDE) != 0)
5510 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5511 tinfo->user.protocol_version = 4;
5512 if ((ahc->features & AHC_DT) != 0)
5513 tinfo->user.transport_version = 3;
5515 tinfo->user.transport_version = 2;
5516 tinfo->goal.protocol_version = 2;
5517 tinfo->goal.transport_version = 2;
5518 tinfo->curr.protocol_version = 2;
5519 tinfo->curr.transport_version = 2;
5521 tstate->ultraenb = 0;
5523 ahc->user_discenable = discenable;
5524 ahc->user_tagenable = tagenable;
5526 return (ahc->bus_chip_init(ahc));
5530 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5534 hcntrl = ahc_inb(ahc, HCNTRL);
5536 ahc->pause &= ~INTEN;
5537 ahc->unpause &= ~INTEN;
5540 ahc->pause |= INTEN;
5541 ahc->unpause |= INTEN;
5543 ahc_outb(ahc, HCNTRL, hcntrl);
5547 * Ensure that the card is paused in a location
5548 * outside of all critical sections and that all
5549 * pending work is completed prior to returning.
5550 * This routine should only be called from outside
5551 * an interrupt context.
5554 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5561 ahc->flags |= AHC_ALL_INTERRUPTS;
5567 * Give the sequencer some time to service
5568 * any active selections.
5575 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5576 intstat = ahc_inb(ahc, INTSTAT);
5577 if ((intstat & INT_PEND) == 0) {
5578 ahc_clear_critical_section(ahc);
5579 intstat = ahc_inb(ahc, INTSTAT);
5582 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5583 && ((intstat & INT_PEND) != 0
5584 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5585 if (maxloops == 0) {
5586 printk("Infinite interrupt loop, INTSTAT = %x",
5587 ahc_inb(ahc, INTSTAT));
5589 ahc_platform_flushwork(ahc);
5590 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5595 ahc_suspend(struct ahc_softc *ahc)
5598 ahc_pause_and_flushwork(ahc);
5600 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5605 #ifdef AHC_TARGET_MODE
5607 * XXX What about ATIOs that have not yet been serviced?
5608 * Perhaps we should just refuse to be suspended if we
5609 * are acting in a target role.
5611 if (ahc->pending_device != NULL) {
5621 ahc_resume(struct ahc_softc *ahc)
5624 ahc_reset(ahc, /*reinit*/TRUE);
5625 ahc_intr_enable(ahc, TRUE);
5630 /************************** Busy Target Table *********************************/
5632 * Return the untagged transaction id for a given target/channel lun.
5633 * Optionally, clear the entry.
5636 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5639 u_int target_offset;
5641 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5644 saved_scbptr = ahc_inb(ahc, SCBPTR);
5645 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5646 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5647 ahc_outb(ahc, SCBPTR, saved_scbptr);
5649 target_offset = TCL_TARGET_OFFSET(tcl);
5650 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5657 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5659 u_int target_offset;
5661 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5664 saved_scbptr = ahc_inb(ahc, SCBPTR);
5665 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5666 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5667 ahc_outb(ahc, SCBPTR, saved_scbptr);
5669 target_offset = TCL_TARGET_OFFSET(tcl);
5670 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5675 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5677 u_int target_offset;
5679 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5682 saved_scbptr = ahc_inb(ahc, SCBPTR);
5683 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5684 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5685 ahc_outb(ahc, SCBPTR, saved_scbptr);
5687 target_offset = TCL_TARGET_OFFSET(tcl);
5688 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5692 /************************** SCB and SCB queue management **********************/
5694 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5695 char channel, int lun, u_int tag, role_t role)
5697 int targ = SCB_GET_TARGET(ahc, scb);
5698 char chan = SCB_GET_CHANNEL(ahc, scb);
5699 int slun = SCB_GET_LUN(scb);
5702 match = ((chan == channel) || (channel == ALL_CHANNELS));
5704 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5706 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5708 #ifdef AHC_TARGET_MODE
5711 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5712 if (role == ROLE_INITIATOR) {
5713 match = (group != XPT_FC_GROUP_TMODE)
5714 && ((tag == scb->hscb->tag)
5715 || (tag == SCB_LIST_NULL));
5716 } else if (role == ROLE_TARGET) {
5717 match = (group == XPT_FC_GROUP_TMODE)
5718 && ((tag == scb->io_ctx->csio.tag_id)
5719 || (tag == SCB_LIST_NULL));
5721 #else /* !AHC_TARGET_MODE */
5722 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5723 #endif /* AHC_TARGET_MODE */
5730 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5736 target = SCB_GET_TARGET(ahc, scb);
5737 lun = SCB_GET_LUN(scb);
5738 channel = SCB_GET_CHANNEL(ahc, scb);
5740 ahc_search_qinfifo(ahc, target, channel, lun,
5741 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5742 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5744 ahc_platform_freeze_devq(ahc, scb);
5748 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5750 struct scb *prev_scb;
5753 if (ahc_qinfifo_count(ahc) != 0) {
5757 prev_pos = ahc->qinfifonext - 1;
5758 prev_tag = ahc->qinfifo[prev_pos];
5759 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5761 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5762 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5763 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5765 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5770 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5773 if (prev_scb == NULL) {
5774 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5776 prev_scb->hscb->next = scb->hscb->tag;
5777 ahc_sync_scb(ahc, prev_scb,
5778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5780 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5781 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5782 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5786 ahc_qinfifo_count(struct ahc_softc *ahc)
5791 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5792 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5793 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5795 qinpos = ahc_inb(ahc, QINPOS);
5796 diff = ahc->qinfifonext - qinpos;
5801 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5802 int lun, u_int tag, role_t role, uint32_t status,
5803 ahc_search_action action)
5806 struct scb *prev_scb;
5816 qintail = ahc->qinfifonext;
5817 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5819 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5820 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5822 qinstart = ahc_inb(ahc, QINPOS);
5827 if (action == SEARCH_COMPLETE) {
5829 * Don't attempt to run any queued untagged transactions
5830 * until we are done with the abort process.
5832 ahc_freeze_untagged_queues(ahc);
5836 * Start with an empty queue. Entries that are not chosen
5837 * for removal will be re-added to the queue as we go.
5839 ahc->qinfifonext = qinpos;
5840 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5842 while (qinpos != qintail) {
5843 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5845 printk("qinpos = %d, SCB index = %d\n",
5846 qinpos, ahc->qinfifo[qinpos]);
5850 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5852 * We found an scb that needs to be acted on.
5856 case SEARCH_COMPLETE:
5861 ostat = ahc_get_transaction_status(scb);
5862 if (ostat == CAM_REQ_INPROG)
5863 ahc_set_transaction_status(scb, status);
5864 cstat = ahc_get_transaction_status(scb);
5865 if (cstat != CAM_REQ_CMP)
5866 ahc_freeze_scb(scb);
5867 if ((scb->flags & SCB_ACTIVE) == 0)
5868 printk("Inactive SCB in qinfifo\n");
5876 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5881 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5887 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5888 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5890 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5893 if (action != SEARCH_COUNT
5895 && (qinstart != ahc->qinfifonext)) {
5897 * The sequencer may be in the process of dmaing
5898 * down the SCB at the beginning of the queue.
5899 * This could be problematic if either the first,
5900 * or the second SCB is removed from the queue
5901 * (the first SCB includes a pointer to the "next"
5902 * SCB to dma). If we have removed any entries, swap
5903 * the first element in the queue with the next HSCB
5904 * so the sequencer will notice that NEXT_QUEUED_SCB
5905 * has changed during its dma attempt and will retry
5908 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5911 printk("found = %d, qinstart = %d, qinfifionext = %d\n",
5912 found, qinstart, ahc->qinfifonext);
5913 panic("First/Second Qinfifo fixup\n");
5916 * ahc_swap_with_next_hscb forces our next pointer to
5917 * point to the reserved SCB for future commands. Save
5918 * and restore our original next pointer to maintain
5921 next = scb->hscb->next;
5922 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5923 ahc_swap_with_next_hscb(ahc, scb);
5924 scb->hscb->next = next;
5925 ahc->qinfifo[qinstart] = scb->hscb->tag;
5927 /* Tell the card about the new head of the qinfifo. */
5928 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5930 /* Fixup the tail "next" pointer. */
5931 qintail = ahc->qinfifonext - 1;
5932 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5933 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5937 * Search waiting for selection list.
5939 curscbptr = ahc_inb(ahc, SCBPTR);
5940 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5941 prev = SCB_LIST_NULL;
5943 while (next != SCB_LIST_NULL) {
5946 ahc_outb(ahc, SCBPTR, next);
5947 scb_index = ahc_inb(ahc, SCB_TAG);
5948 if (scb_index >= ahc->scb_data->numscbs) {
5949 printk("Waiting List inconsistency. "
5950 "SCB index == %d, yet numscbs == %d.",
5951 scb_index, ahc->scb_data->numscbs);
5952 ahc_dump_card_state(ahc);
5953 panic("for safety");
5955 scb = ahc_lookup_scb(ahc, scb_index);
5957 printk("scb_index = %d, next = %d\n",
5959 panic("Waiting List traversal\n");
5961 if (ahc_match_scb(ahc, scb, target, channel,
5962 lun, SCB_LIST_NULL, role)) {
5964 * We found an scb that needs to be acted on.
5968 case SEARCH_COMPLETE:
5973 ostat = ahc_get_transaction_status(scb);
5974 if (ostat == CAM_REQ_INPROG)
5975 ahc_set_transaction_status(scb,
5977 cstat = ahc_get_transaction_status(scb);
5978 if (cstat != CAM_REQ_CMP)
5979 ahc_freeze_scb(scb);
5980 if ((scb->flags & SCB_ACTIVE) == 0)
5981 printk("Inactive SCB in Waiting List\n");
5986 next = ahc_rem_wscb(ahc, next, prev);
5990 next = ahc_inb(ahc, SCB_NEXT);
5996 next = ahc_inb(ahc, SCB_NEXT);
5999 ahc_outb(ahc, SCBPTR, curscbptr);
6001 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
6002 channel, lun, status, action);
6004 if (action == SEARCH_COMPLETE)
6005 ahc_release_untagged_queues(ahc);
6010 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
6011 int target, char channel, int lun, uint32_t status,
6012 ahc_search_action action)
6019 if (action == SEARCH_COMPLETE) {
6021 * Don't attempt to run any queued untagged transactions
6022 * until we are done with the abort process.
6024 ahc_freeze_untagged_queues(ahc);
6029 if ((ahc->flags & AHC_SCB_BTT) == 0) {
6032 if (target != CAM_TARGET_WILDCARD) {
6043 for (; i < maxtarget; i++) {
6044 struct scb_tailq *untagged_q;
6045 struct scb *next_scb;
6047 untagged_q = &(ahc->untagged_queues[i]);
6048 next_scb = TAILQ_FIRST(untagged_q);
6049 while (next_scb != NULL) {
6052 next_scb = TAILQ_NEXT(scb, links.tqe);
6055 * The head of the list may be the currently
6056 * active untagged command for a device.
6057 * We're only searching for commands that
6058 * have not been started. A transaction
6059 * marked active but still in the qinfifo
6060 * is removed by the qinfifo scanning code
6063 if ((scb->flags & SCB_ACTIVE) != 0)
6066 if (ahc_match_scb(ahc, scb, target, channel, lun,
6067 SCB_LIST_NULL, ROLE_INITIATOR) == 0
6068 || (ctx != NULL && ctx != scb->io_ctx))
6072 * We found an scb that needs to be acted on.
6076 case SEARCH_COMPLETE:
6081 ostat = ahc_get_transaction_status(scb);
6082 if (ostat == CAM_REQ_INPROG)
6083 ahc_set_transaction_status(scb, status);
6084 cstat = ahc_get_transaction_status(scb);
6085 if (cstat != CAM_REQ_CMP)
6086 ahc_freeze_scb(scb);
6087 if ((scb->flags & SCB_ACTIVE) == 0)
6088 printk("Inactive SCB in untaggedQ\n");
6093 scb->flags &= ~SCB_UNTAGGEDQ;
6094 TAILQ_REMOVE(untagged_q, scb, links.tqe);
6102 if (action == SEARCH_COMPLETE)
6103 ahc_release_untagged_queues(ahc);
6108 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
6109 int lun, u_int tag, int stop_on_first, int remove,
6119 next = ahc_inb(ahc, DISCONNECTED_SCBH);
6120 prev = SCB_LIST_NULL;
6123 /* restore this when we're done */
6124 active_scb = ahc_inb(ahc, SCBPTR);
6126 /* Silence compiler */
6127 active_scb = SCB_LIST_NULL;
6129 while (next != SCB_LIST_NULL) {
6132 ahc_outb(ahc, SCBPTR, next);
6133 scb_index = ahc_inb(ahc, SCB_TAG);
6134 if (scb_index >= ahc->scb_data->numscbs) {
6135 printk("Disconnected List inconsistency. "
6136 "SCB index == %d, yet numscbs == %d.",
6137 scb_index, ahc->scb_data->numscbs);
6138 ahc_dump_card_state(ahc);
6139 panic("for safety");
6143 panic("Disconnected List Loop. "
6144 "cur SCBPTR == %x, prev SCBPTR == %x.",
6147 scbp = ahc_lookup_scb(ahc, scb_index);
6148 if (ahc_match_scb(ahc, scbp, target, channel, lun,
6149 tag, ROLE_INITIATOR)) {
6153 ahc_rem_scb_from_disc_list(ahc, prev, next);
6156 next = ahc_inb(ahc, SCB_NEXT);
6162 next = ahc_inb(ahc, SCB_NEXT);
6166 ahc_outb(ahc, SCBPTR, active_scb);
6171 * Remove an SCB from the on chip list of disconnected transactions.
6172 * This is empty/unused if we are not performing SCB paging.
6175 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
6179 ahc_outb(ahc, SCBPTR, scbptr);
6180 next = ahc_inb(ahc, SCB_NEXT);
6182 ahc_outb(ahc, SCB_CONTROL, 0);
6184 ahc_add_curscb_to_free_list(ahc);
6186 if (prev != SCB_LIST_NULL) {
6187 ahc_outb(ahc, SCBPTR, prev);
6188 ahc_outb(ahc, SCB_NEXT, next);
6190 ahc_outb(ahc, DISCONNECTED_SCBH, next);
6196 * Add the SCB as selected by SCBPTR onto the on chip list of
6197 * free hardware SCBs. This list is empty/unused if we are not
6198 * performing SCB paging.
6201 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
6204 * Invalidate the tag so that our abort
6205 * routines don't think it's active.
6207 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
6209 if ((ahc->flags & AHC_PAGESCBS) != 0) {
6210 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
6211 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
6216 * Manipulate the waiting for selection list and return the
6217 * scb that follows the one that we remove.
6220 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
6225 * Select the SCB we want to abort and
6226 * pull the next pointer out of it.
6228 curscb = ahc_inb(ahc, SCBPTR);
6229 ahc_outb(ahc, SCBPTR, scbpos);
6230 next = ahc_inb(ahc, SCB_NEXT);
6232 /* Clear the necessary fields */
6233 ahc_outb(ahc, SCB_CONTROL, 0);
6235 ahc_add_curscb_to_free_list(ahc);
6237 /* update the waiting list */
6238 if (prev == SCB_LIST_NULL) {
6239 /* First in the list */
6240 ahc_outb(ahc, WAITING_SCBH, next);
6243 * Ensure we aren't attempting to perform
6244 * selection for this entry.
6246 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
6249 * Select the scb that pointed to us
6250 * and update its next pointer.
6252 ahc_outb(ahc, SCBPTR, prev);
6253 ahc_outb(ahc, SCB_NEXT, next);
6257 * Point us back at the original scb position.
6259 ahc_outb(ahc, SCBPTR, curscb);
6263 /******************************** Error Handling ******************************/
6265 * Abort all SCBs that match the given description (target/channel/lun/tag),
6266 * setting their status to the passed in status if the status has not already
6267 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
6268 * is paused before it is called.
6271 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
6272 int lun, u_int tag, role_t role, uint32_t status)
6275 struct scb *scbp_next;
6285 * Don't attempt to run any queued untagged transactions
6286 * until we are done with the abort process.
6288 ahc_freeze_untagged_queues(ahc);
6290 /* restore this when we're done */
6291 active_scb = ahc_inb(ahc, SCBPTR);
6293 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
6294 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
6297 * Clean out the busy target table for any untagged commands.
6301 if (target != CAM_TARGET_WILDCARD) {
6308 if (lun == CAM_LUN_WILDCARD) {
6311 * Unless we are using an SCB based
6312 * busy targets table, there is only
6313 * one table entry for all luns of
6318 if ((ahc->flags & AHC_SCB_BTT) != 0)
6319 maxlun = AHC_NUM_LUNS;
6325 if (role != ROLE_TARGET) {
6326 for (;i < maxtarget; i++) {
6327 for (j = minlun;j < maxlun; j++) {
6331 tcl = BUILD_TCL(i << 4, j);
6332 scbid = ahc_index_busy_tcl(ahc, tcl);
6333 scbp = ahc_lookup_scb(ahc, scbid);
6335 || ahc_match_scb(ahc, scbp, target, channel,
6336 lun, tag, role) == 0)
6338 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
6343 * Go through the disconnected list and remove any entries we
6344 * have queued for completion, 0'ing their control byte too.
6345 * We save the active SCB and restore it ourselves, so there
6346 * is no reason for this search to restore it too.
6348 ahc_search_disc_list(ahc, target, channel, lun, tag,
6349 /*stop_on_first*/FALSE, /*remove*/TRUE,
6350 /*save_state*/FALSE);
6354 * Go through the hardware SCB array looking for commands that
6355 * were active but not on any list. In some cases, these remnants
6356 * might not still have mappings in the scbindex array (e.g. unexpected
6357 * bus free with the same scb queued for an abort). Don't hold this
6360 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6363 ahc_outb(ahc, SCBPTR, i);
6364 scbid = ahc_inb(ahc, SCB_TAG);
6365 scbp = ahc_lookup_scb(ahc, scbid);
6366 if ((scbp == NULL && scbid != SCB_LIST_NULL)
6368 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
6369 ahc_add_curscb_to_free_list(ahc);
6373 * Go through the pending CCB list and look for
6374 * commands for this target that are still active.
6375 * These are other tagged commands that were
6376 * disconnected when the reset occurred.
6378 scbp_next = LIST_FIRST(&ahc->pending_scbs);
6379 while (scbp_next != NULL) {
6381 scbp_next = LIST_NEXT(scbp, pending_links);
6382 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6385 ostat = ahc_get_transaction_status(scbp);
6386 if (ostat == CAM_REQ_INPROG)
6387 ahc_set_transaction_status(scbp, status);
6388 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
6389 ahc_freeze_scb(scbp);
6390 if ((scbp->flags & SCB_ACTIVE) == 0)
6391 printk("Inactive SCB on pending list\n");
6392 ahc_done(ahc, scbp);
6396 ahc_outb(ahc, SCBPTR, active_scb);
6397 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6398 ahc_release_untagged_queues(ahc);
6403 ahc_reset_current_bus(struct ahc_softc *ahc)
6407 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6408 scsiseq = ahc_inb(ahc, SCSISEQ);
6409 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6410 ahc_flush_device_writes(ahc);
6411 ahc_delay(AHC_BUSRESET_DELAY);
6412 /* Turn off the bus reset */
6413 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6415 ahc_clear_intstat(ahc);
6417 /* Re-enable reset interrupts */
6418 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6422 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6424 struct ahc_devinfo devinfo;
6425 u_int initiator, target, max_scsiid;
6433 ahc->pending_device = NULL;
6435 ahc_compile_devinfo(&devinfo,
6436 CAM_TARGET_WILDCARD,
6437 CAM_TARGET_WILDCARD,
6439 channel, ROLE_UNKNOWN);
6442 /* Make sure the sequencer is in a safe location. */
6443 ahc_clear_critical_section(ahc);
6446 * Run our command complete fifos to ensure that we perform
6447 * completion processing on any commands that 'completed'
6448 * before the reset occurred.
6450 ahc_run_qoutfifo(ahc);
6451 #ifdef AHC_TARGET_MODE
6453 * XXX - In Twin mode, the tqinfifo may have commands
6454 * for an unaffected channel in it. However, if
6455 * we have run out of ATIO resources to drain that
6456 * queue, we may not get them all out here. Further,
6457 * the blocked transactions for the reset channel
6458 * should just be killed off, irrespecitve of whether
6459 * we are blocked on ATIO resources. Write a routine
6460 * to compact the tqinfifo appropriately.
6462 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6463 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6468 * Reset the bus if we are initiating this reset
6470 sblkctl = ahc_inb(ahc, SBLKCTL);
6472 if ((ahc->features & AHC_TWIN) != 0
6473 && ((sblkctl & SELBUSB) != 0))
6475 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6476 if (cur_channel != channel) {
6477 /* Case 1: Command for another bus is active
6478 * Stealthily reset the other bus without
6479 * upsetting the current bus.
6481 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6482 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6483 #ifdef AHC_TARGET_MODE
6485 * Bus resets clear ENSELI, so we cannot
6486 * defer re-enabling bus reset interrupts
6487 * if we are in target mode.
6489 if ((ahc->flags & AHC_TARGETROLE) != 0)
6490 simode1 |= ENSCSIRST;
6492 ahc_outb(ahc, SIMODE1, simode1);
6494 ahc_reset_current_bus(ahc);
6495 ahc_clear_intstat(ahc);
6496 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6497 ahc_outb(ahc, SBLKCTL, sblkctl);
6498 restart_needed = FALSE;
6500 /* Case 2: A command from this bus is active or we're idle */
6501 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6502 #ifdef AHC_TARGET_MODE
6504 * Bus resets clear ENSELI, so we cannot
6505 * defer re-enabling bus reset interrupts
6506 * if we are in target mode.
6508 if ((ahc->flags & AHC_TARGETROLE) != 0)
6509 simode1 |= ENSCSIRST;
6511 ahc_outb(ahc, SIMODE1, simode1);
6513 ahc_reset_current_bus(ahc);
6514 ahc_clear_intstat(ahc);
6515 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6516 restart_needed = TRUE;
6520 * Clean up all the state information for the
6521 * pending transactions on this bus.
6523 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6524 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6525 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6527 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6529 #ifdef AHC_TARGET_MODE
6531 * Send an immediate notify ccb to all target more peripheral
6532 * drivers affected by this action.
6534 for (target = 0; target <= max_scsiid; target++) {
6535 struct ahc_tmode_tstate* tstate;
6538 tstate = ahc->enabled_targets[target];
6541 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6542 struct ahc_tmode_lstate* lstate;
6544 lstate = tstate->enabled_luns[lun];
6548 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6549 EVENT_TYPE_BUS_RESET, /*arg*/0);
6550 ahc_send_lstate_events(ahc, lstate);
6554 /* Notify the XPT that a bus reset occurred */
6555 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6556 CAM_LUN_WILDCARD, AC_BUS_RESET);
6559 * Revert to async/narrow transfers until we renegotiate.
6561 for (target = 0; target <= max_scsiid; target++) {
6563 if (ahc->enabled_targets[target] == NULL)
6565 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6566 struct ahc_devinfo devinfo;
6568 ahc_compile_devinfo(&devinfo, target, initiator,
6570 channel, ROLE_UNKNOWN);
6571 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6572 AHC_TRANS_CUR, /*paused*/TRUE);
6573 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6574 /*period*/0, /*offset*/0,
6575 /*ppr_options*/0, AHC_TRANS_CUR,
6588 /***************************** Residual Processing ****************************/
6590 * Calculate the residual for a just completed SCB.
6593 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6595 struct hardware_scb *hscb;
6596 struct status_pkt *spkt;
6598 uint32_t resid_sgptr;
6604 * SG_RESID_VALID clear in sgptr.
6605 * 2) Transferless command
6606 * 3) Never performed any transfers.
6607 * sgptr has SG_FULL_RESID set.
6608 * 4) No residual but target did not
6609 * save data pointers after the
6610 * last transfer, so sgptr was
6612 * 5) We have a partial residual.
6613 * Use residual_sgptr to determine
6618 sgptr = ahc_le32toh(hscb->sgptr);
6619 if ((sgptr & SG_RESID_VALID) == 0)
6622 sgptr &= ~SG_RESID_VALID;
6624 if ((sgptr & SG_LIST_NULL) != 0)
6628 spkt = &hscb->shared_data.status;
6629 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6630 if ((sgptr & SG_FULL_RESID) != 0) {
6632 resid = ahc_get_transfer_length(scb);
6633 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6636 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6637 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6639 struct ahc_dma_seg *sg;
6642 * Remainder of the SG where the transfer
6645 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6646 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6648 /* The residual sg_ptr always points to the next sg */
6652 * Add up the contents of all residual
6653 * SG segments that are after the SG where
6654 * the transfer stopped.
6656 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6658 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6661 if ((scb->flags & SCB_SENSE) == 0)
6662 ahc_set_residual(scb, resid);
6664 ahc_set_sense_residual(scb, resid);
6667 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6668 ahc_print_path(ahc, scb);
6669 printk("Handled %sResidual of %d bytes\n",
6670 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6675 /******************************* Target Mode **********************************/
6676 #ifdef AHC_TARGET_MODE
6678 * Add a target mode event to this lun's queue
6681 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6682 u_int initiator_id, u_int event_type, u_int event_arg)
6684 struct ahc_tmode_event *event;
6687 xpt_freeze_devq(lstate->path, /*count*/1);
6688 if (lstate->event_w_idx >= lstate->event_r_idx)
6689 pending = lstate->event_w_idx - lstate->event_r_idx;
6691 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6692 - (lstate->event_r_idx - lstate->event_w_idx);
6694 if (event_type == EVENT_TYPE_BUS_RESET
6695 || event_type == MSG_BUS_DEV_RESET) {
6697 * Any earlier events are irrelevant, so reset our buffer.
6698 * This has the effect of allowing us to deal with reset
6699 * floods (an external device holding down the reset line)
6700 * without losing the event that is really interesting.
6702 lstate->event_r_idx = 0;
6703 lstate->event_w_idx = 0;
6704 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6707 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6708 xpt_print_path(lstate->path);
6709 printk("immediate event %x:%x lost\n",
6710 lstate->event_buffer[lstate->event_r_idx].event_type,
6711 lstate->event_buffer[lstate->event_r_idx].event_arg);
6712 lstate->event_r_idx++;
6713 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6714 lstate->event_r_idx = 0;
6715 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6718 event = &lstate->event_buffer[lstate->event_w_idx];
6719 event->initiator_id = initiator_id;
6720 event->event_type = event_type;
6721 event->event_arg = event_arg;
6722 lstate->event_w_idx++;
6723 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6724 lstate->event_w_idx = 0;
6728 * Send any target mode events queued up waiting
6729 * for immediate notify resources.
6732 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6734 struct ccb_hdr *ccbh;
6735 struct ccb_immed_notify *inot;
6737 while (lstate->event_r_idx != lstate->event_w_idx
6738 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6739 struct ahc_tmode_event *event;
6741 event = &lstate->event_buffer[lstate->event_r_idx];
6742 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6743 inot = (struct ccb_immed_notify *)ccbh;
6744 switch (event->event_type) {
6745 case EVENT_TYPE_BUS_RESET:
6746 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6749 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6750 inot->message_args[0] = event->event_type;
6751 inot->message_args[1] = event->event_arg;
6754 inot->initiator_id = event->initiator_id;
6755 inot->sense_len = 0;
6756 xpt_done((union ccb *)inot);
6757 lstate->event_r_idx++;
6758 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6759 lstate->event_r_idx = 0;
6764 /******************** Sequencer Program Patching/Download *********************/
6768 ahc_dumpseq(struct ahc_softc* ahc)
6772 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6773 ahc_outb(ahc, SEQADDR0, 0);
6774 ahc_outb(ahc, SEQADDR1, 0);
6775 for (i = 0; i < ahc->instruction_ram_size; i++) {
6776 uint8_t ins_bytes[4];
6778 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6779 printk("0x%08x\n", ins_bytes[0] << 24
6780 | ins_bytes[1] << 16
6788 ahc_loadseq(struct ahc_softc *ahc)
6790 struct cs cs_table[NUM_CRITICAL_SECTIONS];
6791 u_int begin_set[NUM_CRITICAL_SECTIONS];
6792 u_int end_set[NUM_CRITICAL_SECTIONS];
6793 const struct patch *cur_patch;
6798 u_int sg_prefetch_cnt;
6800 uint8_t download_consts[7];
6803 * Start out with 0 critical sections
6804 * that apply to this firmware load.
6808 memset(begin_set, 0, sizeof(begin_set));
6809 memset(end_set, 0, sizeof(end_set));
6811 /* Setup downloadable constant table */
6812 download_consts[QOUTFIFO_OFFSET] = 0;
6813 if (ahc->targetcmds != NULL)
6814 download_consts[QOUTFIFO_OFFSET] += 32;
6815 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6816 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6817 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6818 sg_prefetch_cnt = ahc->pci_cachesize;
6819 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6820 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6821 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6822 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6823 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6825 cur_patch = patches;
6828 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6829 ahc_outb(ahc, SEQADDR0, 0);
6830 ahc_outb(ahc, SEQADDR1, 0);
6832 for (i = 0; i < sizeof(seqprog)/4; i++) {
6833 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6835 * Don't download this instruction as it
6836 * is in a patch that was removed.
6841 if (downloaded == ahc->instruction_ram_size) {
6843 * We're about to exceed the instruction
6844 * storage capacity for this chip. Fail
6847 printk("\n%s: Program too large for instruction memory "
6848 "size of %d!\n", ahc_name(ahc),
6849 ahc->instruction_ram_size);
6854 * Move through the CS table until we find a CS
6855 * that might apply to this instruction.
6857 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
6858 if (critical_sections[cur_cs].end <= i) {
6859 if (begin_set[cs_count] == TRUE
6860 && end_set[cs_count] == FALSE) {
6861 cs_table[cs_count].end = downloaded;
6862 end_set[cs_count] = TRUE;
6867 if (critical_sections[cur_cs].begin <= i
6868 && begin_set[cs_count] == FALSE) {
6869 cs_table[cs_count].begin = downloaded;
6870 begin_set[cs_count] = TRUE;
6874 ahc_download_instr(ahc, i, download_consts);
6878 ahc->num_critical_sections = cs_count;
6879 if (cs_count != 0) {
6881 cs_count *= sizeof(struct cs);
6882 ahc->critical_sections = kmemdup(cs_table, cs_count, GFP_ATOMIC);
6883 if (ahc->critical_sections == NULL)
6884 panic("ahc_loadseq: Could not malloc");
6886 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6889 printk(" %d instructions downloaded\n", downloaded);
6890 printk("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6891 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6897 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
6898 u_int start_instr, u_int *skip_addr)
6900 const struct patch *cur_patch;
6901 const struct patch *last_patch;
6904 num_patches = ARRAY_SIZE(patches);
6905 last_patch = &patches[num_patches];
6906 cur_patch = *start_patch;
6908 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6910 if (cur_patch->patch_func(ahc) == 0) {
6912 /* Start rejecting code */
6913 *skip_addr = start_instr + cur_patch->skip_instr;
6914 cur_patch += cur_patch->skip_patch;
6916 /* Accepted this patch. Advance to the next
6917 * one and wait for our intruction pointer to
6924 *start_patch = cur_patch;
6925 if (start_instr < *skip_addr)
6926 /* Still skipping */
6933 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6935 union ins_formats instr;
6936 struct ins_format1 *fmt1_ins;
6937 struct ins_format3 *fmt3_ins;
6941 * The firmware is always compiled into a little endian format.
6943 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6945 fmt1_ins = &instr.format1;
6948 /* Pull the opcode */
6949 opcode = instr.format1.opcode;
6960 const struct patch *cur_patch;
6966 fmt3_ins = &instr.format3;
6968 address = fmt3_ins->address;
6969 cur_patch = patches;
6972 for (i = 0; i < address;) {
6974 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6976 if (skip_addr > i) {
6979 end_addr = min(address, skip_addr);
6980 address_offset += end_addr - i;
6986 address -= address_offset;
6987 fmt3_ins->address = address;
6996 if (fmt1_ins->parity != 0) {
6997 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6999 fmt1_ins->parity = 0;
7000 if ((ahc->features & AHC_CMD_CHAN) == 0
7001 && opcode == AIC_OP_BMOV) {
7003 * Block move was added at the same time
7004 * as the command channel. Verify that
7005 * this is only a move of a single element
7006 * and convert the BMOV to a MOV
7007 * (AND with an immediate of FF).
7009 if (fmt1_ins->immediate != 1)
7010 panic("%s: BMOV not supported\n",
7012 fmt1_ins->opcode = AIC_OP_AND;
7013 fmt1_ins->immediate = 0xff;
7017 if ((ahc->features & AHC_ULTRA2) != 0) {
7020 /* Calculate odd parity for the instruction */
7021 for (i = 0, count = 0; i < 31; i++) {
7025 if ((instr.integer & mask) != 0)
7028 if ((count & 0x01) == 0)
7029 instr.format1.parity = 1;
7031 /* Compress the instruction for older sequencers */
7032 if (fmt3_ins != NULL) {
7035 | (fmt3_ins->source << 8)
7036 | (fmt3_ins->address << 16)
7037 | (fmt3_ins->opcode << 25);
7041 | (fmt1_ins->source << 8)
7042 | (fmt1_ins->destination << 16)
7043 | (fmt1_ins->ret << 24)
7044 | (fmt1_ins->opcode << 25);
7047 /* The sequencer is a little endian cpu */
7048 instr.integer = ahc_htole32(instr.integer);
7049 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
7052 panic("Unknown opcode encountered in seq program");
7058 ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries,
7059 const char *name, u_int address, u_int value,
7060 u_int *cur_column, u_int wrap_point)
7065 if (cur_column != NULL && *cur_column >= wrap_point) {
7069 printed = printk("%s[0x%x]", name, value);
7070 if (table == NULL) {
7071 printed += printk(" ");
7072 *cur_column += printed;
7076 while (printed_mask != 0xFF) {
7079 for (entry = 0; entry < num_entries; entry++) {
7080 if (((value & table[entry].mask)
7081 != table[entry].value)
7082 || ((printed_mask & table[entry].mask)
7083 == table[entry].mask))
7086 printed += printk("%s%s",
7087 printed_mask == 0 ? ":(" : "|",
7089 printed_mask |= table[entry].mask;
7093 if (entry >= num_entries)
7096 if (printed_mask != 0)
7097 printed += printk(") ");
7099 printed += printk(" ");
7100 if (cur_column != NULL)
7101 *cur_column += printed;
7106 ahc_dump_card_state(struct ahc_softc *ahc)
7109 struct scb_tailq *untagged_q;
7120 uint8_t saved_scbptr;
7122 if (ahc_is_paused(ahc)) {
7129 saved_scbptr = ahc_inb(ahc, SCBPTR);
7130 last_phase = ahc_inb(ahc, LASTPHASE);
7131 printk(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
7132 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
7133 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
7134 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
7136 printk("Card was paused\n");
7137 printk("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
7138 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
7139 ahc_inb(ahc, ARG_2));
7140 printk("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
7141 ahc_inb(ahc, SCBPTR));
7143 if ((ahc->features & AHC_DT) != 0)
7144 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
7145 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
7146 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
7147 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
7148 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
7149 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
7150 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
7151 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
7152 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
7153 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
7154 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
7155 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
7156 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
7157 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
7158 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
7159 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
7160 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
7161 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
7162 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
7166 for (i = 0; i < STACK_SIZE; i++)
7167 printk(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
7168 printk("\nSCB count = %d\n", ahc->scb_data->numscbs);
7169 printk("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
7170 printk("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
7172 printk("QINFIFO entries: ");
7173 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
7174 qinpos = ahc_inb(ahc, SNSCB_QOFF);
7175 ahc_outb(ahc, SNSCB_QOFF, qinpos);
7177 qinpos = ahc_inb(ahc, QINPOS);
7178 qintail = ahc->qinfifonext;
7179 while (qinpos != qintail) {
7180 printk("%d ", ahc->qinfifo[qinpos]);
7185 printk("Waiting Queue entries: ");
7186 scb_index = ahc_inb(ahc, WAITING_SCBH);
7188 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7189 ahc_outb(ahc, SCBPTR, scb_index);
7190 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
7191 scb_index = ahc_inb(ahc, SCB_NEXT);
7195 printk("Disconnected Queue entries: ");
7196 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
7198 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7199 ahc_outb(ahc, SCBPTR, scb_index);
7200 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
7201 scb_index = ahc_inb(ahc, SCB_NEXT);
7205 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
7206 printk("QOUTFIFO entries: ");
7207 qoutpos = ahc->qoutfifonext;
7209 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
7210 printk("%d ", ahc->qoutfifo[qoutpos]);
7215 printk("Sequencer Free SCB List: ");
7216 scb_index = ahc_inb(ahc, FREE_SCBH);
7218 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7219 ahc_outb(ahc, SCBPTR, scb_index);
7220 printk("%d ", scb_index);
7221 scb_index = ahc_inb(ahc, SCB_NEXT);
7225 printk("Sequencer SCB Info: ");
7226 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
7227 ahc_outb(ahc, SCBPTR, i);
7228 cur_col = printk("\n%3d ", i);
7230 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
7231 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
7232 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
7233 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7237 printk("Pending list: ");
7239 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7242 cur_col = printk("\n%3d ", scb->hscb->tag);
7243 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
7244 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
7245 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
7246 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7247 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7249 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
7251 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7257 printk("Kernel Free SCB list: ");
7259 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
7262 printk("%d ", scb->hscb->tag);
7266 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
7267 for (target = 0; target <= maxtarget; target++) {
7268 untagged_q = &ahc->untagged_queues[target];
7269 if (TAILQ_FIRST(untagged_q) == NULL)
7271 printk("Untagged Q(%d): ", target);
7273 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
7276 printk("%d ", scb->hscb->tag);
7281 printk("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
7282 ahc_outb(ahc, SCBPTR, saved_scbptr);
7287 /************************* Target Mode ****************************************/
7288 #ifdef AHC_TARGET_MODE
7290 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7291 struct ahc_tmode_tstate **tstate,
7292 struct ahc_tmode_lstate **lstate,
7293 int notfound_failure)
7296 if ((ahc->features & AHC_TARGETMODE) == 0)
7297 return (CAM_REQ_INVALID);
7300 * Handle the 'black hole' device that sucks up
7301 * requests to unattached luns on enabled targets.
7303 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7304 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7306 *lstate = ahc->black_hole;
7310 max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
7311 if (ccb->ccb_h.target_id >= max_id)
7312 return (CAM_TID_INVALID);
7314 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7315 return (CAM_LUN_INVALID);
7317 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7319 if (*tstate != NULL)
7321 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7324 if (notfound_failure != 0 && *lstate == NULL)
7325 return (CAM_PATH_INVALID);
7327 return (CAM_REQ_CMP);
7331 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7333 struct ahc_tmode_tstate *tstate;
7334 struct ahc_tmode_lstate *lstate;
7335 struct ccb_en_lun *cel;
7345 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7346 /*notfound_failure*/FALSE);
7348 if (status != CAM_REQ_CMP) {
7349 ccb->ccb_h.status = status;
7353 if (cam_sim_bus(sim) == 0)
7354 our_id = ahc->our_id;
7356 our_id = ahc->our_id_b;
7358 if (ccb->ccb_h.target_id != our_id) {
7360 * our_id represents our initiator ID, or
7361 * the ID of the first target to have an
7362 * enabled lun in target mode. There are
7363 * two cases that may preclude enabling a
7364 * target id other than our_id.
7366 * o our_id is for an active initiator role.
7367 * Since the hardware does not support
7368 * reselections to the initiator role at
7369 * anything other than our_id, and our_id
7370 * is used by the hardware to indicate the
7371 * ID to use for both select-out and
7372 * reselect-out operations, the only target
7373 * ID we can support in this mode is our_id.
7375 * o The MULTARGID feature is not available and
7376 * a previous target mode ID has been enabled.
7378 if ((ahc->features & AHC_MULTIROLE) != 0) {
7380 if ((ahc->features & AHC_MULTI_TID) != 0
7381 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7383 * Only allow additional targets if
7384 * the initiator role is disabled.
7385 * The hardware cannot handle a re-select-in
7386 * on the initiator id during a re-select-out
7387 * on a different target id.
7389 status = CAM_TID_INVALID;
7390 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7391 || ahc->enabled_luns > 0) {
7393 * Only allow our target id to change
7394 * if the initiator role is not configured
7395 * and there are no enabled luns which
7396 * are attached to the currently registered
7399 status = CAM_TID_INVALID;
7401 } else if ((ahc->features & AHC_MULTI_TID) == 0
7402 && ahc->enabled_luns > 0) {
7404 status = CAM_TID_INVALID;
7408 if (status != CAM_REQ_CMP) {
7409 ccb->ccb_h.status = status;
7414 * We now have an id that is valid.
7415 * If we aren't in target mode, switch modes.
7417 if ((ahc->flags & AHC_TARGETROLE) == 0
7418 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7420 ahc_flag saved_flags;
7422 printk("Configuring Target Mode\n");
7424 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7425 ccb->ccb_h.status = CAM_BUSY;
7426 ahc_unlock(ahc, &s);
7429 saved_flags = ahc->flags;
7430 ahc->flags |= AHC_TARGETROLE;
7431 if ((ahc->features & AHC_MULTIROLE) == 0)
7432 ahc->flags &= ~AHC_INITIATORROLE;
7434 error = ahc_loadseq(ahc);
7437 * Restore original configuration and notify
7438 * the caller that we cannot support target mode.
7439 * Since the adapter started out in this
7440 * configuration, the firmware load will succeed,
7441 * so there is no point in checking ahc_loadseq's
7444 ahc->flags = saved_flags;
7445 (void)ahc_loadseq(ahc);
7447 ahc_unlock(ahc, &s);
7448 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7452 ahc_unlock(ahc, &s);
7455 target = ccb->ccb_h.target_id;
7456 lun = ccb->ccb_h.target_lun;
7457 channel = SIM_CHANNEL(ahc, sim);
7458 target_mask = 0x01 << target;
7462 if (cel->enable != 0) {
7465 /* Are we already enabled?? */
7466 if (lstate != NULL) {
7467 xpt_print_path(ccb->ccb_h.path);
7468 printk("Lun already enabled\n");
7469 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7473 if (cel->grp6_len != 0
7474 || cel->grp7_len != 0) {
7476 * Don't (yet?) support vendor
7477 * specific commands.
7479 ccb->ccb_h.status = CAM_REQ_INVALID;
7480 printk("Non-zero Group Codes\n");
7486 * Setup our data structures.
7488 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7489 tstate = ahc_alloc_tstate(ahc, target, channel);
7490 if (tstate == NULL) {
7491 xpt_print_path(ccb->ccb_h.path);
7492 printk("Couldn't allocate tstate\n");
7493 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7497 lstate = kzalloc(sizeof(*lstate), GFP_ATOMIC);
7498 if (lstate == NULL) {
7499 xpt_print_path(ccb->ccb_h.path);
7500 printk("Couldn't allocate lstate\n");
7501 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7504 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7505 xpt_path_path_id(ccb->ccb_h.path),
7506 xpt_path_target_id(ccb->ccb_h.path),
7507 xpt_path_lun_id(ccb->ccb_h.path));
7508 if (status != CAM_REQ_CMP) {
7510 xpt_print_path(ccb->ccb_h.path);
7511 printk("Couldn't allocate path\n");
7512 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7515 SLIST_INIT(&lstate->accept_tios);
7516 SLIST_INIT(&lstate->immed_notifies);
7519 if (target != CAM_TARGET_WILDCARD) {
7520 tstate->enabled_luns[lun] = lstate;
7521 ahc->enabled_luns++;
7523 if ((ahc->features & AHC_MULTI_TID) != 0) {
7526 targid_mask = ahc_inb(ahc, TARGID)
7527 | (ahc_inb(ahc, TARGID + 1) << 8);
7529 targid_mask |= target_mask;
7530 ahc_outb(ahc, TARGID, targid_mask);
7531 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7533 ahc_update_scsiid(ahc, targid_mask);
7538 channel = SIM_CHANNEL(ahc, sim);
7539 our_id = SIM_SCSI_ID(ahc, sim);
7542 * This can only happen if selections
7545 if (target != our_id) {
7550 sblkctl = ahc_inb(ahc, SBLKCTL);
7551 cur_channel = (sblkctl & SELBUSB)
7553 if ((ahc->features & AHC_TWIN) == 0)
7555 swap = cur_channel != channel;
7557 ahc->our_id = target;
7559 ahc->our_id_b = target;
7562 ahc_outb(ahc, SBLKCTL,
7565 ahc_outb(ahc, SCSIID, target);
7568 ahc_outb(ahc, SBLKCTL, sblkctl);
7572 ahc->black_hole = lstate;
7573 /* Allow select-in operations */
7574 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7575 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7577 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7578 scsiseq = ahc_inb(ahc, SCSISEQ);
7580 ahc_outb(ahc, SCSISEQ, scsiseq);
7583 ahc_unlock(ahc, &s);
7584 ccb->ccb_h.status = CAM_REQ_CMP;
7585 xpt_print_path(ccb->ccb_h.path);
7586 printk("Lun now enabled for target mode\n");
7591 if (lstate == NULL) {
7592 ccb->ccb_h.status = CAM_LUN_INVALID;
7598 ccb->ccb_h.status = CAM_REQ_CMP;
7599 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7600 struct ccb_hdr *ccbh;
7602 ccbh = &scb->io_ctx->ccb_h;
7603 if (ccbh->func_code == XPT_CONT_TARGET_IO
7604 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7605 printk("CTIO pending\n");
7606 ccb->ccb_h.status = CAM_REQ_INVALID;
7607 ahc_unlock(ahc, &s);
7612 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7613 printk("ATIOs pending\n");
7614 ccb->ccb_h.status = CAM_REQ_INVALID;
7617 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7618 printk("INOTs pending\n");
7619 ccb->ccb_h.status = CAM_REQ_INVALID;
7622 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7623 ahc_unlock(ahc, &s);
7627 xpt_print_path(ccb->ccb_h.path);
7628 printk("Target mode disabled\n");
7629 xpt_free_path(lstate->path);
7633 /* Can we clean up the target too? */
7634 if (target != CAM_TARGET_WILDCARD) {
7635 tstate->enabled_luns[lun] = NULL;
7636 ahc->enabled_luns--;
7637 for (empty = 1, i = 0; i < 8; i++)
7638 if (tstate->enabled_luns[i] != NULL) {
7644 ahc_free_tstate(ahc, target, channel,
7646 if (ahc->features & AHC_MULTI_TID) {
7649 targid_mask = ahc_inb(ahc, TARGID)
7650 | (ahc_inb(ahc, TARGID + 1)
7653 targid_mask &= ~target_mask;
7654 ahc_outb(ahc, TARGID, targid_mask);
7655 ahc_outb(ahc, TARGID+1,
7656 (targid_mask >> 8));
7657 ahc_update_scsiid(ahc, targid_mask);
7662 ahc->black_hole = NULL;
7665 * We can't allow selections without
7666 * our black hole device.
7670 if (ahc->enabled_luns == 0) {
7671 /* Disallow select-in */
7674 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7676 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7677 scsiseq = ahc_inb(ahc, SCSISEQ);
7679 ahc_outb(ahc, SCSISEQ, scsiseq);
7681 if ((ahc->features & AHC_MULTIROLE) == 0) {
7682 printk("Configuring Initiator Mode\n");
7683 ahc->flags &= ~AHC_TARGETROLE;
7684 ahc->flags |= AHC_INITIATORROLE;
7686 * Returning to a configuration that
7687 * fit previously will always succeed.
7689 (void)ahc_loadseq(ahc);
7692 * Unpaused. The extra unpause
7693 * that follows is harmless.
7698 ahc_unlock(ahc, &s);
7703 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7708 if ((ahc->features & AHC_MULTI_TID) == 0)
7709 panic("ahc_update_scsiid called on non-multitid unit\n");
7712 * Since we will rely on the TARGID mask
7713 * for selection enables, ensure that OID
7714 * in SCSIID is not set to some other ID
7715 * that we don't want to allow selections on.
7717 if ((ahc->features & AHC_ULTRA2) != 0)
7718 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7720 scsiid = ahc_inb(ahc, SCSIID);
7721 scsiid_mask = 0x1 << (scsiid & OID);
7722 if ((targid_mask & scsiid_mask) == 0) {
7725 /* ffs counts from 1 */
7726 our_id = ffs(targid_mask);
7728 our_id = ahc->our_id;
7734 if ((ahc->features & AHC_ULTRA2) != 0)
7735 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7737 ahc_outb(ahc, SCSIID, scsiid);
7741 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7743 struct target_cmd *cmd;
7746 * If the card supports auto-access pause,
7747 * we can access the card directly regardless
7748 * of whether it is paused or not.
7750 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7753 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7754 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7757 * Only advance through the queue if we
7758 * have the resources to process the command.
7760 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7764 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7765 ahc->shared_data_dmamap,
7766 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7767 sizeof(struct target_cmd),
7768 BUS_DMASYNC_PREREAD);
7769 ahc->tqinfifonext++;
7772 * Lazily update our position in the target mode incoming
7773 * command queue as seen by the sequencer.
7775 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7776 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7779 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7780 hs_mailbox &= ~HOST_TQINPOS;
7781 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7782 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7786 ahc_outb(ahc, KERNEL_TQINPOS,
7787 ahc->tqinfifonext & HOST_TQINPOS);
7796 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7798 struct ahc_tmode_tstate *tstate;
7799 struct ahc_tmode_lstate *lstate;
7800 struct ccb_accept_tio *atio;
7806 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7807 target = SCSIID_OUR_ID(cmd->scsiid);
7808 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7811 tstate = ahc->enabled_targets[target];
7814 lstate = tstate->enabled_luns[lun];
7817 * Commands for disabled luns go to the black hole driver.
7820 lstate = ahc->black_hole;
7822 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7824 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7826 * Wait for more ATIOs from the peripheral driver for this lun.
7829 printk("%s: ATIOs exhausted\n", ahc_name(ahc));
7832 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7834 printk("Incoming command from %d for %d:%d%s\n",
7835 initiator, target, lun,
7836 lstate == ahc->black_hole ? "(Black Holed)" : "");
7838 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7840 if (lstate == ahc->black_hole) {
7841 /* Fill in the wildcards */
7842 atio->ccb_h.target_id = target;
7843 atio->ccb_h.target_lun = lun;
7847 * Package it up and send it off to
7848 * whomever has this lun enabled.
7850 atio->sense_len = 0;
7851 atio->init_id = initiator;
7852 if (byte[0] != 0xFF) {
7853 /* Tag was included */
7854 atio->tag_action = *byte++;
7855 atio->tag_id = *byte++;
7856 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7858 atio->ccb_h.flags = 0;
7862 /* Okay. Now determine the cdb size based on the command code */
7863 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7879 /* Only copy the opcode. */
7881 printk("Reserved or VU command code type encountered\n");
7885 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7887 atio->ccb_h.status |= CAM_CDB_RECVD;
7889 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7891 * We weren't allowed to disconnect.
7892 * We're hanging on the bus until a
7893 * continue target I/O comes in response
7894 * to this accept tio.
7897 printk("Received Immediate Command %d:%d:%d - %p\n",
7898 initiator, target, lun, ahc->pending_device);
7900 ahc->pending_device = lstate;
7901 ahc_freeze_ccb((union ccb *)atio);
7902 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7904 xpt_done((union ccb*)atio);