2 * An i2c driver for the Xicor/Intersil X1205 RTC
3 * Copyright 2004 Karen Spearel
4 * Copyright 2005 Alessandro Zummo
6 * please send all reports to:
7 * Karen Spearel <kas111 at gmail dot com>
8 * Alessandro Zummo <a.zummo@towertech.it>
10 * based on a lot of other RTC drivers.
12 * Information and datasheet:
13 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/i2c.h>
21 #include <linux/bcd.h>
22 #include <linux/rtc.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/bitops.h>
27 #define DRV_VERSION "1.0.8"
29 /* offsets into CCR area */
40 #define X1205_REG_SR 0x3F /* status register */
41 #define X1205_REG_Y2K 0x37
42 #define X1205_REG_DW 0x36
43 #define X1205_REG_YR 0x35
44 #define X1205_REG_MO 0x34
45 #define X1205_REG_DT 0x33
46 #define X1205_REG_HR 0x32
47 #define X1205_REG_MN 0x31
48 #define X1205_REG_SC 0x30
49 #define X1205_REG_DTR 0x13
50 #define X1205_REG_ATR 0x12
51 #define X1205_REG_INT 0x11
52 #define X1205_REG_0 0x10
53 #define X1205_REG_Y2K1 0x0F
54 #define X1205_REG_DWA1 0x0E
55 #define X1205_REG_YRA1 0x0D
56 #define X1205_REG_MOA1 0x0C
57 #define X1205_REG_DTA1 0x0B
58 #define X1205_REG_HRA1 0x0A
59 #define X1205_REG_MNA1 0x09
60 #define X1205_REG_SCA1 0x08
61 #define X1205_REG_Y2K0 0x07
62 #define X1205_REG_DWA0 0x06
63 #define X1205_REG_YRA0 0x05
64 #define X1205_REG_MOA0 0x04
65 #define X1205_REG_DTA0 0x03
66 #define X1205_REG_HRA0 0x02
67 #define X1205_REG_MNA0 0x01
68 #define X1205_REG_SCA0 0x00
70 #define X1205_CCR_BASE 0x30 /* Base address of CCR */
71 #define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
73 #define X1205_SR_RTCF 0x01 /* Clock failure */
74 #define X1205_SR_WEL 0x02 /* Write Enable Latch */
75 #define X1205_SR_RWEL 0x04 /* Register Write Enable */
76 #define X1205_SR_AL0 0x20 /* Alarm 0 match */
78 #define X1205_DTR_DTR0 0x01
79 #define X1205_DTR_DTR1 0x02
80 #define X1205_DTR_DTR2 0x04
82 #define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
84 #define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
86 static struct i2c_driver x1205_driver;
89 * In the routines that deal directly with the x1205 hardware, we use
90 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
91 * Epoch is initialized as 2000. Time is set to UTC.
93 static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
94 unsigned char reg_base)
96 unsigned char dt_addr[2] = { 0, reg_base };
100 struct i2c_msg msgs[] = {
101 {/* setup read ptr */
102 .addr = client->addr,
107 .addr = client->addr,
114 /* read date registers */
115 if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
116 dev_err(&client->dev, "%s: read error\n", __func__);
120 dev_dbg(&client->dev,
121 "%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
122 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
124 buf[0], buf[1], buf[2], buf[3],
125 buf[4], buf[5], buf[6], buf[7]);
127 /* Mask out the enable bits if these are alarm registers */
128 if (reg_base < X1205_CCR_BASE)
129 for (i = 0; i <= 4; i++)
132 tm->tm_sec = bcd2bin(buf[CCR_SEC]);
133 tm->tm_min = bcd2bin(buf[CCR_MIN]);
134 tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
135 tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
136 tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
137 tm->tm_year = bcd2bin(buf[CCR_YEAR])
138 + (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
139 tm->tm_wday = buf[CCR_WDAY];
141 dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
142 "mday=%d, mon=%d, year=%d, wday=%d\n",
144 tm->tm_sec, tm->tm_min, tm->tm_hour,
145 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
150 static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
152 static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
154 struct i2c_msg msgs[] = {
155 { /* setup read ptr */
156 .addr = client->addr,
161 .addr = client->addr,
168 /* read status register */
169 if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
170 dev_err(&client->dev, "%s: read error\n", __func__);
177 static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
178 u8 reg_base, unsigned char alm_enable)
181 unsigned char rdata[10] = { 0, reg_base };
182 unsigned char *buf = rdata + 2;
184 static const unsigned char wel[3] = { 0, X1205_REG_SR,
187 static const unsigned char rwel[3] = { 0, X1205_REG_SR,
188 X1205_SR_WEL | X1205_SR_RWEL };
190 static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
192 dev_dbg(&client->dev,
193 "%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
194 __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
195 tm->tm_mon, tm->tm_year, tm->tm_wday);
197 buf[CCR_SEC] = bin2bcd(tm->tm_sec);
198 buf[CCR_MIN] = bin2bcd(tm->tm_min);
200 /* set hour and 24hr bit */
201 buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
203 buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
206 buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
208 /* year, since the rtc epoch*/
209 buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
210 buf[CCR_WDAY] = tm->tm_wday & 0x07;
211 buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
213 /* If writing alarm registers, set compare bits on registers 0-4 */
214 if (reg_base < X1205_CCR_BASE)
215 for (i = 0; i <= 4; i++)
218 /* this sequence is required to unlock the chip */
219 xfer = i2c_master_send(client, wel, 3);
221 dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
225 xfer = i2c_master_send(client, rwel, 3);
227 dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
231 xfer = i2c_master_send(client, rdata, sizeof(rdata));
232 if (xfer != sizeof(rdata)) {
233 dev_err(&client->dev,
234 "%s: result=%d addr=%02x, data=%02x\n",
236 xfer, rdata[1], rdata[2]);
240 /* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
241 if (reg_base < X1205_CCR_BASE) {
242 unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
246 /* ...and set or clear the AL0E bit in the INT register */
248 /* Need to set RWEL again as the write has cleared it */
249 xfer = i2c_master_send(client, rwel, 3);
251 dev_err(&client->dev,
252 "%s: aloe rwel - %d\n",
259 al0e[2] = X1205_INT_AL0E;
261 xfer = i2c_master_send(client, al0e, 3);
263 dev_err(&client->dev,
270 /* and wait 10msec again for this write to complete */
274 /* disable further writes */
275 xfer = i2c_master_send(client, diswe, 3);
277 dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
284 static int x1205_fix_osc(struct i2c_client *client)
289 memset(&tm, 0, sizeof(tm));
291 err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
293 dev_err(&client->dev, "unable to restart the oscillator\n");
298 static int x1205_get_dtrim(struct i2c_client *client, int *trim)
301 static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
303 struct i2c_msg msgs[] = {
304 { /* setup read ptr */
305 .addr = client->addr,
310 .addr = client->addr,
317 /* read dtr register */
318 if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
319 dev_err(&client->dev, "%s: read error\n", __func__);
323 dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
327 if (dtr & X1205_DTR_DTR0)
330 if (dtr & X1205_DTR_DTR1)
333 if (dtr & X1205_DTR_DTR2)
339 static int x1205_get_atrim(struct i2c_client *client, int *trim)
342 static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
344 struct i2c_msg msgs[] = {
345 {/* setup read ptr */
346 .addr = client->addr,
351 .addr = client->addr,
358 /* read atr register */
359 if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
360 dev_err(&client->dev, "%s: read error\n", __func__);
364 dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
366 /* atr is a two's complement value on 6 bits,
367 * perform sign extension. The formula is
368 * Catr = (atr * 0.25pF) + 11.00pF.
370 atr = sign_extend32(atr, 5);
372 dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
374 *trim = (atr * 250) + 11000;
376 dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
382 unsigned char reg, mask, min, max;
385 static int x1205_validate_client(struct i2c_client *client)
389 /* Probe array. We will read the register at the specified
390 * address and check if the given bits are zero.
392 static const unsigned char probe_zero_pattern[] = {
401 static const struct x1205_limit probe_limits_pattern[] = {
402 /* register, mask, min, max */
403 { X1205_REG_Y2K, 0xFF, 19, 20 },
404 { X1205_REG_DW, 0xFF, 0, 6 },
405 { X1205_REG_YR, 0xFF, 0, 99 },
406 { X1205_REG_MO, 0xFF, 0, 12 },
407 { X1205_REG_DT, 0xFF, 0, 31 },
408 { X1205_REG_HR, 0x7F, 0, 23 },
409 { X1205_REG_MN, 0xFF, 0, 59 },
410 { X1205_REG_SC, 0xFF, 0, 59 },
411 { X1205_REG_Y2K1, 0xFF, 19, 20 },
412 { X1205_REG_Y2K0, 0xFF, 19, 20 },
415 /* check that registers have bits a 0 where expected */
416 for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
419 unsigned char addr[2] = { 0, probe_zero_pattern[i] };
421 struct i2c_msg msgs[2] = {
423 .addr = client->addr,
428 .addr = client->addr,
435 xfer = i2c_transfer(client->adapter, msgs, 2);
437 dev_err(&client->dev,
438 "%s: could not read register %x\n",
439 __func__, probe_zero_pattern[i]);
444 if ((buf & probe_zero_pattern[i+1]) != 0) {
445 dev_err(&client->dev,
446 "%s: register=%02x, zero pattern=%d, value=%x\n",
447 __func__, probe_zero_pattern[i], i, buf);
453 /* check limits (only registers with bcd values) */
454 for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
455 unsigned char reg, value;
457 unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
459 struct i2c_msg msgs[2] = {
461 .addr = client->addr,
466 .addr = client->addr,
473 xfer = i2c_transfer(client->adapter, msgs, 2);
475 dev_err(&client->dev,
476 "%s: could not read register %x\n",
477 __func__, probe_limits_pattern[i].reg);
482 value = bcd2bin(reg & probe_limits_pattern[i].mask);
484 if (value > probe_limits_pattern[i].max ||
485 value < probe_limits_pattern[i].min) {
486 dev_dbg(&client->dev,
487 "%s: register=%x, lim pattern=%d, value=%d\n",
488 __func__, probe_limits_pattern[i].reg,
498 static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
501 unsigned char intreg, status;
502 static unsigned char int_addr[2] = { 0, X1205_REG_INT };
503 struct i2c_client *client = to_i2c_client(dev);
504 struct i2c_msg msgs[] = {
505 { /* setup read ptr */
506 .addr = client->addr,
510 {/* read INT register */
512 .addr = client->addr,
519 /* read interrupt register and status register */
520 if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
521 dev_err(&client->dev, "%s: read error\n", __func__);
524 err = x1205_get_status(client, &status);
526 alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
527 alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
528 err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
533 static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
535 return x1205_set_datetime(to_i2c_client(dev),
536 &alrm->time, X1205_ALM0_BASE, alrm->enabled);
539 static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
541 return x1205_get_datetime(to_i2c_client(dev),
545 static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
547 return x1205_set_datetime(to_i2c_client(dev),
548 tm, X1205_CCR_BASE, 0);
551 static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
553 int err, dtrim, atrim;
555 err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
557 seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
559 err = x1205_get_atrim(to_i2c_client(dev), &atrim);
561 seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
562 atrim / 1000, atrim % 1000);
566 static const struct rtc_class_ops x1205_rtc_ops = {
567 .proc = x1205_rtc_proc,
568 .read_time = x1205_rtc_read_time,
569 .set_time = x1205_rtc_set_time,
570 .read_alarm = x1205_rtc_read_alarm,
571 .set_alarm = x1205_rtc_set_alarm,
574 static ssize_t x1205_sysfs_show_atrim(struct device *dev,
575 struct device_attribute *attr, char *buf)
579 err = x1205_get_atrim(to_i2c_client(dev), &atrim);
583 return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
585 static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
587 static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
588 struct device_attribute *attr, char *buf)
592 err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
596 return sprintf(buf, "%d ppm\n", dtrim);
598 static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
600 static int x1205_sysfs_register(struct device *dev)
604 err = device_create_file(dev, &dev_attr_atrim);
608 err = device_create_file(dev, &dev_attr_dtrim);
610 device_remove_file(dev, &dev_attr_atrim);
615 static void x1205_sysfs_unregister(struct device *dev)
617 device_remove_file(dev, &dev_attr_atrim);
618 device_remove_file(dev, &dev_attr_dtrim);
622 static int x1205_probe(struct i2c_client *client,
623 const struct i2c_device_id *id)
627 struct rtc_device *rtc;
629 dev_dbg(&client->dev, "%s\n", __func__);
631 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
634 if (x1205_validate_client(client) < 0)
637 dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");
639 rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
640 &x1205_rtc_ops, THIS_MODULE);
645 i2c_set_clientdata(client, rtc);
647 /* Check for power failures and eventually enable the osc */
648 err = x1205_get_status(client, &sr);
650 if (sr & X1205_SR_RTCF) {
651 dev_err(&client->dev,
652 "power failure detected, "
653 "please set the clock\n");
655 x1205_fix_osc(client);
658 dev_err(&client->dev, "couldn't read status\n");
661 err = x1205_sysfs_register(&client->dev);
663 dev_err(&client->dev, "Unable to create sysfs entries\n");
668 static int x1205_remove(struct i2c_client *client)
670 x1205_sysfs_unregister(&client->dev);
674 static const struct i2c_device_id x1205_id[] = {
678 MODULE_DEVICE_TABLE(i2c, x1205_id);
680 static struct i2c_driver x1205_driver = {
684 .probe = x1205_probe,
685 .remove = x1205_remove,
686 .id_table = x1205_id,
689 module_i2c_driver(x1205_driver);
692 "Karen Spearel <kas111 at gmail dot com>, "
693 "Alessandro Zummo <a.zummo@towertech.it>");
694 MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
695 MODULE_LICENSE("GPL");
696 MODULE_VERSION(DRV_VERSION);