1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
5 #include <linux/init.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_wakeirq.h>
13 #include <linux/rtc.h>
14 #include <linux/clk.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/regmap.h>
18 #define SNVS_LPREGISTER_OFFSET 0x34
20 /* These register offsets are relative to LP (Low Power) range */
21 #define SNVS_LPCR 0x04
22 #define SNVS_LPSR 0x18
23 #define SNVS_LPSRTCMR 0x1c
24 #define SNVS_LPSRTCLR 0x20
25 #define SNVS_LPTAR 0x24
26 #define SNVS_LPPGDR 0x30
28 #define SNVS_LPCR_SRTC_ENV (1 << 0)
29 #define SNVS_LPCR_LPTA_EN (1 << 1)
30 #define SNVS_LPCR_LPWUI_EN (1 << 3)
31 #define SNVS_LPSR_LPTA (1 << 0)
33 #define SNVS_LPPGDR_INIT 0x41736166
34 #define CNTR_TO_SECS_SH 15
36 /* The maximum RTC clock cycles that are allowed to pass between two
37 * consecutive clock counter register reads. If the values are corrupted a
38 * bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
39 * we end at 10ms which should be enough for most cases. If it once takes
40 * longer than expected we do a retry.
42 #define MAX_RTC_READ_DIFF_CYCLES 320
44 struct snvs_rtc_data {
45 struct rtc_device *rtc;
46 struct regmap *regmap;
52 /* Read 64 bit timer register, which could be in inconsistent state */
53 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
57 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
58 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
59 return (u64)msb << 32 | lsb;
62 /* Read the secure real time counter, taking care to deal with the cases of the
63 * counter updating while being read.
65 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
69 unsigned int timeout = 100;
71 /* As expected, the registers might update between the read of the LSB
72 * reg and the MSB reg. It's also possible that one register might be
73 * in partially modified state as well.
75 read1 = rtc_read_lpsrt(data);
78 read1 = rtc_read_lpsrt(data);
80 } while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
82 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
84 /* Convert 47-bit counter to 32-bit raw second count */
85 return (u32) (read1 >> CNTR_TO_SECS_SH);
88 /* Just read the lsb from the counter, dealing with inconsistent state */
89 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
93 unsigned int timeout = 100;
95 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
98 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
99 diff = count1 - count2;
100 } while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
102 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
110 static int rtc_write_sync_lp(struct snvs_rtc_data *data)
114 unsigned int timeout = 1000;
117 ret = rtc_read_lp_counter_lsb(data, &count1);
121 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
123 ret = rtc_read_lp_counter_lsb(data, &count2);
126 elapsed = count2 - count1; /* wrap around _is_ handled! */
127 } while (elapsed < 3 && --timeout);
129 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
135 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
140 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
141 enable ? SNVS_LPCR_SRTC_ENV : 0);
144 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
147 if (lpcr & SNVS_LPCR_SRTC_ENV)
150 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
161 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
163 struct snvs_rtc_data *data = dev_get_drvdata(dev);
164 unsigned long time = rtc_read_lp_counter(data);
166 rtc_time64_to_tm(time, tm);
171 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
173 struct snvs_rtc_data *data = dev_get_drvdata(dev);
174 unsigned long time = rtc_tm_to_time64(tm);
177 /* Disable RTC first */
178 ret = snvs_rtc_enable(data, false);
182 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
183 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
184 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
186 /* Enable RTC again */
187 ret = snvs_rtc_enable(data, true);
192 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
194 struct snvs_rtc_data *data = dev_get_drvdata(dev);
197 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
198 rtc_time64_to_tm(lptar, &alrm->time);
200 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
201 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
206 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
208 struct snvs_rtc_data *data = dev_get_drvdata(dev);
210 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
211 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
212 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
214 return rtc_write_sync_lp(data);
217 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
219 struct snvs_rtc_data *data = dev_get_drvdata(dev);
220 unsigned long time = rtc_tm_to_time64(&alrm->time);
223 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
224 ret = rtc_write_sync_lp(data);
227 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
229 /* Clear alarm interrupt status bit */
230 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
232 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
235 static const struct rtc_class_ops snvs_rtc_ops = {
236 .read_time = snvs_rtc_read_time,
237 .set_time = snvs_rtc_set_time,
238 .read_alarm = snvs_rtc_read_alarm,
239 .set_alarm = snvs_rtc_set_alarm,
240 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
243 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
245 struct device *dev = dev_id;
246 struct snvs_rtc_data *data = dev_get_drvdata(dev);
251 clk_enable(data->clk);
253 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
255 if (lpsr & SNVS_LPSR_LPTA) {
256 events |= (RTC_AF | RTC_IRQF);
258 /* RTC alarm should be one-shot */
259 snvs_rtc_alarm_irq_enable(dev, 0);
261 rtc_update_irq(data->rtc, 1, events);
264 /* clear interrupt status */
265 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
268 clk_disable(data->clk);
270 return events ? IRQ_HANDLED : IRQ_NONE;
273 static const struct regmap_config snvs_rtc_config = {
279 static int snvs_rtc_probe(struct platform_device *pdev)
281 struct snvs_rtc_data *data;
285 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
289 data->rtc = devm_rtc_allocate_device(&pdev->dev);
290 if (IS_ERR(data->rtc))
291 return PTR_ERR(data->rtc);
293 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
295 if (IS_ERR(data->regmap)) {
296 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
298 mmio = devm_platform_ioremap_resource(pdev, 0);
300 return PTR_ERR(mmio);
302 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
304 data->offset = SNVS_LPREGISTER_OFFSET;
305 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
308 if (IS_ERR(data->regmap)) {
309 dev_err(&pdev->dev, "Can't find snvs syscon\n");
313 data->irq = platform_get_irq(pdev, 0);
317 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
318 if (IS_ERR(data->clk)) {
321 ret = clk_prepare_enable(data->clk);
324 "Could not prepare or enable the snvs clock\n");
329 platform_set_drvdata(pdev, data);
331 /* Initialize glitch detect */
332 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
334 /* Clear interrupt status */
335 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
338 ret = snvs_rtc_enable(data, true);
340 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
341 goto error_rtc_device_register;
344 device_init_wakeup(&pdev->dev, true);
345 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
347 dev_err(&pdev->dev, "failed to enable irq wake\n");
349 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
350 IRQF_SHARED, "rtc alarm", &pdev->dev);
352 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
354 goto error_rtc_device_register;
357 data->rtc->ops = &snvs_rtc_ops;
358 data->rtc->range_max = U32_MAX;
359 ret = rtc_register_device(data->rtc);
361 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
362 goto error_rtc_device_register;
367 error_rtc_device_register:
369 clk_disable_unprepare(data->clk);
374 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
376 struct snvs_rtc_data *data = dev_get_drvdata(dev);
379 clk_disable_unprepare(data->clk);
384 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
386 struct snvs_rtc_data *data = dev_get_drvdata(dev);
389 return clk_prepare_enable(data->clk);
394 static const struct dev_pm_ops snvs_rtc_pm_ops = {
395 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
398 static const struct of_device_id snvs_dt_ids[] = {
399 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
402 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
404 static struct platform_driver snvs_rtc_driver = {
407 .pm = &snvs_rtc_pm_ops,
408 .of_match_table = snvs_dt_ids,
410 .probe = snvs_rtc_probe,
412 module_platform_driver(snvs_rtc_driver);
414 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
415 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
416 MODULE_LICENSE("GPL");