drivers/rtc/rtc-ds1307.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
   4  *
   5  *  Copyright (C) 2005 James Chapman (ds1337 core)
   6  *  Copyright (C) 2006 David Brownell
   7  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
   8  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
   9  */
  10
  11 #include <linux/acpi.h>
  12 #include <linux/bcd.h>
  13 #include <linux/i2c.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/rtc/ds1307.h>
  18 #include <linux/rtc.h>
  19 #include <linux/slab.h>
  20 #include <linux/string.h>
  21 #include <linux/hwmon.h>
  22 #include <linux/hwmon-sysfs.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25
  26 /*
  27  * We can't determine type by probing, but if we expect pre-Linux code
  28  * to have set the chip up as a clock (turning on the oscillator and
  29  * setting the date and time), Linux can ignore the non-clock features.
  30  * That's a natural job for a factory or repair bench.
  31  */
  32 enum ds_type {
  33         ds_1307,
  34         ds_1308,
  35         ds_1337,
  36         ds_1338,
  37         ds_1339,
  38         ds_1340,
  39         ds_1341,
  40         ds_1388,
  41         ds_3231,
  42         m41t0,
  43         m41t00,
  44         m41t11,
  45         mcp794xx,
  46         rx_8025,
  47         rx_8130,
  48         last_ds_type /* always last */
  49         /* rs5c372 too?  different address... */
  50 };
  51
  52 /* RTC registers don't differ much, except for the century flag */
  53 #define DS1307_REG_SECS         0x00    /* 00-59 */
  54 #       define DS1307_BIT_CH            0x80
  55 #       define DS1340_BIT_nEOSC         0x80
  56 #       define MCP794XX_BIT_ST          0x80
  57 #define DS1307_REG_MIN          0x01    /* 00-59 */
  58 #       define M41T0_BIT_OF             0x80
  59 #define DS1307_REG_HOUR         0x02    /* 00-23, or 1-12{am,pm} */
  60 #       define DS1307_BIT_12HR          0x40    /* in REG_HOUR */
  61 #       define DS1307_BIT_PM            0x20    /* in REG_HOUR */
  62 #       define DS1340_BIT_CENTURY_EN    0x80    /* in REG_HOUR */
  63 #       define DS1340_BIT_CENTURY       0x40    /* in REG_HOUR */
  64 #define DS1307_REG_WDAY         0x03    /* 01-07 */
  65 #       define MCP794XX_BIT_VBATEN      0x08
  66 #define DS1307_REG_MDAY         0x04    /* 01-31 */
  67 #define DS1307_REG_MONTH        0x05    /* 01-12 */
  68 #       define DS1337_BIT_CENTURY       0x80    /* in REG_MONTH */
  69 #define DS1307_REG_YEAR         0x06    /* 00-99 */
  70
  71 /*
  72  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  73  * start at 7, and they differ a LOT. Only control and status matter for
  74  * basic RTC date and time functionality; be careful using them.
  75  */
  76 #define DS1307_REG_CONTROL      0x07            /* or ds1338 */
  77 #       define DS1307_BIT_OUT           0x80
  78 #       define DS1338_BIT_OSF           0x20
  79 #       define DS1307_BIT_SQWE          0x10
  80 #       define DS1307_BIT_RS1           0x02
  81 #       define DS1307_BIT_RS0           0x01
  82 #define DS1337_REG_CONTROL      0x0e
  83 #       define DS1337_BIT_nEOSC         0x80
  84 #       define DS1339_BIT_BBSQI         0x20
  85 #       define DS3231_BIT_BBSQW         0x40 /* same as BBSQI */
  86 #       define DS1337_BIT_RS2           0x10
  87 #       define DS1337_BIT_RS1           0x08
  88 #       define DS1337_BIT_INTCN         0x04
  89 #       define DS1337_BIT_A2IE          0x02
  90 #       define DS1337_BIT_A1IE          0x01
  91 #define DS1340_REG_CONTROL      0x07
  92 #       define DS1340_BIT_OUT           0x80
  93 #       define DS1340_BIT_FT            0x40
  94 #       define DS1340_BIT_CALIB_SIGN    0x20
  95 #       define DS1340_M_CALIBRATION     0x1f
  96 #define DS1340_REG_FLAG         0x09
  97 #       define DS1340_BIT_OSF           0x80
  98 #define DS1337_REG_STATUS       0x0f
  99 #       define DS1337_BIT_OSF           0x80
 100 #       define DS3231_BIT_EN32KHZ       0x08
 101 #       define DS1337_BIT_A2I           0x02
 102 #       define DS1337_BIT_A1I           0x01
 103 #define DS1339_REG_ALARM1_SECS  0x07
 104
 105 #define DS13XX_TRICKLE_CHARGER_MAGIC    0xa0
 106
 107 #define RX8025_REG_CTRL1        0x0e
 108 #       define RX8025_BIT_2412          0x20
 109 #define RX8025_REG_CTRL2        0x0f
 110 #       define RX8025_BIT_PON           0x10
 111 #       define RX8025_BIT_VDET          0x40
 112 #       define RX8025_BIT_XST           0x20
 113
 114 #define RX8130_REG_ALARM_MIN            0x17
 115 #define RX8130_REG_ALARM_HOUR           0x18
 116 #define RX8130_REG_ALARM_WEEK_OR_DAY    0x19
 117 #define RX8130_REG_EXTENSION            0x1c
 118 #define RX8130_REG_EXTENSION_WADA       BIT(3)
 119 #define RX8130_REG_FLAG                 0x1d
 120 #define RX8130_REG_FLAG_VLF             BIT(1)
 121 #define RX8130_REG_FLAG_AF              BIT(3)
 122 #define RX8130_REG_CONTROL0             0x1e
 123 #define RX8130_REG_CONTROL0_AIE         BIT(3)
 124
 125 #define MCP794XX_REG_CONTROL            0x07
 126 #       define MCP794XX_BIT_ALM0_EN     0x10
 127 #       define MCP794XX_BIT_ALM1_EN     0x20
 128 #define MCP794XX_REG_ALARM0_BASE        0x0a
 129 #define MCP794XX_REG_ALARM0_CTRL        0x0d
 130 #define MCP794XX_REG_ALARM1_BASE        0x11
 131 #define MCP794XX_REG_ALARM1_CTRL        0x14
 132 #       define MCP794XX_BIT_ALMX_IF     BIT(3)
 133 #       define MCP794XX_BIT_ALMX_C0     BIT(4)
 134 #       define MCP794XX_BIT_ALMX_C1     BIT(5)
 135 #       define MCP794XX_BIT_ALMX_C2     BIT(6)
 136 #       define MCP794XX_BIT_ALMX_POL    BIT(7)
 137 #       define MCP794XX_MSK_ALMX_MATCH  (MCP794XX_BIT_ALMX_C0 | \
 138                                          MCP794XX_BIT_ALMX_C1 | \
 139                                          MCP794XX_BIT_ALMX_C2)
 140
 141 #define M41TXX_REG_CONTROL      0x07
 142 #       define M41TXX_BIT_OUT           BIT(7)
 143 #       define M41TXX_BIT_FT            BIT(6)
 144 #       define M41TXX_BIT_CALIB_SIGN    BIT(5)
 145 #       define M41TXX_M_CALIBRATION     GENMASK(4, 0)
 146
 147 /* negative offset step is -2.034ppm */
 148 #define M41TXX_NEG_OFFSET_STEP_PPB      2034
 149 /* positive offset step is +4.068ppm */
 150 #define M41TXX_POS_OFFSET_STEP_PPB      4068
 151 /* Min and max values supported with 'offset' interface by M41TXX */
 152 #define M41TXX_MIN_OFFSET       ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
 153 #define M41TXX_MAX_OFFSET       ((31) * M41TXX_POS_OFFSET_STEP_PPB)
 154
 155 struct ds1307 {
 156         enum ds_type            type;
 157         unsigned long           flags;
 158 #define HAS_NVRAM       0               /* bit 0 == sysfs file active */
 159 #define HAS_ALARM       1               /* bit 1 == irq claimed */
 160         struct device           *dev;
 161         struct regmap           *regmap;
 162         const char              *name;
 163         struct rtc_device       *rtc;
 164 #ifdef CONFIG_COMMON_CLK
 165         struct clk_hw           clks[2];
 166 #endif
 167 };
 168
 169 struct chip_desc {
 170         unsigned                alarm:1;
 171         u16                     nvram_offset;
 172         u16                     nvram_size;
 173         u8                      offset; /* register's offset */
 174         u8                      century_reg;
 175         u8                      century_enable_bit;
 176         u8                      century_bit;
 177         u8                      bbsqi_bit;
 178         irq_handler_t           irq_handler;
 179         const struct rtc_class_ops *rtc_ops;
 180         u16                     trickle_charger_reg;
 181         u8                      (*do_trickle_setup)(struct ds1307 *, u32,
 182                                                     bool);
 183 };
 184
 185 static const struct chip_desc chips[last_ds_type];
 186
 187 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
 188 {
 189         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 190         int             tmp, ret;
 191         const struct chip_desc *chip = &chips[ds1307->type];
 192         u8 regs[7];
 193
 194         if (ds1307->type == rx_8130) {
 195                 unsigned int regflag;
 196                 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
 197                 if (ret) {
 198                         dev_err(dev, "%s error %d\n", "read", ret);
 199                         return ret;
 200                 }
 201
 202                 if (regflag & RX8130_REG_FLAG_VLF) {
 203                         dev_warn_once(dev, "oscillator failed, set time!\n");
 204                         return -EINVAL;
 205                 }
 206         }
 207
 208         /* read the RTC date and time registers all at once */
 209         ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
 210                                sizeof(regs));
 211         if (ret) {
 212                 dev_err(dev, "%s error %d\n", "read", ret);
 213                 return ret;
 214         }
 215
 216         dev_dbg(dev, "%s: %7ph\n", "read", regs);
 217
 218         /* if oscillator fail bit is set, no data can be trusted */
 219         if (ds1307->type == m41t0 &&
 220             regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
 221                 dev_warn_once(dev, "oscillator failed, set time!\n");
 222                 return -EINVAL;
 223         }
 224
 225         tmp = regs[DS1307_REG_SECS];
 226         switch (ds1307->type) {
 227         case ds_1307:
 228         case m41t0:
 229         case m41t00:
 230         case m41t11:
 231                 if (tmp & DS1307_BIT_CH)
 232                         return -EINVAL;
 233                 break;
 234         case ds_1308:
 235         case ds_1338:
 236                 if (tmp & DS1307_BIT_CH)
 237                         return -EINVAL;
 238
 239                 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
 240                 if (ret)
 241                         return ret;
 242                 if (tmp & DS1338_BIT_OSF)
 243                         return -EINVAL;
 244                 break;
 245         case ds_1340:
 246                 if (tmp & DS1340_BIT_nEOSC)
 247                         return -EINVAL;
 248
 249                 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
 250                 if (ret)
 251                         return ret;
 252                 if (tmp & DS1340_BIT_OSF)
 253                         return -EINVAL;
 254                 break;
 255         case mcp794xx:
 256                 if (!(tmp & MCP794XX_BIT_ST))
 257                         return -EINVAL;
 258
 259                 break;
 260         default:
 261                 break;
 262         }
 263
 264         t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
 265         t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
 266         tmp = regs[DS1307_REG_HOUR] & 0x3f;
 267         t->tm_hour = bcd2bin(tmp);
 268         /* rx8130 is bit position, not BCD */
 269         if (ds1307->type == rx_8130)
 270                 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
 271         else
 272                 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
 273         t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
 274         tmp = regs[DS1307_REG_MONTH] & 0x1f;
 275         t->tm_mon = bcd2bin(tmp) - 1;
 276         t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
 277
 278         if (regs[chip->century_reg] & chip->century_bit &&
 279             IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
 280                 t->tm_year += 100;
 281
 282         dev_dbg(dev, "%s secs=%d, mins=%d, "
 283                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 284                 "read", t->tm_sec, t->tm_min,
 285                 t->tm_hour, t->tm_mday,
 286                 t->tm_mon, t->tm_year, t->tm_wday);
 287
 288         return 0;
 289 }
 290
 291 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
 292 {
 293         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 294         const struct chip_desc *chip = &chips[ds1307->type];
 295         int             result;
 296         int             tmp;
 297         u8              regs[7];
 298
 299         dev_dbg(dev, "%s secs=%d, mins=%d, "
 300                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 301                 "write", t->tm_sec, t->tm_min,
 302                 t->tm_hour, t->tm_mday,
 303                 t->tm_mon, t->tm_year, t->tm_wday);
 304
 305         if (t->tm_year < 100)
 306                 return -EINVAL;
 307
 308 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
 309         if (t->tm_year > (chip->century_bit ? 299 : 199))
 310                 return -EINVAL;
 311 #else
 312         if (t->tm_year > 199)
 313                 return -EINVAL;
 314 #endif
 315
 316         regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
 317         regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
 318         regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
 319         /* rx8130 is bit position, not BCD */
 320         if (ds1307->type == rx_8130)
 321                 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
 322         else
 323                 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
 324         regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
 325         regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
 326
 327         /* assume 20YY not 19YY */
 328         tmp = t->tm_year - 100;
 329         regs[DS1307_REG_YEAR] = bin2bcd(tmp);
 330
 331         if (chip->century_enable_bit)
 332                 regs[chip->century_reg] |= chip->century_enable_bit;
 333         if (t->tm_year > 199 && chip->century_bit)
 334                 regs[chip->century_reg] |= chip->century_bit;
 335
 336         switch (ds1307->type) {
 337         case ds_1308:
 338         case ds_1338:
 339                 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
 340                                    DS1338_BIT_OSF, 0);
 341                 break;
 342         case ds_1340:
 343                 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
 344                                    DS1340_BIT_OSF, 0);
 345                 break;
 346         case mcp794xx:
 347                 /*
 348                  * these bits were cleared when preparing the date/time
 349                  * values and need to be set again before writing the
 350                  * regsfer out to the device.
 351                  */
 352                 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
 353                 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
 354                 break;
 355         default:
 356                 break;
 357         }
 358
 359         dev_dbg(dev, "%s: %7ph\n", "write", regs);
 360
 361         result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
 362                                    sizeof(regs));
 363         if (result) {
 364                 dev_err(dev, "%s error %d\n", "write", result);
 365                 return result;
 366         }
 367
 368         if (ds1307->type == rx_8130) {
 369                 /* clear Voltage Loss Flag as data is available now */
 370                 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
 371                                       ~(u8)RX8130_REG_FLAG_VLF);
 372                 if (result) {
 373                         dev_err(dev, "%s error %d\n", "write", result);
 374                         return result;
 375                 }
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 382 {
 383         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 384         int                     ret;
 385         u8                      regs[9];
 386
 387         if (!test_bit(HAS_ALARM, &ds1307->flags))
 388                 return -EINVAL;
 389
 390         /* read all ALARM1, ALARM2, and status registers at once */
 391         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
 392                                regs, sizeof(regs));
 393         if (ret) {
 394                 dev_err(dev, "%s error %d\n", "alarm read", ret);
 395                 return ret;
 396         }
 397
 398         dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
 399                 &regs[0], &regs[4], &regs[7]);
 400
 401         /*
 402          * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
 403          * and that all four fields are checked matches
 404          */
 405         t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
 406         t->time.tm_min = bcd2bin(regs[1] & 0x7f);
 407         t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
 408         t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
 409
 410         /* ... and status */
 411         t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
 412         t->pending = !!(regs[8] & DS1337_BIT_A1I);
 413
 414         dev_dbg(dev, "%s secs=%d, mins=%d, "
 415                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 416                 "alarm read", t->time.tm_sec, t->time.tm_min,
 417                 t->time.tm_hour, t->time.tm_mday,
 418                 t->enabled, t->pending);
 419
 420         return 0;
 421 }
 422
 423 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 424 {
 425         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 426         unsigned char           regs[9];
 427         u8                      control, status;
 428         int                     ret;
 429
 430         if (!test_bit(HAS_ALARM, &ds1307->flags))
 431                 return -EINVAL;
 432
 433         dev_dbg(dev, "%s secs=%d, mins=%d, "
 434                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 435                 "alarm set", t->time.tm_sec, t->time.tm_min,
 436                 t->time.tm_hour, t->time.tm_mday,
 437                 t->enabled, t->pending);
 438
 439         /* read current status of both alarms and the chip */
 440         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 441                                sizeof(regs));
 442         if (ret) {
 443                 dev_err(dev, "%s error %d\n", "alarm write", ret);
 444                 return ret;
 445         }
 446         control = regs[7];
 447         status = regs[8];
 448
 449         dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
 450                 &regs[0], &regs[4], control, status);
 451
 452         /* set ALARM1, using 24 hour and day-of-month modes */
 453         regs[0] = bin2bcd(t->time.tm_sec);
 454         regs[1] = bin2bcd(t->time.tm_min);
 455         regs[2] = bin2bcd(t->time.tm_hour);
 456         regs[3] = bin2bcd(t->time.tm_mday);
 457
 458         /* set ALARM2 to non-garbage */
 459         regs[4] = 0;
 460         regs[5] = 0;
 461         regs[6] = 0;
 462
 463         /* disable alarms */
 464         regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
 465         regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
 466
 467         ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 468                                 sizeof(regs));
 469         if (ret) {
 470                 dev_err(dev, "can't set alarm time\n");
 471                 return ret;
 472         }
 473
 474         /* optionally enable ALARM1 */
 475         if (t->enabled) {
 476                 dev_dbg(dev, "alarm IRQ armed\n");
 477                 regs[7] |= DS1337_BIT_A1IE;     /* only ALARM1 is used */
 478                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
 479         }
 480
 481         return 0;
 482 }
 483
 484 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
 485 {
 486         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 487
 488         if (!test_bit(HAS_ALARM, &ds1307->flags))
 489                 return -ENOTTY;
 490
 491         return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 492                                   DS1337_BIT_A1IE,
 493                                   enabled ? DS1337_BIT_A1IE : 0);
 494 }
 495
 496 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
 497 {
 498         u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
 499                 DS1307_TRICKLE_CHARGER_NO_DIODE;
 500
 501         switch (ohms) {
 502         case 250:
 503                 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
 504                 break;
 505         case 2000:
 506                 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
 507                 break;
 508         case 4000:
 509                 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
 510                 break;
 511         default:
 512                 dev_warn(ds1307->dev,
 513                          "Unsupported ohm value %u in dt\n", ohms);
 514                 return 0;
 515         }
 516         return setup;
 517 }
 518
 519 static irqreturn_t rx8130_irq(int irq, void *dev_id)
 520 {
 521         struct ds1307           *ds1307 = dev_id;
 522         struct mutex            *lock = &ds1307->rtc->ops_lock;
 523         u8 ctl[3];
 524         int ret;
 525
 526         mutex_lock(lock);
 527
 528         /* Read control registers. */
 529         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 530                                sizeof(ctl));
 531         if (ret < 0)
 532                 goto out;
 533         if (!(ctl[1] & RX8130_REG_FLAG_AF))
 534                 goto out;
 535         ctl[1] &= ~RX8130_REG_FLAG_AF;
 536         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 537
 538         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 539                                 sizeof(ctl));
 540         if (ret < 0)
 541                 goto out;
 542
 543         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 544
 545 out:
 546         mutex_unlock(lock);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 552 {
 553         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 554         u8 ald[3], ctl[3];
 555         int ret;
 556
 557         if (!test_bit(HAS_ALARM, &ds1307->flags))
 558                 return -EINVAL;
 559
 560         /* Read alarm registers. */
 561         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 562                                sizeof(ald));
 563         if (ret < 0)
 564                 return ret;
 565
 566         /* Read control registers. */
 567         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 568                                sizeof(ctl));
 569         if (ret < 0)
 570                 return ret;
 571
 572         t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
 573         t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
 574
 575         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 576         t->time.tm_sec = -1;
 577         t->time.tm_min = bcd2bin(ald[0] & 0x7f);
 578         t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
 579         t->time.tm_wday = -1;
 580         t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
 581         t->time.tm_mon = -1;
 582         t->time.tm_year = -1;
 583         t->time.tm_yday = -1;
 584         t->time.tm_isdst = -1;
 585
 586         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
 587                 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 588                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
 589
 590         return 0;
 591 }
 592
 593 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 594 {
 595         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 596         u8 ald[3], ctl[3];
 597         int ret;
 598
 599         if (!test_bit(HAS_ALARM, &ds1307->flags))
 600                 return -EINVAL;
 601
 602         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 603                 "enabled=%d pending=%d\n", __func__,
 604                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 605                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 606                 t->enabled, t->pending);
 607
 608         /* Read control registers. */
 609         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 610                                sizeof(ctl));
 611         if (ret < 0)
 612                 return ret;
 613
 614         ctl[0] &= RX8130_REG_EXTENSION_WADA;
 615         ctl[1] &= ~RX8130_REG_FLAG_AF;
 616         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 617
 618         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 619                                 sizeof(ctl));
 620         if (ret < 0)
 621                 return ret;
 622
 623         /* Hardware alarm precision is 1 minute! */
 624         ald[0] = bin2bcd(t->time.tm_min);
 625         ald[1] = bin2bcd(t->time.tm_hour);
 626         ald[2] = bin2bcd(t->time.tm_mday);
 627
 628         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 629                                 sizeof(ald));
 630         if (ret < 0)
 631                 return ret;
 632
 633         if (!t->enabled)
 634                 return 0;
 635
 636         ctl[2] |= RX8130_REG_CONTROL0_AIE;
 637
 638         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
 639 }
 640
 641 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
 642 {
 643         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 644         int ret, reg;
 645
 646         if (!test_bit(HAS_ALARM, &ds1307->flags))
 647                 return -EINVAL;
 648
 649         ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
 650         if (ret < 0)
 651                 return ret;
 652
 653         if (enabled)
 654                 reg |= RX8130_REG_CONTROL0_AIE;
 655         else
 656                 reg &= ~RX8130_REG_CONTROL0_AIE;
 657
 658         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
 659 }
 660
 661 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
 662 {
 663         struct ds1307           *ds1307 = dev_id;
 664         struct mutex            *lock = &ds1307->rtc->ops_lock;
 665         int reg, ret;
 666
 667         mutex_lock(lock);
 668
 669         /* Check and clear alarm 0 interrupt flag. */
 670         ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
 671         if (ret)
 672                 goto out;
 673         if (!(reg & MCP794XX_BIT_ALMX_IF))
 674                 goto out;
 675         reg &= ~MCP794XX_BIT_ALMX_IF;
 676         ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
 677         if (ret)
 678                 goto out;
 679
 680         /* Disable alarm 0. */
 681         ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 682                                  MCP794XX_BIT_ALM0_EN, 0);
 683         if (ret)
 684                 goto out;
 685
 686         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 687
 688 out:
 689         mutex_unlock(lock);
 690
 691         return IRQ_HANDLED;
 692 }
 693
 694 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 695 {
 696         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 697         u8 regs[10];
 698         int ret;
 699
 700         if (!test_bit(HAS_ALARM, &ds1307->flags))
 701                 return -EINVAL;
 702
 703         /* Read control and alarm 0 registers. */
 704         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 705                                sizeof(regs));
 706         if (ret)
 707                 return ret;
 708
 709         t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
 710
 711         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 712         t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
 713         t->time.tm_min = bcd2bin(regs[4] & 0x7f);
 714         t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
 715         t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
 716         t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
 717         t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
 718         t->time.tm_year = -1;
 719         t->time.tm_yday = -1;
 720         t->time.tm_isdst = -1;
 721
 722         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 723                 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
 724                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 725                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
 726                 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
 727                 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
 728                 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
 729
 730         return 0;
 731 }
 732
 733 /*
 734  * We may have a random RTC weekday, therefore calculate alarm weekday based
 735  * on current weekday we read from the RTC timekeeping regs
 736  */
 737 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
 738 {
 739         struct rtc_time tm_now;
 740         int days_now, days_alarm, ret;
 741
 742         ret = ds1307_get_time(dev, &tm_now);
 743         if (ret)
 744                 return ret;
 745
 746         days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
 747         days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
 748
 749         return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
 750 }
 751
 752 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 753 {
 754         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 755         unsigned char regs[10];
 756         int wday, ret;
 757
 758         if (!test_bit(HAS_ALARM, &ds1307->flags))
 759                 return -EINVAL;
 760
 761         wday = mcp794xx_alm_weekday(dev, &t->time);
 762         if (wday < 0)
 763                 return wday;
 764
 765         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 766                 "enabled=%d pending=%d\n", __func__,
 767                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 768                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 769                 t->enabled, t->pending);
 770
 771         /* Read control and alarm 0 registers. */
 772         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 773                                sizeof(regs));
 774         if (ret)
 775                 return ret;
 776
 777         /* Set alarm 0, using 24-hour and day-of-month modes. */
 778         regs[3] = bin2bcd(t->time.tm_sec);
 779         regs[4] = bin2bcd(t->time.tm_min);
 780         regs[5] = bin2bcd(t->time.tm_hour);
 781         regs[6] = wday;
 782         regs[7] = bin2bcd(t->time.tm_mday);
 783         regs[8] = bin2bcd(t->time.tm_mon + 1);
 784
 785         /* Clear the alarm 0 interrupt flag. */
 786         regs[6] &= ~MCP794XX_BIT_ALMX_IF;
 787         /* Set alarm match: second, minute, hour, day, date, month. */
 788         regs[6] |= MCP794XX_MSK_ALMX_MATCH;
 789         /* Disable interrupt. We will not enable until completely programmed */
 790         regs[0] &= ~MCP794XX_BIT_ALM0_EN;
 791
 792         ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 793                                 sizeof(regs));
 794         if (ret)
 795                 return ret;
 796
 797         if (!t->enabled)
 798                 return 0;
 799         regs[0] |= MCP794XX_BIT_ALM0_EN;
 800         return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
 801 }
 802
 803 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 804 {
 805         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 806
 807         if (!test_bit(HAS_ALARM, &ds1307->flags))
 808                 return -EINVAL;
 809
 810         return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 811                                   MCP794XX_BIT_ALM0_EN,
 812                                   enabled ? MCP794XX_BIT_ALM0_EN : 0);
 813 }
 814
 815 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
 816 {
 817         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 818         unsigned int ctrl_reg;
 819         u8 val;
 820
 821         regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
 822
 823         val = ctrl_reg & M41TXX_M_CALIBRATION;
 824
 825         /* check if positive */
 826         if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
 827                 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
 828         else
 829                 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
 830
 831         return 0;
 832 }
 833
 834 static int m41txx_rtc_set_offset(struct device *dev, long offset)
 835 {
 836         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 837         unsigned int ctrl_reg;
 838
 839         if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
 840                 return -ERANGE;
 841
 842         if (offset >= 0) {
 843                 ctrl_reg = DIV_ROUND_CLOSEST(offset,
 844                                              M41TXX_POS_OFFSET_STEP_PPB);
 845                 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
 846         } else {
 847                 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
 848                                              M41TXX_NEG_OFFSET_STEP_PPB);
 849         }
 850
 851         return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
 852                                   M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
 853                                   ctrl_reg);
 854 }
 855
 856 static const struct rtc_class_ops rx8130_rtc_ops = {
 857         .read_time      = ds1307_get_time,
 858         .set_time       = ds1307_set_time,
 859         .read_alarm     = rx8130_read_alarm,
 860         .set_alarm      = rx8130_set_alarm,
 861         .alarm_irq_enable = rx8130_alarm_irq_enable,
 862 };
 863
 864 static const struct rtc_class_ops mcp794xx_rtc_ops = {
 865         .read_time      = ds1307_get_time,
 866         .set_time       = ds1307_set_time,
 867         .read_alarm     = mcp794xx_read_alarm,
 868         .set_alarm      = mcp794xx_set_alarm,
 869         .alarm_irq_enable = mcp794xx_alarm_irq_enable,
 870 };
 871
 872 static const struct rtc_class_ops m41txx_rtc_ops = {
 873         .read_time      = ds1307_get_time,
 874         .set_time       = ds1307_set_time,
 875         .read_alarm     = ds1337_read_alarm,
 876         .set_alarm      = ds1337_set_alarm,
 877         .alarm_irq_enable = ds1307_alarm_irq_enable,
 878         .read_offset    = m41txx_rtc_read_offset,
 879         .set_offset     = m41txx_rtc_set_offset,
 880 };
 881
 882 static const struct chip_desc chips[last_ds_type] = {
 883         [ds_1307] = {
 884                 .nvram_offset   = 8,
 885                 .nvram_size     = 56,
 886         },
 887         [ds_1308] = {
 888                 .nvram_offset   = 8,
 889                 .nvram_size     = 56,
 890         },
 891         [ds_1337] = {
 892                 .alarm          = 1,
 893                 .century_reg    = DS1307_REG_MONTH,
 894                 .century_bit    = DS1337_BIT_CENTURY,
 895         },
 896         [ds_1338] = {
 897                 .nvram_offset   = 8,
 898                 .nvram_size     = 56,
 899         },
 900         [ds_1339] = {
 901                 .alarm          = 1,
 902                 .century_reg    = DS1307_REG_MONTH,
 903                 .century_bit    = DS1337_BIT_CENTURY,
 904                 .bbsqi_bit      = DS1339_BIT_BBSQI,
 905                 .trickle_charger_reg = 0x10,
 906                 .do_trickle_setup = &do_trickle_setup_ds1339,
 907         },
 908         [ds_1340] = {
 909                 .century_reg    = DS1307_REG_HOUR,
 910                 .century_enable_bit = DS1340_BIT_CENTURY_EN,
 911                 .century_bit    = DS1340_BIT_CENTURY,
 912                 .do_trickle_setup = &do_trickle_setup_ds1339,
 913                 .trickle_charger_reg = 0x08,
 914         },
 915         [ds_1341] = {
 916                 .century_reg    = DS1307_REG_MONTH,
 917                 .century_bit    = DS1337_BIT_CENTURY,
 918         },
 919         [ds_1388] = {
 920                 .offset         = 1,
 921                 .trickle_charger_reg = 0x0a,
 922         },
 923         [ds_3231] = {
 924                 .alarm          = 1,
 925                 .century_reg    = DS1307_REG_MONTH,
 926                 .century_bit    = DS1337_BIT_CENTURY,
 927                 .bbsqi_bit      = DS3231_BIT_BBSQW,
 928         },
 929         [rx_8130] = {
 930                 .alarm          = 1,
 931                 /* this is battery backed SRAM */
 932                 .nvram_offset   = 0x20,
 933                 .nvram_size     = 4,    /* 32bit (4 word x 8 bit) */
 934                 .offset         = 0x10,
 935                 .irq_handler = rx8130_irq,
 936                 .rtc_ops = &rx8130_rtc_ops,
 937         },
 938         [m41t0] = {
 939                 .rtc_ops        = &m41txx_rtc_ops,
 940         },
 941         [m41t00] = {
 942                 .rtc_ops        = &m41txx_rtc_ops,
 943         },
 944         [m41t11] = {
 945                 /* this is battery backed SRAM */
 946                 .nvram_offset   = 8,
 947                 .nvram_size     = 56,
 948                 .rtc_ops        = &m41txx_rtc_ops,
 949         },
 950         [mcp794xx] = {
 951                 .alarm          = 1,
 952                 /* this is battery backed SRAM */
 953                 .nvram_offset   = 0x20,
 954                 .nvram_size     = 0x40,
 955                 .irq_handler = mcp794xx_irq,
 956                 .rtc_ops = &mcp794xx_rtc_ops,
 957         },
 958 };
 959
 960 static const struct i2c_device_id ds1307_id[] = {
 961         { "ds1307", ds_1307 },
 962         { "ds1308", ds_1308 },
 963         { "ds1337", ds_1337 },
 964         { "ds1338", ds_1338 },
 965         { "ds1339", ds_1339 },
 966         { "ds1388", ds_1388 },
 967         { "ds1340", ds_1340 },
 968         { "ds1341", ds_1341 },
 969         { "ds3231", ds_3231 },
 970         { "m41t0", m41t0 },
 971         { "m41t00", m41t00 },
 972         { "m41t11", m41t11 },
 973         { "mcp7940x", mcp794xx },
 974         { "mcp7941x", mcp794xx },
 975         { "pt7c4338", ds_1307 },
 976         { "rx8025", rx_8025 },
 977         { "isl12057", ds_1337 },
 978         { "rx8130", rx_8130 },
 979         { }
 980 };
 981 MODULE_DEVICE_TABLE(i2c, ds1307_id);
 982
 983 #ifdef CONFIG_OF
 984 static const struct of_device_id ds1307_of_match[] = {
 985         {
 986                 .compatible = "dallas,ds1307",
 987                 .data = (void *)ds_1307
 988         },
 989         {
 990                 .compatible = "dallas,ds1308",
 991                 .data = (void *)ds_1308
 992         },
 993         {
 994                 .compatible = "dallas,ds1337",
 995                 .data = (void *)ds_1337
 996         },
 997         {
 998                 .compatible = "dallas,ds1338",
 999                 .data = (void *)ds_1338
1000         },
1001         {
1002                 .compatible = "dallas,ds1339",
1003                 .data = (void *)ds_1339
1004         },
1005         {
1006                 .compatible = "dallas,ds1388",
1007                 .data = (void *)ds_1388
1008         },
1009         {
1010                 .compatible = "dallas,ds1340",
1011                 .data = (void *)ds_1340
1012         },
1013         {
1014                 .compatible = "dallas,ds1341",
1015                 .data = (void *)ds_1341
1016         },
1017         {
1018                 .compatible = "maxim,ds3231",
1019                 .data = (void *)ds_3231
1020         },
1021         {
1022                 .compatible = "st,m41t0",
1023                 .data = (void *)m41t0
1024         },
1025         {
1026                 .compatible = "st,m41t00",
1027                 .data = (void *)m41t00
1028         },
1029         {
1030                 .compatible = "st,m41t11",
1031                 .data = (void *)m41t11
1032         },
1033         {
1034                 .compatible = "microchip,mcp7940x",
1035                 .data = (void *)mcp794xx
1036         },
1037         {
1038                 .compatible = "microchip,mcp7941x",
1039                 .data = (void *)mcp794xx
1040         },
1041         {
1042                 .compatible = "pericom,pt7c4338",
1043                 .data = (void *)ds_1307
1044         },
1045         {
1046                 .compatible = "epson,rx8025",
1047                 .data = (void *)rx_8025
1048         },
1049         {
1050                 .compatible = "isil,isl12057",
1051                 .data = (void *)ds_1337
1052         },
1053         {
1054                 .compatible = "epson,rx8130",
1055                 .data = (void *)rx_8130
1056         },
1057         { }
1058 };
1059 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1060 #endif
1061
1062 #ifdef CONFIG_ACPI
1063 static const struct acpi_device_id ds1307_acpi_ids[] = {
1064         { .id = "DS1307", .driver_data = ds_1307 },
1065         { .id = "DS1308", .driver_data = ds_1308 },
1066         { .id = "DS1337", .driver_data = ds_1337 },
1067         { .id = "DS1338", .driver_data = ds_1338 },
1068         { .id = "DS1339", .driver_data = ds_1339 },
1069         { .id = "DS1388", .driver_data = ds_1388 },
1070         { .id = "DS1340", .driver_data = ds_1340 },
1071         { .id = "DS1341", .driver_data = ds_1341 },
1072         { .id = "DS3231", .driver_data = ds_3231 },
1073         { .id = "M41T0", .driver_data = m41t0 },
1074         { .id = "M41T00", .driver_data = m41t00 },
1075         { .id = "M41T11", .driver_data = m41t11 },
1076         { .id = "MCP7940X", .driver_data = mcp794xx },
1077         { .id = "MCP7941X", .driver_data = mcp794xx },
1078         { .id = "PT7C4338", .driver_data = ds_1307 },
1079         { .id = "RX8025", .driver_data = rx_8025 },
1080         { .id = "ISL12057", .driver_data = ds_1337 },
1081         { .id = "RX8130", .driver_data = rx_8130 },
1082         { }
1083 };
1084 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1085 #endif
1086
1087 /*
1088  * The ds1337 and ds1339 both have two alarms, but we only use the first
1089  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
1090  * signal; ds1339 chips have only one alarm signal.
1091  */
1092 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1093 {
1094         struct ds1307           *ds1307 = dev_id;
1095         struct mutex            *lock = &ds1307->rtc->ops_lock;
1096         int                     stat, ret;
1097
1098         mutex_lock(lock);
1099         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1100         if (ret)
1101                 goto out;
1102
1103         if (stat & DS1337_BIT_A1I) {
1104                 stat &= ~DS1337_BIT_A1I;
1105                 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1106
1107                 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1108                                          DS1337_BIT_A1IE, 0);
1109                 if (ret)
1110                         goto out;
1111
1112                 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1113         }
1114
1115 out:
1116         mutex_unlock(lock);
1117
1118         return IRQ_HANDLED;
1119 }
1120
1121 /*----------------------------------------------------------------------*/
1122
1123 static const struct rtc_class_ops ds13xx_rtc_ops = {
1124         .read_time      = ds1307_get_time,
1125         .set_time       = ds1307_set_time,
1126         .read_alarm     = ds1337_read_alarm,
1127         .set_alarm      = ds1337_set_alarm,
1128         .alarm_irq_enable = ds1307_alarm_irq_enable,
1129 };
1130
1131 static ssize_t frequency_test_store(struct device *dev,
1132                                     struct device_attribute *attr,
1133                                     const char *buf, size_t count)
1134 {
1135         struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1136         bool freq_test_en;
1137         int ret;
1138
1139         ret = kstrtobool(buf, &freq_test_en);
1140         if (ret) {
1141                 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1142                 return ret;
1143         }
1144
1145         regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1146                            freq_test_en ? M41TXX_BIT_FT : 0);
1147
1148         return count;
1149 }
1150
1151 static ssize_t frequency_test_show(struct device *dev,
1152                                    struct device_attribute *attr,
1153                                    char *buf)
1154 {
1155         struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1156         unsigned int ctrl_reg;
1157
1158         regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1159
1160         return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1161                         "off\n");
1162 }
1163
1164 static DEVICE_ATTR_RW(frequency_test);
1165
1166 static struct attribute *rtc_freq_test_attrs[] = {
1167         &dev_attr_frequency_test.attr,
1168         NULL,
1169 };
1170
1171 static const struct attribute_group rtc_freq_test_attr_group = {
1172         .attrs          = rtc_freq_test_attrs,
1173 };
1174
1175 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1176 {
1177         int err;
1178
1179         switch (ds1307->type) {
1180         case m41t0:
1181         case m41t00:
1182         case m41t11:
1183                 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1184                 if (err)
1185                         return err;
1186                 break;
1187         default:
1188                 break;
1189         }
1190
1191         return 0;
1192 }
1193
1194 /*----------------------------------------------------------------------*/
1195
1196 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1197                              size_t bytes)
1198 {
1199         struct ds1307 *ds1307 = priv;
1200         const struct chip_desc *chip = &chips[ds1307->type];
1201
1202         return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1203                                 val, bytes);
1204 }
1205
1206 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1207                               size_t bytes)
1208 {
1209         struct ds1307 *ds1307 = priv;
1210         const struct chip_desc *chip = &chips[ds1307->type];
1211
1212         return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1213                                  val, bytes);
1214 }
1215
1216 /*----------------------------------------------------------------------*/
1217
1218 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1219                               const struct chip_desc *chip)
1220 {
1221         u32 ohms;
1222         bool diode = true;
1223
1224         if (!chip->do_trickle_setup)
1225                 return 0;
1226
1227         if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1228                                      &ohms))
1229                 return 0;
1230
1231         if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1232                 diode = false;
1233
1234         return chip->do_trickle_setup(ds1307, ohms, diode);
1235 }
1236
1237 /*----------------------------------------------------------------------*/
1238
1239 #if IS_REACHABLE(CONFIG_HWMON)
1240
1241 /*
1242  * Temperature sensor support for ds3231 devices.
1243  */
1244
1245 #define DS3231_REG_TEMPERATURE  0x11
1246
1247 /*
1248  * A user-initiated temperature conversion is not started by this function,
1249  * so the temperature is updated once every 64 seconds.
1250  */
1251 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1252 {
1253         struct ds1307 *ds1307 = dev_get_drvdata(dev);
1254         u8 temp_buf[2];
1255         s16 temp;
1256         int ret;
1257
1258         ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1259                                temp_buf, sizeof(temp_buf));
1260         if (ret)
1261                 return ret;
1262         /*
1263          * Temperature is represented as a 10-bit code with a resolution of
1264          * 0.25 degree celsius and encoded in two's complement format.
1265          */
1266         temp = (temp_buf[0] << 8) | temp_buf[1];
1267         temp >>= 6;
1268         *mC = temp * 250;
1269
1270         return 0;
1271 }
1272
1273 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1274                                       struct device_attribute *attr, char *buf)
1275 {
1276         int ret;
1277         s32 temp;
1278
1279         ret = ds3231_hwmon_read_temp(dev, &temp);
1280         if (ret)
1281                 return ret;
1282
1283         return sprintf(buf, "%d\n", temp);
1284 }
1285 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1286                           NULL, 0);
1287
1288 static struct attribute *ds3231_hwmon_attrs[] = {
1289         &sensor_dev_attr_temp1_input.dev_attr.attr,
1290         NULL,
1291 };
1292 ATTRIBUTE_GROUPS(ds3231_hwmon);
1293
1294 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1295 {
1296         struct device *dev;
1297
1298         if (ds1307->type != ds_3231)
1299                 return;
1300
1301         dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1302                                                      ds1307,
1303                                                      ds3231_hwmon_groups);
1304         if (IS_ERR(dev)) {
1305                 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1306                          PTR_ERR(dev));
1307         }
1308 }
1309
1310 #else
1311
1312 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1313 {
1314 }
1315
1316 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1317
1318 /*----------------------------------------------------------------------*/
1319
1320 /*
1321  * Square-wave output support for DS3231
1322  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1323  */
1324 #ifdef CONFIG_COMMON_CLK
1325
1326 enum {
1327         DS3231_CLK_SQW = 0,
1328         DS3231_CLK_32KHZ,
1329 };
1330
1331 #define clk_sqw_to_ds1307(clk)  \
1332         container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1333 #define clk_32khz_to_ds1307(clk)        \
1334         container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1335
1336 static int ds3231_clk_sqw_rates[] = {
1337         1,
1338         1024,
1339         4096,
1340         8192,
1341 };
1342
1343 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1344 {
1345         struct mutex *lock = &ds1307->rtc->ops_lock;
1346         int ret;
1347
1348         mutex_lock(lock);
1349         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1350                                  mask, value);
1351         mutex_unlock(lock);
1352
1353         return ret;
1354 }
1355
1356 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1357                                                 unsigned long parent_rate)
1358 {
1359         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1360         int control, ret;
1361         int rate_sel = 0;
1362
1363         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1364         if (ret)
1365                 return ret;
1366         if (control & DS1337_BIT_RS1)
1367                 rate_sel += 1;
1368         if (control & DS1337_BIT_RS2)
1369                 rate_sel += 2;
1370
1371         return ds3231_clk_sqw_rates[rate_sel];
1372 }
1373
1374 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1375                                       unsigned long *prate)
1376 {
1377         int i;
1378
1379         for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1380                 if (ds3231_clk_sqw_rates[i] <= rate)
1381                         return ds3231_clk_sqw_rates[i];
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1388                                    unsigned long parent_rate)
1389 {
1390         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1391         int control = 0;
1392         int rate_sel;
1393
1394         for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1395                         rate_sel++) {
1396                 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1397                         break;
1398         }
1399
1400         if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1401                 return -EINVAL;
1402
1403         if (rate_sel & 1)
1404                 control |= DS1337_BIT_RS1;
1405         if (rate_sel & 2)
1406                 control |= DS1337_BIT_RS2;
1407
1408         return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1409                                 control);
1410 }
1411
1412 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1413 {
1414         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1415
1416         return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1417 }
1418
1419 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1420 {
1421         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1422
1423         ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1424 }
1425
1426 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1427 {
1428         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1429         int control, ret;
1430
1431         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1432         if (ret)
1433                 return ret;
1434
1435         return !(control & DS1337_BIT_INTCN);
1436 }
1437
1438 static const struct clk_ops ds3231_clk_sqw_ops = {
1439         .prepare = ds3231_clk_sqw_prepare,
1440         .unprepare = ds3231_clk_sqw_unprepare,
1441         .is_prepared = ds3231_clk_sqw_is_prepared,
1442         .recalc_rate = ds3231_clk_sqw_recalc_rate,
1443         .round_rate = ds3231_clk_sqw_round_rate,
1444         .set_rate = ds3231_clk_sqw_set_rate,
1445 };
1446
1447 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1448                                                   unsigned long parent_rate)
1449 {
1450         return 32768;
1451 }
1452
1453 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1454 {
1455         struct mutex *lock = &ds1307->rtc->ops_lock;
1456         int ret;
1457
1458         mutex_lock(lock);
1459         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1460                                  DS3231_BIT_EN32KHZ,
1461                                  enable ? DS3231_BIT_EN32KHZ : 0);
1462         mutex_unlock(lock);
1463
1464         return ret;
1465 }
1466
1467 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1468 {
1469         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1470
1471         return ds3231_clk_32khz_control(ds1307, true);
1472 }
1473
1474 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1475 {
1476         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1477
1478         ds3231_clk_32khz_control(ds1307, false);
1479 }
1480
1481 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1482 {
1483         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1484         int status, ret;
1485
1486         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1487         if (ret)
1488                 return ret;
1489
1490         return !!(status & DS3231_BIT_EN32KHZ);
1491 }
1492
1493 static const struct clk_ops ds3231_clk_32khz_ops = {
1494         .prepare = ds3231_clk_32khz_prepare,
1495         .unprepare = ds3231_clk_32khz_unprepare,
1496         .is_prepared = ds3231_clk_32khz_is_prepared,
1497         .recalc_rate = ds3231_clk_32khz_recalc_rate,
1498 };
1499
1500 static struct clk_init_data ds3231_clks_init[] = {
1501         [DS3231_CLK_SQW] = {
1502                 .name = "ds3231_clk_sqw",
1503                 .ops = &ds3231_clk_sqw_ops,
1504         },
1505         [DS3231_CLK_32KHZ] = {
1506                 .name = "ds3231_clk_32khz",
1507                 .ops = &ds3231_clk_32khz_ops,
1508         },
1509 };
1510
1511 static int ds3231_clks_register(struct ds1307 *ds1307)
1512 {
1513         struct device_node *node = ds1307->dev->of_node;
1514         struct clk_onecell_data *onecell;
1515         int i;
1516
1517         onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1518         if (!onecell)
1519                 return -ENOMEM;
1520
1521         onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1522         onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1523                                      sizeof(onecell->clks[0]), GFP_KERNEL);
1524         if (!onecell->clks)
1525                 return -ENOMEM;
1526
1527         for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1528                 struct clk_init_data init = ds3231_clks_init[i];
1529
1530                 /*
1531                  * Interrupt signal due to alarm conditions and square-wave
1532                  * output share same pin, so don't initialize both.
1533                  */
1534                 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1535                         continue;
1536
1537                 /* optional override of the clockname */
1538                 of_property_read_string_index(node, "clock-output-names", i,
1539                                               &init.name);
1540                 ds1307->clks[i].init = &init;
1541
1542                 onecell->clks[i] = devm_clk_register(ds1307->dev,
1543                                                      &ds1307->clks[i]);
1544                 if (IS_ERR(onecell->clks[i]))
1545                         return PTR_ERR(onecell->clks[i]);
1546         }
1547
1548         if (!node)
1549                 return 0;
1550
1551         of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1552
1553         return 0;
1554 }
1555
1556 static void ds1307_clks_register(struct ds1307 *ds1307)
1557 {
1558         int ret;
1559
1560         if (ds1307->type != ds_3231)
1561                 return;
1562
1563         ret = ds3231_clks_register(ds1307);
1564         if (ret) {
1565                 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1566                          ret);
1567         }
1568 }
1569
1570 #else
1571
1572 static void ds1307_clks_register(struct ds1307 *ds1307)
1573 {
1574 }
1575
1576 #endif /* CONFIG_COMMON_CLK */
1577
1578 static const struct regmap_config regmap_config = {
1579         .reg_bits = 8,
1580         .val_bits = 8,
1581 };
1582
1583 static int ds1307_probe(struct i2c_client *client,
1584                         const struct i2c_device_id *id)
1585 {
1586         struct ds1307           *ds1307;
1587         int                     err = -ENODEV;
1588         int                     tmp;
1589         const struct chip_desc  *chip;
1590         bool                    want_irq;
1591         bool                    ds1307_can_wakeup_device = false;
1592         unsigned char           regs[8];
1593         struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1594         u8                      trickle_charger_setup = 0;
1595
1596         ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1597         if (!ds1307)
1598                 return -ENOMEM;
1599
1600         dev_set_drvdata(&client->dev, ds1307);
1601         ds1307->dev = &client->dev;
1602         ds1307->name = client->name;
1603
1604         ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1605         if (IS_ERR(ds1307->regmap)) {
1606                 dev_err(ds1307->dev, "regmap allocation failed\n");
1607                 return PTR_ERR(ds1307->regmap);
1608         }
1609
1610         i2c_set_clientdata(client, ds1307);
1611
1612         if (client->dev.of_node) {
1613                 ds1307->type = (enum ds_type)
1614                         of_device_get_match_data(&client->dev);
1615                 chip = &chips[ds1307->type];
1616         } else if (id) {
1617                 chip = &chips[id->driver_data];
1618                 ds1307->type = id->driver_data;
1619         } else {
1620                 const struct acpi_device_id *acpi_id;
1621
1622                 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1623                                             ds1307->dev);
1624                 if (!acpi_id)
1625                         return -ENODEV;
1626                 chip = &chips[acpi_id->driver_data];
1627                 ds1307->type = acpi_id->driver_data;
1628         }
1629
1630         want_irq = client->irq > 0 && chip->alarm;
1631
1632         if (!pdata)
1633                 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1634         else if (pdata->trickle_charger_setup)
1635                 trickle_charger_setup = pdata->trickle_charger_setup;
1636
1637         if (trickle_charger_setup && chip->trickle_charger_reg) {
1638                 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1639                 dev_dbg(ds1307->dev,
1640                         "writing trickle charger info 0x%x to 0x%x\n",
1641                         trickle_charger_setup, chip->trickle_charger_reg);
1642                 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1643                              trickle_charger_setup);
1644         }
1645
1646 #ifdef CONFIG_OF
1647 /*
1648  * For devices with no IRQ directly connected to the SoC, the RTC chip
1649  * can be forced as a wakeup source by stating that explicitly in
1650  * the device's .dts file using the "wakeup-source" boolean property.
1651  * If the "wakeup-source" property is set, don't request an IRQ.
1652  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1653  * if supported by the RTC.
1654  */
1655         if (chip->alarm && of_property_read_bool(client->dev.of_node,
1656                                                  "wakeup-source"))
1657                 ds1307_can_wakeup_device = true;
1658 #endif
1659
1660         switch (ds1307->type) {
1661         case ds_1337:
1662         case ds_1339:
1663         case ds_1341:
1664         case ds_3231:
1665                 /* get registers that the "rtc" read below won't read... */
1666                 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1667                                        regs, 2);
1668                 if (err) {
1669                         dev_dbg(ds1307->dev, "read error %d\n", err);
1670                         goto exit;
1671                 }
1672
1673                 /* oscillator off?  turn it on, so clock can tick. */
1674                 if (regs[0] & DS1337_BIT_nEOSC)
1675                         regs[0] &= ~DS1337_BIT_nEOSC;
1676
1677                 /*
1678                  * Using IRQ or defined as wakeup-source?
1679                  * Disable the square wave and both alarms.
1680                  * For some variants, be sure alarms can trigger when we're
1681                  * running on Vbackup (BBSQI/BBSQW)
1682                  */
1683                 if (want_irq || ds1307_can_wakeup_device) {
1684                         regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1685                         regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1686                 }
1687
1688                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1689                              regs[0]);
1690
1691                 /* oscillator fault?  clear flag, and warn */
1692                 if (regs[1] & DS1337_BIT_OSF) {
1693                         regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1694                                      regs[1] & ~DS1337_BIT_OSF);
1695                         dev_warn(ds1307->dev, "SET TIME!\n");
1696                 }
1697                 break;
1698
1699         case rx_8025:
1700                 err = regmap_bulk_read(ds1307->regmap,
1701                                        RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1702                 if (err) {
1703                         dev_dbg(ds1307->dev, "read error %d\n", err);
1704                         goto exit;
1705                 }
1706
1707                 /* oscillator off?  turn it on, so clock can tick. */
1708                 if (!(regs[1] & RX8025_BIT_XST)) {
1709                         regs[1] |= RX8025_BIT_XST;
1710                         regmap_write(ds1307->regmap,
1711                                      RX8025_REG_CTRL2 << 4 | 0x08,
1712                                      regs[1]);
1713                         dev_warn(ds1307->dev,
1714                                  "oscillator stop detected - SET TIME!\n");
1715                 }
1716
1717                 if (regs[1] & RX8025_BIT_PON) {
1718                         regs[1] &= ~RX8025_BIT_PON;
1719                         regmap_write(ds1307->regmap,
1720                                      RX8025_REG_CTRL2 << 4 | 0x08,
1721                                      regs[1]);
1722                         dev_warn(ds1307->dev, "power-on detected\n");
1723                 }
1724
1725                 if (regs[1] & RX8025_BIT_VDET) {
1726                         regs[1] &= ~RX8025_BIT_VDET;
1727                         regmap_write(ds1307->regmap,
1728                                      RX8025_REG_CTRL2 << 4 | 0x08,
1729                                      regs[1]);
1730                         dev_warn(ds1307->dev, "voltage drop detected\n");
1731                 }
1732
1733                 /* make sure we are running in 24hour mode */
1734                 if (!(regs[0] & RX8025_BIT_2412)) {
1735                         u8 hour;
1736
1737                         /* switch to 24 hour mode */
1738                         regmap_write(ds1307->regmap,
1739                                      RX8025_REG_CTRL1 << 4 | 0x08,
1740                                      regs[0] | RX8025_BIT_2412);
1741
1742                         err = regmap_bulk_read(ds1307->regmap,
1743                                                RX8025_REG_CTRL1 << 4 | 0x08,
1744                                                regs, 2);
1745                         if (err) {
1746                                 dev_dbg(ds1307->dev, "read error %d\n", err);
1747                                 goto exit;
1748                         }
1749
1750                         /* correct hour */
1751                         hour = bcd2bin(regs[DS1307_REG_HOUR]);
1752                         if (hour == 12)
1753                                 hour = 0;
1754                         if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1755                                 hour += 12;
1756
1757                         regmap_write(ds1307->regmap,
1758                                      DS1307_REG_HOUR << 4 | 0x08, hour);
1759                 }
1760                 break;
1761         default:
1762                 break;
1763         }
1764
1765         /* read RTC registers */
1766         err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1767                                sizeof(regs));
1768         if (err) {
1769                 dev_dbg(ds1307->dev, "read error %d\n", err);
1770                 goto exit;
1771         }
1772
1773         if (ds1307->type == mcp794xx &&
1774             !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1775                 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1776                              regs[DS1307_REG_WDAY] |
1777                              MCP794XX_BIT_VBATEN);
1778         }
1779
1780         tmp = regs[DS1307_REG_HOUR];
1781         switch (ds1307->type) {
1782         case ds_1340:
1783         case m41t0:
1784         case m41t00:
1785         case m41t11:
1786                 /*
1787                  * NOTE: ignores century bits; fix before deploying
1788                  * systems that will run through year 2100.
1789                  */
1790                 break;
1791         case rx_8025:
1792                 break;
1793         default:
1794                 if (!(tmp & DS1307_BIT_12HR))
1795                         break;
1796
1797                 /*
1798                  * Be sure we're in 24 hour mode.  Multi-master systems
1799                  * take note...
1800                  */
1801                 tmp = bcd2bin(tmp & 0x1f);
1802                 if (tmp == 12)
1803                         tmp = 0;
1804                 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1805                         tmp += 12;
1806                 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1807                              bin2bcd(tmp));
1808         }
1809
1810         if (want_irq || ds1307_can_wakeup_device) {
1811                 device_set_wakeup_capable(ds1307->dev, true);
1812                 set_bit(HAS_ALARM, &ds1307->flags);
1813         }
1814
1815         ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1816         if (IS_ERR(ds1307->rtc))
1817                 return PTR_ERR(ds1307->rtc);
1818
1819         if (ds1307_can_wakeup_device && !want_irq) {
1820                 dev_info(ds1307->dev,
1821                          "'wakeup-source' is set, request for an IRQ is disabled!\n");
1822                 /* We cannot support UIE mode if we do not have an IRQ line */
1823                 ds1307->rtc->uie_unsupported = 1;
1824         }
1825
1826         if (want_irq) {
1827                 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1828                                                 chip->irq_handler ?: ds1307_irq,
1829                                                 IRQF_SHARED | IRQF_ONESHOT,
1830                                                 ds1307->name, ds1307);
1831                 if (err) {
1832                         client->irq = 0;
1833                         device_set_wakeup_capable(ds1307->dev, false);
1834                         clear_bit(HAS_ALARM, &ds1307->flags);
1835                         dev_err(ds1307->dev, "unable to request IRQ!\n");
1836                 } else {
1837                         dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1838                 }
1839         }
1840
1841         ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1842         err = ds1307_add_frequency_test(ds1307);
1843         if (err)
1844                 return err;
1845
1846         err = rtc_register_device(ds1307->rtc);
1847         if (err)
1848                 return err;
1849
1850         if (chip->nvram_size) {
1851                 struct nvmem_config nvmem_cfg = {
1852                         .name = "ds1307_nvram",
1853                         .word_size = 1,
1854                         .stride = 1,
1855                         .size = chip->nvram_size,
1856                         .reg_read = ds1307_nvram_read,
1857                         .reg_write = ds1307_nvram_write,
1858                         .priv = ds1307,
1859                 };
1860
1861                 ds1307->rtc->nvram_old_abi = true;
1862                 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1863         }
1864
1865         ds1307_hwmon_register(ds1307);
1866         ds1307_clks_register(ds1307);
1867
1868         return 0;
1869
1870 exit:
1871         return err;
1872 }
1873
1874 static struct i2c_driver ds1307_driver = {
1875         .driver = {
1876                 .name   = "rtc-ds1307",
1877                 .of_match_table = of_match_ptr(ds1307_of_match),
1878                 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1879         },
1880         .probe          = ds1307_probe,
1881         .id_table       = ds1307_id,
1882 };
1883
1884 module_i2c_driver(ds1307_driver);
1885
1886 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1887 MODULE_LICENSE("GPL");