drivers/rtc/rtc-ds1307.c

   1 /*
   2  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
   3  *
   4  *  Copyright (C) 2005 James Chapman (ds1337 core)
   5  *  Copyright (C) 2006 David Brownell
   6  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
   7  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/bcd.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/rtc/ds1307.h>
  21 #include <linux/rtc.h>
  22 #include <linux/slab.h>
  23 #include <linux/string.h>
  24 #include <linux/hwmon.h>
  25 #include <linux/hwmon-sysfs.h>
  26 #include <linux/clk-provider.h>
  27 #include <linux/regmap.h>
  28
  29 /*
  30  * We can't determine type by probing, but if we expect pre-Linux code
  31  * to have set the chip up as a clock (turning on the oscillator and
  32  * setting the date and time), Linux can ignore the non-clock features.
  33  * That's a natural job for a factory or repair bench.
  34  */
  35 enum ds_type {
  36         ds_1307,
  37         ds_1308,
  38         ds_1337,
  39         ds_1338,
  40         ds_1339,
  41         ds_1340,
  42         ds_1341,
  43         ds_1388,
  44         ds_3231,
  45         m41t0,
  46         m41t00,
  47         mcp794xx,
  48         rx_8025,
  49         rx_8130,
  50         last_ds_type /* always last */
  51         /* rs5c372 too?  different address... */
  52 };
  53
  54 /* RTC registers don't differ much, except for the century flag */
  55 #define DS1307_REG_SECS         0x00    /* 00-59 */
  56 #       define DS1307_BIT_CH            0x80
  57 #       define DS1340_BIT_nEOSC         0x80
  58 #       define MCP794XX_BIT_ST          0x80
  59 #define DS1307_REG_MIN          0x01    /* 00-59 */
  60 #       define M41T0_BIT_OF             0x80
  61 #define DS1307_REG_HOUR         0x02    /* 00-23, or 1-12{am,pm} */
  62 #       define DS1307_BIT_12HR          0x40    /* in REG_HOUR */
  63 #       define DS1307_BIT_PM            0x20    /* in REG_HOUR */
  64 #       define DS1340_BIT_CENTURY_EN    0x80    /* in REG_HOUR */
  65 #       define DS1340_BIT_CENTURY       0x40    /* in REG_HOUR */
  66 #define DS1307_REG_WDAY         0x03    /* 01-07 */
  67 #       define MCP794XX_BIT_VBATEN      0x08
  68 #define DS1307_REG_MDAY         0x04    /* 01-31 */
  69 #define DS1307_REG_MONTH        0x05    /* 01-12 */
  70 #       define DS1337_BIT_CENTURY       0x80    /* in REG_MONTH */
  71 #define DS1307_REG_YEAR         0x06    /* 00-99 */
  72
  73 /*
  74  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  75  * start at 7, and they differ a LOT. Only control and status matter for
  76  * basic RTC date and time functionality; be careful using them.
  77  */
  78 #define DS1307_REG_CONTROL      0x07            /* or ds1338 */
  79 #       define DS1307_BIT_OUT           0x80
  80 #       define DS1338_BIT_OSF           0x20
  81 #       define DS1307_BIT_SQWE          0x10
  82 #       define DS1307_BIT_RS1           0x02
  83 #       define DS1307_BIT_RS0           0x01
  84 #define DS1337_REG_CONTROL      0x0e
  85 #       define DS1337_BIT_nEOSC         0x80
  86 #       define DS1339_BIT_BBSQI         0x20
  87 #       define DS3231_BIT_BBSQW         0x40 /* same as BBSQI */
  88 #       define DS1337_BIT_RS2           0x10
  89 #       define DS1337_BIT_RS1           0x08
  90 #       define DS1337_BIT_INTCN         0x04
  91 #       define DS1337_BIT_A2IE          0x02
  92 #       define DS1337_BIT_A1IE          0x01
  93 #define DS1340_REG_CONTROL      0x07
  94 #       define DS1340_BIT_OUT           0x80
  95 #       define DS1340_BIT_FT            0x40
  96 #       define DS1340_BIT_CALIB_SIGN    0x20
  97 #       define DS1340_M_CALIBRATION     0x1f
  98 #define DS1340_REG_FLAG         0x09
  99 #       define DS1340_BIT_OSF           0x80
 100 #define DS1337_REG_STATUS       0x0f
 101 #       define DS1337_BIT_OSF           0x80
 102 #       define DS3231_BIT_EN32KHZ       0x08
 103 #       define DS1337_BIT_A2I           0x02
 104 #       define DS1337_BIT_A1I           0x01
 105 #define DS1339_REG_ALARM1_SECS  0x07
 106
 107 #define DS13XX_TRICKLE_CHARGER_MAGIC    0xa0
 108
 109 #define RX8025_REG_CTRL1        0x0e
 110 #       define RX8025_BIT_2412          0x20
 111 #define RX8025_REG_CTRL2        0x0f
 112 #       define RX8025_BIT_PON           0x10
 113 #       define RX8025_BIT_VDET          0x40
 114 #       define RX8025_BIT_XST           0x20
 115
 116 struct ds1307 {
 117         struct nvmem_config     nvmem_cfg;
 118         enum ds_type            type;
 119         unsigned long           flags;
 120 #define HAS_NVRAM       0               /* bit 0 == sysfs file active */
 121 #define HAS_ALARM       1               /* bit 1 == irq claimed */
 122         struct device           *dev;
 123         struct regmap           *regmap;
 124         const char              *name;
 125         struct rtc_device       *rtc;
 126 #ifdef CONFIG_COMMON_CLK
 127         struct clk_hw           clks[2];
 128 #endif
 129 };
 130
 131 struct chip_desc {
 132         unsigned                alarm:1;
 133         u16                     nvram_offset;
 134         u16                     nvram_size;
 135         u8                      offset; /* register's offset */
 136         u8                      century_reg;
 137         u8                      century_enable_bit;
 138         u8                      century_bit;
 139         u8                      bbsqi_bit;
 140         irq_handler_t           irq_handler;
 141         const struct rtc_class_ops *rtc_ops;
 142         u16                     trickle_charger_reg;
 143         u8                      (*do_trickle_setup)(struct ds1307 *, u32,
 144                                                     bool);
 145 };
 146
 147 static int ds1307_get_time(struct device *dev, struct rtc_time *t);
 148 static int ds1307_set_time(struct device *dev, struct rtc_time *t);
 149 static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
 150 static irqreturn_t rx8130_irq(int irq, void *dev_id);
 151 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
 152 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
 153 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
 154 static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
 155 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
 156 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
 157 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
 158
 159 static const struct rtc_class_ops rx8130_rtc_ops = {
 160         .read_time      = ds1307_get_time,
 161         .set_time       = ds1307_set_time,
 162         .read_alarm     = rx8130_read_alarm,
 163         .set_alarm      = rx8130_set_alarm,
 164         .alarm_irq_enable = rx8130_alarm_irq_enable,
 165 };
 166
 167 static const struct rtc_class_ops mcp794xx_rtc_ops = {
 168         .read_time      = ds1307_get_time,
 169         .set_time       = ds1307_set_time,
 170         .read_alarm     = mcp794xx_read_alarm,
 171         .set_alarm      = mcp794xx_set_alarm,
 172         .alarm_irq_enable = mcp794xx_alarm_irq_enable,
 173 };
 174
 175 static const struct chip_desc chips[last_ds_type] = {
 176         [ds_1307] = {
 177                 .nvram_offset   = 8,
 178                 .nvram_size     = 56,
 179         },
 180         [ds_1308] = {
 181                 .nvram_offset   = 8,
 182                 .nvram_size     = 56,
 183         },
 184         [ds_1337] = {
 185                 .alarm          = 1,
 186                 .century_reg    = DS1307_REG_MONTH,
 187                 .century_bit    = DS1337_BIT_CENTURY,
 188         },
 189         [ds_1338] = {
 190                 .nvram_offset   = 8,
 191                 .nvram_size     = 56,
 192         },
 193         [ds_1339] = {
 194                 .alarm          = 1,
 195                 .century_reg    = DS1307_REG_MONTH,
 196                 .century_bit    = DS1337_BIT_CENTURY,
 197                 .bbsqi_bit      = DS1339_BIT_BBSQI,
 198                 .trickle_charger_reg = 0x10,
 199                 .do_trickle_setup = &do_trickle_setup_ds1339,
 200         },
 201         [ds_1340] = {
 202                 .century_reg    = DS1307_REG_HOUR,
 203                 .century_enable_bit = DS1340_BIT_CENTURY_EN,
 204                 .century_bit    = DS1340_BIT_CENTURY,
 205                 .trickle_charger_reg = 0x08,
 206         },
 207         [ds_1341] = {
 208                 .century_reg    = DS1307_REG_MONTH,
 209                 .century_bit    = DS1337_BIT_CENTURY,
 210         },
 211         [ds_1388] = {
 212                 .offset         = 1,
 213                 .trickle_charger_reg = 0x0a,
 214         },
 215         [ds_3231] = {
 216                 .alarm          = 1,
 217                 .century_reg    = DS1307_REG_MONTH,
 218                 .century_bit    = DS1337_BIT_CENTURY,
 219                 .bbsqi_bit      = DS3231_BIT_BBSQW,
 220         },
 221         [rx_8130] = {
 222                 .alarm          = 1,
 223                 /* this is battery backed SRAM */
 224                 .nvram_offset   = 0x20,
 225                 .nvram_size     = 4,    /* 32bit (4 word x 8 bit) */
 226                 .offset         = 0x10,
 227                 .irq_handler = rx8130_irq,
 228                 .rtc_ops = &rx8130_rtc_ops,
 229         },
 230         [mcp794xx] = {
 231                 .alarm          = 1,
 232                 /* this is battery backed SRAM */
 233                 .nvram_offset   = 0x20,
 234                 .nvram_size     = 0x40,
 235                 .irq_handler = mcp794xx_irq,
 236                 .rtc_ops = &mcp794xx_rtc_ops,
 237         },
 238 };
 239
 240 static const struct i2c_device_id ds1307_id[] = {
 241         { "ds1307", ds_1307 },
 242         { "ds1308", ds_1308 },
 243         { "ds1337", ds_1337 },
 244         { "ds1338", ds_1338 },
 245         { "ds1339", ds_1339 },
 246         { "ds1388", ds_1388 },
 247         { "ds1340", ds_1340 },
 248         { "ds1341", ds_1341 },
 249         { "ds3231", ds_3231 },
 250         { "m41t0", m41t0 },
 251         { "m41t00", m41t00 },
 252         { "mcp7940x", mcp794xx },
 253         { "mcp7941x", mcp794xx },
 254         { "pt7c4338", ds_1307 },
 255         { "rx8025", rx_8025 },
 256         { "isl12057", ds_1337 },
 257         { "rx8130", rx_8130 },
 258         { }
 259 };
 260 MODULE_DEVICE_TABLE(i2c, ds1307_id);
 261
 262 #ifdef CONFIG_OF
 263 static const struct of_device_id ds1307_of_match[] = {
 264         {
 265                 .compatible = "dallas,ds1307",
 266                 .data = (void *)ds_1307
 267         },
 268         {
 269                 .compatible = "dallas,ds1308",
 270                 .data = (void *)ds_1308
 271         },
 272         {
 273                 .compatible = "dallas,ds1337",
 274                 .data = (void *)ds_1337
 275         },
 276         {
 277                 .compatible = "dallas,ds1338",
 278                 .data = (void *)ds_1338
 279         },
 280         {
 281                 .compatible = "dallas,ds1339",
 282                 .data = (void *)ds_1339
 283         },
 284         {
 285                 .compatible = "dallas,ds1388",
 286                 .data = (void *)ds_1388
 287         },
 288         {
 289                 .compatible = "dallas,ds1340",
 290                 .data = (void *)ds_1340
 291         },
 292         {
 293                 .compatible = "dallas,ds1341",
 294                 .data = (void *)ds_1341
 295         },
 296         {
 297                 .compatible = "maxim,ds3231",
 298                 .data = (void *)ds_3231
 299         },
 300         {
 301                 .compatible = "st,m41t0",
 302                 .data = (void *)m41t00
 303         },
 304         {
 305                 .compatible = "st,m41t00",
 306                 .data = (void *)m41t00
 307         },
 308         {
 309                 .compatible = "microchip,mcp7940x",
 310                 .data = (void *)mcp794xx
 311         },
 312         {
 313                 .compatible = "microchip,mcp7941x",
 314                 .data = (void *)mcp794xx
 315         },
 316         {
 317                 .compatible = "pericom,pt7c4338",
 318                 .data = (void *)ds_1307
 319         },
 320         {
 321                 .compatible = "epson,rx8025",
 322                 .data = (void *)rx_8025
 323         },
 324         {
 325                 .compatible = "isil,isl12057",
 326                 .data = (void *)ds_1337
 327         },
 328         { }
 329 };
 330 MODULE_DEVICE_TABLE(of, ds1307_of_match);
 331 #endif
 332
 333 #ifdef CONFIG_ACPI
 334 static const struct acpi_device_id ds1307_acpi_ids[] = {
 335         { .id = "DS1307", .driver_data = ds_1307 },
 336         { .id = "DS1308", .driver_data = ds_1308 },
 337         { .id = "DS1337", .driver_data = ds_1337 },
 338         { .id = "DS1338", .driver_data = ds_1338 },
 339         { .id = "DS1339", .driver_data = ds_1339 },
 340         { .id = "DS1388", .driver_data = ds_1388 },
 341         { .id = "DS1340", .driver_data = ds_1340 },
 342         { .id = "DS1341", .driver_data = ds_1341 },
 343         { .id = "DS3231", .driver_data = ds_3231 },
 344         { .id = "M41T0", .driver_data = m41t0 },
 345         { .id = "M41T00", .driver_data = m41t00 },
 346         { .id = "MCP7940X", .driver_data = mcp794xx },
 347         { .id = "MCP7941X", .driver_data = mcp794xx },
 348         { .id = "PT7C4338", .driver_data = ds_1307 },
 349         { .id = "RX8025", .driver_data = rx_8025 },
 350         { .id = "ISL12057", .driver_data = ds_1337 },
 351         { }
 352 };
 353 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
 354 #endif
 355
 356 /*
 357  * The ds1337 and ds1339 both have two alarms, but we only use the first
 358  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
 359  * signal; ds1339 chips have only one alarm signal.
 360  */
 361 static irqreturn_t ds1307_irq(int irq, void *dev_id)
 362 {
 363         struct ds1307           *ds1307 = dev_id;
 364         struct mutex            *lock = &ds1307->rtc->ops_lock;
 365         int                     stat, ret;
 366
 367         mutex_lock(lock);
 368         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
 369         if (ret)
 370                 goto out;
 371
 372         if (stat & DS1337_BIT_A1I) {
 373                 stat &= ~DS1337_BIT_A1I;
 374                 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
 375
 376                 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 377                                          DS1337_BIT_A1IE, 0);
 378                 if (ret)
 379                         goto out;
 380
 381                 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 382         }
 383
 384 out:
 385         mutex_unlock(lock);
 386
 387         return IRQ_HANDLED;
 388 }
 389
 390 /*----------------------------------------------------------------------*/
 391
 392 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
 393 {
 394         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 395         int             tmp, ret;
 396         const struct chip_desc *chip = &chips[ds1307->type];
 397         u8 regs[7];
 398
 399         /* read the RTC date and time registers all at once */
 400         ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
 401                                sizeof(regs));
 402         if (ret) {
 403                 dev_err(dev, "%s error %d\n", "read", ret);
 404                 return ret;
 405         }
 406
 407         dev_dbg(dev, "%s: %7ph\n", "read", regs);
 408
 409         /* if oscillator fail bit is set, no data can be trusted */
 410         if (ds1307->type == m41t0 &&
 411             regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
 412                 dev_warn_once(dev, "oscillator failed, set time!\n");
 413                 return -EINVAL;
 414         }
 415
 416         t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
 417         t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
 418         tmp = regs[DS1307_REG_HOUR] & 0x3f;
 419         t->tm_hour = bcd2bin(tmp);
 420         /* rx8130 is bit position, not BCD */
 421         if (ds1307->type == rx_8130)
 422                 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
 423         else
 424                 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
 425         t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
 426         tmp = regs[DS1307_REG_MONTH] & 0x1f;
 427         t->tm_mon = bcd2bin(tmp) - 1;
 428         t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
 429
 430         if (regs[chip->century_reg] & chip->century_bit &&
 431             IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
 432                 t->tm_year += 100;
 433
 434         dev_dbg(dev, "%s secs=%d, mins=%d, "
 435                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 436                 "read", t->tm_sec, t->tm_min,
 437                 t->tm_hour, t->tm_mday,
 438                 t->tm_mon, t->tm_year, t->tm_wday);
 439
 440         /* initial clock setting can be undefined */
 441         return rtc_valid_tm(t);
 442 }
 443
 444 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
 445 {
 446         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 447         const struct chip_desc *chip = &chips[ds1307->type];
 448         int             result;
 449         int             tmp;
 450         u8              regs[7];
 451
 452         dev_dbg(dev, "%s secs=%d, mins=%d, "
 453                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 454                 "write", t->tm_sec, t->tm_min,
 455                 t->tm_hour, t->tm_mday,
 456                 t->tm_mon, t->tm_year, t->tm_wday);
 457
 458         if (t->tm_year < 100)
 459                 return -EINVAL;
 460
 461 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
 462         if (t->tm_year > (chip->century_bit ? 299 : 199))
 463                 return -EINVAL;
 464 #else
 465         if (t->tm_year > 199)
 466                 return -EINVAL;
 467 #endif
 468
 469         regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
 470         regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
 471         regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
 472         /* rx8130 is bit position, not BCD */
 473         if (ds1307->type == rx_8130)
 474                 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
 475         else
 476                 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
 477         regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
 478         regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
 479
 480         /* assume 20YY not 19YY */
 481         tmp = t->tm_year - 100;
 482         regs[DS1307_REG_YEAR] = bin2bcd(tmp);
 483
 484         if (chip->century_enable_bit)
 485                 regs[chip->century_reg] |= chip->century_enable_bit;
 486         if (t->tm_year > 199 && chip->century_bit)
 487                 regs[chip->century_reg] |= chip->century_bit;
 488
 489         if (ds1307->type == mcp794xx) {
 490                 /*
 491                  * these bits were cleared when preparing the date/time
 492                  * values and need to be set again before writing the
 493                  * regsfer out to the device.
 494                  */
 495                 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
 496                 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
 497         }
 498
 499         dev_dbg(dev, "%s: %7ph\n", "write", regs);
 500
 501         result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
 502                                    sizeof(regs));
 503         if (result) {
 504                 dev_err(dev, "%s error %d\n", "write", result);
 505                 return result;
 506         }
 507         return 0;
 508 }
 509
 510 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 511 {
 512         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 513         int                     ret;
 514         u8                      regs[9];
 515
 516         if (!test_bit(HAS_ALARM, &ds1307->flags))
 517                 return -EINVAL;
 518
 519         /* read all ALARM1, ALARM2, and status registers at once */
 520         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
 521                                regs, sizeof(regs));
 522         if (ret) {
 523                 dev_err(dev, "%s error %d\n", "alarm read", ret);
 524                 return ret;
 525         }
 526
 527         dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
 528                 &regs[0], &regs[4], &regs[7]);
 529
 530         /*
 531          * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
 532          * and that all four fields are checked matches
 533          */
 534         t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
 535         t->time.tm_min = bcd2bin(regs[1] & 0x7f);
 536         t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
 537         t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
 538
 539         /* ... and status */
 540         t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
 541         t->pending = !!(regs[8] & DS1337_BIT_A1I);
 542
 543         dev_dbg(dev, "%s secs=%d, mins=%d, "
 544                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 545                 "alarm read", t->time.tm_sec, t->time.tm_min,
 546                 t->time.tm_hour, t->time.tm_mday,
 547                 t->enabled, t->pending);
 548
 549         return 0;
 550 }
 551
 552 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 553 {
 554         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 555         unsigned char           regs[9];
 556         u8                      control, status;
 557         int                     ret;
 558
 559         if (!test_bit(HAS_ALARM, &ds1307->flags))
 560                 return -EINVAL;
 561
 562         dev_dbg(dev, "%s secs=%d, mins=%d, "
 563                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 564                 "alarm set", t->time.tm_sec, t->time.tm_min,
 565                 t->time.tm_hour, t->time.tm_mday,
 566                 t->enabled, t->pending);
 567
 568         /* read current status of both alarms and the chip */
 569         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 570                                sizeof(regs));
 571         if (ret) {
 572                 dev_err(dev, "%s error %d\n", "alarm write", ret);
 573                 return ret;
 574         }
 575         control = regs[7];
 576         status = regs[8];
 577
 578         dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
 579                 &regs[0], &regs[4], control, status);
 580
 581         /* set ALARM1, using 24 hour and day-of-month modes */
 582         regs[0] = bin2bcd(t->time.tm_sec);
 583         regs[1] = bin2bcd(t->time.tm_min);
 584         regs[2] = bin2bcd(t->time.tm_hour);
 585         regs[3] = bin2bcd(t->time.tm_mday);
 586
 587         /* set ALARM2 to non-garbage */
 588         regs[4] = 0;
 589         regs[5] = 0;
 590         regs[6] = 0;
 591
 592         /* disable alarms */
 593         regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
 594         regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
 595
 596         ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 597                                 sizeof(regs));
 598         if (ret) {
 599                 dev_err(dev, "can't set alarm time\n");
 600                 return ret;
 601         }
 602
 603         /* optionally enable ALARM1 */
 604         if (t->enabled) {
 605                 dev_dbg(dev, "alarm IRQ armed\n");
 606                 regs[7] |= DS1337_BIT_A1IE;     /* only ALARM1 is used */
 607                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
 614 {
 615         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 616
 617         if (!test_bit(HAS_ALARM, &ds1307->flags))
 618                 return -ENOTTY;
 619
 620         return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 621                                   DS1337_BIT_A1IE,
 622                                   enabled ? DS1337_BIT_A1IE : 0);
 623 }
 624
 625 static const struct rtc_class_ops ds13xx_rtc_ops = {
 626         .read_time      = ds1307_get_time,
 627         .set_time       = ds1307_set_time,
 628         .read_alarm     = ds1337_read_alarm,
 629         .set_alarm      = ds1337_set_alarm,
 630         .alarm_irq_enable = ds1307_alarm_irq_enable,
 631 };
 632
 633 /*----------------------------------------------------------------------*/
 634
 635 /*
 636  * Alarm support for rx8130 devices.
 637  */
 638
 639 #define RX8130_REG_ALARM_MIN            0x07
 640 #define RX8130_REG_ALARM_HOUR           0x08
 641 #define RX8130_REG_ALARM_WEEK_OR_DAY    0x09
 642 #define RX8130_REG_EXTENSION            0x0c
 643 #define RX8130_REG_EXTENSION_WADA       BIT(3)
 644 #define RX8130_REG_FLAG                 0x0d
 645 #define RX8130_REG_FLAG_AF              BIT(3)
 646 #define RX8130_REG_CONTROL0             0x0e
 647 #define RX8130_REG_CONTROL0_AIE         BIT(3)
 648
 649 static irqreturn_t rx8130_irq(int irq, void *dev_id)
 650 {
 651         struct ds1307           *ds1307 = dev_id;
 652         struct mutex            *lock = &ds1307->rtc->ops_lock;
 653         u8 ctl[3];
 654         int ret;
 655
 656         mutex_lock(lock);
 657
 658         /* Read control registers. */
 659         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 660                                sizeof(ctl));
 661         if (ret < 0)
 662                 goto out;
 663         if (!(ctl[1] & RX8130_REG_FLAG_AF))
 664                 goto out;
 665         ctl[1] &= ~RX8130_REG_FLAG_AF;
 666         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 667
 668         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 669                                 sizeof(ctl));
 670         if (ret < 0)
 671                 goto out;
 672
 673         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 674
 675 out:
 676         mutex_unlock(lock);
 677
 678         return IRQ_HANDLED;
 679 }
 680
 681 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 682 {
 683         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 684         u8 ald[3], ctl[3];
 685         int ret;
 686
 687         if (!test_bit(HAS_ALARM, &ds1307->flags))
 688                 return -EINVAL;
 689
 690         /* Read alarm registers. */
 691         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 692                                sizeof(ald));
 693         if (ret < 0)
 694                 return ret;
 695
 696         /* Read control registers. */
 697         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 698                                sizeof(ctl));
 699         if (ret < 0)
 700                 return ret;
 701
 702         t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
 703         t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
 704
 705         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 706         t->time.tm_sec = -1;
 707         t->time.tm_min = bcd2bin(ald[0] & 0x7f);
 708         t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
 709         t->time.tm_wday = -1;
 710         t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
 711         t->time.tm_mon = -1;
 712         t->time.tm_year = -1;
 713         t->time.tm_yday = -1;
 714         t->time.tm_isdst = -1;
 715
 716         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
 717                 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 718                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
 719
 720         return 0;
 721 }
 722
 723 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 724 {
 725         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 726         u8 ald[3], ctl[3];
 727         int ret;
 728
 729         if (!test_bit(HAS_ALARM, &ds1307->flags))
 730                 return -EINVAL;
 731
 732         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 733                 "enabled=%d pending=%d\n", __func__,
 734                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 735                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 736                 t->enabled, t->pending);
 737
 738         /* Read control registers. */
 739         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 740                                sizeof(ctl));
 741         if (ret < 0)
 742                 return ret;
 743
 744         ctl[0] &= RX8130_REG_EXTENSION_WADA;
 745         ctl[1] &= ~RX8130_REG_FLAG_AF;
 746         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 747
 748         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 749                                 sizeof(ctl));
 750         if (ret < 0)
 751                 return ret;
 752
 753         /* Hardware alarm precision is 1 minute! */
 754         ald[0] = bin2bcd(t->time.tm_min);
 755         ald[1] = bin2bcd(t->time.tm_hour);
 756         ald[2] = bin2bcd(t->time.tm_mday);
 757
 758         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 759                                 sizeof(ald));
 760         if (ret < 0)
 761                 return ret;
 762
 763         if (!t->enabled)
 764                 return 0;
 765
 766         ctl[2] |= RX8130_REG_CONTROL0_AIE;
 767
 768         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
 769 }
 770
 771 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
 772 {
 773         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 774         int ret, reg;
 775
 776         if (!test_bit(HAS_ALARM, &ds1307->flags))
 777                 return -EINVAL;
 778
 779         ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
 780         if (ret < 0)
 781                 return ret;
 782
 783         if (enabled)
 784                 reg |= RX8130_REG_CONTROL0_AIE;
 785         else
 786                 reg &= ~RX8130_REG_CONTROL0_AIE;
 787
 788         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
 789 }
 790
 791 /*----------------------------------------------------------------------*/
 792
 793 /*
 794  * Alarm support for mcp794xx devices.
 795  */
 796
 797 #define MCP794XX_REG_WEEKDAY            0x3
 798 #define MCP794XX_REG_WEEKDAY_WDAY_MASK  0x7
 799 #define MCP794XX_REG_CONTROL            0x07
 800 #       define MCP794XX_BIT_ALM0_EN     0x10
 801 #       define MCP794XX_BIT_ALM1_EN     0x20
 802 #define MCP794XX_REG_ALARM0_BASE        0x0a
 803 #define MCP794XX_REG_ALARM0_CTRL        0x0d
 804 #define MCP794XX_REG_ALARM1_BASE        0x11
 805 #define MCP794XX_REG_ALARM1_CTRL        0x14
 806 #       define MCP794XX_BIT_ALMX_IF     BIT(3)
 807 #       define MCP794XX_BIT_ALMX_C0     BIT(4)
 808 #       define MCP794XX_BIT_ALMX_C1     BIT(5)
 809 #       define MCP794XX_BIT_ALMX_C2     BIT(6)
 810 #       define MCP794XX_BIT_ALMX_POL    BIT(7)
 811 #       define MCP794XX_MSK_ALMX_MATCH  (MCP794XX_BIT_ALMX_C0 | \
 812                                          MCP794XX_BIT_ALMX_C1 | \
 813                                          MCP794XX_BIT_ALMX_C2)
 814
 815 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
 816 {
 817         struct ds1307           *ds1307 = dev_id;
 818         struct mutex            *lock = &ds1307->rtc->ops_lock;
 819         int reg, ret;
 820
 821         mutex_lock(lock);
 822
 823         /* Check and clear alarm 0 interrupt flag. */
 824         ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
 825         if (ret)
 826                 goto out;
 827         if (!(reg & MCP794XX_BIT_ALMX_IF))
 828                 goto out;
 829         reg &= ~MCP794XX_BIT_ALMX_IF;
 830         ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
 831         if (ret)
 832                 goto out;
 833
 834         /* Disable alarm 0. */
 835         ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 836                                  MCP794XX_BIT_ALM0_EN, 0);
 837         if (ret)
 838                 goto out;
 839
 840         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 841
 842 out:
 843         mutex_unlock(lock);
 844
 845         return IRQ_HANDLED;
 846 }
 847
 848 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 849 {
 850         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 851         u8 regs[10];
 852         int ret;
 853
 854         if (!test_bit(HAS_ALARM, &ds1307->flags))
 855                 return -EINVAL;
 856
 857         /* Read control and alarm 0 registers. */
 858         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 859                                sizeof(regs));
 860         if (ret)
 861                 return ret;
 862
 863         t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
 864
 865         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 866         t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
 867         t->time.tm_min = bcd2bin(regs[4] & 0x7f);
 868         t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
 869         t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
 870         t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
 871         t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
 872         t->time.tm_year = -1;
 873         t->time.tm_yday = -1;
 874         t->time.tm_isdst = -1;
 875
 876         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 877                 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
 878                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 879                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
 880                 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
 881                 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
 882                 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
 883
 884         return 0;
 885 }
 886
 887 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 888 {
 889         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 890         unsigned char regs[10];
 891         int ret;
 892
 893         if (!test_bit(HAS_ALARM, &ds1307->flags))
 894                 return -EINVAL;
 895
 896         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 897                 "enabled=%d pending=%d\n", __func__,
 898                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 899                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 900                 t->enabled, t->pending);
 901
 902         /* Read control and alarm 0 registers. */
 903         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 904                                sizeof(regs));
 905         if (ret)
 906                 return ret;
 907
 908         /* Set alarm 0, using 24-hour and day-of-month modes. */
 909         regs[3] = bin2bcd(t->time.tm_sec);
 910         regs[4] = bin2bcd(t->time.tm_min);
 911         regs[5] = bin2bcd(t->time.tm_hour);
 912         regs[6] = bin2bcd(t->time.tm_wday + 1);
 913         regs[7] = bin2bcd(t->time.tm_mday);
 914         regs[8] = bin2bcd(t->time.tm_mon + 1);
 915
 916         /* Clear the alarm 0 interrupt flag. */
 917         regs[6] &= ~MCP794XX_BIT_ALMX_IF;
 918         /* Set alarm match: second, minute, hour, day, date, month. */
 919         regs[6] |= MCP794XX_MSK_ALMX_MATCH;
 920         /* Disable interrupt. We will not enable until completely programmed */
 921         regs[0] &= ~MCP794XX_BIT_ALM0_EN;
 922
 923         ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 924                                 sizeof(regs));
 925         if (ret)
 926                 return ret;
 927
 928         if (!t->enabled)
 929                 return 0;
 930         regs[0] |= MCP794XX_BIT_ALM0_EN;
 931         return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
 932 }
 933
 934 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 935 {
 936         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 937
 938         if (!test_bit(HAS_ALARM, &ds1307->flags))
 939                 return -EINVAL;
 940
 941         return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 942                                   MCP794XX_BIT_ALM0_EN,
 943                                   enabled ? MCP794XX_BIT_ALM0_EN : 0);
 944 }
 945
 946 /*----------------------------------------------------------------------*/
 947
 948 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
 949                              size_t bytes)
 950 {
 951         struct ds1307 *ds1307 = priv;
 952         const struct chip_desc *chip = &chips[ds1307->type];
 953
 954         return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
 955                                 val, bytes);
 956 }
 957
 958 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
 959                               size_t bytes)
 960 {
 961         struct ds1307 *ds1307 = priv;
 962         const struct chip_desc *chip = &chips[ds1307->type];
 963
 964         return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
 965                                  val, bytes);
 966 }
 967
 968 /*----------------------------------------------------------------------*/
 969
 970 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
 971                                   u32 ohms, bool diode)
 972 {
 973         u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
 974                 DS1307_TRICKLE_CHARGER_NO_DIODE;
 975
 976         switch (ohms) {
 977         case 250:
 978                 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
 979                 break;
 980         case 2000:
 981                 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
 982                 break;
 983         case 4000:
 984                 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
 985                 break;
 986         default:
 987                 dev_warn(ds1307->dev,
 988                          "Unsupported ohm value %u in dt\n", ohms);
 989                 return 0;
 990         }
 991         return setup;
 992 }
 993
 994 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
 995                               const struct chip_desc *chip)
 996 {
 997         u32 ohms;
 998         bool diode = true;
 999
1000         if (!chip->do_trickle_setup)
1001                 return 0;
1002
1003         if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1004                                      &ohms))
1005                 return 0;
1006
1007         if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1008                 diode = false;
1009
1010         return chip->do_trickle_setup(ds1307, ohms, diode);
1011 }
1012
1013 /*----------------------------------------------------------------------*/
1014
1015 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
1016
1017 /*
1018  * Temperature sensor support for ds3231 devices.
1019  */
1020
1021 #define DS3231_REG_TEMPERATURE  0x11
1022
1023 /*
1024  * A user-initiated temperature conversion is not started by this function,
1025  * so the temperature is updated once every 64 seconds.
1026  */
1027 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1028 {
1029         struct ds1307 *ds1307 = dev_get_drvdata(dev);
1030         u8 temp_buf[2];
1031         s16 temp;
1032         int ret;
1033
1034         ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1035                                temp_buf, sizeof(temp_buf));
1036         if (ret)
1037                 return ret;
1038         /*
1039          * Temperature is represented as a 10-bit code with a resolution of
1040          * 0.25 degree celsius and encoded in two's complement format.
1041          */
1042         temp = (temp_buf[0] << 8) | temp_buf[1];
1043         temp >>= 6;
1044         *mC = temp * 250;
1045
1046         return 0;
1047 }
1048
1049 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1050                                       struct device_attribute *attr, char *buf)
1051 {
1052         int ret;
1053         s32 temp;
1054
1055         ret = ds3231_hwmon_read_temp(dev, &temp);
1056         if (ret)
1057                 return ret;
1058
1059         return sprintf(buf, "%d\n", temp);
1060 }
1061 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1062                           NULL, 0);
1063
1064 static struct attribute *ds3231_hwmon_attrs[] = {
1065         &sensor_dev_attr_temp1_input.dev_attr.attr,
1066         NULL,
1067 };
1068 ATTRIBUTE_GROUPS(ds3231_hwmon);
1069
1070 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1071 {
1072         struct device *dev;
1073
1074         if (ds1307->type != ds_3231)
1075                 return;
1076
1077         dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1078                                                      ds1307,
1079                                                      ds3231_hwmon_groups);
1080         if (IS_ERR(dev)) {
1081                 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1082                          PTR_ERR(dev));
1083         }
1084 }
1085
1086 #else
1087
1088 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1089 {
1090 }
1091
1092 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1093
1094 /*----------------------------------------------------------------------*/
1095
1096 /*
1097  * Square-wave output support for DS3231
1098  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1099  */
1100 #ifdef CONFIG_COMMON_CLK
1101
1102 enum {
1103         DS3231_CLK_SQW = 0,
1104         DS3231_CLK_32KHZ,
1105 };
1106
1107 #define clk_sqw_to_ds1307(clk)  \
1108         container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1109 #define clk_32khz_to_ds1307(clk)        \
1110         container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1111
1112 static int ds3231_clk_sqw_rates[] = {
1113         1,
1114         1024,
1115         4096,
1116         8192,
1117 };
1118
1119 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1120 {
1121         struct mutex *lock = &ds1307->rtc->ops_lock;
1122         int ret;
1123
1124         mutex_lock(lock);
1125         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1126                                  mask, value);
1127         mutex_unlock(lock);
1128
1129         return ret;
1130 }
1131
1132 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1133                                                 unsigned long parent_rate)
1134 {
1135         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1136         int control, ret;
1137         int rate_sel = 0;
1138
1139         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1140         if (ret)
1141                 return ret;
1142         if (control & DS1337_BIT_RS1)
1143                 rate_sel += 1;
1144         if (control & DS1337_BIT_RS2)
1145                 rate_sel += 2;
1146
1147         return ds3231_clk_sqw_rates[rate_sel];
1148 }
1149
1150 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1151                                       unsigned long *prate)
1152 {
1153         int i;
1154
1155         for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1156                 if (ds3231_clk_sqw_rates[i] <= rate)
1157                         return ds3231_clk_sqw_rates[i];
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1164                                    unsigned long parent_rate)
1165 {
1166         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1167         int control = 0;
1168         int rate_sel;
1169
1170         for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1171                         rate_sel++) {
1172                 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1173                         break;
1174         }
1175
1176         if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1177                 return -EINVAL;
1178
1179         if (rate_sel & 1)
1180                 control |= DS1337_BIT_RS1;
1181         if (rate_sel & 2)
1182                 control |= DS1337_BIT_RS2;
1183
1184         return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1185                                 control);
1186 }
1187
1188 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1189 {
1190         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1191
1192         return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1193 }
1194
1195 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1196 {
1197         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1198
1199         ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1200 }
1201
1202 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1203 {
1204         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1205         int control, ret;
1206
1207         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1208         if (ret)
1209                 return ret;
1210
1211         return !(control & DS1337_BIT_INTCN);
1212 }
1213
1214 static const struct clk_ops ds3231_clk_sqw_ops = {
1215         .prepare = ds3231_clk_sqw_prepare,
1216         .unprepare = ds3231_clk_sqw_unprepare,
1217         .is_prepared = ds3231_clk_sqw_is_prepared,
1218         .recalc_rate = ds3231_clk_sqw_recalc_rate,
1219         .round_rate = ds3231_clk_sqw_round_rate,
1220         .set_rate = ds3231_clk_sqw_set_rate,
1221 };
1222
1223 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1224                                                   unsigned long parent_rate)
1225 {
1226         return 32768;
1227 }
1228
1229 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1230 {
1231         struct mutex *lock = &ds1307->rtc->ops_lock;
1232         int ret;
1233
1234         mutex_lock(lock);
1235         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1236                                  DS3231_BIT_EN32KHZ,
1237                                  enable ? DS3231_BIT_EN32KHZ : 0);
1238         mutex_unlock(lock);
1239
1240         return ret;
1241 }
1242
1243 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1244 {
1245         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1246
1247         return ds3231_clk_32khz_control(ds1307, true);
1248 }
1249
1250 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1251 {
1252         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1253
1254         ds3231_clk_32khz_control(ds1307, false);
1255 }
1256
1257 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1258 {
1259         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1260         int status, ret;
1261
1262         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1263         if (ret)
1264                 return ret;
1265
1266         return !!(status & DS3231_BIT_EN32KHZ);
1267 }
1268
1269 static const struct clk_ops ds3231_clk_32khz_ops = {
1270         .prepare = ds3231_clk_32khz_prepare,
1271         .unprepare = ds3231_clk_32khz_unprepare,
1272         .is_prepared = ds3231_clk_32khz_is_prepared,
1273         .recalc_rate = ds3231_clk_32khz_recalc_rate,
1274 };
1275
1276 static struct clk_init_data ds3231_clks_init[] = {
1277         [DS3231_CLK_SQW] = {
1278                 .name = "ds3231_clk_sqw",
1279                 .ops = &ds3231_clk_sqw_ops,
1280         },
1281         [DS3231_CLK_32KHZ] = {
1282                 .name = "ds3231_clk_32khz",
1283                 .ops = &ds3231_clk_32khz_ops,
1284         },
1285 };
1286
1287 static int ds3231_clks_register(struct ds1307 *ds1307)
1288 {
1289         struct device_node *node = ds1307->dev->of_node;
1290         struct clk_onecell_data *onecell;
1291         int i;
1292
1293         onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1294         if (!onecell)
1295                 return -ENOMEM;
1296
1297         onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1298         onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1299                                      sizeof(onecell->clks[0]), GFP_KERNEL);
1300         if (!onecell->clks)
1301                 return -ENOMEM;
1302
1303         for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1304                 struct clk_init_data init = ds3231_clks_init[i];
1305
1306                 /*
1307                  * Interrupt signal due to alarm conditions and square-wave
1308                  * output share same pin, so don't initialize both.
1309                  */
1310                 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1311                         continue;
1312
1313                 /* optional override of the clockname */
1314                 of_property_read_string_index(node, "clock-output-names", i,
1315                                               &init.name);
1316                 ds1307->clks[i].init = &init;
1317
1318                 onecell->clks[i] = devm_clk_register(ds1307->dev,
1319                                                      &ds1307->clks[i]);
1320                 if (IS_ERR(onecell->clks[i]))
1321                         return PTR_ERR(onecell->clks[i]);
1322         }
1323
1324         if (!node)
1325                 return 0;
1326
1327         of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1328
1329         return 0;
1330 }
1331
1332 static void ds1307_clks_register(struct ds1307 *ds1307)
1333 {
1334         int ret;
1335
1336         if (ds1307->type != ds_3231)
1337                 return;
1338
1339         ret = ds3231_clks_register(ds1307);
1340         if (ret) {
1341                 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1342                          ret);
1343         }
1344 }
1345
1346 #else
1347
1348 static void ds1307_clks_register(struct ds1307 *ds1307)
1349 {
1350 }
1351
1352 #endif /* CONFIG_COMMON_CLK */
1353
1354 static const struct regmap_config regmap_config = {
1355         .reg_bits = 8,
1356         .val_bits = 8,
1357 };
1358
1359 static int ds1307_probe(struct i2c_client *client,
1360                         const struct i2c_device_id *id)
1361 {
1362         struct ds1307           *ds1307;
1363         int                     err = -ENODEV;
1364         int                     tmp, wday;
1365         const struct chip_desc  *chip;
1366         bool                    want_irq;
1367         bool                    ds1307_can_wakeup_device = false;
1368         unsigned char           regs[8];
1369         struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1370         struct rtc_time         tm;
1371         unsigned long           timestamp;
1372         u8                      trickle_charger_setup = 0;
1373
1374         ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1375         if (!ds1307)
1376                 return -ENOMEM;
1377
1378         dev_set_drvdata(&client->dev, ds1307);
1379         ds1307->dev = &client->dev;
1380         ds1307->name = client->name;
1381
1382         ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1383         if (IS_ERR(ds1307->regmap)) {
1384                 dev_err(ds1307->dev, "regmap allocation failed\n");
1385                 return PTR_ERR(ds1307->regmap);
1386         }
1387
1388         i2c_set_clientdata(client, ds1307);
1389
1390         if (client->dev.of_node) {
1391                 ds1307->type = (enum ds_type)
1392                         of_device_get_match_data(&client->dev);
1393                 chip = &chips[ds1307->type];
1394         } else if (id) {
1395                 chip = &chips[id->driver_data];
1396                 ds1307->type = id->driver_data;
1397         } else {
1398                 const struct acpi_device_id *acpi_id;
1399
1400                 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1401                                             ds1307->dev);
1402                 if (!acpi_id)
1403                         return -ENODEV;
1404                 chip = &chips[acpi_id->driver_data];
1405                 ds1307->type = acpi_id->driver_data;
1406         }
1407
1408         want_irq = client->irq > 0 && chip->alarm;
1409
1410         if (!pdata)
1411                 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1412         else if (pdata->trickle_charger_setup)
1413                 trickle_charger_setup = pdata->trickle_charger_setup;
1414
1415         if (trickle_charger_setup && chip->trickle_charger_reg) {
1416                 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1417                 dev_dbg(ds1307->dev,
1418                         "writing trickle charger info 0x%x to 0x%x\n",
1419                         trickle_charger_setup, chip->trickle_charger_reg);
1420                 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1421                              trickle_charger_setup);
1422         }
1423
1424 #ifdef CONFIG_OF
1425 /*
1426  * For devices with no IRQ directly connected to the SoC, the RTC chip
1427  * can be forced as a wakeup source by stating that explicitly in
1428  * the device's .dts file using the "wakeup-source" boolean property.
1429  * If the "wakeup-source" property is set, don't request an IRQ.
1430  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1431  * if supported by the RTC.
1432  */
1433         if (chip->alarm && of_property_read_bool(client->dev.of_node,
1434                                                  "wakeup-source"))
1435                 ds1307_can_wakeup_device = true;
1436 #endif
1437
1438         switch (ds1307->type) {
1439         case ds_1337:
1440         case ds_1339:
1441         case ds_1341:
1442         case ds_3231:
1443                 /* get registers that the "rtc" read below won't read... */
1444                 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1445                                        regs, 2);
1446                 if (err) {
1447                         dev_dbg(ds1307->dev, "read error %d\n", err);
1448                         goto exit;
1449                 }
1450
1451                 /* oscillator off?  turn it on, so clock can tick. */
1452                 if (regs[0] & DS1337_BIT_nEOSC)
1453                         regs[0] &= ~DS1337_BIT_nEOSC;
1454
1455                 /*
1456                  * Using IRQ or defined as wakeup-source?
1457                  * Disable the square wave and both alarms.
1458                  * For some variants, be sure alarms can trigger when we're
1459                  * running on Vbackup (BBSQI/BBSQW)
1460                  */
1461                 if (want_irq || ds1307_can_wakeup_device) {
1462                         regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1463                         regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1464                 }
1465
1466                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1467                              regs[0]);
1468
1469                 /* oscillator fault?  clear flag, and warn */
1470                 if (regs[1] & DS1337_BIT_OSF) {
1471                         regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1472                                      regs[1] & ~DS1337_BIT_OSF);
1473                         dev_warn(ds1307->dev, "SET TIME!\n");
1474                 }
1475                 break;
1476
1477         case rx_8025:
1478                 err = regmap_bulk_read(ds1307->regmap,
1479                                        RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1480                 if (err) {
1481                         dev_dbg(ds1307->dev, "read error %d\n", err);
1482                         goto exit;
1483                 }
1484
1485                 /* oscillator off?  turn it on, so clock can tick. */
1486                 if (!(regs[1] & RX8025_BIT_XST)) {
1487                         regs[1] |= RX8025_BIT_XST;
1488                         regmap_write(ds1307->regmap,
1489                                      RX8025_REG_CTRL2 << 4 | 0x08,
1490                                      regs[1]);
1491                         dev_warn(ds1307->dev,
1492                                  "oscillator stop detected - SET TIME!\n");
1493                 }
1494
1495                 if (regs[1] & RX8025_BIT_PON) {
1496                         regs[1] &= ~RX8025_BIT_PON;
1497                         regmap_write(ds1307->regmap,
1498                                      RX8025_REG_CTRL2 << 4 | 0x08,
1499                                      regs[1]);
1500                         dev_warn(ds1307->dev, "power-on detected\n");
1501                 }
1502
1503                 if (regs[1] & RX8025_BIT_VDET) {
1504                         regs[1] &= ~RX8025_BIT_VDET;
1505                         regmap_write(ds1307->regmap,
1506                                      RX8025_REG_CTRL2 << 4 | 0x08,
1507                                      regs[1]);
1508                         dev_warn(ds1307->dev, "voltage drop detected\n");
1509                 }
1510
1511                 /* make sure we are running in 24hour mode */
1512                 if (!(regs[0] & RX8025_BIT_2412)) {
1513                         u8 hour;
1514
1515                         /* switch to 24 hour mode */
1516                         regmap_write(ds1307->regmap,
1517                                      RX8025_REG_CTRL1 << 4 | 0x08,
1518                                      regs[0] | RX8025_BIT_2412);
1519
1520                         err = regmap_bulk_read(ds1307->regmap,
1521                                                RX8025_REG_CTRL1 << 4 | 0x08,
1522                                                regs, 2);
1523                         if (err) {
1524                                 dev_dbg(ds1307->dev, "read error %d\n", err);
1525                                 goto exit;
1526                         }
1527
1528                         /* correct hour */
1529                         hour = bcd2bin(regs[DS1307_REG_HOUR]);
1530                         if (hour == 12)
1531                                 hour = 0;
1532                         if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1533                                 hour += 12;
1534
1535                         regmap_write(ds1307->regmap,
1536                                      DS1307_REG_HOUR << 4 | 0x08, hour);
1537                 }
1538                 break;
1539         default:
1540                 break;
1541         }
1542
1543 read_rtc:
1544         /* read RTC registers */
1545         err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1546                                sizeof(regs));
1547         if (err) {
1548                 dev_dbg(ds1307->dev, "read error %d\n", err);
1549                 goto exit;
1550         }
1551
1552         /*
1553          * minimal sanity checking; some chips (like DS1340) don't
1554          * specify the extra bits as must-be-zero, but there are
1555          * still a few values that are clearly out-of-range.
1556          */
1557         tmp = regs[DS1307_REG_SECS];
1558         switch (ds1307->type) {
1559         case ds_1307:
1560         case m41t0:
1561         case m41t00:
1562                 /* clock halted?  turn it on, so clock can tick. */
1563                 if (tmp & DS1307_BIT_CH) {
1564                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1565                         dev_warn(ds1307->dev, "SET TIME!\n");
1566                         goto read_rtc;
1567                 }
1568                 break;
1569         case ds_1308:
1570         case ds_1338:
1571                 /* clock halted?  turn it on, so clock can tick. */
1572                 if (tmp & DS1307_BIT_CH)
1573                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1574
1575                 /* oscillator fault?  clear flag, and warn */
1576                 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1577                         regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1578                                      regs[DS1307_REG_CONTROL] &
1579                                      ~DS1338_BIT_OSF);
1580                         dev_warn(ds1307->dev, "SET TIME!\n");
1581                         goto read_rtc;
1582                 }
1583                 break;
1584         case ds_1340:
1585                 /* clock halted?  turn it on, so clock can tick. */
1586                 if (tmp & DS1340_BIT_nEOSC)
1587                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1588
1589                 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1590                 if (err) {
1591                         dev_dbg(ds1307->dev, "read error %d\n", err);
1592                         goto exit;
1593                 }
1594
1595                 /* oscillator fault?  clear flag, and warn */
1596                 if (tmp & DS1340_BIT_OSF) {
1597                         regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1598                         dev_warn(ds1307->dev, "SET TIME!\n");
1599                 }
1600                 break;
1601         case mcp794xx:
1602                 /* make sure that the backup battery is enabled */
1603                 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1604                         regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1605                                      regs[DS1307_REG_WDAY] |
1606                                      MCP794XX_BIT_VBATEN);
1607                 }
1608
1609                 /* clock halted?  turn it on, so clock can tick. */
1610                 if (!(tmp & MCP794XX_BIT_ST)) {
1611                         regmap_write(ds1307->regmap, DS1307_REG_SECS,
1612                                      MCP794XX_BIT_ST);
1613                         dev_warn(ds1307->dev, "SET TIME!\n");
1614                         goto read_rtc;
1615                 }
1616
1617                 break;
1618         default:
1619                 break;
1620         }
1621
1622         tmp = regs[DS1307_REG_HOUR];
1623         switch (ds1307->type) {
1624         case ds_1340:
1625         case m41t0:
1626         case m41t00:
1627                 /*
1628                  * NOTE: ignores century bits; fix before deploying
1629                  * systems that will run through year 2100.
1630                  */
1631                 break;
1632         case rx_8025:
1633                 break;
1634         default:
1635                 if (!(tmp & DS1307_BIT_12HR))
1636                         break;
1637
1638                 /*
1639                  * Be sure we're in 24 hour mode.  Multi-master systems
1640                  * take note...
1641                  */
1642                 tmp = bcd2bin(tmp & 0x1f);
1643                 if (tmp == 12)
1644                         tmp = 0;
1645                 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1646                         tmp += 12;
1647                 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1648                              bin2bcd(tmp));
1649         }
1650
1651         /*
1652          * Some IPs have weekday reset value = 0x1 which might not correct
1653          * hence compute the wday using the current date/month/year values
1654          */
1655         ds1307_get_time(ds1307->dev, &tm);
1656         wday = tm.tm_wday;
1657         timestamp = rtc_tm_to_time64(&tm);
1658         rtc_time64_to_tm(timestamp, &tm);
1659
1660         /*
1661          * Check if reset wday is different from the computed wday
1662          * If different then set the wday which we computed using
1663          * timestamp
1664          */
1665         if (wday != tm.tm_wday)
1666                 regmap_update_bits(ds1307->regmap, MCP794XX_REG_WEEKDAY,
1667                                    MCP794XX_REG_WEEKDAY_WDAY_MASK,
1668                                    tm.tm_wday + 1);
1669
1670         if (want_irq || ds1307_can_wakeup_device) {
1671                 device_set_wakeup_capable(ds1307->dev, true);
1672                 set_bit(HAS_ALARM, &ds1307->flags);
1673         }
1674
1675         ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1676         if (IS_ERR(ds1307->rtc))
1677                 return PTR_ERR(ds1307->rtc);
1678
1679         if (ds1307_can_wakeup_device && !want_irq) {
1680                 dev_info(ds1307->dev,
1681                          "'wakeup-source' is set, request for an IRQ is disabled!\n");
1682                 /* We cannot support UIE mode if we do not have an IRQ line */
1683                 ds1307->rtc->uie_unsupported = 1;
1684         }
1685
1686         if (want_irq) {
1687                 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1688                                                 chip->irq_handler ?: ds1307_irq,
1689                                                 IRQF_SHARED | IRQF_ONESHOT,
1690                                                 ds1307->name, ds1307);
1691                 if (err) {
1692                         client->irq = 0;
1693                         device_set_wakeup_capable(ds1307->dev, false);
1694                         clear_bit(HAS_ALARM, &ds1307->flags);
1695                         dev_err(ds1307->dev, "unable to request IRQ!\n");
1696                 } else {
1697                         dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1698                 }
1699         }
1700
1701         if (chip->nvram_size) {
1702                 ds1307->nvmem_cfg.name = "ds1307_nvram";
1703                 ds1307->nvmem_cfg.word_size = 1;
1704                 ds1307->nvmem_cfg.stride = 1;
1705                 ds1307->nvmem_cfg.size = chip->nvram_size;
1706                 ds1307->nvmem_cfg.reg_read = ds1307_nvram_read;
1707                 ds1307->nvmem_cfg.reg_write = ds1307_nvram_write;
1708                 ds1307->nvmem_cfg.priv = ds1307;
1709
1710                 ds1307->rtc->nvmem_config = &ds1307->nvmem_cfg;
1711                 ds1307->rtc->nvram_old_abi = true;
1712         }
1713
1714         ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1715         err = rtc_register_device(ds1307->rtc);
1716         if (err)
1717                 return err;
1718
1719         ds1307_hwmon_register(ds1307);
1720         ds1307_clks_register(ds1307);
1721
1722         return 0;
1723
1724 exit:
1725         return err;
1726 }
1727
1728 static struct i2c_driver ds1307_driver = {
1729         .driver = {
1730                 .name   = "rtc-ds1307",
1731                 .of_match_table = of_match_ptr(ds1307_of_match),
1732                 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1733         },
1734         .probe          = ds1307_probe,
1735         .id_table       = ds1307_id,
1736 };
1737
1738 module_i2c_driver(ds1307_driver);
1739
1740 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1741 MODULE_LICENSE("GPL");