drivers/reset/reset-simple.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Simple Reset Controller Driver
   4  *
   5  * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
   6  *
   7  * Based on Allwinner SoCs Reset Controller driver
   8  *
   9  * Copyright 2013 Maxime Ripard
  10  *
  11  * Maxime Ripard <maxime.ripard@free-electrons.com>
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/device.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reset-controller.h>
  22 #include <linux/reset/reset-simple.h>
  23 #include <linux/spinlock.h>
  24
  25 static inline struct reset_simple_data *
  26 to_reset_simple_data(struct reset_controller_dev *rcdev)
  27 {
  28         return container_of(rcdev, struct reset_simple_data, rcdev);
  29 }
  30
  31 static int reset_simple_update(struct reset_controller_dev *rcdev,
  32                                unsigned long id, bool assert)
  33 {
  34         struct reset_simple_data *data = to_reset_simple_data(rcdev);
  35         int reg_width = sizeof(u32);
  36         int bank = id / (reg_width * BITS_PER_BYTE);
  37         int offset = id % (reg_width * BITS_PER_BYTE);
  38         unsigned long flags;
  39         u32 reg;
  40
  41         spin_lock_irqsave(&data->lock, flags);
  42
  43         reg = readl(data->membase + (bank * reg_width));
  44         if (assert ^ data->active_low)
  45                 reg |= BIT(offset);
  46         else
  47                 reg &= ~BIT(offset);
  48         writel(reg, data->membase + (bank * reg_width));
  49
  50         spin_unlock_irqrestore(&data->lock, flags);
  51
  52         return 0;
  53 }
  54
  55 static int reset_simple_assert(struct reset_controller_dev *rcdev,
  56                                unsigned long id)
  57 {
  58         return reset_simple_update(rcdev, id, true);
  59 }
  60
  61 static int reset_simple_deassert(struct reset_controller_dev *rcdev,
  62                                  unsigned long id)
  63 {
  64         return reset_simple_update(rcdev, id, false);
  65 }
  66
  67 static int reset_simple_reset(struct reset_controller_dev *rcdev,
  68                               unsigned long id)
  69 {
  70         struct reset_simple_data *data = to_reset_simple_data(rcdev);
  71         int ret;
  72
  73         if (!data->reset_us)
  74                 return -ENOTSUPP;
  75
  76         ret = reset_simple_assert(rcdev, id);
  77         if (ret)
  78                 return ret;
  79
  80         usleep_range(data->reset_us, data->reset_us * 2);
  81
  82         return reset_simple_deassert(rcdev, id);
  83 }
  84
  85 static int reset_simple_status(struct reset_controller_dev *rcdev,
  86                                unsigned long id)
  87 {
  88         struct reset_simple_data *data = to_reset_simple_data(rcdev);
  89         int reg_width = sizeof(u32);
  90         int bank = id / (reg_width * BITS_PER_BYTE);
  91         int offset = id % (reg_width * BITS_PER_BYTE);
  92         u32 reg;
  93
  94         reg = readl(data->membase + (bank * reg_width));
  95
  96         return !(reg & BIT(offset)) ^ !data->status_active_low;
  97 }
  98
  99 const struct reset_control_ops reset_simple_ops = {
 100         .assert         = reset_simple_assert,
 101         .deassert       = reset_simple_deassert,
 102         .reset          = reset_simple_reset,
 103         .status         = reset_simple_status,
 104 };
 105 EXPORT_SYMBOL_GPL(reset_simple_ops);
 106
 107 /**
 108  * struct reset_simple_devdata - simple reset controller properties
 109  * @reg_offset: offset between base address and first reset register.
 110  * @nr_resets: number of resets. If not set, default to resource size in bits.
 111  * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
 112  *              are set to assert the reset.
 113  * @status_active_low: if true, bits read back as cleared while the reset is
 114  *                     asserted. Otherwise, bits read back as set while the
 115  *                     reset is asserted.
 116  */
 117 struct reset_simple_devdata {
 118         u32 reg_offset;
 119         u32 nr_resets;
 120         bool active_low;
 121         bool status_active_low;
 122 };
 123
 124 #define SOCFPGA_NR_BANKS        8
 125
 126 static const struct reset_simple_devdata reset_simple_socfpga = {
 127         .reg_offset = 0x20,
 128         .nr_resets = SOCFPGA_NR_BANKS * 32,
 129         .status_active_low = true,
 130 };
 131
 132 static const struct reset_simple_devdata reset_simple_active_low = {
 133         .active_low = true,
 134         .status_active_low = true,
 135 };
 136
 137 static const struct of_device_id reset_simple_dt_ids[] = {
 138         { .compatible = "altr,stratix10-rst-mgr",
 139                 .data = &reset_simple_socfpga },
 140         { .compatible = "st,stm32-rcc", },
 141         { .compatible = "allwinner,sun6i-a31-clock-reset",
 142                 .data = &reset_simple_active_low },
 143         { .compatible = "zte,zx296718-reset",
 144                 .data = &reset_simple_active_low },
 145         { .compatible = "aspeed,ast2400-lpc-reset" },
 146         { .compatible = "aspeed,ast2500-lpc-reset" },
 147         { .compatible = "aspeed,ast2600-lpc-reset" },
 148         { .compatible = "bitmain,bm1880-reset",
 149                 .data = &reset_simple_active_low },
 150         { .compatible = "brcm,bcm4908-misc-pcie-reset",
 151                 .data = &reset_simple_active_low },
 152         { .compatible = "snps,dw-high-reset" },
 153         { .compatible = "snps,dw-low-reset",
 154                 .data = &reset_simple_active_low },
 155         { /* sentinel */ },
 156 };
 157
 158 static int reset_simple_probe(struct platform_device *pdev)
 159 {
 160         struct device *dev = &pdev->dev;
 161         const struct reset_simple_devdata *devdata;
 162         struct reset_simple_data *data;
 163         void __iomem *membase;
 164         struct resource *res;
 165         u32 reg_offset = 0;
 166
 167         devdata = of_device_get_match_data(dev);
 168
 169         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 170         if (!data)
 171                 return -ENOMEM;
 172
 173         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 174         membase = devm_ioremap_resource(dev, res);
 175         if (IS_ERR(membase))
 176                 return PTR_ERR(membase);
 177
 178         spin_lock_init(&data->lock);
 179         data->membase = membase;
 180         data->rcdev.owner = THIS_MODULE;
 181         data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
 182         data->rcdev.ops = &reset_simple_ops;
 183         data->rcdev.of_node = dev->of_node;
 184
 185         if (devdata) {
 186                 reg_offset = devdata->reg_offset;
 187                 if (devdata->nr_resets)
 188                         data->rcdev.nr_resets = devdata->nr_resets;
 189                 data->active_low = devdata->active_low;
 190                 data->status_active_low = devdata->status_active_low;
 191         }
 192
 193         data->membase += reg_offset;
 194
 195         return devm_reset_controller_register(dev, &data->rcdev);
 196 }
 197
 198 static struct platform_driver reset_simple_driver = {
 199         .probe  = reset_simple_probe,
 200         .driver = {
 201                 .name           = "simple-reset",
 202                 .of_match_table = reset_simple_dt_ids,
 203         },
 204 };
 205 builtin_platform_driver(reset_simple_driver);