2 * Qualcomm Peripheral Image Loader
4 * Copyright (C) 2016 Linaro Ltd.
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/remoteproc.h>
31 #include <linux/reset.h>
32 #include <linux/soc/qcom/mdt_loader.h>
33 #include <linux/iopoll.h>
35 #include "remoteproc_internal.h"
36 #include "qcom_common.h"
37 #include "qcom_q6v5.h"
39 #include <linux/qcom_scm.h>
41 #define MPSS_CRASH_REASON_SMEM 421
43 /* RMB Status Register Values */
44 #define RMB_PBL_SUCCESS 0x1
46 #define RMB_MBA_XPU_UNLOCKED 0x1
47 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
48 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
49 #define RMB_MBA_AUTH_COMPLETE 0x4
51 /* PBL/MBA interface registers */
52 #define RMB_MBA_IMAGE_REG 0x00
53 #define RMB_PBL_STATUS_REG 0x04
54 #define RMB_MBA_COMMAND_REG 0x08
55 #define RMB_MBA_STATUS_REG 0x0C
56 #define RMB_PMI_META_DATA_REG 0x10
57 #define RMB_PMI_CODE_START_REG 0x14
58 #define RMB_PMI_CODE_LENGTH_REG 0x18
59 #define RMB_MBA_MSS_STATUS 0x40
60 #define RMB_MBA_ALT_RESET 0x44
62 #define RMB_CMD_META_DATA_READY 0x1
63 #define RMB_CMD_LOAD_READY 0x2
65 /* QDSP6SS Register Offsets */
66 #define QDSP6SS_RESET_REG 0x014
67 #define QDSP6SS_GFMUX_CTL_REG 0x020
68 #define QDSP6SS_PWR_CTL_REG 0x030
69 #define QDSP6SS_MEM_PWR_CTL 0x0B0
70 #define QDSP6SS_STRAP_ACC 0x110
72 /* AXI Halt Register Offsets */
73 #define AXI_HALTREQ_REG 0x0
74 #define AXI_HALTACK_REG 0x4
75 #define AXI_IDLE_REG 0x8
77 #define HALT_ACK_TIMEOUT_MS 100
80 #define Q6SS_STOP_CORE BIT(0)
81 #define Q6SS_CORE_ARES BIT(1)
82 #define Q6SS_BUS_ARES_ENABLE BIT(2)
84 /* QDSP6SS_GFMUX_CTL */
85 #define Q6SS_CLK_ENABLE BIT(1)
88 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
89 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
90 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
91 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
92 #define Q6SS_ETB_SLP_NRET_N BIT(17)
93 #define Q6SS_L2DATA_STBY_N BIT(18)
94 #define Q6SS_SLP_RET_N BIT(19)
95 #define Q6SS_CLAMP_IO BIT(20)
96 #define QDSS_BHS_ON BIT(21)
97 #define QDSS_LDO_BYP BIT(22)
99 /* QDSP6v56 parameters */
100 #define QDSP6v56_LDO_BYP BIT(25)
101 #define QDSP6v56_BHS_ON BIT(24)
102 #define QDSP6v56_CLAMP_WL BIT(21)
103 #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
104 #define HALT_CHECK_MAX_LOOPS 200
105 #define QDSP6SS_XO_CBCR 0x0038
106 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
108 /* QDSP6v65 parameters */
109 #define QDSP6SS_SLEEP 0x3C
110 #define QDSP6SS_BOOT_CORE_START 0x400
111 #define QDSP6SS_BOOT_CMD 0x404
112 #define SLEEP_CHECK_MAX_LOOPS 200
113 #define BOOT_FSM_TIMEOUT 10000
116 struct regulator *reg;
121 struct qcom_mss_reg_res {
127 struct rproc_hexagon_res {
128 const char *hexagon_mba_image;
129 struct qcom_mss_reg_res *proxy_supply;
130 struct qcom_mss_reg_res *active_supply;
131 char **proxy_clk_names;
132 char **reset_clk_names;
133 char **active_clk_names;
135 bool need_mem_protection;
143 void __iomem *reg_base;
144 void __iomem *rmb_base;
146 struct regmap *halt_map;
151 struct reset_control *mss_restart;
153 struct qcom_q6v5 q6v5;
155 struct clk *active_clks[8];
156 struct clk *reset_clks[4];
157 struct clk *proxy_clks[4];
158 int active_clk_count;
162 struct reg_info active_regs[1];
163 struct reg_info proxy_regs[3];
164 int active_reg_count;
169 phys_addr_t mba_phys;
173 phys_addr_t mpss_phys;
174 phys_addr_t mpss_reloc;
178 struct qcom_rproc_glink glink_subdev;
179 struct qcom_rproc_subdev smd_subdev;
180 struct qcom_rproc_ssr ssr_subdev;
181 struct qcom_sysmon *sysmon;
182 bool need_mem_protection;
196 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
197 const struct qcom_mss_reg_res *reg_res)
205 for (i = 0; reg_res[i].supply; i++) {
206 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
207 if (IS_ERR(regs[i].reg)) {
208 rc = PTR_ERR(regs[i].reg);
209 if (rc != -EPROBE_DEFER)
210 dev_err(dev, "Failed to get %s\n regulator",
215 regs[i].uV = reg_res[i].uV;
216 regs[i].uA = reg_res[i].uA;
222 static int q6v5_regulator_enable(struct q6v5 *qproc,
223 struct reg_info *regs, int count)
228 for (i = 0; i < count; i++) {
229 if (regs[i].uV > 0) {
230 ret = regulator_set_voltage(regs[i].reg,
231 regs[i].uV, INT_MAX);
234 "Failed to request voltage for %d.\n",
240 if (regs[i].uA > 0) {
241 ret = regulator_set_load(regs[i].reg,
245 "Failed to set regulator mode\n");
250 ret = regulator_enable(regs[i].reg);
252 dev_err(qproc->dev, "Regulator enable failed\n");
259 for (; i >= 0; i--) {
261 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
264 regulator_set_load(regs[i].reg, 0);
266 regulator_disable(regs[i].reg);
272 static void q6v5_regulator_disable(struct q6v5 *qproc,
273 struct reg_info *regs, int count)
277 for (i = 0; i < count; i++) {
279 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
282 regulator_set_load(regs[i].reg, 0);
284 regulator_disable(regs[i].reg);
288 static int q6v5_clk_enable(struct device *dev,
289 struct clk **clks, int count)
294 for (i = 0; i < count; i++) {
295 rc = clk_prepare_enable(clks[i]);
297 dev_err(dev, "Clock enable failed\n");
304 for (i--; i >= 0; i--)
305 clk_disable_unprepare(clks[i]);
310 static void q6v5_clk_disable(struct device *dev,
311 struct clk **clks, int count)
315 for (i = 0; i < count; i++)
316 clk_disable_unprepare(clks[i]);
319 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
320 bool remote_owner, phys_addr_t addr,
323 struct qcom_scm_vmperm next;
325 if (!qproc->need_mem_protection)
327 if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA))
329 if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS))
332 next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS;
333 next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX;
335 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
336 current_perm, &next, 1);
339 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
341 struct q6v5 *qproc = rproc->priv;
343 /* MBA is restricted to a maximum size of 1M */
344 if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
345 dev_err(qproc->dev, "MBA firmware load failed\n");
349 memcpy(qproc->mba_region, fw->data, fw->size);
354 static int q6v5_reset_assert(struct q6v5 *qproc)
356 if (qproc->has_alt_reset)
357 return reset_control_reset(qproc->mss_restart);
359 return reset_control_assert(qproc->mss_restart);
362 static int q6v5_reset_deassert(struct q6v5 *qproc)
366 if (qproc->has_alt_reset) {
367 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
368 ret = reset_control_reset(qproc->mss_restart);
369 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
371 ret = reset_control_deassert(qproc->mss_restart);
377 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
379 unsigned long timeout;
382 timeout = jiffies + msecs_to_jiffies(ms);
384 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
388 if (time_after(jiffies, timeout))
397 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
400 unsigned long timeout;
403 timeout = jiffies + msecs_to_jiffies(ms);
405 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
411 else if (status && val == status)
414 if (time_after(jiffies, timeout))
423 static int q6v5proc_reset(struct q6v5 *qproc)
429 if (qproc->version == MSS_SDM845) {
430 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
432 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
434 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
435 val, !(val & BIT(31)), 1,
436 SLEEP_CHECK_MAX_LOOPS);
438 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
442 /* De-assert QDSP6 stop core */
443 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
444 /* Trigger boot FSM */
445 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
447 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
448 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
450 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
451 /* Reset the modem so that boot FSM is in reset state */
452 q6v5_reset_deassert(qproc);
457 } else if (qproc->version == MSS_MSM8996) {
458 /* Override the ACC value if required */
459 writel(QDSP6SS_ACC_OVERRIDE_VAL,
460 qproc->reg_base + QDSP6SS_STRAP_ACC);
462 /* Assert resets, stop core */
463 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
464 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
465 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
467 /* BHS require xo cbcr to be enabled */
468 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
470 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
472 /* Read CLKOFF bit to go low indicating CLK is enabled */
473 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
474 val, !(val & BIT(31)), 1,
475 HALT_CHECK_MAX_LOOPS);
478 "xo cbcr enabling timed out (rc:%d)\n", ret);
481 /* Enable power block headswitch and wait for it to stabilize */
482 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
483 val |= QDSP6v56_BHS_ON;
484 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
485 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
488 /* Put LDO in bypass mode */
489 val |= QDSP6v56_LDO_BYP;
490 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
492 /* Deassert QDSP6 compiler memory clamp */
493 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
494 val &= ~QDSP6v56_CLAMP_QMC_MEM;
495 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
497 /* Deassert memory peripheral sleep and L2 memory standby */
498 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
499 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
501 /* Turn on L1, L2, ETB and JU memories 1 at a time */
502 val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
503 for (i = 19; i >= 0; i--) {
505 writel(val, qproc->reg_base +
506 QDSP6SS_MEM_PWR_CTL);
508 * Read back value to ensure the write is done then
509 * wait for 1us for both memory peripheral and data
512 val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
515 /* Remove word line clamp */
516 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
517 val &= ~QDSP6v56_CLAMP_WL;
518 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
520 /* Assert resets, stop core */
521 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
522 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
523 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
525 /* Enable power block headswitch and wait for it to stabilize */
526 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
527 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
528 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
529 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
532 * Turn on memories. L2 banks should be done individually
533 * to minimize inrush current.
535 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
536 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
537 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
538 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
539 val |= Q6SS_L2DATA_SLP_NRET_N_2;
540 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
541 val |= Q6SS_L2DATA_SLP_NRET_N_1;
542 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
543 val |= Q6SS_L2DATA_SLP_NRET_N_0;
544 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
546 /* Remove IO clamp */
547 val &= ~Q6SS_CLAMP_IO;
548 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
550 /* Bring core out of reset */
551 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
552 val &= ~Q6SS_CORE_ARES;
553 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
555 /* Turn on core clock */
556 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
557 val |= Q6SS_CLK_ENABLE;
558 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
560 /* Start core execution */
561 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
562 val &= ~Q6SS_STOP_CORE;
563 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
566 /* Wait for PBL status */
567 ret = q6v5_rmb_pbl_wait(qproc, 1000);
568 if (ret == -ETIMEDOUT) {
569 dev_err(qproc->dev, "PBL boot timed out\n");
570 } else if (ret != RMB_PBL_SUCCESS) {
571 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
580 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
581 struct regmap *halt_map,
584 unsigned long timeout;
588 /* Check if we're already idle */
589 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
593 /* Assert halt request */
594 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
597 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
599 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
600 if (ret || val || time_after(jiffies, timeout))
606 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
608 dev_err(qproc->dev, "port failed halt\n");
610 /* Clear halt request (port will remain halted until reset) */
611 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
614 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
616 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
623 ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs);
625 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
629 memcpy(ptr, fw->data, fw->size);
631 /* Hypervisor mapping to access metadata by modem */
632 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
633 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm,
634 true, phys, fw->size);
637 "assigning Q6 access to metadata failed: %d\n", ret);
642 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
643 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
645 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
646 if (ret == -ETIMEDOUT)
647 dev_err(qproc->dev, "MPSS header authentication timed out\n");
649 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
651 /* Metadata authentication done, remove modem access */
652 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm,
653 false, phys, fw->size);
656 "mdt buffer not reclaimed system may become unstable\n");
659 dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs);
661 return ret < 0 ? ret : 0;
664 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
666 if (phdr->p_type != PT_LOAD)
669 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
678 static int q6v5_mpss_load(struct q6v5 *qproc)
680 const struct elf32_phdr *phdrs;
681 const struct elf32_phdr *phdr;
682 const struct firmware *seg_fw;
683 const struct firmware *fw;
684 struct elf32_hdr *ehdr;
685 phys_addr_t mpss_reloc;
686 phys_addr_t boot_addr;
687 phys_addr_t min_addr = PHYS_ADDR_MAX;
688 phys_addr_t max_addr = 0;
689 bool relocate = false;
697 ret = reject_firmware(&fw, "/*(DEBLOBBED)*/", qproc->dev);
699 dev_err(qproc->dev, "unable to load /*(DEBLOBBED)*/\n");
703 /* Initialize the RMB validator */
704 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
706 ret = q6v5_mpss_init_image(qproc, fw);
708 goto release_firmware;
710 ehdr = (struct elf32_hdr *)fw->data;
711 phdrs = (struct elf32_phdr *)(ehdr + 1);
713 for (i = 0; i < ehdr->e_phnum; i++) {
716 if (!q6v5_phdr_valid(phdr))
719 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
722 if (phdr->p_paddr < min_addr)
723 min_addr = phdr->p_paddr;
725 if (phdr->p_paddr + phdr->p_memsz > max_addr)
726 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
729 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
730 /* Load firmware segments */
731 for (i = 0; i < ehdr->e_phnum; i++) {
734 if (!q6v5_phdr_valid(phdr))
737 offset = phdr->p_paddr - mpss_reloc;
738 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
739 dev_err(qproc->dev, "segment outside memory range\n");
741 goto release_firmware;
744 ptr = qproc->mpss_region + offset;
746 if (phdr->p_filesz) {
747 snprintf(seg_name, sizeof(seg_name), "/*(DEBLOBBED)*/", i);
748 ret = reject_firmware_into_buf(&seg_fw, seg_name, qproc->dev,
749 ptr, phdr->p_filesz);
751 dev_err(qproc->dev, "failed to load %s\n", seg_name);
752 goto release_firmware;
755 release_firmware(seg_fw);
758 if (phdr->p_memsz > phdr->p_filesz) {
759 memset(ptr + phdr->p_filesz, 0,
760 phdr->p_memsz - phdr->p_filesz);
762 size += phdr->p_memsz;
765 /* Transfer ownership of modem ddr region to q6 */
766 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true,
767 qproc->mpss_phys, qproc->mpss_size);
770 "assigning Q6 access to mpss memory failed: %d\n", ret);
772 goto release_firmware;
775 boot_addr = relocate ? qproc->mpss_phys : min_addr;
776 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
777 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
778 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
780 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
781 if (ret == -ETIMEDOUT)
782 dev_err(qproc->dev, "MPSS authentication timed out\n");
784 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
787 release_firmware(fw);
789 return ret < 0 ? ret : 0;
792 static int q6v5_start(struct rproc *rproc)
794 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
798 qcom_q6v5_prepare(&qproc->q6v5);
800 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
801 qproc->proxy_reg_count);
803 dev_err(qproc->dev, "failed to enable proxy supplies\n");
807 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
808 qproc->proxy_clk_count);
810 dev_err(qproc->dev, "failed to enable proxy clocks\n");
811 goto disable_proxy_reg;
814 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
815 qproc->active_reg_count);
817 dev_err(qproc->dev, "failed to enable supplies\n");
818 goto disable_proxy_clk;
821 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
822 qproc->reset_clk_count);
824 dev_err(qproc->dev, "failed to enable reset clocks\n");
828 ret = q6v5_reset_deassert(qproc);
830 dev_err(qproc->dev, "failed to deassert mss restart\n");
831 goto disable_reset_clks;
834 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
835 qproc->active_clk_count);
837 dev_err(qproc->dev, "failed to enable clocks\n");
841 /* Assign MBA image access in DDR to q6 */
842 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
843 qproc->mba_phys, qproc->mba_size);
846 "assigning Q6 access to mba memory failed: %d\n", ret);
847 goto disable_active_clks;
850 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
852 ret = q6v5proc_reset(qproc);
856 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
857 if (ret == -ETIMEDOUT) {
858 dev_err(qproc->dev, "MBA boot timed out\n");
860 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
861 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
862 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
867 dev_info(qproc->dev, "MBA booted, loading mpss\n");
869 ret = q6v5_mpss_load(qproc);
873 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
874 if (ret == -ETIMEDOUT) {
875 dev_err(qproc->dev, "start timed out\n");
879 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
884 "Failed to reclaim mba buffer system may become unstable\n");
885 qproc->running = true;
890 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
891 false, qproc->mpss_phys,
893 WARN_ON(xfermemop_ret);
896 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
897 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
898 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
901 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
906 "Failed to reclaim mba buffer, system may become unstable\n");
910 q6v5_clk_disable(qproc->dev, qproc->active_clks,
911 qproc->active_clk_count);
914 q6v5_reset_assert(qproc);
916 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
917 qproc->reset_clk_count);
919 q6v5_regulator_disable(qproc, qproc->active_regs,
920 qproc->active_reg_count);
922 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
923 qproc->proxy_clk_count);
925 q6v5_regulator_disable(qproc, qproc->proxy_regs,
926 qproc->proxy_reg_count);
929 qcom_q6v5_unprepare(&qproc->q6v5);
934 static int q6v5_stop(struct rproc *rproc)
936 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
940 qproc->running = false;
942 ret = qcom_q6v5_request_stop(&qproc->q6v5);
943 if (ret == -ETIMEDOUT)
944 dev_err(qproc->dev, "timed out on wait\n");
946 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
947 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
948 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
949 if (qproc->version == MSS_MSM8996) {
951 * To avoid high MX current during LPASS/MSS restart.
953 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
954 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
955 QDSP6v56_CLAMP_QMC_MEM;
956 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
960 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false,
961 qproc->mpss_phys, qproc->mpss_size);
964 q6v5_reset_assert(qproc);
966 ret = qcom_q6v5_unprepare(&qproc->q6v5);
968 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
969 qproc->proxy_clk_count);
970 q6v5_regulator_disable(qproc, qproc->proxy_regs,
971 qproc->proxy_reg_count);
974 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
975 qproc->reset_clk_count);
976 q6v5_clk_disable(qproc->dev, qproc->active_clks,
977 qproc->active_clk_count);
978 q6v5_regulator_disable(qproc, qproc->active_regs,
979 qproc->active_reg_count);
984 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
986 struct q6v5 *qproc = rproc->priv;
989 offset = da - qproc->mpss_reloc;
990 if (offset < 0 || offset + len > qproc->mpss_size)
993 return qproc->mpss_region + offset;
996 static const struct rproc_ops q6v5_ops = {
999 .da_to_va = q6v5_da_to_va,
1003 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1005 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1007 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1008 qproc->proxy_clk_count);
1009 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1010 qproc->proxy_reg_count);
1013 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1015 struct of_phandle_args args;
1016 struct resource *res;
1019 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1020 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1021 if (IS_ERR(qproc->reg_base))
1022 return PTR_ERR(qproc->reg_base);
1024 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1025 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1026 if (IS_ERR(qproc->rmb_base))
1027 return PTR_ERR(qproc->rmb_base);
1029 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1030 "qcom,halt-regs", 3, 0, &args);
1032 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1036 qproc->halt_map = syscon_node_to_regmap(args.np);
1037 of_node_put(args.np);
1038 if (IS_ERR(qproc->halt_map))
1039 return PTR_ERR(qproc->halt_map);
1041 qproc->halt_q6 = args.args[0];
1042 qproc->halt_modem = args.args[1];
1043 qproc->halt_nc = args.args[2];
1048 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1056 for (i = 0; clk_names[i]; i++) {
1057 clks[i] = devm_clk_get(dev, clk_names[i]);
1058 if (IS_ERR(clks[i])) {
1059 int rc = PTR_ERR(clks[i]);
1061 if (rc != -EPROBE_DEFER)
1062 dev_err(dev, "Failed to get %s clock\n",
1071 static int q6v5_init_reset(struct q6v5 *qproc)
1073 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1075 if (IS_ERR(qproc->mss_restart)) {
1076 dev_err(qproc->dev, "failed to acquire mss restart\n");
1077 return PTR_ERR(qproc->mss_restart);
1083 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1085 struct device_node *child;
1086 struct device_node *node;
1090 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1091 node = of_parse_phandle(child, "memory-region", 0);
1092 ret = of_address_to_resource(node, 0, &r);
1094 dev_err(qproc->dev, "unable to resolve mba region\n");
1099 qproc->mba_phys = r.start;
1100 qproc->mba_size = resource_size(&r);
1101 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1102 if (!qproc->mba_region) {
1103 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1104 &r.start, qproc->mba_size);
1108 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1109 node = of_parse_phandle(child, "memory-region", 0);
1110 ret = of_address_to_resource(node, 0, &r);
1112 dev_err(qproc->dev, "unable to resolve mpss region\n");
1117 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1118 qproc->mpss_size = resource_size(&r);
1119 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
1120 if (!qproc->mpss_region) {
1121 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1122 &r.start, qproc->mpss_size);
1129 static int q6v5_probe(struct platform_device *pdev)
1131 const struct rproc_hexagon_res *desc;
1133 struct rproc *rproc;
1136 desc = of_device_get_match_data(&pdev->dev);
1140 if (desc->need_mem_protection && !qcom_scm_is_available())
1141 return -EPROBE_DEFER;
1143 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1144 desc->hexagon_mba_image, sizeof(*qproc));
1146 dev_err(&pdev->dev, "failed to allocate rproc\n");
1150 qproc = (struct q6v5 *)rproc->priv;
1151 qproc->dev = &pdev->dev;
1152 qproc->rproc = rproc;
1153 platform_set_drvdata(pdev, qproc);
1155 ret = q6v5_init_mem(qproc, pdev);
1159 ret = q6v5_alloc_memory_region(qproc);
1163 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1164 desc->proxy_clk_names);
1166 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1169 qproc->proxy_clk_count = ret;
1171 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1172 desc->reset_clk_names);
1174 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1177 qproc->reset_clk_count = ret;
1179 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1180 desc->active_clk_names);
1182 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1185 qproc->active_clk_count = ret;
1187 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1188 desc->proxy_supply);
1190 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1193 qproc->proxy_reg_count = ret;
1195 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1196 desc->active_supply);
1198 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1201 qproc->active_reg_count = ret;
1203 ret = q6v5_init_reset(qproc);
1207 qproc->version = desc->version;
1208 qproc->has_alt_reset = desc->has_alt_reset;
1209 qproc->need_mem_protection = desc->need_mem_protection;
1211 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1216 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1217 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1218 qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
1219 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1220 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1221 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1223 ret = rproc_add(rproc);
1235 static int q6v5_remove(struct platform_device *pdev)
1237 struct q6v5 *qproc = platform_get_drvdata(pdev);
1239 rproc_del(qproc->rproc);
1241 qcom_remove_sysmon_subdev(qproc->sysmon);
1242 qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
1243 qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
1244 qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
1245 rproc_free(qproc->rproc);
1250 static const struct rproc_hexagon_res sdm845_mss = {
1251 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1252 .proxy_clk_names = (char*[]){
1257 .reset_clk_names = (char*[]){
1262 .active_clk_names = (char*[]){
1269 .need_mem_protection = true,
1270 .has_alt_reset = true,
1271 .version = MSS_SDM845,
1274 static const struct rproc_hexagon_res msm8996_mss = {
1275 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1276 .proxy_supply = (struct qcom_mss_reg_res[]) {
1283 .proxy_clk_names = (char*[]){
1289 .active_clk_names = (char*[]){
1298 .need_mem_protection = true,
1299 .has_alt_reset = false,
1300 .version = MSS_MSM8996,
1303 static const struct rproc_hexagon_res msm8916_mss = {
1304 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1305 .proxy_supply = (struct qcom_mss_reg_res[]) {
1320 .proxy_clk_names = (char*[]){
1324 .active_clk_names = (char*[]){
1330 .need_mem_protection = false,
1331 .has_alt_reset = false,
1332 .version = MSS_MSM8916,
1335 static const struct rproc_hexagon_res msm8974_mss = {
1336 .hexagon_mba_image = "/*(DEBLOBBED)*/",
1337 .proxy_supply = (struct qcom_mss_reg_res[]) {
1352 .active_supply = (struct qcom_mss_reg_res[]) {
1360 .proxy_clk_names = (char*[]){
1364 .active_clk_names = (char*[]){
1370 .need_mem_protection = false,
1371 .has_alt_reset = false,
1372 .version = MSS_MSM8974,
1375 static const struct of_device_id q6v5_of_match[] = {
1376 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1377 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1378 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1379 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
1380 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
1383 MODULE_DEVICE_TABLE(of, q6v5_of_match);
1385 static struct platform_driver q6v5_driver = {
1386 .probe = q6v5_probe,
1387 .remove = q6v5_remove,
1389 .name = "qcom-q6v5-pil",
1390 .of_match_table = q6v5_of_match,
1393 module_platform_driver(q6v5_driver);
1395 MODULE_DESCRIPTION("Peripheral Image Loader for Hexagon");
1396 MODULE_LICENSE("GPL v2");