2 * Qualcomm Peripheral Image Loader
4 * Copyright (C) 2016 Linaro Ltd.
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/remoteproc.h>
30 #include <linux/reset.h>
31 #include <linux/soc/qcom/smem.h>
32 #include <linux/soc/qcom/smem_state.h>
34 #include "remoteproc_internal.h"
35 #include "qcom_mdt_loader.h"
37 #include <linux/qcom_scm.h>
39 #define MBA_FIRMWARE_NAME "/*(DEBLOBBED)*/"
40 #define MPSS_FIRMWARE_NAME "/*(DEBLOBBED)*/"
42 #define MPSS_CRASH_REASON_SMEM 421
44 /* RMB Status Register Values */
45 #define RMB_PBL_SUCCESS 0x1
47 #define RMB_MBA_XPU_UNLOCKED 0x1
48 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
49 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
50 #define RMB_MBA_AUTH_COMPLETE 0x4
52 /* PBL/MBA interface registers */
53 #define RMB_MBA_IMAGE_REG 0x00
54 #define RMB_PBL_STATUS_REG 0x04
55 #define RMB_MBA_COMMAND_REG 0x08
56 #define RMB_MBA_STATUS_REG 0x0C
57 #define RMB_PMI_META_DATA_REG 0x10
58 #define RMB_PMI_CODE_START_REG 0x14
59 #define RMB_PMI_CODE_LENGTH_REG 0x18
61 #define RMB_CMD_META_DATA_READY 0x1
62 #define RMB_CMD_LOAD_READY 0x2
64 /* QDSP6SS Register Offsets */
65 #define QDSP6SS_RESET_REG 0x014
66 #define QDSP6SS_GFMUX_CTL_REG 0x020
67 #define QDSP6SS_PWR_CTL_REG 0x030
69 /* AXI Halt Register Offsets */
70 #define AXI_HALTREQ_REG 0x0
71 #define AXI_HALTACK_REG 0x4
72 #define AXI_IDLE_REG 0x8
74 #define HALT_ACK_TIMEOUT_MS 100
77 #define Q6SS_STOP_CORE BIT(0)
78 #define Q6SS_CORE_ARES BIT(1)
79 #define Q6SS_BUS_ARES_ENABLE BIT(2)
81 /* QDSP6SS_GFMUX_CTL */
82 #define Q6SS_CLK_ENABLE BIT(1)
85 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
86 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
87 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
88 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
89 #define Q6SS_ETB_SLP_NRET_N BIT(17)
90 #define Q6SS_L2DATA_STBY_N BIT(18)
91 #define Q6SS_SLP_RET_N BIT(19)
92 #define Q6SS_CLAMP_IO BIT(20)
93 #define QDSS_BHS_ON BIT(21)
94 #define QDSS_LDO_BYP BIT(22)
100 void __iomem *reg_base;
101 void __iomem *rmb_base;
103 struct regmap *halt_map;
108 struct reset_control *mss_restart;
110 struct qcom_smem_state *state;
113 struct regulator_bulk_data supply[4];
119 struct completion start_done;
120 struct completion stop_done;
123 phys_addr_t mba_phys;
127 phys_addr_t mpss_phys;
128 phys_addr_t mpss_reloc;
140 static int q6v5_regulator_init(struct q6v5 *qproc)
144 qproc->supply[Q6V5_SUPPLY_CX].supply = "cx";
145 qproc->supply[Q6V5_SUPPLY_MX].supply = "mx";
146 qproc->supply[Q6V5_SUPPLY_MSS].supply = "mss";
147 qproc->supply[Q6V5_SUPPLY_PLL].supply = "pll";
149 ret = devm_regulator_bulk_get(qproc->dev,
150 ARRAY_SIZE(qproc->supply), qproc->supply);
152 dev_err(qproc->dev, "failed to get supplies\n");
156 regulator_set_load(qproc->supply[Q6V5_SUPPLY_CX].consumer, 100000);
157 regulator_set_load(qproc->supply[Q6V5_SUPPLY_MSS].consumer, 100000);
158 regulator_set_load(qproc->supply[Q6V5_SUPPLY_PLL].consumer, 10000);
163 static int q6v5_regulator_enable(struct q6v5 *qproc)
165 struct regulator *mss = qproc->supply[Q6V5_SUPPLY_MSS].consumer;
166 struct regulator *mx = qproc->supply[Q6V5_SUPPLY_MX].consumer;
169 /* TODO: Q6V5_SUPPLY_CX is supposed to be set to super-turbo here */
171 ret = regulator_set_voltage(mx, 1050000, INT_MAX);
175 regulator_set_voltage(mss, 1000000, 1150000);
177 return regulator_bulk_enable(ARRAY_SIZE(qproc->supply), qproc->supply);
180 static void q6v5_regulator_disable(struct q6v5 *qproc)
182 struct regulator *mss = qproc->supply[Q6V5_SUPPLY_MSS].consumer;
183 struct regulator *mx = qproc->supply[Q6V5_SUPPLY_MX].consumer;
185 /* TODO: Q6V5_SUPPLY_CX corner votes should be released */
187 regulator_bulk_disable(ARRAY_SIZE(qproc->supply), qproc->supply);
188 regulator_set_voltage(mx, 0, INT_MAX);
189 regulator_set_voltage(mss, 0, 1150000);
192 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
194 struct q6v5 *qproc = rproc->priv;
196 /* MBA is restricted to a maximum size of 1M */
197 if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
198 dev_err(qproc->dev, "MBA firmware load failed\n");
202 memcpy(qproc->mba_region, fw->data, fw->size);
207 static const struct rproc_fw_ops q6v5_fw_ops = {
208 .find_rsc_table = qcom_mdt_find_rsc_table,
212 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
214 unsigned long timeout;
217 timeout = jiffies + msecs_to_jiffies(ms);
219 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
223 if (time_after(jiffies, timeout))
232 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
235 unsigned long timeout;
238 timeout = jiffies + msecs_to_jiffies(ms);
240 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
246 else if (status && val == status)
249 if (time_after(jiffies, timeout))
258 static int q6v5proc_reset(struct q6v5 *qproc)
263 /* Assert resets, stop core */
264 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
265 val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE);
266 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
268 /* Enable power block headswitch, and wait for it to stabilize */
269 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
270 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
271 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
275 * Turn on memories. L2 banks should be done individually
276 * to minimize inrush current.
278 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
279 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
280 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
281 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
282 val |= Q6SS_L2DATA_SLP_NRET_N_2;
283 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
284 val |= Q6SS_L2DATA_SLP_NRET_N_1;
285 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
286 val |= Q6SS_L2DATA_SLP_NRET_N_0;
287 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
289 /* Remove IO clamp */
290 val &= ~Q6SS_CLAMP_IO;
291 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
293 /* Bring core out of reset */
294 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
295 val &= ~Q6SS_CORE_ARES;
296 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
298 /* Turn on core clock */
299 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
300 val |= Q6SS_CLK_ENABLE;
301 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
303 /* Start core execution */
304 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
305 val &= ~Q6SS_STOP_CORE;
306 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
308 /* Wait for PBL status */
309 ret = q6v5_rmb_pbl_wait(qproc, 1000);
310 if (ret == -ETIMEDOUT) {
311 dev_err(qproc->dev, "PBL boot timed out\n");
312 } else if (ret != RMB_PBL_SUCCESS) {
313 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
322 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
323 struct regmap *halt_map,
326 unsigned long timeout;
330 /* Check if we're already idle */
331 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
335 /* Assert halt request */
336 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
339 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
341 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
342 if (ret || val || time_after(jiffies, timeout))
348 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
350 dev_err(qproc->dev, "port failed halt\n");
352 /* Clear halt request (port will remain halted until reset) */
353 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
356 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
358 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
363 ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs);
365 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
369 memcpy(ptr, fw->data, fw->size);
371 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
372 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
374 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
375 if (ret == -ETIMEDOUT)
376 dev_err(qproc->dev, "MPSS header authentication timed out\n");
378 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
380 dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs);
382 return ret < 0 ? ret : 0;
385 static int q6v5_mpss_validate(struct q6v5 *qproc, const struct firmware *fw)
387 const struct elf32_phdr *phdrs;
388 const struct elf32_phdr *phdr;
389 struct elf32_hdr *ehdr;
390 phys_addr_t boot_addr;
397 ret = qcom_mdt_parse(fw, &fw_addr, NULL, &relocate);
399 dev_err(qproc->dev, "failed to parse mdt header\n");
404 boot_addr = qproc->mpss_phys;
408 ehdr = (struct elf32_hdr *)fw->data;
409 phdrs = (struct elf32_phdr *)(ehdr + 1);
410 for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
413 if (phdr->p_type != PT_LOAD)
416 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
422 size = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
424 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
425 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
428 size += phdr->p_memsz;
429 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
432 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
433 if (ret == -ETIMEDOUT)
434 dev_err(qproc->dev, "MPSS authentication timed out\n");
436 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
438 return ret < 0 ? ret : 0;
441 static int q6v5_mpss_load(struct q6v5 *qproc)
443 const struct firmware *fw;
448 ret = reject_firmware(&fw, MPSS_FIRMWARE_NAME, qproc->dev);
450 dev_err(qproc->dev, "unable to load " MPSS_FIRMWARE_NAME "\n");
454 ret = qcom_mdt_parse(fw, &fw_addr, NULL, &relocate);
456 dev_err(qproc->dev, "failed to parse mdt header\n");
457 goto release_firmware;
461 qproc->mpss_reloc = fw_addr;
463 /* Initialize the RMB validator */
464 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
466 ret = q6v5_mpss_init_image(qproc, fw);
468 goto release_firmware;
470 ret = qcom_mdt_load(qproc->rproc, fw, MPSS_FIRMWARE_NAME);
472 goto release_firmware;
474 ret = q6v5_mpss_validate(qproc, fw);
477 release_firmware(fw);
479 return ret < 0 ? ret : 0;
482 static int q6v5_start(struct rproc *rproc)
484 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
487 ret = q6v5_regulator_enable(qproc);
489 dev_err(qproc->dev, "failed to enable supplies\n");
493 ret = reset_control_deassert(qproc->mss_restart);
495 dev_err(qproc->dev, "failed to deassert mss restart\n");
499 ret = clk_prepare_enable(qproc->ahb_clk);
503 ret = clk_prepare_enable(qproc->axi_clk);
505 goto disable_ahb_clk;
507 ret = clk_prepare_enable(qproc->rom_clk);
509 goto disable_axi_clk;
511 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
513 ret = q6v5proc_reset(qproc);
517 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
518 if (ret == -ETIMEDOUT) {
519 dev_err(qproc->dev, "MBA boot timed out\n");
521 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
522 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
523 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
528 dev_info(qproc->dev, "MBA booted, loading mpss\n");
530 ret = q6v5_mpss_load(qproc);
534 ret = wait_for_completion_timeout(&qproc->start_done,
535 msecs_to_jiffies(5000));
537 dev_err(qproc->dev, "start timed out\n");
542 qproc->running = true;
544 /* TODO: All done, release the handover resources */
549 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
550 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
551 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
553 clk_disable_unprepare(qproc->rom_clk);
555 clk_disable_unprepare(qproc->axi_clk);
557 clk_disable_unprepare(qproc->ahb_clk);
559 reset_control_assert(qproc->mss_restart);
561 q6v5_regulator_disable(qproc);
566 static int q6v5_stop(struct rproc *rproc)
568 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
571 qproc->running = false;
573 qcom_smem_state_update_bits(qproc->state,
574 BIT(qproc->stop_bit), BIT(qproc->stop_bit));
576 ret = wait_for_completion_timeout(&qproc->stop_done,
577 msecs_to_jiffies(5000));
579 dev_err(qproc->dev, "timed out on wait\n");
581 qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
583 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
584 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
585 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
587 reset_control_assert(qproc->mss_restart);
588 clk_disable_unprepare(qproc->rom_clk);
589 clk_disable_unprepare(qproc->axi_clk);
590 clk_disable_unprepare(qproc->ahb_clk);
591 q6v5_regulator_disable(qproc);
596 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
598 struct q6v5 *qproc = rproc->priv;
601 offset = da - qproc->mpss_reloc;
602 if (offset < 0 || offset + len > qproc->mpss_size)
605 return qproc->mpss_region + offset;
608 static const struct rproc_ops q6v5_ops = {
611 .da_to_va = q6v5_da_to_va,
614 static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
616 struct q6v5 *qproc = dev;
620 /* Sometimes the stop triggers a watchdog rather than a stop-ack */
621 if (!qproc->running) {
622 complete(&qproc->stop_done);
626 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
627 if (!IS_ERR(msg) && len > 0 && msg[0])
628 dev_err(qproc->dev, "watchdog received: %s\n", msg);
630 dev_err(qproc->dev, "watchdog without message\n");
632 rproc_report_crash(qproc->rproc, RPROC_WATCHDOG);
640 static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
642 struct q6v5 *qproc = dev;
646 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
647 if (!IS_ERR(msg) && len > 0 && msg[0])
648 dev_err(qproc->dev, "fatal error received: %s\n", msg);
650 dev_err(qproc->dev, "fatal error without message\n");
652 rproc_report_crash(qproc->rproc, RPROC_FATAL_ERROR);
660 static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
662 struct q6v5 *qproc = dev;
664 complete(&qproc->start_done);
668 static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
670 struct q6v5 *qproc = dev;
672 complete(&qproc->stop_done);
676 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
678 struct of_phandle_args args;
679 struct resource *res;
682 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
683 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
684 if (IS_ERR(qproc->reg_base))
685 return PTR_ERR(qproc->reg_base);
687 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
688 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
689 if (IS_ERR(qproc->rmb_base))
690 return PTR_ERR(qproc->rmb_base);
692 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
693 "qcom,halt-regs", 3, 0, &args);
695 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
699 qproc->halt_map = syscon_node_to_regmap(args.np);
700 of_node_put(args.np);
701 if (IS_ERR(qproc->halt_map))
702 return PTR_ERR(qproc->halt_map);
704 qproc->halt_q6 = args.args[0];
705 qproc->halt_modem = args.args[1];
706 qproc->halt_nc = args.args[2];
711 static int q6v5_init_clocks(struct q6v5 *qproc)
713 qproc->ahb_clk = devm_clk_get(qproc->dev, "iface");
714 if (IS_ERR(qproc->ahb_clk)) {
715 dev_err(qproc->dev, "failed to get iface clock\n");
716 return PTR_ERR(qproc->ahb_clk);
719 qproc->axi_clk = devm_clk_get(qproc->dev, "bus");
720 if (IS_ERR(qproc->axi_clk)) {
721 dev_err(qproc->dev, "failed to get bus clock\n");
722 return PTR_ERR(qproc->axi_clk);
725 qproc->rom_clk = devm_clk_get(qproc->dev, "mem");
726 if (IS_ERR(qproc->rom_clk)) {
727 dev_err(qproc->dev, "failed to get mem clock\n");
728 return PTR_ERR(qproc->rom_clk);
734 static int q6v5_init_reset(struct q6v5 *qproc)
736 qproc->mss_restart = devm_reset_control_get(qproc->dev, NULL);
737 if (IS_ERR(qproc->mss_restart)) {
738 dev_err(qproc->dev, "failed to acquire mss restart\n");
739 return PTR_ERR(qproc->mss_restart);
745 static int q6v5_request_irq(struct q6v5 *qproc,
746 struct platform_device *pdev,
748 irq_handler_t thread_fn)
752 ret = platform_get_irq_byname(pdev, name);
754 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
758 ret = devm_request_threaded_irq(&pdev->dev, ret,
760 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
763 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
768 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
770 struct device_node *child;
771 struct device_node *node;
775 child = of_get_child_by_name(qproc->dev->of_node, "mba");
776 node = of_parse_phandle(child, "memory-region", 0);
777 ret = of_address_to_resource(node, 0, &r);
779 dev_err(qproc->dev, "unable to resolve mba region\n");
783 qproc->mba_phys = r.start;
784 qproc->mba_size = resource_size(&r);
785 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
786 if (!qproc->mba_region) {
787 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
788 &r.start, qproc->mba_size);
792 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
793 node = of_parse_phandle(child, "memory-region", 0);
794 ret = of_address_to_resource(node, 0, &r);
796 dev_err(qproc->dev, "unable to resolve mpss region\n");
800 qproc->mpss_phys = qproc->mpss_reloc = r.start;
801 qproc->mpss_size = resource_size(&r);
802 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
803 if (!qproc->mpss_region) {
804 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
805 &r.start, qproc->mpss_size);
812 static int q6v5_probe(struct platform_device *pdev)
818 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
819 MBA_FIRMWARE_NAME, sizeof(*qproc));
821 dev_err(&pdev->dev, "failed to allocate rproc\n");
825 rproc->fw_ops = &q6v5_fw_ops;
827 qproc = (struct q6v5 *)rproc->priv;
828 qproc->dev = &pdev->dev;
829 qproc->rproc = rproc;
830 platform_set_drvdata(pdev, qproc);
832 init_completion(&qproc->start_done);
833 init_completion(&qproc->stop_done);
835 ret = q6v5_init_mem(qproc, pdev);
839 ret = q6v5_alloc_memory_region(qproc);
843 ret = q6v5_init_clocks(qproc);
847 ret = q6v5_regulator_init(qproc);
851 ret = q6v5_init_reset(qproc);
855 ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
859 ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
863 ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
867 ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
871 qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit);
872 if (IS_ERR(qproc->state)) {
873 ret = PTR_ERR(qproc->state);
877 ret = rproc_add(rproc);
889 static int q6v5_remove(struct platform_device *pdev)
891 struct q6v5 *qproc = platform_get_drvdata(pdev);
893 rproc_del(qproc->rproc);
894 rproc_free(qproc->rproc);
899 static const struct of_device_id q6v5_of_match[] = {
900 { .compatible = "qcom,q6v5-pil", },
904 static struct platform_driver q6v5_driver = {
906 .remove = q6v5_remove,
908 .name = "qcom-q6v5-pil",
909 .of_match_table = q6v5_of_match,
912 module_platform_driver(q6v5_driver);
914 MODULE_DESCRIPTION("Peripheral Image Loader for Hexagon");
915 MODULE_LICENSE("GPL v2");