drivers/remoteproc/qcom_q6v5_mss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm self-authenticating modem subsystem remoteproc driver
   4  *
   5  * Copyright (C) 2016 Linaro Ltd.
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/module.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_device.h>
  19 #include <linux/of_reserved_mem.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/remoteproc.h>
  26 #include <linux/reset.h>
  27 #include <linux/soc/qcom/mdt_loader.h>
  28 #include <linux/iopoll.h>
  29
  30 #include "remoteproc_internal.h"
  31 #include "qcom_common.h"
  32 #include "qcom_q6v5.h"
  33
  34 #include <linux/qcom_scm.h>
  35
  36 #define MPSS_CRASH_REASON_SMEM          421
  37
  38 /* RMB Status Register Values */
  39 #define RMB_PBL_SUCCESS                 0x1
  40
  41 #define RMB_MBA_XPU_UNLOCKED            0x1
  42 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  43 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  44 #define RMB_MBA_AUTH_COMPLETE           0x4
  45
  46 /* PBL/MBA interface registers */
  47 #define RMB_MBA_IMAGE_REG               0x00
  48 #define RMB_PBL_STATUS_REG              0x04
  49 #define RMB_MBA_COMMAND_REG             0x08
  50 #define RMB_MBA_STATUS_REG              0x0C
  51 #define RMB_PMI_META_DATA_REG           0x10
  52 #define RMB_PMI_CODE_START_REG          0x14
  53 #define RMB_PMI_CODE_LENGTH_REG         0x18
  54 #define RMB_MBA_MSS_STATUS              0x40
  55 #define RMB_MBA_ALT_RESET               0x44
  56
  57 #define RMB_CMD_META_DATA_READY         0x1
  58 #define RMB_CMD_LOAD_READY              0x2
  59
  60 /* QDSP6SS Register Offsets */
  61 #define QDSP6SS_RESET_REG               0x014
  62 #define QDSP6SS_GFMUX_CTL_REG           0x020
  63 #define QDSP6SS_PWR_CTL_REG             0x030
  64 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  65 #define QDSP6SS_STRAP_ACC               0x110
  66
  67 /* AXI Halt Register Offsets */
  68 #define AXI_HALTREQ_REG                 0x0
  69 #define AXI_HALTACK_REG                 0x4
  70 #define AXI_IDLE_REG                    0x8
  71
  72 #define HALT_ACK_TIMEOUT_MS             100
  73
  74 /* QDSP6SS_RESET */
  75 #define Q6SS_STOP_CORE                  BIT(0)
  76 #define Q6SS_CORE_ARES                  BIT(1)
  77 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  78
  79 /* QDSP6SS_GFMUX_CTL */
  80 #define Q6SS_CLK_ENABLE                 BIT(1)
  81
  82 /* QDSP6SS_PWR_CTL */
  83 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
  84 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
  85 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
  86 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
  87 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
  88 #define Q6SS_L2DATA_STBY_N              BIT(18)
  89 #define Q6SS_SLP_RET_N                  BIT(19)
  90 #define Q6SS_CLAMP_IO                   BIT(20)
  91 #define QDSS_BHS_ON                     BIT(21)
  92 #define QDSS_LDO_BYP                    BIT(22)
  93
  94 /* QDSP6v56 parameters */
  95 #define QDSP6v56_LDO_BYP                BIT(25)
  96 #define QDSP6v56_BHS_ON         BIT(24)
  97 #define QDSP6v56_CLAMP_WL               BIT(21)
  98 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
  99 #define HALT_CHECK_MAX_LOOPS            200
 100 #define QDSP6SS_XO_CBCR         0x0038
 101 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 102
 103 /* QDSP6v65 parameters */
 104 #define QDSP6SS_SLEEP                   0x3C
 105 #define QDSP6SS_BOOT_CORE_START         0x400
 106 #define QDSP6SS_BOOT_CMD                0x404
 107 #define SLEEP_CHECK_MAX_LOOPS           200
 108 #define BOOT_FSM_TIMEOUT                10000
 109
 110 struct reg_info {
 111         struct regulator *reg;
 112         int uV;
 113         int uA;
 114 };
 115
 116 struct qcom_mss_reg_res {
 117         const char *supply;
 118         int uV;
 119         int uA;
 120 };
 121
 122 struct rproc_hexagon_res {
 123         const char *hexagon_mba_image;
 124         struct qcom_mss_reg_res *proxy_supply;
 125         struct qcom_mss_reg_res *active_supply;
 126         char **proxy_clk_names;
 127         char **reset_clk_names;
 128         char **active_clk_names;
 129         char **active_pd_names;
 130         char **proxy_pd_names;
 131         int version;
 132         bool need_mem_protection;
 133         bool has_alt_reset;
 134 };
 135
 136 struct q6v5 {
 137         struct device *dev;
 138         struct rproc *rproc;
 139
 140         void __iomem *reg_base;
 141         void __iomem *rmb_base;
 142
 143         struct regmap *halt_map;
 144         u32 halt_q6;
 145         u32 halt_modem;
 146         u32 halt_nc;
 147
 148         struct reset_control *mss_restart;
 149         struct reset_control *pdc_reset;
 150
 151         struct qcom_q6v5 q6v5;
 152
 153         struct clk *active_clks[8];
 154         struct clk *reset_clks[4];
 155         struct clk *proxy_clks[4];
 156         struct device *active_pds[1];
 157         struct device *proxy_pds[3];
 158         int active_clk_count;
 159         int reset_clk_count;
 160         int proxy_clk_count;
 161         int active_pd_count;
 162         int proxy_pd_count;
 163
 164         struct reg_info active_regs[1];
 165         struct reg_info proxy_regs[3];
 166         int active_reg_count;
 167         int proxy_reg_count;
 168
 169         bool running;
 170
 171         bool dump_mba_loaded;
 172         unsigned long dump_segment_mask;
 173         unsigned long dump_complete_mask;
 174
 175         phys_addr_t mba_phys;
 176         void *mba_region;
 177         size_t mba_size;
 178
 179         phys_addr_t mdata_phys;
 180         size_t mdata_size;
 181
 182         phys_addr_t mpss_phys;
 183         phys_addr_t mpss_reloc;
 184         void *mpss_region;
 185         size_t mpss_size;
 186
 187         struct qcom_rproc_glink glink_subdev;
 188         struct qcom_rproc_subdev smd_subdev;
 189         struct qcom_rproc_ssr ssr_subdev;
 190         struct qcom_sysmon *sysmon;
 191         bool need_mem_protection;
 192         bool has_alt_reset;
 193         int mpss_perm;
 194         int mba_perm;
 195         const char *hexagon_mdt_image;
 196         int version;
 197 };
 198
 199 enum {
 200         MSS_MSM8916,
 201         MSS_MSM8974,
 202         MSS_MSM8996,
 203         MSS_SDM845,
 204 };
 205
 206 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 207                                const struct qcom_mss_reg_res *reg_res)
 208 {
 209         int rc;
 210         int i;
 211
 212         if (!reg_res)
 213                 return 0;
 214
 215         for (i = 0; reg_res[i].supply; i++) {
 216                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 217                 if (IS_ERR(regs[i].reg)) {
 218                         rc = PTR_ERR(regs[i].reg);
 219                         if (rc != -EPROBE_DEFER)
 220                                 dev_err(dev, "Failed to get %s\n regulator",
 221                                         reg_res[i].supply);
 222                         return rc;
 223                 }
 224
 225                 regs[i].uV = reg_res[i].uV;
 226                 regs[i].uA = reg_res[i].uA;
 227         }
 228
 229         return i;
 230 }
 231
 232 static int q6v5_regulator_enable(struct q6v5 *qproc,
 233                                  struct reg_info *regs, int count)
 234 {
 235         int ret;
 236         int i;
 237
 238         for (i = 0; i < count; i++) {
 239                 if (regs[i].uV > 0) {
 240                         ret = regulator_set_voltage(regs[i].reg,
 241                                         regs[i].uV, INT_MAX);
 242                         if (ret) {
 243                                 dev_err(qproc->dev,
 244                                         "Failed to request voltage for %d.\n",
 245                                                 i);
 246                                 goto err;
 247                         }
 248                 }
 249
 250                 if (regs[i].uA > 0) {
 251                         ret = regulator_set_load(regs[i].reg,
 252                                                  regs[i].uA);
 253                         if (ret < 0) {
 254                                 dev_err(qproc->dev,
 255                                         "Failed to set regulator mode\n");
 256                                 goto err;
 257                         }
 258                 }
 259
 260                 ret = regulator_enable(regs[i].reg);
 261                 if (ret) {
 262                         dev_err(qproc->dev, "Regulator enable failed\n");
 263                         goto err;
 264                 }
 265         }
 266
 267         return 0;
 268 err:
 269         for (; i >= 0; i--) {
 270                 if (regs[i].uV > 0)
 271                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 272
 273                 if (regs[i].uA > 0)
 274                         regulator_set_load(regs[i].reg, 0);
 275
 276                 regulator_disable(regs[i].reg);
 277         }
 278
 279         return ret;
 280 }
 281
 282 static void q6v5_regulator_disable(struct q6v5 *qproc,
 283                                    struct reg_info *regs, int count)
 284 {
 285         int i;
 286
 287         for (i = 0; i < count; i++) {
 288                 if (regs[i].uV > 0)
 289                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 290
 291                 if (regs[i].uA > 0)
 292                         regulator_set_load(regs[i].reg, 0);
 293
 294                 regulator_disable(regs[i].reg);
 295         }
 296 }
 297
 298 static int q6v5_clk_enable(struct device *dev,
 299                            struct clk **clks, int count)
 300 {
 301         int rc;
 302         int i;
 303
 304         for (i = 0; i < count; i++) {
 305                 rc = clk_prepare_enable(clks[i]);
 306                 if (rc) {
 307                         dev_err(dev, "Clock enable failed\n");
 308                         goto err;
 309                 }
 310         }
 311
 312         return 0;
 313 err:
 314         for (i--; i >= 0; i--)
 315                 clk_disable_unprepare(clks[i]);
 316
 317         return rc;
 318 }
 319
 320 static void q6v5_clk_disable(struct device *dev,
 321                              struct clk **clks, int count)
 322 {
 323         int i;
 324
 325         for (i = 0; i < count; i++)
 326                 clk_disable_unprepare(clks[i]);
 327 }
 328
 329 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 330                            size_t pd_count)
 331 {
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < pd_count; i++) {
 336                 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 337                 ret = pm_runtime_get_sync(pds[i]);
 338                 if (ret < 0) {
 339                         pm_runtime_put_noidle(pds[i]);
 340                         dev_pm_genpd_set_performance_state(pds[i], 0);
 341                         goto unroll_pd_votes;
 342                 }
 343         }
 344
 345         return 0;
 346
 347 unroll_pd_votes:
 348         for (i--; i >= 0; i--) {
 349                 dev_pm_genpd_set_performance_state(pds[i], 0);
 350                 pm_runtime_put(pds[i]);
 351         }
 352
 353         return ret;
 354 };
 355
 356 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 357                              size_t pd_count)
 358 {
 359         int i;
 360
 361         for (i = 0; i < pd_count; i++) {
 362                 dev_pm_genpd_set_performance_state(pds[i], 0);
 363                 pm_runtime_put(pds[i]);
 364         }
 365 }
 366
 367 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 368                                    bool remote_owner, phys_addr_t addr,
 369                                    size_t size)
 370 {
 371         struct qcom_scm_vmperm next;
 372
 373         if (!qproc->need_mem_protection)
 374                 return 0;
 375         if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA))
 376                 return 0;
 377         if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS))
 378                 return 0;
 379
 380         next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS;
 381         next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX;
 382
 383         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 384                                    current_perm, &next, 1);
 385 }
 386
 387 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 388 {
 389         struct q6v5 *qproc = rproc->priv;
 390
 391         /* MBA is restricted to a maximum size of 1M */
 392         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 393                 dev_err(qproc->dev, "MBA firmware load failed\n");
 394                 return -EINVAL;
 395         }
 396
 397         memcpy(qproc->mba_region, fw->data, fw->size);
 398
 399         return 0;
 400 }
 401
 402 static int q6v5_reset_assert(struct q6v5 *qproc)
 403 {
 404         int ret;
 405
 406         if (qproc->has_alt_reset) {
 407                 reset_control_assert(qproc->pdc_reset);
 408                 ret = reset_control_reset(qproc->mss_restart);
 409                 reset_control_deassert(qproc->pdc_reset);
 410         } else {
 411                 ret = reset_control_assert(qproc->mss_restart);
 412         }
 413
 414         return ret;
 415 }
 416
 417 static int q6v5_reset_deassert(struct q6v5 *qproc)
 418 {
 419         int ret;
 420
 421         if (qproc->has_alt_reset) {
 422                 reset_control_assert(qproc->pdc_reset);
 423                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 424                 ret = reset_control_reset(qproc->mss_restart);
 425                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 426                 reset_control_deassert(qproc->pdc_reset);
 427         } else {
 428                 ret = reset_control_deassert(qproc->mss_restart);
 429         }
 430
 431         return ret;
 432 }
 433
 434 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 435 {
 436         unsigned long timeout;
 437         s32 val;
 438
 439         timeout = jiffies + msecs_to_jiffies(ms);
 440         for (;;) {
 441                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 442                 if (val)
 443                         break;
 444
 445                 if (time_after(jiffies, timeout))
 446                         return -ETIMEDOUT;
 447
 448                 msleep(1);
 449         }
 450
 451         return val;
 452 }
 453
 454 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 455 {
 456
 457         unsigned long timeout;
 458         s32 val;
 459
 460         timeout = jiffies + msecs_to_jiffies(ms);
 461         for (;;) {
 462                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 463                 if (val < 0)
 464                         break;
 465
 466                 if (!status && val)
 467                         break;
 468                 else if (status && val == status)
 469                         break;
 470
 471                 if (time_after(jiffies, timeout))
 472                         return -ETIMEDOUT;
 473
 474                 msleep(1);
 475         }
 476
 477         return val;
 478 }
 479
 480 static int q6v5proc_reset(struct q6v5 *qproc)
 481 {
 482         u32 val;
 483         int ret;
 484         int i;
 485
 486         if (qproc->version == MSS_SDM845) {
 487                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 488                 val |= 0x1;
 489                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 490
 491                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 492                                          val, !(val & BIT(31)), 1,
 493                                          SLEEP_CHECK_MAX_LOOPS);
 494                 if (ret) {
 495                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 496                         return -ETIMEDOUT;
 497                 }
 498
 499                 /* De-assert QDSP6 stop core */
 500                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 501                 /* Trigger boot FSM */
 502                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 503
 504                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 505                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 506                 if (ret) {
 507                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 508                         /* Reset the modem so that boot FSM is in reset state */
 509                         q6v5_reset_deassert(qproc);
 510                         return ret;
 511                 }
 512
 513                 goto pbl_wait;
 514         } else if (qproc->version == MSS_MSM8996) {
 515                 /* Override the ACC value if required */
 516                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 517                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 518
 519                 /* Assert resets, stop core */
 520                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 521                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 522                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 523
 524                 /* BHS require xo cbcr to be enabled */
 525                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 526                 val |= 0x1;
 527                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 528
 529                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 530                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 531                                          val, !(val & BIT(31)), 1,
 532                                          HALT_CHECK_MAX_LOOPS);
 533                 if (ret) {
 534                         dev_err(qproc->dev,
 535                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 536                         return ret;
 537                 }
 538                 /* Enable power block headswitch and wait for it to stabilize */
 539                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 540                 val |= QDSP6v56_BHS_ON;
 541                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 542                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 543                 udelay(1);
 544
 545                 /* Put LDO in bypass mode */
 546                 val |= QDSP6v56_LDO_BYP;
 547                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 548
 549                 /* Deassert QDSP6 compiler memory clamp */
 550                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 551                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 552                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 553
 554                 /* Deassert memory peripheral sleep and L2 memory standby */
 555                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 556                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 557
 558                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 559                 val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
 560                 for (i = 19; i >= 0; i--) {
 561                         val |= BIT(i);
 562                         writel(val, qproc->reg_base +
 563                                                 QDSP6SS_MEM_PWR_CTL);
 564                         /*
 565                          * Read back value to ensure the write is done then
 566                          * wait for 1us for both memory peripheral and data
 567                          * array to turn on.
 568                          */
 569                         val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
 570                         udelay(1);
 571                 }
 572                 /* Remove word line clamp */
 573                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 574                 val &= ~QDSP6v56_CLAMP_WL;
 575                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 576         } else {
 577                 /* Assert resets, stop core */
 578                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 579                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 580                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 581
 582                 /* Enable power block headswitch and wait for it to stabilize */
 583                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 584                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 585                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 586                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 587                 udelay(1);
 588                 /*
 589                  * Turn on memories. L2 banks should be done individually
 590                  * to minimize inrush current.
 591                  */
 592                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 593                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 594                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 595                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 596                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 597                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 598                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 599                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 600                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 601                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 602         }
 603         /* Remove IO clamp */
 604         val &= ~Q6SS_CLAMP_IO;
 605         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 606
 607         /* Bring core out of reset */
 608         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 609         val &= ~Q6SS_CORE_ARES;
 610         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 611
 612         /* Turn on core clock */
 613         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 614         val |= Q6SS_CLK_ENABLE;
 615         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 616
 617         /* Start core execution */
 618         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 619         val &= ~Q6SS_STOP_CORE;
 620         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 621
 622 pbl_wait:
 623         /* Wait for PBL status */
 624         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 625         if (ret == -ETIMEDOUT) {
 626                 dev_err(qproc->dev, "PBL boot timed out\n");
 627         } else if (ret != RMB_PBL_SUCCESS) {
 628                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 629                 ret = -EINVAL;
 630         } else {
 631                 ret = 0;
 632         }
 633
 634         return ret;
 635 }
 636
 637 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 638                                    struct regmap *halt_map,
 639                                    u32 offset)
 640 {
 641         unsigned long timeout;
 642         unsigned int val;
 643         int ret;
 644
 645         /* Check if we're already idle */
 646         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 647         if (!ret && val)
 648                 return;
 649
 650         /* Assert halt request */
 651         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 652
 653         /* Wait for halt */
 654         timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
 655         for (;;) {
 656                 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
 657                 if (ret || val || time_after(jiffies, timeout))
 658                         break;
 659
 660                 msleep(1);
 661         }
 662
 663         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 664         if (ret || !val)
 665                 dev_err(qproc->dev, "port failed halt\n");
 666
 667         /* Clear halt request (port will remain halted until reset) */
 668         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 669 }
 670
 671 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 672 {
 673         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 674         dma_addr_t phys;
 675         void *metadata;
 676         int mdata_perm;
 677         int xferop_ret;
 678         size_t size;
 679         void *ptr;
 680         int ret;
 681
 682         metadata = qcom_mdt_read_metadata(fw, &size);
 683         if (IS_ERR(metadata))
 684                 return PTR_ERR(metadata);
 685
 686         if (qproc->mdata_phys) {
 687                 if (size > qproc->mdata_size) {
 688                         ret = -EINVAL;
 689                         dev_err(qproc->dev, "metadata size outside memory range\n");
 690                         goto free_metadata;
 691                 }
 692
 693                 phys = qproc->mdata_phys;
 694                 ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC);
 695                 if (!ptr) {
 696                         ret = -EBUSY;
 697                         dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 698                                 &qproc->mdata_phys, size);
 699                         goto free_metadata;
 700                 }
 701         } else {
 702                 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
 703                 if (!ptr) {
 704                         ret = -ENOMEM;
 705                         dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 706                         goto free_metadata;
 707                 }
 708         }
 709
 710         memcpy(ptr, metadata, size);
 711
 712         if (qproc->mdata_phys)
 713                 memunmap(ptr);
 714
 715         /* Hypervisor mapping to access metadata by modem */
 716         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 717         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, phys, size);
 718         if (ret) {
 719                 dev_err(qproc->dev,
 720                         "assigning Q6 access to metadata failed: %d\n", ret);
 721                 ret = -EAGAIN;
 722                 goto free_dma_attrs;
 723         }
 724
 725         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 726         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 727
 728         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 729         if (ret == -ETIMEDOUT)
 730                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 731         else if (ret < 0)
 732                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
 733
 734         /* Metadata authentication done, remove modem access */
 735         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, phys, size);
 736         if (xferop_ret)
 737                 dev_warn(qproc->dev,
 738                          "mdt buffer not reclaimed system may become unstable\n");
 739
 740 free_dma_attrs:
 741         if (!qproc->mdata_phys)
 742                 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
 743 free_metadata:
 744         kfree(metadata);
 745
 746         return ret < 0 ? ret : 0;
 747 }
 748
 749 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
 750 {
 751         if (phdr->p_type != PT_LOAD)
 752                 return false;
 753
 754         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 755                 return false;
 756
 757         if (!phdr->p_memsz)
 758                 return false;
 759
 760         return true;
 761 }
 762
 763 static int q6v5_mba_load(struct q6v5 *qproc)
 764 {
 765         int ret;
 766         int xfermemop_ret;
 767
 768         qcom_q6v5_prepare(&qproc->q6v5);
 769
 770         ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
 771         if (ret < 0) {
 772                 dev_err(qproc->dev, "failed to enable active power domains\n");
 773                 goto disable_irqs;
 774         }
 775
 776         ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
 777         if (ret < 0) {
 778                 dev_err(qproc->dev, "failed to enable proxy power domains\n");
 779                 goto disable_active_pds;
 780         }
 781
 782         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
 783                                     qproc->proxy_reg_count);
 784         if (ret) {
 785                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
 786                 goto disable_proxy_pds;
 787         }
 788
 789         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
 790                               qproc->proxy_clk_count);
 791         if (ret) {
 792                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
 793                 goto disable_proxy_reg;
 794         }
 795
 796         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
 797                                     qproc->active_reg_count);
 798         if (ret) {
 799                 dev_err(qproc->dev, "failed to enable supplies\n");
 800                 goto disable_proxy_clk;
 801         }
 802
 803         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
 804                               qproc->reset_clk_count);
 805         if (ret) {
 806                 dev_err(qproc->dev, "failed to enable reset clocks\n");
 807                 goto disable_vdd;
 808         }
 809
 810         ret = q6v5_reset_deassert(qproc);
 811         if (ret) {
 812                 dev_err(qproc->dev, "failed to deassert mss restart\n");
 813                 goto disable_reset_clks;
 814         }
 815
 816         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
 817                               qproc->active_clk_count);
 818         if (ret) {
 819                 dev_err(qproc->dev, "failed to enable clocks\n");
 820                 goto assert_reset;
 821         }
 822
 823         /* Assign MBA image access in DDR to q6 */
 824         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
 825                                       qproc->mba_phys, qproc->mba_size);
 826         if (ret) {
 827                 dev_err(qproc->dev,
 828                         "assigning Q6 access to mba memory failed: %d\n", ret);
 829                 goto disable_active_clks;
 830         }
 831
 832         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
 833
 834         ret = q6v5proc_reset(qproc);
 835         if (ret)
 836                 goto reclaim_mba;
 837
 838         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
 839         if (ret == -ETIMEDOUT) {
 840                 dev_err(qproc->dev, "MBA boot timed out\n");
 841                 goto halt_axi_ports;
 842         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
 843                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
 844                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
 845                 ret = -EINVAL;
 846                 goto halt_axi_ports;
 847         }
 848
 849         qproc->dump_mba_loaded = true;
 850         return 0;
 851
 852 halt_axi_ports:
 853         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 854         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 855         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 856
 857 reclaim_mba:
 858         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
 859                                                 qproc->mba_phys,
 860                                                 qproc->mba_size);
 861         if (xfermemop_ret) {
 862                 dev_err(qproc->dev,
 863                         "Failed to reclaim mba buffer, system may become unstable\n");
 864         }
 865
 866 disable_active_clks:
 867         q6v5_clk_disable(qproc->dev, qproc->active_clks,
 868                          qproc->active_clk_count);
 869 assert_reset:
 870         q6v5_reset_assert(qproc);
 871 disable_reset_clks:
 872         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
 873                          qproc->reset_clk_count);
 874 disable_vdd:
 875         q6v5_regulator_disable(qproc, qproc->active_regs,
 876                                qproc->active_reg_count);
 877 disable_proxy_clk:
 878         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
 879                          qproc->proxy_clk_count);
 880 disable_proxy_reg:
 881         q6v5_regulator_disable(qproc, qproc->proxy_regs,
 882                                qproc->proxy_reg_count);
 883 disable_proxy_pds:
 884         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
 885 disable_active_pds:
 886         q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
 887 disable_irqs:
 888         qcom_q6v5_unprepare(&qproc->q6v5);
 889
 890         return ret;
 891 }
 892
 893 static void q6v5_mba_reclaim(struct q6v5 *qproc)
 894 {
 895         int ret;
 896         u32 val;
 897
 898         qproc->dump_mba_loaded = false;
 899
 900         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 901         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 902         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 903         if (qproc->version == MSS_MSM8996) {
 904                 /*
 905                  * To avoid high MX current during LPASS/MSS restart.
 906                  */
 907                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 908                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
 909                         QDSP6v56_CLAMP_QMC_MEM;
 910                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 911         }
 912
 913         q6v5_reset_assert(qproc);
 914
 915         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
 916                          qproc->reset_clk_count);
 917         q6v5_clk_disable(qproc->dev, qproc->active_clks,
 918                          qproc->active_clk_count);
 919         q6v5_regulator_disable(qproc, qproc->active_regs,
 920                                qproc->active_reg_count);
 921         q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
 922
 923         /* In case of failure or coredump scenario where reclaiming MBA memory
 924          * could not happen reclaim it here.
 925          */
 926         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
 927                                       qproc->mba_phys,
 928                                       qproc->mba_size);
 929         WARN_ON(ret);
 930
 931         ret = qcom_q6v5_unprepare(&qproc->q6v5);
 932         if (ret) {
 933                 q6v5_pds_disable(qproc, qproc->proxy_pds,
 934                                  qproc->proxy_pd_count);
 935                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
 936                                  qproc->proxy_clk_count);
 937                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
 938                                        qproc->proxy_reg_count);
 939         }
 940 }
 941
 942 static int q6v5_reload_mba(struct rproc *rproc)
 943 {
 944         struct q6v5 *qproc = rproc->priv;
 945         const struct firmware *fw;
 946         int ret;
 947
 948         ret = reject_firmware(&fw, rproc->firmware, qproc->dev);
 949         if (ret < 0)
 950                 return ret;
 951
 952         q6v5_load(rproc, fw);
 953         ret = q6v5_mba_load(qproc);
 954         release_firmware(fw);
 955
 956         return ret;
 957 }
 958
 959 static int q6v5_mpss_load(struct q6v5 *qproc)
 960 {
 961         const struct elf32_phdr *phdrs;
 962         const struct elf32_phdr *phdr;
 963         const struct firmware *seg_fw;
 964         const struct firmware *fw;
 965         struct elf32_hdr *ehdr;
 966         phys_addr_t mpss_reloc;
 967         phys_addr_t boot_addr;
 968         phys_addr_t min_addr = PHYS_ADDR_MAX;
 969         phys_addr_t max_addr = 0;
 970         bool relocate = false;
 971         char *fw_name;
 972         size_t fw_name_len;
 973         ssize_t offset;
 974         size_t size = 0;
 975         void *ptr;
 976         int ret;
 977         int i;
 978
 979         fw_name_len = strlen(qproc->hexagon_mdt_image);
 980         if (fw_name_len <= 4)
 981                 return -EINVAL;
 982
 983         fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
 984         if (!fw_name)
 985                 return -ENOMEM;
 986
 987         ret = reject_firmware(&fw, fw_name, qproc->dev);
 988         if (ret < 0) {
 989                 dev_err(qproc->dev, "unable to load %s\n", fw_name);
 990                 goto out;
 991         }
 992
 993         /* Initialize the RMB validator */
 994         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 995
 996         ret = q6v5_mpss_init_image(qproc, fw);
 997         if (ret)
 998                 goto release_firmware;
 999
1000         ehdr = (struct elf32_hdr *)fw->data;
1001         phdrs = (struct elf32_phdr *)(ehdr + 1);
1002
1003         for (i = 0; i < ehdr->e_phnum; i++) {
1004                 phdr = &phdrs[i];
1005
1006                 if (!q6v5_phdr_valid(phdr))
1007                         continue;
1008
1009                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1010                         relocate = true;
1011
1012                 if (phdr->p_paddr < min_addr)
1013                         min_addr = phdr->p_paddr;
1014
1015                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1016                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1017         }
1018
1019         /**
1020          * In case of a modem subsystem restart on secure devices, the modem
1021          * memory can be reclaimed only after MBA is loaded. For modem cold
1022          * boot this will be a nop
1023          */
1024         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false,
1025                                 qproc->mpss_phys, qproc->mpss_size);
1026
1027         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1028         qproc->mpss_reloc = mpss_reloc;
1029         /* Load firmware segments */
1030         for (i = 0; i < ehdr->e_phnum; i++) {
1031                 phdr = &phdrs[i];
1032
1033                 if (!q6v5_phdr_valid(phdr))
1034                         continue;
1035
1036                 offset = phdr->p_paddr - mpss_reloc;
1037                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1038                         dev_err(qproc->dev, "segment outside memory range\n");
1039                         ret = -EINVAL;
1040                         goto release_firmware;
1041                 }
1042
1043                 ptr = ioremap_wc(qproc->mpss_phys + offset, phdr->p_memsz);
1044                 if (!ptr) {
1045                         dev_err(qproc->dev,
1046                                 "unable to map memory region: %pa+%zx-%x\n",
1047                                 &qproc->mpss_phys, offset, phdr->p_memsz);
1048                         goto release_firmware;
1049                 }
1050
1051                 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1052                         /* Firmware is large enough to be non-split */
1053                         if (phdr->p_offset + phdr->p_filesz > fw->size) {
1054                                 dev_err(qproc->dev,
1055                                         "failed to load segment %d from truncated file %s\n",
1056                                         i, fw_name);
1057                                 ret = -EINVAL;
1058                                 iounmap(ptr);
1059                                 goto release_firmware;
1060                         }
1061
1062                         memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1063                 } else if (phdr->p_filesz) {
1064                         /* Replace "xxx.xxx" with "xxx.bxx" */
1065                         sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1066                         ret = reject_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1067                                                         ptr, phdr->p_filesz);
1068                         if (ret) {
1069                                 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1070                                 iounmap(ptr);
1071                                 goto release_firmware;
1072                         }
1073
1074                         release_firmware(seg_fw);
1075                 }
1076
1077                 if (phdr->p_memsz > phdr->p_filesz) {
1078                         memset(ptr + phdr->p_filesz, 0,
1079                                phdr->p_memsz - phdr->p_filesz);
1080                 }
1081                 iounmap(ptr);
1082                 size += phdr->p_memsz;
1083         }
1084
1085         /* Transfer ownership of modem ddr region to q6 */
1086         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true,
1087                                       qproc->mpss_phys, qproc->mpss_size);
1088         if (ret) {
1089                 dev_err(qproc->dev,
1090                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1091                 ret = -EAGAIN;
1092                 goto release_firmware;
1093         }
1094
1095         boot_addr = relocate ? qproc->mpss_phys : min_addr;
1096         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1097         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1098         writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1099
1100         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1101         if (ret == -ETIMEDOUT)
1102                 dev_err(qproc->dev, "MPSS authentication timed out\n");
1103         else if (ret < 0)
1104                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1105
1106 release_firmware:
1107         release_firmware(fw);
1108 out:
1109         kfree(fw_name);
1110
1111         return ret < 0 ? ret : 0;
1112 }
1113
1114 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1115                                    struct rproc_dump_segment *segment,
1116                                    void *dest)
1117 {
1118         int ret = 0;
1119         struct q6v5 *qproc = rproc->priv;
1120         unsigned long mask = BIT((unsigned long)segment->priv);
1121         int offset = segment->da - qproc->mpss_reloc;
1122         void *ptr = NULL;
1123
1124         /* Unlock mba before copying segments */
1125         if (!qproc->dump_mba_loaded) {
1126                 ret = q6v5_reload_mba(rproc);
1127                 if (!ret) {
1128                         /* Reset ownership back to Linux to copy segments */
1129                         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1130                                                       false,
1131                                                       qproc->mpss_phys,
1132                                                       qproc->mpss_size);
1133                 }
1134         }
1135
1136         if (!ret)
1137                 ptr = ioremap_wc(qproc->mpss_phys + offset, segment->size);
1138
1139         if (ptr) {
1140                 memcpy(dest, ptr, segment->size);
1141                 iounmap(ptr);
1142         } else {
1143                 memset(dest, 0xff, segment->size);
1144         }
1145
1146         qproc->dump_segment_mask |= mask;
1147
1148         /* Reclaim mba after copying segments */
1149         if (qproc->dump_segment_mask == qproc->dump_complete_mask) {
1150                 if (qproc->dump_mba_loaded) {
1151                         /* Try to reset ownership back to Q6 */
1152                         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1153                                                 true,
1154                                                 qproc->mpss_phys,
1155                                                 qproc->mpss_size);
1156                         q6v5_mba_reclaim(qproc);
1157                 }
1158         }
1159 }
1160
1161 static int q6v5_start(struct rproc *rproc)
1162 {
1163         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1164         int xfermemop_ret;
1165         int ret;
1166
1167         ret = q6v5_mba_load(qproc);
1168         if (ret)
1169                 return ret;
1170
1171         dev_info(qproc->dev, "MBA booted, loading mpss\n");
1172
1173         ret = q6v5_mpss_load(qproc);
1174         if (ret)
1175                 goto reclaim_mpss;
1176
1177         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1178         if (ret == -ETIMEDOUT) {
1179                 dev_err(qproc->dev, "start timed out\n");
1180                 goto reclaim_mpss;
1181         }
1182
1183         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
1184                                                 qproc->mba_phys,
1185                                                 qproc->mba_size);
1186         if (xfermemop_ret)
1187                 dev_err(qproc->dev,
1188                         "Failed to reclaim mba buffer system may become unstable\n");
1189
1190         /* Reset Dump Segment Mask */
1191         qproc->dump_segment_mask = 0;
1192         qproc->running = true;
1193
1194         return 0;
1195
1196 reclaim_mpss:
1197         q6v5_mba_reclaim(qproc);
1198
1199         return ret;
1200 }
1201
1202 static int q6v5_stop(struct rproc *rproc)
1203 {
1204         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1205         int ret;
1206
1207         qproc->running = false;
1208
1209         ret = qcom_q6v5_request_stop(&qproc->q6v5);
1210         if (ret == -ETIMEDOUT)
1211                 dev_err(qproc->dev, "timed out on wait\n");
1212
1213         q6v5_mba_reclaim(qproc);
1214
1215         return 0;
1216 }
1217
1218 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
1219 {
1220         struct q6v5 *qproc = rproc->priv;
1221         int offset;
1222
1223         offset = da - qproc->mpss_reloc;
1224         if (offset < 0 || offset + len > qproc->mpss_size)
1225                 return NULL;
1226
1227         return qproc->mpss_region + offset;
1228 }
1229
1230 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1231                                             const struct firmware *mba_fw)
1232 {
1233         const struct firmware *fw;
1234         const struct elf32_phdr *phdrs;
1235         const struct elf32_phdr *phdr;
1236         const struct elf32_hdr *ehdr;
1237         struct q6v5 *qproc = rproc->priv;
1238         unsigned long i;
1239         int ret;
1240
1241         ret = reject_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1242         if (ret < 0) {
1243                 dev_err(qproc->dev, "unable to load %s\n",
1244                         qproc->hexagon_mdt_image);
1245                 return ret;
1246         }
1247
1248         ehdr = (struct elf32_hdr *)fw->data;
1249         phdrs = (struct elf32_phdr *)(ehdr + 1);
1250         qproc->dump_complete_mask = 0;
1251
1252         for (i = 0; i < ehdr->e_phnum; i++) {
1253                 phdr = &phdrs[i];
1254
1255                 if (!q6v5_phdr_valid(phdr))
1256                         continue;
1257
1258                 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1259                                                         phdr->p_memsz,
1260                                                         qcom_q6v5_dump_segment,
1261                                                         (void *)i);
1262                 if (ret)
1263                         break;
1264
1265                 qproc->dump_complete_mask |= BIT(i);
1266         }
1267
1268         release_firmware(fw);
1269         return ret;
1270 }
1271
1272 static const struct rproc_ops q6v5_ops = {
1273         .start = q6v5_start,
1274         .stop = q6v5_stop,
1275         .da_to_va = q6v5_da_to_va,
1276         .parse_fw = qcom_q6v5_register_dump_segments,
1277         .load = q6v5_load,
1278 };
1279
1280 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1281 {
1282         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1283
1284         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1285                          qproc->proxy_clk_count);
1286         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1287                                qproc->proxy_reg_count);
1288         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1289 }
1290
1291 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1292 {
1293         struct of_phandle_args args;
1294         struct resource *res;
1295         int ret;
1296
1297         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1298         qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1299         if (IS_ERR(qproc->reg_base))
1300                 return PTR_ERR(qproc->reg_base);
1301
1302         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1303         qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1304         if (IS_ERR(qproc->rmb_base))
1305                 return PTR_ERR(qproc->rmb_base);
1306
1307         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1308                                                "qcom,halt-regs", 3, 0, &args);
1309         if (ret < 0) {
1310                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1311                 return -EINVAL;
1312         }
1313
1314         qproc->halt_map = syscon_node_to_regmap(args.np);
1315         of_node_put(args.np);
1316         if (IS_ERR(qproc->halt_map))
1317                 return PTR_ERR(qproc->halt_map);
1318
1319         qproc->halt_q6 = args.args[0];
1320         qproc->halt_modem = args.args[1];
1321         qproc->halt_nc = args.args[2];
1322
1323         return 0;
1324 }
1325
1326 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1327                 char **clk_names)
1328 {
1329         int i;
1330
1331         if (!clk_names)
1332                 return 0;
1333
1334         for (i = 0; clk_names[i]; i++) {
1335                 clks[i] = devm_clk_get(dev, clk_names[i]);
1336                 if (IS_ERR(clks[i])) {
1337                         int rc = PTR_ERR(clks[i]);
1338
1339                         if (rc != -EPROBE_DEFER)
1340                                 dev_err(dev, "Failed to get %s clock\n",
1341                                         clk_names[i]);
1342                         return rc;
1343                 }
1344         }
1345
1346         return i;
1347 }
1348
1349 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1350                            char **pd_names)
1351 {
1352         size_t num_pds = 0;
1353         int ret;
1354         int i;
1355
1356         if (!pd_names)
1357                 return 0;
1358
1359         while (pd_names[num_pds])
1360                 num_pds++;
1361
1362         for (i = 0; i < num_pds; i++) {
1363                 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1364                 if (IS_ERR_OR_NULL(devs[i])) {
1365                         ret = PTR_ERR(devs[i]) ? : -ENODATA;
1366                         goto unroll_attach;
1367                 }
1368         }
1369
1370         return num_pds;
1371
1372 unroll_attach:
1373         for (i--; i >= 0; i--)
1374                 dev_pm_domain_detach(devs[i], false);
1375
1376         return ret;
1377 };
1378
1379 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1380                             size_t pd_count)
1381 {
1382         int i;
1383
1384         for (i = 0; i < pd_count; i++)
1385                 dev_pm_domain_detach(pds[i], false);
1386 }
1387
1388 static int q6v5_init_reset(struct q6v5 *qproc)
1389 {
1390         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1391                                                               "mss_restart");
1392         if (IS_ERR(qproc->mss_restart)) {
1393                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1394                 return PTR_ERR(qproc->mss_restart);
1395         }
1396
1397         if (qproc->has_alt_reset) {
1398                 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1399                                                                     "pdc_reset");
1400                 if (IS_ERR(qproc->pdc_reset)) {
1401                         dev_err(qproc->dev, "failed to acquire pdc reset\n");
1402                         return PTR_ERR(qproc->pdc_reset);
1403                 }
1404         }
1405
1406         return 0;
1407 }
1408
1409 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1410 {
1411         struct device_node *child;
1412         struct reserved_mem *rmem;
1413         struct device_node *node;
1414         struct resource r;
1415         int ret;
1416
1417         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1418         node = of_parse_phandle(child, "memory-region", 0);
1419         ret = of_address_to_resource(node, 0, &r);
1420         if (ret) {
1421                 dev_err(qproc->dev, "unable to resolve mba region\n");
1422                 return ret;
1423         }
1424         of_node_put(node);
1425
1426         qproc->mba_phys = r.start;
1427         qproc->mba_size = resource_size(&r);
1428         qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1429         if (!qproc->mba_region) {
1430                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1431                         &r.start, qproc->mba_size);
1432                 return -EBUSY;
1433         }
1434
1435         child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1436         node = of_parse_phandle(child, "memory-region", 0);
1437         ret = of_address_to_resource(node, 0, &r);
1438         if (ret) {
1439                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1440                 return ret;
1441         }
1442         of_node_put(node);
1443
1444         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1445         qproc->mpss_size = resource_size(&r);
1446
1447         if (!child) {
1448                 node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2);
1449         } else {
1450                 child = of_get_child_by_name(qproc->dev->of_node, "metadata");
1451                 node = of_parse_phandle(child, "memory-region", 0);
1452                 of_node_put(child);
1453         }
1454
1455         if (!node)
1456                 return 0;
1457
1458         rmem = of_reserved_mem_lookup(node);
1459         if (!rmem) {
1460                 dev_err(qproc->dev, "unable to resolve metadata region\n");
1461                 return -EINVAL;
1462         }
1463
1464         qproc->mdata_phys = rmem->base;
1465         qproc->mdata_size = rmem->size;
1466
1467         return 0;
1468 }
1469
1470 static int q6v5_probe(struct platform_device *pdev)
1471 {
1472         const struct rproc_hexagon_res *desc;
1473         struct q6v5 *qproc;
1474         struct rproc *rproc;
1475         const char *mba_image;
1476         int ret;
1477
1478         desc = of_device_get_match_data(&pdev->dev);
1479         if (!desc)
1480                 return -EINVAL;
1481
1482         if (desc->need_mem_protection && !qcom_scm_is_available())
1483                 return -EPROBE_DEFER;
1484
1485         mba_image = desc->hexagon_mba_image;
1486         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1487                                             0, &mba_image);
1488         if (ret < 0 && ret != -EINVAL)
1489                 return ret;
1490
1491         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1492                             mba_image, sizeof(*qproc));
1493         if (!rproc) {
1494                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1495                 return -ENOMEM;
1496         }
1497
1498         rproc->auto_boot = false;
1499
1500         qproc = (struct q6v5 *)rproc->priv;
1501         qproc->dev = &pdev->dev;
1502         qproc->rproc = rproc;
1503         qproc->hexagon_mdt_image = "/*(DEBLOBBED)*/";
1504         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1505                                             1, &qproc->hexagon_mdt_image);
1506         if (ret < 0 && ret != -EINVAL)
1507                 goto free_rproc;
1508
1509         platform_set_drvdata(pdev, qproc);
1510
1511         ret = q6v5_init_mem(qproc, pdev);
1512         if (ret)
1513                 goto free_rproc;
1514
1515         ret = q6v5_alloc_memory_region(qproc);
1516         if (ret)
1517                 goto free_rproc;
1518
1519         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1520                                desc->proxy_clk_names);
1521         if (ret < 0) {
1522                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1523                 goto free_rproc;
1524         }
1525         qproc->proxy_clk_count = ret;
1526
1527         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1528                                desc->reset_clk_names);
1529         if (ret < 0) {
1530                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1531                 goto free_rproc;
1532         }
1533         qproc->reset_clk_count = ret;
1534
1535         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1536                                desc->active_clk_names);
1537         if (ret < 0) {
1538                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1539                 goto free_rproc;
1540         }
1541         qproc->active_clk_count = ret;
1542
1543         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1544                                   desc->proxy_supply);
1545         if (ret < 0) {
1546                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1547                 goto free_rproc;
1548         }
1549         qproc->proxy_reg_count = ret;
1550
1551         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
1552                                   desc->active_supply);
1553         if (ret < 0) {
1554                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1555                 goto free_rproc;
1556         }
1557         qproc->active_reg_count = ret;
1558
1559         ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1560                               desc->active_pd_names);
1561         if (ret < 0) {
1562                 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1563                 goto free_rproc;
1564         }
1565         qproc->active_pd_count = ret;
1566
1567         ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1568                               desc->proxy_pd_names);
1569         if (ret < 0) {
1570                 dev_err(&pdev->dev, "Failed to init power domains\n");
1571                 goto detach_active_pds;
1572         }
1573         qproc->proxy_pd_count = ret;
1574
1575         qproc->has_alt_reset = desc->has_alt_reset;
1576         ret = q6v5_init_reset(qproc);
1577         if (ret)
1578                 goto detach_proxy_pds;
1579
1580         qproc->version = desc->version;
1581         qproc->need_mem_protection = desc->need_mem_protection;
1582
1583         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1584                              qcom_msa_handover);
1585         if (ret)
1586                 goto detach_proxy_pds;
1587
1588         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1589         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1590         qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
1591         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1592         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1593         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1594         if (IS_ERR(qproc->sysmon)) {
1595                 ret = PTR_ERR(qproc->sysmon);
1596                 goto detach_proxy_pds;
1597         }
1598
1599         ret = rproc_add(rproc);
1600         if (ret)
1601                 goto detach_proxy_pds;
1602
1603         return 0;
1604
1605 detach_proxy_pds:
1606         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1607 detach_active_pds:
1608         q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1609 free_rproc:
1610         rproc_free(rproc);
1611
1612         return ret;
1613 }
1614
1615 static int q6v5_remove(struct platform_device *pdev)
1616 {
1617         struct q6v5 *qproc = platform_get_drvdata(pdev);
1618
1619         rproc_del(qproc->rproc);
1620
1621         qcom_remove_sysmon_subdev(qproc->sysmon);
1622         qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
1623         qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
1624         qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
1625
1626         q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1627         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1628
1629         rproc_free(qproc->rproc);
1630
1631         return 0;
1632 }
1633
1634 static const struct rproc_hexagon_res sdm845_mss = {
1635         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1636         .proxy_clk_names = (char*[]){
1637                         "xo",
1638                         "prng",
1639                         NULL
1640         },
1641         .reset_clk_names = (char*[]){
1642                         "iface",
1643                         "snoc_axi",
1644                         NULL
1645         },
1646         .active_clk_names = (char*[]){
1647                         "bus",
1648                         "mem",
1649                         "gpll0_mss",
1650                         "mnoc_axi",
1651                         NULL
1652         },
1653         .active_pd_names = (char*[]){
1654                         "load_state",
1655                         NULL
1656         },
1657         .proxy_pd_names = (char*[]){
1658                         "cx",
1659                         "mx",
1660                         "mss",
1661                         NULL
1662         },
1663         .need_mem_protection = true,
1664         .has_alt_reset = true,
1665         .version = MSS_SDM845,
1666 };
1667
1668 static const struct rproc_hexagon_res msm8996_mss = {
1669         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1670         .proxy_supply = (struct qcom_mss_reg_res[]) {
1671                 {
1672                         .supply = "pll",
1673                         .uA = 100000,
1674                 },
1675                 {}
1676         },
1677         .proxy_clk_names = (char*[]){
1678                         "xo",
1679                         "pnoc",
1680                         "qdss",
1681                         NULL
1682         },
1683         .active_clk_names = (char*[]){
1684                         "iface",
1685                         "bus",
1686                         "mem",
1687                         "gpll0_mss",
1688                         "snoc_axi",
1689                         "mnoc_axi",
1690                         NULL
1691         },
1692         .need_mem_protection = true,
1693         .has_alt_reset = false,
1694         .version = MSS_MSM8996,
1695 };
1696
1697 static const struct rproc_hexagon_res msm8916_mss = {
1698         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1699         .proxy_supply = (struct qcom_mss_reg_res[]) {
1700                 {
1701                         .supply = "mx",
1702                         .uV = 1050000,
1703                 },
1704                 {
1705                         .supply = "cx",
1706                         .uA = 100000,
1707                 },
1708                 {
1709                         .supply = "pll",
1710                         .uA = 100000,
1711                 },
1712                 {}
1713         },
1714         .proxy_clk_names = (char*[]){
1715                 "xo",
1716                 NULL
1717         },
1718         .active_clk_names = (char*[]){
1719                 "iface",
1720                 "bus",
1721                 "mem",
1722                 NULL
1723         },
1724         .need_mem_protection = false,
1725         .has_alt_reset = false,
1726         .version = MSS_MSM8916,
1727 };
1728
1729 static const struct rproc_hexagon_res msm8974_mss = {
1730         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1731         .proxy_supply = (struct qcom_mss_reg_res[]) {
1732                 {
1733                         .supply = "mx",
1734                         .uV = 1050000,
1735                 },
1736                 {
1737                         .supply = "cx",
1738                         .uA = 100000,
1739                 },
1740                 {
1741                         .supply = "pll",
1742                         .uA = 100000,
1743                 },
1744                 {}
1745         },
1746         .active_supply = (struct qcom_mss_reg_res[]) {
1747                 {
1748                         .supply = "mss",
1749                         .uV = 1050000,
1750                         .uA = 100000,
1751                 },
1752                 {}
1753         },
1754         .proxy_clk_names = (char*[]){
1755                 "xo",
1756                 NULL
1757         },
1758         .active_clk_names = (char*[]){
1759                 "iface",
1760                 "bus",
1761                 "mem",
1762                 NULL
1763         },
1764         .need_mem_protection = false,
1765         .has_alt_reset = false,
1766         .version = MSS_MSM8974,
1767 };
1768
1769 static const struct of_device_id q6v5_of_match[] = {
1770         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1771         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1772         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
1773         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
1774         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
1775         { },
1776 };
1777 MODULE_DEVICE_TABLE(of, q6v5_of_match);
1778
1779 static struct platform_driver q6v5_driver = {
1780         .probe = q6v5_probe,
1781         .remove = q6v5_remove,
1782         .driver = {
1783                 .name = "qcom-q6v5-mss",
1784                 .of_match_table = q6v5_of_match,
1785         },
1786 };
1787 module_platform_driver(q6v5_driver);
1788
1789 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
1790 MODULE_LICENSE("GPL v2");