drivers/remoteproc/qcom_q6v5_mss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm self-authenticating modem subsystem remoteproc driver
   4  *
   5  * Copyright (C) 2016 Linaro Ltd.
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/devcoredump.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/remoteproc.h>
  26 #include <linux/reset.h>
  27 #include <linux/soc/qcom/mdt_loader.h>
  28 #include <linux/iopoll.h>
  29 #include <linux/slab.h>
  30
  31 #include "remoteproc_internal.h"
  32 #include "qcom_common.h"
  33 #include "qcom_pil_info.h"
  34 #include "qcom_q6v5.h"
  35
  36 #include <linux/qcom_scm.h>
  37
  38 #define MPSS_CRASH_REASON_SMEM          421
  39
  40 #define MBA_LOG_SIZE                    SZ_4K
  41
  42 /* RMB Status Register Values */
  43 #define RMB_PBL_SUCCESS                 0x1
  44
  45 #define RMB_MBA_XPU_UNLOCKED            0x1
  46 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  47 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  48 #define RMB_MBA_AUTH_COMPLETE           0x4
  49
  50 /* PBL/MBA interface registers */
  51 #define RMB_MBA_IMAGE_REG               0x00
  52 #define RMB_PBL_STATUS_REG              0x04
  53 #define RMB_MBA_COMMAND_REG             0x08
  54 #define RMB_MBA_STATUS_REG              0x0C
  55 #define RMB_PMI_META_DATA_REG           0x10
  56 #define RMB_PMI_CODE_START_REG          0x14
  57 #define RMB_PMI_CODE_LENGTH_REG         0x18
  58 #define RMB_MBA_MSS_STATUS              0x40
  59 #define RMB_MBA_ALT_RESET               0x44
  60
  61 #define RMB_CMD_META_DATA_READY         0x1
  62 #define RMB_CMD_LOAD_READY              0x2
  63
  64 /* QDSP6SS Register Offsets */
  65 #define QDSP6SS_RESET_REG               0x014
  66 #define QDSP6SS_GFMUX_CTL_REG           0x020
  67 #define QDSP6SS_PWR_CTL_REG             0x030
  68 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  69 #define QDSP6V6SS_MEM_PWR_CTL           0x034
  70 #define QDSP6SS_STRAP_ACC               0x110
  71
  72 /* AXI Halt Register Offsets */
  73 #define AXI_HALTREQ_REG                 0x0
  74 #define AXI_HALTACK_REG                 0x4
  75 #define AXI_IDLE_REG                    0x8
  76 #define AXI_GATING_VALID_OVERRIDE       BIT(0)
  77
  78 #define HALT_ACK_TIMEOUT_US             100000
  79
  80 /* QDSP6SS_RESET */
  81 #define Q6SS_STOP_CORE                  BIT(0)
  82 #define Q6SS_CORE_ARES                  BIT(1)
  83 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  84
  85 /* QDSP6SS CBCR */
  86 #define Q6SS_CBCR_CLKEN                 BIT(0)
  87 #define Q6SS_CBCR_CLKOFF                BIT(31)
  88 #define Q6SS_CBCR_TIMEOUT_US            200
  89
  90 /* QDSP6SS_GFMUX_CTL */
  91 #define Q6SS_CLK_ENABLE                 BIT(1)
  92
  93 /* QDSP6SS_PWR_CTL */
  94 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
  95 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
  96 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
  97 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
  98 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
  99 #define Q6SS_L2DATA_STBY_N              BIT(18)
 100 #define Q6SS_SLP_RET_N                  BIT(19)
 101 #define Q6SS_CLAMP_IO                   BIT(20)
 102 #define QDSS_BHS_ON                     BIT(21)
 103 #define QDSS_LDO_BYP                    BIT(22)
 104
 105 /* QDSP6v56 parameters */
 106 #define QDSP6v56_LDO_BYP                BIT(25)
 107 #define QDSP6v56_BHS_ON         BIT(24)
 108 #define QDSP6v56_CLAMP_WL               BIT(21)
 109 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
 110 #define QDSP6SS_XO_CBCR         0x0038
 111 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 112
 113 /* QDSP6v65 parameters */
 114 #define QDSP6SS_CORE_CBCR               0x20
 115 #define QDSP6SS_SLEEP                   0x3C
 116 #define QDSP6SS_BOOT_CORE_START         0x400
 117 #define QDSP6SS_BOOT_CMD                0x404
 118 #define BOOT_FSM_TIMEOUT                10000
 119
 120 struct reg_info {
 121         struct regulator *reg;
 122         int uV;
 123         int uA;
 124 };
 125
 126 struct qcom_mss_reg_res {
 127         const char *supply;
 128         int uV;
 129         int uA;
 130 };
 131
 132 struct rproc_hexagon_res {
 133         const char *hexagon_mba_image;
 134         struct qcom_mss_reg_res *proxy_supply;
 135         struct qcom_mss_reg_res *active_supply;
 136         char **proxy_clk_names;
 137         char **reset_clk_names;
 138         char **active_clk_names;
 139         char **active_pd_names;
 140         char **proxy_pd_names;
 141         int version;
 142         bool need_mem_protection;
 143         bool has_alt_reset;
 144         bool has_mba_logs;
 145         bool has_spare_reg;
 146 };
 147
 148 struct q6v5 {
 149         struct device *dev;
 150         struct rproc *rproc;
 151
 152         void __iomem *reg_base;
 153         void __iomem *rmb_base;
 154
 155         struct regmap *halt_map;
 156         struct regmap *conn_map;
 157
 158         u32 halt_q6;
 159         u32 halt_modem;
 160         u32 halt_nc;
 161         u32 conn_box;
 162
 163         struct reset_control *mss_restart;
 164         struct reset_control *pdc_reset;
 165
 166         struct qcom_q6v5 q6v5;
 167
 168         struct clk *active_clks[8];
 169         struct clk *reset_clks[4];
 170         struct clk *proxy_clks[4];
 171         struct device *active_pds[1];
 172         struct device *proxy_pds[3];
 173         int active_clk_count;
 174         int reset_clk_count;
 175         int proxy_clk_count;
 176         int active_pd_count;
 177         int proxy_pd_count;
 178
 179         struct reg_info active_regs[1];
 180         struct reg_info proxy_regs[3];
 181         int active_reg_count;
 182         int proxy_reg_count;
 183
 184         bool dump_mba_loaded;
 185         size_t current_dump_size;
 186         size_t total_dump_size;
 187
 188         phys_addr_t mba_phys;
 189         void *mba_region;
 190         size_t mba_size;
 191         size_t dp_size;
 192
 193         phys_addr_t mpss_phys;
 194         phys_addr_t mpss_reloc;
 195         size_t mpss_size;
 196
 197         struct qcom_rproc_glink glink_subdev;
 198         struct qcom_rproc_subdev smd_subdev;
 199         struct qcom_rproc_ssr ssr_subdev;
 200         struct qcom_sysmon *sysmon;
 201         bool need_mem_protection;
 202         bool has_alt_reset;
 203         bool has_mba_logs;
 204         bool has_spare_reg;
 205         int mpss_perm;
 206         int mba_perm;
 207         const char *hexagon_mdt_image;
 208         int version;
 209 };
 210
 211 enum {
 212         MSS_MSM8916,
 213         MSS_MSM8974,
 214         MSS_MSM8996,
 215         MSS_MSM8998,
 216         MSS_SC7180,
 217         MSS_SDM845,
 218 };
 219
 220 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 221                                const struct qcom_mss_reg_res *reg_res)
 222 {
 223         int rc;
 224         int i;
 225
 226         if (!reg_res)
 227                 return 0;
 228
 229         for (i = 0; reg_res[i].supply; i++) {
 230                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 231                 if (IS_ERR(regs[i].reg)) {
 232                         rc = PTR_ERR(regs[i].reg);
 233                         if (rc != -EPROBE_DEFER)
 234                                 dev_err(dev, "Failed to get %s\n regulator",
 235                                         reg_res[i].supply);
 236                         return rc;
 237                 }
 238
 239                 regs[i].uV = reg_res[i].uV;
 240                 regs[i].uA = reg_res[i].uA;
 241         }
 242
 243         return i;
 244 }
 245
 246 static int q6v5_regulator_enable(struct q6v5 *qproc,
 247                                  struct reg_info *regs, int count)
 248 {
 249         int ret;
 250         int i;
 251
 252         for (i = 0; i < count; i++) {
 253                 if (regs[i].uV > 0) {
 254                         ret = regulator_set_voltage(regs[i].reg,
 255                                         regs[i].uV, INT_MAX);
 256                         if (ret) {
 257                                 dev_err(qproc->dev,
 258                                         "Failed to request voltage for %d.\n",
 259                                                 i);
 260                                 goto err;
 261                         }
 262                 }
 263
 264                 if (regs[i].uA > 0) {
 265                         ret = regulator_set_load(regs[i].reg,
 266                                                  regs[i].uA);
 267                         if (ret < 0) {
 268                                 dev_err(qproc->dev,
 269                                         "Failed to set regulator mode\n");
 270                                 goto err;
 271                         }
 272                 }
 273
 274                 ret = regulator_enable(regs[i].reg);
 275                 if (ret) {
 276                         dev_err(qproc->dev, "Regulator enable failed\n");
 277                         goto err;
 278                 }
 279         }
 280
 281         return 0;
 282 err:
 283         for (; i >= 0; i--) {
 284                 if (regs[i].uV > 0)
 285                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 286
 287                 if (regs[i].uA > 0)
 288                         regulator_set_load(regs[i].reg, 0);
 289
 290                 regulator_disable(regs[i].reg);
 291         }
 292
 293         return ret;
 294 }
 295
 296 static void q6v5_regulator_disable(struct q6v5 *qproc,
 297                                    struct reg_info *regs, int count)
 298 {
 299         int i;
 300
 301         for (i = 0; i < count; i++) {
 302                 if (regs[i].uV > 0)
 303                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 304
 305                 if (regs[i].uA > 0)
 306                         regulator_set_load(regs[i].reg, 0);
 307
 308                 regulator_disable(regs[i].reg);
 309         }
 310 }
 311
 312 static int q6v5_clk_enable(struct device *dev,
 313                            struct clk **clks, int count)
 314 {
 315         int rc;
 316         int i;
 317
 318         for (i = 0; i < count; i++) {
 319                 rc = clk_prepare_enable(clks[i]);
 320                 if (rc) {
 321                         dev_err(dev, "Clock enable failed\n");
 322                         goto err;
 323                 }
 324         }
 325
 326         return 0;
 327 err:
 328         for (i--; i >= 0; i--)
 329                 clk_disable_unprepare(clks[i]);
 330
 331         return rc;
 332 }
 333
 334 static void q6v5_clk_disable(struct device *dev,
 335                              struct clk **clks, int count)
 336 {
 337         int i;
 338
 339         for (i = 0; i < count; i++)
 340                 clk_disable_unprepare(clks[i]);
 341 }
 342
 343 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 344                            size_t pd_count)
 345 {
 346         int ret;
 347         int i;
 348
 349         for (i = 0; i < pd_count; i++) {
 350                 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 351                 ret = pm_runtime_get_sync(pds[i]);
 352                 if (ret < 0) {
 353                         pm_runtime_put_noidle(pds[i]);
 354                         dev_pm_genpd_set_performance_state(pds[i], 0);
 355                         goto unroll_pd_votes;
 356                 }
 357         }
 358
 359         return 0;
 360
 361 unroll_pd_votes:
 362         for (i--; i >= 0; i--) {
 363                 dev_pm_genpd_set_performance_state(pds[i], 0);
 364                 pm_runtime_put(pds[i]);
 365         }
 366
 367         return ret;
 368 }
 369
 370 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 371                              size_t pd_count)
 372 {
 373         int i;
 374
 375         for (i = 0; i < pd_count; i++) {
 376                 dev_pm_genpd_set_performance_state(pds[i], 0);
 377                 pm_runtime_put(pds[i]);
 378         }
 379 }
 380
 381 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 382                                    bool local, bool remote, phys_addr_t addr,
 383                                    size_t size)
 384 {
 385         struct qcom_scm_vmperm next[2];
 386         int perms = 0;
 387
 388         if (!qproc->need_mem_protection)
 389                 return 0;
 390
 391         if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
 392             remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
 393                 return 0;
 394
 395         if (local) {
 396                 next[perms].vmid = QCOM_SCM_VMID_HLOS;
 397                 next[perms].perm = QCOM_SCM_PERM_RWX;
 398                 perms++;
 399         }
 400
 401         if (remote) {
 402                 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
 403                 next[perms].perm = QCOM_SCM_PERM_RW;
 404                 perms++;
 405         }
 406
 407         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 408                                    current_perm, next, perms);
 409 }
 410
 411 static void q6v5_debug_policy_load(struct q6v5 *qproc)
 412 {
 413         const struct firmware *dp_fw;
 414
 415         if (reject_firmware_direct(&dp_fw, "msadp", qproc->dev))
 416                 return;
 417
 418         if (SZ_1M + dp_fw->size <= qproc->mba_size) {
 419                 memcpy(qproc->mba_region + SZ_1M, dp_fw->data, dp_fw->size);
 420                 qproc->dp_size = dp_fw->size;
 421         }
 422
 423         release_firmware(dp_fw);
 424 }
 425
 426 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 427 {
 428         struct q6v5 *qproc = rproc->priv;
 429
 430         /* MBA is restricted to a maximum size of 1M */
 431         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 432                 dev_err(qproc->dev, "MBA firmware load failed\n");
 433                 return -EINVAL;
 434         }
 435
 436         memcpy(qproc->mba_region, fw->data, fw->size);
 437         q6v5_debug_policy_load(qproc);
 438
 439         return 0;
 440 }
 441
 442 static int q6v5_reset_assert(struct q6v5 *qproc)
 443 {
 444         int ret;
 445
 446         if (qproc->has_alt_reset) {
 447                 reset_control_assert(qproc->pdc_reset);
 448                 ret = reset_control_reset(qproc->mss_restart);
 449                 reset_control_deassert(qproc->pdc_reset);
 450         } else if (qproc->has_spare_reg) {
 451                 /*
 452                  * When the AXI pipeline is being reset with the Q6 modem partly
 453                  * operational there is possibility of AXI valid signal to
 454                  * glitch, leading to spurious transactions and Q6 hangs. A work
 455                  * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
 456                  * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
 457                  * is withdrawn post MSS assert followed by a MSS deassert,
 458                  * while holding the PDC reset.
 459                  */
 460                 reset_control_assert(qproc->pdc_reset);
 461                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 462                                    AXI_GATING_VALID_OVERRIDE, 1);
 463                 reset_control_assert(qproc->mss_restart);
 464                 reset_control_deassert(qproc->pdc_reset);
 465                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 466                                    AXI_GATING_VALID_OVERRIDE, 0);
 467                 ret = reset_control_deassert(qproc->mss_restart);
 468         } else {
 469                 ret = reset_control_assert(qproc->mss_restart);
 470         }
 471
 472         return ret;
 473 }
 474
 475 static int q6v5_reset_deassert(struct q6v5 *qproc)
 476 {
 477         int ret;
 478
 479         if (qproc->has_alt_reset) {
 480                 reset_control_assert(qproc->pdc_reset);
 481                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 482                 ret = reset_control_reset(qproc->mss_restart);
 483                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 484                 reset_control_deassert(qproc->pdc_reset);
 485         } else if (qproc->has_spare_reg) {
 486                 ret = reset_control_reset(qproc->mss_restart);
 487         } else {
 488                 ret = reset_control_deassert(qproc->mss_restart);
 489         }
 490
 491         return ret;
 492 }
 493
 494 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 495 {
 496         unsigned long timeout;
 497         s32 val;
 498
 499         timeout = jiffies + msecs_to_jiffies(ms);
 500         for (;;) {
 501                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 502                 if (val)
 503                         break;
 504
 505                 if (time_after(jiffies, timeout))
 506                         return -ETIMEDOUT;
 507
 508                 msleep(1);
 509         }
 510
 511         return val;
 512 }
 513
 514 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 515 {
 516
 517         unsigned long timeout;
 518         s32 val;
 519
 520         timeout = jiffies + msecs_to_jiffies(ms);
 521         for (;;) {
 522                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 523                 if (val < 0)
 524                         break;
 525
 526                 if (!status && val)
 527                         break;
 528                 else if (status && val == status)
 529                         break;
 530
 531                 if (time_after(jiffies, timeout))
 532                         return -ETIMEDOUT;
 533
 534                 msleep(1);
 535         }
 536
 537         return val;
 538 }
 539
 540 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
 541 {
 542         struct rproc *rproc = qproc->rproc;
 543         void *data;
 544
 545         if (!qproc->has_mba_logs)
 546                 return;
 547
 548         if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
 549                                     qproc->mba_size))
 550                 return;
 551
 552         data = vmalloc(MBA_LOG_SIZE);
 553         if (!data)
 554                 return;
 555
 556         memcpy(data, qproc->mba_region, MBA_LOG_SIZE);
 557         dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
 558 }
 559
 560 static int q6v5proc_reset(struct q6v5 *qproc)
 561 {
 562         u32 val;
 563         int ret;
 564         int i;
 565
 566         if (qproc->version == MSS_SDM845) {
 567                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 568                 val |= Q6SS_CBCR_CLKEN;
 569                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 570
 571                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 572                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 573                                          Q6SS_CBCR_TIMEOUT_US);
 574                 if (ret) {
 575                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 576                         return -ETIMEDOUT;
 577                 }
 578
 579                 /* De-assert QDSP6 stop core */
 580                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 581                 /* Trigger boot FSM */
 582                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 583
 584                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 585                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 586                 if (ret) {
 587                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 588                         /* Reset the modem so that boot FSM is in reset state */
 589                         q6v5_reset_deassert(qproc);
 590                         return ret;
 591                 }
 592
 593                 goto pbl_wait;
 594         } else if (qproc->version == MSS_SC7180) {
 595                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 596                 val |= Q6SS_CBCR_CLKEN;
 597                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 598
 599                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 600                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 601                                          Q6SS_CBCR_TIMEOUT_US);
 602                 if (ret) {
 603                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 604                         return -ETIMEDOUT;
 605                 }
 606
 607                 /* Turn on the XO clock needed for PLL setup */
 608                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 609                 val |= Q6SS_CBCR_CLKEN;
 610                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 611
 612                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 613                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 614                                          Q6SS_CBCR_TIMEOUT_US);
 615                 if (ret) {
 616                         dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
 617                         return -ETIMEDOUT;
 618                 }
 619
 620                 /* Configure Q6 core CBCR to auto-enable after reset sequence */
 621                 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
 622                 val |= Q6SS_CBCR_CLKEN;
 623                 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
 624
 625                 /* De-assert the Q6 stop core signal */
 626                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 627
 628                 /* Wait for 10 us for any staggering logic to settle */
 629                 usleep_range(10, 20);
 630
 631                 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
 632                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 633
 634                 /* Poll the MSS_STATUS for FSM completion */
 635                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 636                                          val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 637                 if (ret) {
 638                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 639                         /* Reset the modem so that boot FSM is in reset state */
 640                         q6v5_reset_deassert(qproc);
 641                         return ret;
 642                 }
 643                 goto pbl_wait;
 644         } else if (qproc->version == MSS_MSM8996 ||
 645                    qproc->version == MSS_MSM8998) {
 646                 int mem_pwr_ctl;
 647
 648                 /* Override the ACC value if required */
 649                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 650                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 651
 652                 /* Assert resets, stop core */
 653                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 654                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 655                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 656
 657                 /* BHS require xo cbcr to be enabled */
 658                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 659                 val |= Q6SS_CBCR_CLKEN;
 660                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 661
 662                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 663                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 664                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 665                                          Q6SS_CBCR_TIMEOUT_US);
 666                 if (ret) {
 667                         dev_err(qproc->dev,
 668                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 669                         return ret;
 670                 }
 671                 /* Enable power block headswitch and wait for it to stabilize */
 672                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 673                 val |= QDSP6v56_BHS_ON;
 674                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 675                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 676                 udelay(1);
 677
 678                 /* Put LDO in bypass mode */
 679                 val |= QDSP6v56_LDO_BYP;
 680                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 681
 682                 /* Deassert QDSP6 compiler memory clamp */
 683                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 684                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 685                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 686
 687                 /* Deassert memory peripheral sleep and L2 memory standby */
 688                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 689                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 690
 691                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 692                 if (qproc->version == MSS_MSM8996) {
 693                         mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
 694                         i = 19;
 695                 } else {
 696                         /* MSS_MSM8998 */
 697                         mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
 698                         i = 28;
 699                 }
 700                 val = readl(qproc->reg_base + mem_pwr_ctl);
 701                 for (; i >= 0; i--) {
 702                         val |= BIT(i);
 703                         writel(val, qproc->reg_base + mem_pwr_ctl);
 704                         /*
 705                          * Read back value to ensure the write is done then
 706                          * wait for 1us for both memory peripheral and data
 707                          * array to turn on.
 708                          */
 709                         val |= readl(qproc->reg_base + mem_pwr_ctl);
 710                         udelay(1);
 711                 }
 712                 /* Remove word line clamp */
 713                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 714                 val &= ~QDSP6v56_CLAMP_WL;
 715                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 716         } else {
 717                 /* Assert resets, stop core */
 718                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 719                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 720                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 721
 722                 /* Enable power block headswitch and wait for it to stabilize */
 723                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 724                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 725                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 726                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 727                 udelay(1);
 728                 /*
 729                  * Turn on memories. L2 banks should be done individually
 730                  * to minimize inrush current.
 731                  */
 732                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 733                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 734                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 735                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 736                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 737                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 738                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 739                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 740                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 741                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 742         }
 743         /* Remove IO clamp */
 744         val &= ~Q6SS_CLAMP_IO;
 745         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 746
 747         /* Bring core out of reset */
 748         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 749         val &= ~Q6SS_CORE_ARES;
 750         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 751
 752         /* Turn on core clock */
 753         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 754         val |= Q6SS_CLK_ENABLE;
 755         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 756
 757         /* Start core execution */
 758         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 759         val &= ~Q6SS_STOP_CORE;
 760         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 761
 762 pbl_wait:
 763         /* Wait for PBL status */
 764         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 765         if (ret == -ETIMEDOUT) {
 766                 dev_err(qproc->dev, "PBL boot timed out\n");
 767         } else if (ret != RMB_PBL_SUCCESS) {
 768                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 769                 ret = -EINVAL;
 770         } else {
 771                 ret = 0;
 772         }
 773
 774         return ret;
 775 }
 776
 777 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 778                                    struct regmap *halt_map,
 779                                    u32 offset)
 780 {
 781         unsigned int val;
 782         int ret;
 783
 784         /* Check if we're already idle */
 785         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 786         if (!ret && val)
 787                 return;
 788
 789         /* Assert halt request */
 790         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 791
 792         /* Wait for halt */
 793         regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
 794                                  val, 1000, HALT_ACK_TIMEOUT_US);
 795
 796         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 797         if (ret || !val)
 798                 dev_err(qproc->dev, "port failed halt\n");
 799
 800         /* Clear halt request (port will remain halted until reset) */
 801         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 802 }
 803
 804 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 805 {
 806         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 807         dma_addr_t phys;
 808         void *metadata;
 809         int mdata_perm;
 810         int xferop_ret;
 811         size_t size;
 812         void *ptr;
 813         int ret;
 814
 815         metadata = qcom_mdt_read_metadata(fw, &size);
 816         if (IS_ERR(metadata))
 817                 return PTR_ERR(metadata);
 818
 819         ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
 820         if (!ptr) {
 821                 kfree(metadata);
 822                 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 823                 return -ENOMEM;
 824         }
 825
 826         memcpy(ptr, metadata, size);
 827
 828         /* Hypervisor mapping to access metadata by modem */
 829         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 830         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
 831                                       phys, size);
 832         if (ret) {
 833                 dev_err(qproc->dev,
 834                         "assigning Q6 access to metadata failed: %d\n", ret);
 835                 ret = -EAGAIN;
 836                 goto free_dma_attrs;
 837         }
 838
 839         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 840         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 841
 842         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 843         if (ret == -ETIMEDOUT)
 844                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 845         else if (ret < 0)
 846                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
 847
 848         /* Metadata authentication done, remove modem access */
 849         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
 850                                              phys, size);
 851         if (xferop_ret)
 852                 dev_warn(qproc->dev,
 853                          "mdt buffer not reclaimed system may become unstable\n");
 854
 855 free_dma_attrs:
 856         dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
 857         kfree(metadata);
 858
 859         return ret < 0 ? ret : 0;
 860 }
 861
 862 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
 863 {
 864         if (phdr->p_type != PT_LOAD)
 865                 return false;
 866
 867         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 868                 return false;
 869
 870         if (!phdr->p_memsz)
 871                 return false;
 872
 873         return true;
 874 }
 875
 876 static int q6v5_mba_load(struct q6v5 *qproc)
 877 {
 878         int ret;
 879         int xfermemop_ret;
 880         bool mba_load_err = false;
 881
 882         qcom_q6v5_prepare(&qproc->q6v5);
 883
 884         ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
 885         if (ret < 0) {
 886                 dev_err(qproc->dev, "failed to enable active power domains\n");
 887                 goto disable_irqs;
 888         }
 889
 890         ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
 891         if (ret < 0) {
 892                 dev_err(qproc->dev, "failed to enable proxy power domains\n");
 893                 goto disable_active_pds;
 894         }
 895
 896         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
 897                                     qproc->proxy_reg_count);
 898         if (ret) {
 899                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
 900                 goto disable_proxy_pds;
 901         }
 902
 903         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
 904                               qproc->proxy_clk_count);
 905         if (ret) {
 906                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
 907                 goto disable_proxy_reg;
 908         }
 909
 910         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
 911                                     qproc->active_reg_count);
 912         if (ret) {
 913                 dev_err(qproc->dev, "failed to enable supplies\n");
 914                 goto disable_proxy_clk;
 915         }
 916
 917         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
 918                               qproc->reset_clk_count);
 919         if (ret) {
 920                 dev_err(qproc->dev, "failed to enable reset clocks\n");
 921                 goto disable_vdd;
 922         }
 923
 924         ret = q6v5_reset_deassert(qproc);
 925         if (ret) {
 926                 dev_err(qproc->dev, "failed to deassert mss restart\n");
 927                 goto disable_reset_clks;
 928         }
 929
 930         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
 931                               qproc->active_clk_count);
 932         if (ret) {
 933                 dev_err(qproc->dev, "failed to enable clocks\n");
 934                 goto assert_reset;
 935         }
 936
 937         /*
 938          * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
 939          * the Q6 access to this region.
 940          */
 941         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
 942                                       qproc->mpss_phys, qproc->mpss_size);
 943         if (ret) {
 944                 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
 945                 goto disable_active_clks;
 946         }
 947
 948         /* Assign MBA image access in DDR to q6 */
 949         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
 950                                       qproc->mba_phys, qproc->mba_size);
 951         if (ret) {
 952                 dev_err(qproc->dev,
 953                         "assigning Q6 access to mba memory failed: %d\n", ret);
 954                 goto disable_active_clks;
 955         }
 956
 957         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
 958         if (qproc->dp_size) {
 959                 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
 960                 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 961         }
 962
 963         ret = q6v5proc_reset(qproc);
 964         if (ret)
 965                 goto reclaim_mba;
 966
 967         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
 968         if (ret == -ETIMEDOUT) {
 969                 dev_err(qproc->dev, "MBA boot timed out\n");
 970                 goto halt_axi_ports;
 971         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
 972                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
 973                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
 974                 ret = -EINVAL;
 975                 goto halt_axi_ports;
 976         }
 977
 978         qproc->dump_mba_loaded = true;
 979         return 0;
 980
 981 halt_axi_ports:
 982         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 983         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 984         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 985         mba_load_err = true;
 986 reclaim_mba:
 987         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
 988                                                 false, qproc->mba_phys,
 989                                                 qproc->mba_size);
 990         if (xfermemop_ret) {
 991                 dev_err(qproc->dev,
 992                         "Failed to reclaim mba buffer, system may become unstable\n");
 993         } else if (mba_load_err) {
 994                 q6v5_dump_mba_logs(qproc);
 995         }
 996
 997 disable_active_clks:
 998         q6v5_clk_disable(qproc->dev, qproc->active_clks,
 999                          qproc->active_clk_count);
1000 assert_reset:
1001         q6v5_reset_assert(qproc);
1002 disable_reset_clks:
1003         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1004                          qproc->reset_clk_count);
1005 disable_vdd:
1006         q6v5_regulator_disable(qproc, qproc->active_regs,
1007                                qproc->active_reg_count);
1008 disable_proxy_clk:
1009         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1010                          qproc->proxy_clk_count);
1011 disable_proxy_reg:
1012         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1013                                qproc->proxy_reg_count);
1014 disable_proxy_pds:
1015         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1016 disable_active_pds:
1017         q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1018 disable_irqs:
1019         qcom_q6v5_unprepare(&qproc->q6v5);
1020
1021         return ret;
1022 }
1023
1024 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1025 {
1026         int ret;
1027         u32 val;
1028
1029         qproc->dump_mba_loaded = false;
1030         qproc->dp_size = 0;
1031
1032         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1033         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1034         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1035         if (qproc->version == MSS_MSM8996) {
1036                 /*
1037                  * To avoid high MX current during LPASS/MSS restart.
1038                  */
1039                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1040                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1041                         QDSP6v56_CLAMP_QMC_MEM;
1042                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1043         }
1044
1045         q6v5_reset_assert(qproc);
1046
1047         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1048                          qproc->reset_clk_count);
1049         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1050                          qproc->active_clk_count);
1051         q6v5_regulator_disable(qproc, qproc->active_regs,
1052                                qproc->active_reg_count);
1053         q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
1054
1055         /* In case of failure or coredump scenario where reclaiming MBA memory
1056          * could not happen reclaim it here.
1057          */
1058         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1059                                       qproc->mba_phys,
1060                                       qproc->mba_size);
1061         WARN_ON(ret);
1062
1063         ret = qcom_q6v5_unprepare(&qproc->q6v5);
1064         if (ret) {
1065                 q6v5_pds_disable(qproc, qproc->proxy_pds,
1066                                  qproc->proxy_pd_count);
1067                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1068                                  qproc->proxy_clk_count);
1069                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1070                                        qproc->proxy_reg_count);
1071         }
1072 }
1073
1074 static int q6v5_reload_mba(struct rproc *rproc)
1075 {
1076         struct q6v5 *qproc = rproc->priv;
1077         const struct firmware *fw;
1078         int ret;
1079
1080         ret = reject_firmware(&fw, rproc->firmware, qproc->dev);
1081         if (ret < 0)
1082                 return ret;
1083
1084         q6v5_load(rproc, fw);
1085         ret = q6v5_mba_load(qproc);
1086         release_firmware(fw);
1087
1088         return ret;
1089 }
1090
1091 static int q6v5_mpss_load(struct q6v5 *qproc)
1092 {
1093         const struct elf32_phdr *phdrs;
1094         const struct elf32_phdr *phdr;
1095         const struct firmware *seg_fw;
1096         const struct firmware *fw;
1097         struct elf32_hdr *ehdr;
1098         phys_addr_t mpss_reloc;
1099         phys_addr_t boot_addr;
1100         phys_addr_t min_addr = PHYS_ADDR_MAX;
1101         phys_addr_t max_addr = 0;
1102         u32 code_length;
1103         bool relocate = false;
1104         char *fw_name;
1105         size_t fw_name_len;
1106         ssize_t offset;
1107         size_t size = 0;
1108         void *ptr;
1109         int ret;
1110         int i;
1111
1112         fw_name_len = strlen(qproc->hexagon_mdt_image);
1113         if (fw_name_len <= 4)
1114                 return -EINVAL;
1115
1116         fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1117         if (!fw_name)
1118                 return -ENOMEM;
1119
1120         ret = reject_firmware(&fw, fw_name, qproc->dev);
1121         if (ret < 0) {
1122                 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1123                 goto out;
1124         }
1125
1126         /* Initialize the RMB validator */
1127         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1128
1129         ret = q6v5_mpss_init_image(qproc, fw);
1130         if (ret)
1131                 goto release_firmware;
1132
1133         ehdr = (struct elf32_hdr *)fw->data;
1134         phdrs = (struct elf32_phdr *)(ehdr + 1);
1135
1136         for (i = 0; i < ehdr->e_phnum; i++) {
1137                 phdr = &phdrs[i];
1138
1139                 if (!q6v5_phdr_valid(phdr))
1140                         continue;
1141
1142                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1143                         relocate = true;
1144
1145                 if (phdr->p_paddr < min_addr)
1146                         min_addr = phdr->p_paddr;
1147
1148                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1149                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1150         }
1151
1152         /*
1153          * In case of a modem subsystem restart on secure devices, the modem
1154          * memory can be reclaimed only after MBA is loaded.
1155          */
1156         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1157                                 qproc->mpss_phys, qproc->mpss_size);
1158
1159         /* Share ownership between Linux and MSS, during segment loading */
1160         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1161                                       qproc->mpss_phys, qproc->mpss_size);
1162         if (ret) {
1163                 dev_err(qproc->dev,
1164                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1165                 ret = -EAGAIN;
1166                 goto release_firmware;
1167         }
1168
1169         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1170         qproc->mpss_reloc = mpss_reloc;
1171         /* Load firmware segments */
1172         for (i = 0; i < ehdr->e_phnum; i++) {
1173                 phdr = &phdrs[i];
1174
1175                 if (!q6v5_phdr_valid(phdr))
1176                         continue;
1177
1178                 offset = phdr->p_paddr - mpss_reloc;
1179                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1180                         dev_err(qproc->dev, "segment outside memory range\n");
1181                         ret = -EINVAL;
1182                         goto release_firmware;
1183                 }
1184
1185                 if (phdr->p_filesz > phdr->p_memsz) {
1186                         dev_err(qproc->dev,
1187                                 "refusing to load segment %d with p_filesz > p_memsz\n",
1188                                 i);
1189                         ret = -EINVAL;
1190                         goto release_firmware;
1191                 }
1192
1193                 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1194                 if (!ptr) {
1195                         dev_err(qproc->dev,
1196                                 "unable to map memory region: %pa+%zx-%x\n",
1197                                 &qproc->mpss_phys, offset, phdr->p_memsz);
1198                         goto release_firmware;
1199                 }
1200
1201                 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1202                         /* Firmware is large enough to be non-split */
1203                         if (phdr->p_offset + phdr->p_filesz > fw->size) {
1204                                 dev_err(qproc->dev,
1205                                         "failed to load segment %d from truncated file %s\n",
1206                                         i, fw_name);
1207                                 ret = -EINVAL;
1208                                 memunmap(ptr);
1209                                 goto release_firmware;
1210                         }
1211
1212                         memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1213                 } else if (phdr->p_filesz) {
1214                         /* Replace "xxx.xxx" with "xxx.bxx" */
1215                         sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1216                         ret = reject_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1217                                                         ptr, phdr->p_filesz);
1218                         if (ret) {
1219                                 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1220                                 memunmap(ptr);
1221                                 goto release_firmware;
1222                         }
1223
1224                         if (seg_fw->size != phdr->p_filesz) {
1225                                 dev_err(qproc->dev,
1226                                         "failed to load segment %d from truncated file %s\n",
1227                                         i, fw_name);
1228                                 ret = -EINVAL;
1229                                 release_firmware(seg_fw);
1230                                 memunmap(ptr);
1231                                 goto release_firmware;
1232                         }
1233
1234                         release_firmware(seg_fw);
1235                 }
1236
1237                 if (phdr->p_memsz > phdr->p_filesz) {
1238                         memset(ptr + phdr->p_filesz, 0,
1239                                phdr->p_memsz - phdr->p_filesz);
1240                 }
1241                 memunmap(ptr);
1242                 size += phdr->p_memsz;
1243
1244                 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1245                 if (!code_length) {
1246                         boot_addr = relocate ? qproc->mpss_phys : min_addr;
1247                         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1248                         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1249                 }
1250                 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1251
1252                 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1253                 if (ret < 0) {
1254                         dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1255                                 ret);
1256                         goto release_firmware;
1257                 }
1258         }
1259
1260         /* Transfer ownership of modem ddr region to q6 */
1261         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1262                                       qproc->mpss_phys, qproc->mpss_size);
1263         if (ret) {
1264                 dev_err(qproc->dev,
1265                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1266                 ret = -EAGAIN;
1267                 goto release_firmware;
1268         }
1269
1270         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1271         if (ret == -ETIMEDOUT)
1272                 dev_err(qproc->dev, "MPSS authentication timed out\n");
1273         else if (ret < 0)
1274                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1275
1276         qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1277
1278 release_firmware:
1279         release_firmware(fw);
1280 out:
1281         kfree(fw_name);
1282
1283         return ret < 0 ? ret : 0;
1284 }
1285
1286 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1287                                    struct rproc_dump_segment *segment,
1288                                    void *dest, size_t cp_offset, size_t size)
1289 {
1290         int ret = 0;
1291         struct q6v5 *qproc = rproc->priv;
1292         int offset = segment->da - qproc->mpss_reloc;
1293         void *ptr = NULL;
1294
1295         /* Unlock mba before copying segments */
1296         if (!qproc->dump_mba_loaded) {
1297                 ret = q6v5_reload_mba(rproc);
1298                 if (!ret) {
1299                         /* Reset ownership back to Linux to copy segments */
1300                         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1301                                                       true, false,
1302                                                       qproc->mpss_phys,
1303                                                       qproc->mpss_size);
1304                 }
1305         }
1306
1307         if (!ret)
1308                 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1309
1310         if (ptr) {
1311                 memcpy(dest, ptr, size);
1312                 memunmap(ptr);
1313         } else {
1314                 memset(dest, 0xff, size);
1315         }
1316
1317         qproc->current_dump_size += size;
1318
1319         /* Reclaim mba after copying segments */
1320         if (qproc->current_dump_size == qproc->total_dump_size) {
1321                 if (qproc->dump_mba_loaded) {
1322                         /* Try to reset ownership back to Q6 */
1323                         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1324                                                 false, true,
1325                                                 qproc->mpss_phys,
1326                                                 qproc->mpss_size);
1327                         q6v5_mba_reclaim(qproc);
1328                 }
1329         }
1330 }
1331
1332 static int q6v5_start(struct rproc *rproc)
1333 {
1334         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1335         int xfermemop_ret;
1336         int ret;
1337
1338         ret = q6v5_mba_load(qproc);
1339         if (ret)
1340                 return ret;
1341
1342         dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1343                  qproc->dp_size ? "" : "out");
1344
1345         ret = q6v5_mpss_load(qproc);
1346         if (ret)
1347                 goto reclaim_mpss;
1348
1349         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1350         if (ret == -ETIMEDOUT) {
1351                 dev_err(qproc->dev, "start timed out\n");
1352                 goto reclaim_mpss;
1353         }
1354
1355         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1356                                                 false, qproc->mba_phys,
1357                                                 qproc->mba_size);
1358         if (xfermemop_ret)
1359                 dev_err(qproc->dev,
1360                         "Failed to reclaim mba buffer system may become unstable\n");
1361
1362         /* Reset Dump Segment Mask */
1363         qproc->current_dump_size = 0;
1364
1365         return 0;
1366
1367 reclaim_mpss:
1368         q6v5_mba_reclaim(qproc);
1369         q6v5_dump_mba_logs(qproc);
1370
1371         return ret;
1372 }
1373
1374 static int q6v5_stop(struct rproc *rproc)
1375 {
1376         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1377         int ret;
1378
1379         ret = qcom_q6v5_request_stop(&qproc->q6v5);
1380         if (ret == -ETIMEDOUT)
1381                 dev_err(qproc->dev, "timed out on wait\n");
1382
1383         q6v5_mba_reclaim(qproc);
1384
1385         return 0;
1386 }
1387
1388 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1389                                             const struct firmware *mba_fw)
1390 {
1391         const struct firmware *fw;
1392         const struct elf32_phdr *phdrs;
1393         const struct elf32_phdr *phdr;
1394         const struct elf32_hdr *ehdr;
1395         struct q6v5 *qproc = rproc->priv;
1396         unsigned long i;
1397         int ret;
1398
1399         ret = reject_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1400         if (ret < 0) {
1401                 dev_err(qproc->dev, "unable to load %s\n",
1402                         qproc->hexagon_mdt_image);
1403                 return ret;
1404         }
1405
1406         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1407
1408         ehdr = (struct elf32_hdr *)fw->data;
1409         phdrs = (struct elf32_phdr *)(ehdr + 1);
1410         qproc->total_dump_size = 0;
1411
1412         for (i = 0; i < ehdr->e_phnum; i++) {
1413                 phdr = &phdrs[i];
1414
1415                 if (!q6v5_phdr_valid(phdr))
1416                         continue;
1417
1418                 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1419                                                         phdr->p_memsz,
1420                                                         qcom_q6v5_dump_segment,
1421                                                         NULL);
1422                 if (ret)
1423                         break;
1424
1425                 qproc->total_dump_size += phdr->p_memsz;
1426         }
1427
1428         release_firmware(fw);
1429         return ret;
1430 }
1431
1432 static const struct rproc_ops q6v5_ops = {
1433         .start = q6v5_start,
1434         .stop = q6v5_stop,
1435         .parse_fw = qcom_q6v5_register_dump_segments,
1436         .load = q6v5_load,
1437 };
1438
1439 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1440 {
1441         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1442
1443         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1444                          qproc->proxy_clk_count);
1445         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1446                                qproc->proxy_reg_count);
1447         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1448 }
1449
1450 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1451 {
1452         struct of_phandle_args args;
1453         struct resource *res;
1454         int ret;
1455
1456         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
1457         qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1458         if (IS_ERR(qproc->reg_base))
1459                 return PTR_ERR(qproc->reg_base);
1460
1461         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
1462         qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
1463         if (IS_ERR(qproc->rmb_base))
1464                 return PTR_ERR(qproc->rmb_base);
1465
1466         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1467                                                "qcom,halt-regs", 3, 0, &args);
1468         if (ret < 0) {
1469                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1470                 return -EINVAL;
1471         }
1472
1473         qproc->halt_map = syscon_node_to_regmap(args.np);
1474         of_node_put(args.np);
1475         if (IS_ERR(qproc->halt_map))
1476                 return PTR_ERR(qproc->halt_map);
1477
1478         qproc->halt_q6 = args.args[0];
1479         qproc->halt_modem = args.args[1];
1480         qproc->halt_nc = args.args[2];
1481
1482         if (qproc->has_spare_reg) {
1483                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1484                                                        "qcom,spare-regs",
1485                                                        1, 0, &args);
1486                 if (ret < 0) {
1487                         dev_err(&pdev->dev, "failed to parse spare-regs\n");
1488                         return -EINVAL;
1489                 }
1490
1491                 qproc->conn_map = syscon_node_to_regmap(args.np);
1492                 of_node_put(args.np);
1493                 if (IS_ERR(qproc->conn_map))
1494                         return PTR_ERR(qproc->conn_map);
1495
1496                 qproc->conn_box = args.args[0];
1497         }
1498
1499         return 0;
1500 }
1501
1502 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1503                 char **clk_names)
1504 {
1505         int i;
1506
1507         if (!clk_names)
1508                 return 0;
1509
1510         for (i = 0; clk_names[i]; i++) {
1511                 clks[i] = devm_clk_get(dev, clk_names[i]);
1512                 if (IS_ERR(clks[i])) {
1513                         int rc = PTR_ERR(clks[i]);
1514
1515                         if (rc != -EPROBE_DEFER)
1516                                 dev_err(dev, "Failed to get %s clock\n",
1517                                         clk_names[i]);
1518                         return rc;
1519                 }
1520         }
1521
1522         return i;
1523 }
1524
1525 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1526                            char **pd_names)
1527 {
1528         size_t num_pds = 0;
1529         int ret;
1530         int i;
1531
1532         if (!pd_names)
1533                 return 0;
1534
1535         while (pd_names[num_pds])
1536                 num_pds++;
1537
1538         for (i = 0; i < num_pds; i++) {
1539                 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1540                 if (IS_ERR_OR_NULL(devs[i])) {
1541                         ret = PTR_ERR(devs[i]) ? : -ENODATA;
1542                         goto unroll_attach;
1543                 }
1544         }
1545
1546         return num_pds;
1547
1548 unroll_attach:
1549         for (i--; i >= 0; i--)
1550                 dev_pm_domain_detach(devs[i], false);
1551
1552         return ret;
1553 }
1554
1555 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1556                             size_t pd_count)
1557 {
1558         int i;
1559
1560         for (i = 0; i < pd_count; i++)
1561                 dev_pm_domain_detach(pds[i], false);
1562 }
1563
1564 static int q6v5_init_reset(struct q6v5 *qproc)
1565 {
1566         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1567                                                               "mss_restart");
1568         if (IS_ERR(qproc->mss_restart)) {
1569                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1570                 return PTR_ERR(qproc->mss_restart);
1571         }
1572
1573         if (qproc->has_alt_reset || qproc->has_spare_reg) {
1574                 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1575                                                                     "pdc_reset");
1576                 if (IS_ERR(qproc->pdc_reset)) {
1577                         dev_err(qproc->dev, "failed to acquire pdc reset\n");
1578                         return PTR_ERR(qproc->pdc_reset);
1579                 }
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1586 {
1587         struct device_node *child;
1588         struct device_node *node;
1589         struct resource r;
1590         int ret;
1591
1592         /*
1593          * In the absence of mba/mpss sub-child, extract the mba and mpss
1594          * reserved memory regions from device's memory-region property.
1595          */
1596         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1597         if (!child) {
1598                 node = of_parse_phandle(qproc->dev->of_node,
1599                                         "memory-region", 0);
1600         } else {
1601                 node = of_parse_phandle(child, "memory-region", 0);
1602                 of_node_put(child);
1603         }
1604
1605         ret = of_address_to_resource(node, 0, &r);
1606         of_node_put(node);
1607         if (ret) {
1608                 dev_err(qproc->dev, "unable to resolve mba region\n");
1609                 return ret;
1610         }
1611
1612         qproc->mba_phys = r.start;
1613         qproc->mba_size = resource_size(&r);
1614         qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1615         if (!qproc->mba_region) {
1616                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1617                         &r.start, qproc->mba_size);
1618                 return -EBUSY;
1619         }
1620
1621         if (!child) {
1622                 node = of_parse_phandle(qproc->dev->of_node,
1623                                         "memory-region", 1);
1624         } else {
1625                 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1626                 node = of_parse_phandle(child, "memory-region", 0);
1627                 of_node_put(child);
1628         }
1629
1630         ret = of_address_to_resource(node, 0, &r);
1631         of_node_put(node);
1632         if (ret) {
1633                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1634                 return ret;
1635         }
1636
1637         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1638         qproc->mpss_size = resource_size(&r);
1639
1640         return 0;
1641 }
1642
1643 static int q6v5_probe(struct platform_device *pdev)
1644 {
1645         const struct rproc_hexagon_res *desc;
1646         struct q6v5 *qproc;
1647         struct rproc *rproc;
1648         const char *mba_image;
1649         int ret;
1650
1651         desc = of_device_get_match_data(&pdev->dev);
1652         if (!desc)
1653                 return -EINVAL;
1654
1655         if (desc->need_mem_protection && !qcom_scm_is_available())
1656                 return -EPROBE_DEFER;
1657
1658         mba_image = desc->hexagon_mba_image;
1659         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1660                                             0, &mba_image);
1661         if (ret < 0 && ret != -EINVAL)
1662                 return ret;
1663
1664         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1665                             mba_image, sizeof(*qproc));
1666         if (!rproc) {
1667                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1668                 return -ENOMEM;
1669         }
1670
1671         rproc->auto_boot = false;
1672         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1673
1674         qproc = (struct q6v5 *)rproc->priv;
1675         qproc->dev = &pdev->dev;
1676         qproc->rproc = rproc;
1677         qproc->hexagon_mdt_image = "/*(DEBLOBBED)*/";
1678         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1679                                             1, &qproc->hexagon_mdt_image);
1680         if (ret < 0 && ret != -EINVAL)
1681                 goto free_rproc;
1682
1683         platform_set_drvdata(pdev, qproc);
1684
1685         qproc->has_spare_reg = desc->has_spare_reg;
1686         ret = q6v5_init_mem(qproc, pdev);
1687         if (ret)
1688                 goto free_rproc;
1689
1690         ret = q6v5_alloc_memory_region(qproc);
1691         if (ret)
1692                 goto free_rproc;
1693
1694         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1695                                desc->proxy_clk_names);
1696         if (ret < 0) {
1697                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1698                 goto free_rproc;
1699         }
1700         qproc->proxy_clk_count = ret;
1701
1702         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1703                                desc->reset_clk_names);
1704         if (ret < 0) {
1705                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1706                 goto free_rproc;
1707         }
1708         qproc->reset_clk_count = ret;
1709
1710         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1711                                desc->active_clk_names);
1712         if (ret < 0) {
1713                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1714                 goto free_rproc;
1715         }
1716         qproc->active_clk_count = ret;
1717
1718         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1719                                   desc->proxy_supply);
1720         if (ret < 0) {
1721                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1722                 goto free_rproc;
1723         }
1724         qproc->proxy_reg_count = ret;
1725
1726         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
1727                                   desc->active_supply);
1728         if (ret < 0) {
1729                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1730                 goto free_rproc;
1731         }
1732         qproc->active_reg_count = ret;
1733
1734         ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
1735                               desc->active_pd_names);
1736         if (ret < 0) {
1737                 dev_err(&pdev->dev, "Failed to attach active power domains\n");
1738                 goto free_rproc;
1739         }
1740         qproc->active_pd_count = ret;
1741
1742         ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1743                               desc->proxy_pd_names);
1744         if (ret < 0) {
1745                 dev_err(&pdev->dev, "Failed to init power domains\n");
1746                 goto detach_active_pds;
1747         }
1748         qproc->proxy_pd_count = ret;
1749
1750         qproc->has_alt_reset = desc->has_alt_reset;
1751         ret = q6v5_init_reset(qproc);
1752         if (ret)
1753                 goto detach_proxy_pds;
1754
1755         qproc->version = desc->version;
1756         qproc->need_mem_protection = desc->need_mem_protection;
1757         qproc->has_mba_logs = desc->has_mba_logs;
1758
1759         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
1760                              qcom_msa_handover);
1761         if (ret)
1762                 goto detach_proxy_pds;
1763
1764         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1765         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1766         qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1767         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1768         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1769         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1770         if (IS_ERR(qproc->sysmon)) {
1771                 ret = PTR_ERR(qproc->sysmon);
1772                 goto remove_subdevs;
1773         }
1774
1775         ret = rproc_add(rproc);
1776         if (ret)
1777                 goto remove_sysmon_subdev;
1778
1779         return 0;
1780
1781 remove_sysmon_subdev:
1782         qcom_remove_sysmon_subdev(qproc->sysmon);
1783 remove_subdevs:
1784         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1785         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1786         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1787 detach_proxy_pds:
1788         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1789 detach_active_pds:
1790         q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1791 free_rproc:
1792         rproc_free(rproc);
1793
1794         return ret;
1795 }
1796
1797 static int q6v5_remove(struct platform_device *pdev)
1798 {
1799         struct q6v5 *qproc = platform_get_drvdata(pdev);
1800         struct rproc *rproc = qproc->rproc;
1801
1802         rproc_del(rproc);
1803
1804         qcom_remove_sysmon_subdev(qproc->sysmon);
1805         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1806         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1807         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
1808
1809         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1810         q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
1811
1812         rproc_free(rproc);
1813
1814         return 0;
1815 }
1816
1817 static const struct rproc_hexagon_res sc7180_mss = {
1818         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1819         .proxy_clk_names = (char*[]){
1820                 "xo",
1821                 NULL
1822         },
1823         .reset_clk_names = (char*[]){
1824                 "iface",
1825                 "bus",
1826                 "snoc_axi",
1827                 NULL
1828         },
1829         .active_clk_names = (char*[]){
1830                 "mnoc_axi",
1831                 "nav",
1832                 NULL
1833         },
1834         .active_pd_names = (char*[]){
1835                 "load_state",
1836                 NULL
1837         },
1838         .proxy_pd_names = (char*[]){
1839                 "cx",
1840                 "mx",
1841                 "mss",
1842                 NULL
1843         },
1844         .need_mem_protection = true,
1845         .has_alt_reset = false,
1846         .has_mba_logs = true,
1847         .has_spare_reg = true,
1848         .version = MSS_SC7180,
1849 };
1850
1851 static const struct rproc_hexagon_res sdm845_mss = {
1852         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1853         .proxy_clk_names = (char*[]){
1854                         "xo",
1855                         "prng",
1856                         NULL
1857         },
1858         .reset_clk_names = (char*[]){
1859                         "iface",
1860                         "snoc_axi",
1861                         NULL
1862         },
1863         .active_clk_names = (char*[]){
1864                         "bus",
1865                         "mem",
1866                         "gpll0_mss",
1867                         "mnoc_axi",
1868                         NULL
1869         },
1870         .active_pd_names = (char*[]){
1871                         "load_state",
1872                         NULL
1873         },
1874         .proxy_pd_names = (char*[]){
1875                         "cx",
1876                         "mx",
1877                         "mss",
1878                         NULL
1879         },
1880         .need_mem_protection = true,
1881         .has_alt_reset = true,
1882         .has_mba_logs = false,
1883         .has_spare_reg = false,
1884         .version = MSS_SDM845,
1885 };
1886
1887 static const struct rproc_hexagon_res msm8998_mss = {
1888         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1889         .proxy_clk_names = (char*[]){
1890                         "xo",
1891                         "qdss",
1892                         "mem",
1893                         NULL
1894         },
1895         .active_clk_names = (char*[]){
1896                         "iface",
1897                         "bus",
1898                         "gpll0_mss",
1899                         "mnoc_axi",
1900                         "snoc_axi",
1901                         NULL
1902         },
1903         .proxy_pd_names = (char*[]){
1904                         "cx",
1905                         "mx",
1906                         NULL
1907         },
1908         .need_mem_protection = true,
1909         .has_alt_reset = false,
1910         .has_mba_logs = false,
1911         .has_spare_reg = false,
1912         .version = MSS_MSM8998,
1913 };
1914
1915 static const struct rproc_hexagon_res msm8996_mss = {
1916         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1917         .proxy_supply = (struct qcom_mss_reg_res[]) {
1918                 {
1919                         .supply = "pll",
1920                         .uA = 100000,
1921                 },
1922                 {}
1923         },
1924         .proxy_clk_names = (char*[]){
1925                         "xo",
1926                         "pnoc",
1927                         "qdss",
1928                         NULL
1929         },
1930         .active_clk_names = (char*[]){
1931                         "iface",
1932                         "bus",
1933                         "mem",
1934                         "gpll0_mss",
1935                         "snoc_axi",
1936                         "mnoc_axi",
1937                         NULL
1938         },
1939         .need_mem_protection = true,
1940         .has_alt_reset = false,
1941         .has_mba_logs = false,
1942         .has_spare_reg = false,
1943         .version = MSS_MSM8996,
1944 };
1945
1946 static const struct rproc_hexagon_res msm8916_mss = {
1947         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1948         .proxy_supply = (struct qcom_mss_reg_res[]) {
1949                 {
1950                         .supply = "mx",
1951                         .uV = 1050000,
1952                 },
1953                 {
1954                         .supply = "cx",
1955                         .uA = 100000,
1956                 },
1957                 {
1958                         .supply = "pll",
1959                         .uA = 100000,
1960                 },
1961                 {}
1962         },
1963         .proxy_clk_names = (char*[]){
1964                 "xo",
1965                 NULL
1966         },
1967         .active_clk_names = (char*[]){
1968                 "iface",
1969                 "bus",
1970                 "mem",
1971                 NULL
1972         },
1973         .need_mem_protection = false,
1974         .has_alt_reset = false,
1975         .has_mba_logs = false,
1976         .has_spare_reg = false,
1977         .version = MSS_MSM8916,
1978 };
1979
1980 static const struct rproc_hexagon_res msm8974_mss = {
1981         .hexagon_mba_image = "/*(DEBLOBBED)*/",
1982         .proxy_supply = (struct qcom_mss_reg_res[]) {
1983                 {
1984                         .supply = "mx",
1985                         .uV = 1050000,
1986                 },
1987                 {
1988                         .supply = "cx",
1989                         .uA = 100000,
1990                 },
1991                 {
1992                         .supply = "pll",
1993                         .uA = 100000,
1994                 },
1995                 {}
1996         },
1997         .active_supply = (struct qcom_mss_reg_res[]) {
1998                 {
1999                         .supply = "mss",
2000                         .uV = 1050000,
2001                         .uA = 100000,
2002                 },
2003                 {}
2004         },
2005         .proxy_clk_names = (char*[]){
2006                 "xo",
2007                 NULL
2008         },
2009         .active_clk_names = (char*[]){
2010                 "iface",
2011                 "bus",
2012                 "mem",
2013                 NULL
2014         },
2015         .need_mem_protection = false,
2016         .has_alt_reset = false,
2017         .has_mba_logs = false,
2018         .has_spare_reg = false,
2019         .version = MSS_MSM8974,
2020 };
2021
2022 static const struct of_device_id q6v5_of_match[] = {
2023         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2024         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2025         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2026         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2027         { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2028         { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2029         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2030         { },
2031 };
2032 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2033
2034 static struct platform_driver q6v5_driver = {
2035         .probe = q6v5_probe,
2036         .remove = q6v5_remove,
2037         .driver = {
2038                 .name = "qcom-q6v5-mss",
2039                 .of_match_table = q6v5_of_match,
2040         },
2041 };
2042 module_platform_driver(q6v5_driver);
2043
2044 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2045 MODULE_LICENSE("GPL v2");