drivers/regulator/cpcap-regulator.c

   1 /*
   2  * Motorola CPCAP PMIC regulator driver
   3  *
   4  * Based on cpcap-regulator.c from Motorola Linux kernel tree
   5  * Copyright (C) 2009-2011 Motorola, Inc.
   6  *
   7  * Rewritten for mainline kernel to use device tree and regmap
   8  * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation version 2.
  13  *
  14  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  15  * kind, whether express or implied; without even the implied warranty
  16  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/regmap.h>
  25 #include <linux/regulator/driver.h>
  26 #include <linux/regulator/machine.h>
  27 #include <linux/regulator/of_regulator.h>
  28 #include <linux/mfd/motorola-cpcap.h>
  29
  30 /*
  31  * Resource assignment register bits. These seem to control the state
  32  * idle modes adn are used at least for omap4.
  33  */
  34
  35 /* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
  36 #define CPCAP_BIT_VSDIO_SEL             BIT(15)
  37 #define CPCAP_BIT_VDIG_SEL              BIT(14)
  38 #define CPCAP_BIT_VCAM_SEL              BIT(13)
  39 #define CPCAP_BIT_SW6_SEL               BIT(12)
  40 #define CPCAP_BIT_SW5_SEL               BIT(11)
  41 #define CPCAP_BIT_SW4_SEL               BIT(10)
  42 #define CPCAP_BIT_SW3_SEL               BIT(9)
  43 #define CPCAP_BIT_SW2_SEL               BIT(8)
  44 #define CPCAP_BIT_SW1_SEL               BIT(7)
  45
  46 /* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
  47 #define CPCAP_BIT_VUSBINT2_SEL          BIT(15)
  48 #define CPCAP_BIT_VUSBINT1_SEL          BIT(14)
  49 #define CPCAP_BIT_VVIB_SEL              BIT(13)
  50 #define CPCAP_BIT_VWLAN1_SEL            BIT(12)
  51 #define CPCAP_BIT_VRF1_SEL              BIT(11)
  52 #define CPCAP_BIT_VHVIO_SEL             BIT(10)
  53 #define CPCAP_BIT_VDAC_SEL              BIT(9)
  54 #define CPCAP_BIT_VUSB_SEL              BIT(8)
  55 #define CPCAP_BIT_VSIM_SEL              BIT(7)
  56 #define CPCAP_BIT_VRFREF_SEL            BIT(6)
  57 #define CPCAP_BIT_VPLL_SEL              BIT(5)
  58 #define CPCAP_BIT_VFUSE_SEL             BIT(4)
  59 #define CPCAP_BIT_VCSI_SEL              BIT(3)
  60 #define CPCAP_BIT_SPARE_14_2            BIT(2)
  61 #define CPCAP_BIT_VWLAN2_SEL            BIT(1)
  62 #define CPCAP_BIT_VRF2_SEL              BIT(0)
  63
  64 /* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
  65 #define CPCAP_BIT_VAUDIO_SEL            BIT(0)
  66
  67 /*
  68  * Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic,
  69  * and not limited to audio regulator. Let's use the Motorola kernel
  70  * naming for now until we have a better understanding of the other
  71  * enable register bits. No idea why BIT(3) is not defined.
  72  */
  73 #define CPCAP_BIT_AUDIO_LOW_PWR         BIT(6)
  74 #define CPCAP_BIT_AUD_LOWPWR_SPEED      BIT(5)
  75 #define CPCAP_BIT_VAUDIOPRISTBY         BIT(4)
  76 #define CPCAP_BIT_VAUDIO_MODE1          BIT(2)
  77 #define CPCAP_BIT_VAUDIO_MODE0          BIT(1)
  78 #define CPCAP_BIT_V_AUDIO_EN            BIT(0)
  79
  80 #define CPCAP_BIT_AUDIO_NORMAL_MODE     0x00
  81
  82 /*
  83  * Off mode configuration bit. Used currently only by SW5 on omap4. There's
  84  * the following comment in Motorola Linux kernel tree for it:
  85  *
  86  * When set in the regulator mode, the regulator assignment will be changed
  87  * to secondary when the regulator is disabled. The mode will be set back to
  88  * primary when the regulator is turned on.
  89  */
  90 #define CPCAP_REG_OFF_MODE_SEC          BIT(15)
  91
  92 /**
  93  * SoC specific configuraion for CPCAP regulator. There are at least three
  94  * different SoCs each with their own parameters: omap3, omap4 and tegra2.
  95  *
  96  * The assign_reg and assign_mask seem to allow toggling between primary
  97  * and secondary mode that at least omap4 uses for off mode.
  98  */
  99 struct cpcap_regulator {
 100         struct regulator_desc rdesc;
 101         const u16 assign_reg;
 102         const u16 assign_mask;
 103         const u16 vsel_shift;
 104 };
 105
 106 #define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl,   \
 107                 mode_mask, volt_mask, volt_shft,                        \
 108                 mode_val, off_val, volt_trans_time) {                   \
 109         .rdesc = {                                                      \
 110                 .name = #_ID,                                           \
 111                 .of_match = of_match_ptr(#_ID),                         \
 112                 .ops = &cpcap_regulator_ops,                            \
 113                 .regulators_node = of_match_ptr("regulators"),          \
 114                 .type = REGULATOR_VOLTAGE,                              \
 115                 .id = CPCAP_##_ID,                                      \
 116                 .owner = THIS_MODULE,                                   \
 117                 .n_voltages = ARRAY_SIZE(val_tbl),                      \
 118                 .volt_table = (val_tbl),                                \
 119                 .vsel_reg = (reg),                                      \
 120                 .vsel_mask = (volt_mask),                               \
 121                 .enable_reg = (reg),                                    \
 122                 .enable_mask = (mode_mask),                             \
 123                 .enable_val = (mode_val),                               \
 124                 .disable_val = (off_val),                               \
 125                 .ramp_delay = (volt_trans_time),                        \
 126                 .of_map_mode = cpcap_map_mode,                          \
 127         },                                                              \
 128         .assign_reg = (assignment_reg),                                 \
 129         .assign_mask = (assignment_mask),                               \
 130         .vsel_shift = (volt_shft),                                      \
 131 }
 132
 133 struct cpcap_ddata {
 134         struct regmap *reg;
 135         struct device *dev;
 136         const struct cpcap_regulator *soc;
 137 };
 138
 139 enum cpcap_regulator_id {
 140         CPCAP_SW1,
 141         CPCAP_SW2,
 142         CPCAP_SW3,
 143         CPCAP_SW4,
 144         CPCAP_SW5,
 145         CPCAP_SW6,
 146         CPCAP_VCAM,
 147         CPCAP_VCSI,
 148         CPCAP_VDAC,
 149         CPCAP_VDIG,
 150         CPCAP_VFUSE,
 151         CPCAP_VHVIO,
 152         CPCAP_VSDIO,
 153         CPCAP_VPLL,
 154         CPCAP_VRF1,
 155         CPCAP_VRF2,
 156         CPCAP_VRFREF,
 157         CPCAP_VWLAN1,
 158         CPCAP_VWLAN2,
 159         CPCAP_VSIM,
 160         CPCAP_VSIMCARD,
 161         CPCAP_VVIB,
 162         CPCAP_VUSB,
 163         CPCAP_VAUDIO,
 164         CPCAP_NR_REGULATORS,
 165 };
 166
 167 /*
 168  * We need to also configure regulator idle mode for SoC off mode if
 169  * CPCAP_REG_OFF_MODE_SEC is set.
 170  */
 171 static int cpcap_regulator_enable(struct regulator_dev *rdev)
 172 {
 173         struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
 174         int error, ignore;
 175
 176         error = regulator_enable_regmap(rdev);
 177         if (error)
 178                 return error;
 179
 180         if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
 181                 error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
 182                                            regulator->assign_mask,
 183                                            regulator->assign_mask);
 184                 if (error)
 185                         ignore = regulator_disable_regmap(rdev);
 186         }
 187
 188         return error;
 189 }
 190
 191 /*
 192  * We need to also configure regulator idle mode for SoC off mode if
 193  * CPCAP_REG_OFF_MODE_SEC is set.
 194  */
 195 static int cpcap_regulator_disable(struct regulator_dev *rdev)
 196 {
 197         struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
 198         int error, ignore;
 199
 200         if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
 201                 error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
 202                                            regulator->assign_mask, 0);
 203                 if (error)
 204                         return error;
 205         }
 206
 207         error = regulator_disable_regmap(rdev);
 208         if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
 209                 ignore = regmap_update_bits(rdev->regmap, regulator->assign_reg,
 210                                             regulator->assign_mask,
 211                                             regulator->assign_mask);
 212         }
 213
 214         return error;
 215 }
 216
 217 static unsigned int cpcap_map_mode(unsigned int mode)
 218 {
 219         switch (mode) {
 220         case CPCAP_BIT_AUDIO_NORMAL_MODE:
 221                 return REGULATOR_MODE_NORMAL;
 222         case CPCAP_BIT_AUDIO_LOW_PWR:
 223                 return REGULATOR_MODE_STANDBY;
 224         default:
 225                 return REGULATOR_MODE_INVALID;
 226         }
 227 }
 228
 229 static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev)
 230 {
 231         int value;
 232
 233         regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);
 234
 235         if (value & CPCAP_BIT_AUDIO_LOW_PWR)
 236                 return REGULATOR_MODE_STANDBY;
 237
 238         return REGULATOR_MODE_NORMAL;
 239 }
 240
 241 static int cpcap_regulator_set_mode(struct regulator_dev *rdev,
 242                                     unsigned int mode)
 243 {
 244         int value;
 245
 246         switch (mode) {
 247         case REGULATOR_MODE_NORMAL:
 248                 value = CPCAP_BIT_AUDIO_NORMAL_MODE;
 249                 break;
 250         case REGULATOR_MODE_STANDBY:
 251                 value = CPCAP_BIT_AUDIO_LOW_PWR;
 252                 break;
 253         default:
 254                 return -EINVAL;
 255         }
 256
 257         return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
 258                                   CPCAP_BIT_AUDIO_LOW_PWR, value);
 259 }
 260
 261 static struct regulator_ops cpcap_regulator_ops = {
 262         .enable = cpcap_regulator_enable,
 263         .disable = cpcap_regulator_disable,
 264         .is_enabled = regulator_is_enabled_regmap,
 265         .list_voltage = regulator_list_voltage_table,
 266         .map_voltage = regulator_map_voltage_iterate,
 267         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 268         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 269         .get_mode = cpcap_regulator_get_mode,
 270         .set_mode = cpcap_regulator_set_mode,
 271 };
 272
 273 static const unsigned int unknown_val_tbl[] = { 0, };
 274 static const unsigned int sw5_val_tbl[] = { 0, 5050000, };
 275 static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000,
 276                                              2900000, };
 277 static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, };
 278 static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000,
 279                                              2500000,};
 280 static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000,
 281                                              1875000, };
 282 static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000,
 283                                               1800000, 1900000, 2000000,
 284                                               2100000, 2200000, 2300000,
 285                                               2400000, 2500000, 2600000,
 286                                               2700000, 3150000, };
 287 static const unsigned int vhvio_val_tbl[] = { 2775000, };
 288 static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000,
 289                                               2600000, 2700000, 2800000,
 290                                               2900000, 3000000, };
 291 static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000,
 292                                              1800000, };
 293 /* Quirk: 2775000 is before 2500000 for vrf1 regulator */
 294 static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, };
 295 static const unsigned int vrf2_val_tbl[] = { 0, 2775000, };
 296 static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, };
 297 static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, };
 298 static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000,
 299                                                3300000, };
 300 static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, };
 301 static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, };
 302 static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000,
 303                                              3000000, };
 304 static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
 305 static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };
 306
 307 /**
 308  * SoC specific configuration for omap4. The data below is comes from Motorola
 309  * Linux kernel tree. It's basically the values of cpcap_regltr_data,
 310  * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
 311  * CPCAP_REG macro above.
 312  *
 313  * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
 314  * VSIMCARD have a shared resource assignment bit.
 315  */
 316 static struct cpcap_regulator omap4_regulators[] = {
 317         CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
 318                   CPCAP_BIT_SW1_SEL, unknown_val_tbl,
 319                   0, 0, 0, 0, 0, 0),
 320         CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
 321                   CPCAP_BIT_SW2_SEL, unknown_val_tbl,
 322                   0, 0, 0, 0, 0, 0),
 323         CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
 324                   CPCAP_BIT_SW3_SEL, unknown_val_tbl,
 325                   0, 0, 0, 0, 0, 0),
 326         CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
 327                   CPCAP_BIT_SW4_SEL, unknown_val_tbl,
 328                   0, 0, 0, 0, 0, 0),
 329         CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
 330                   CPCAP_BIT_SW5_SEL, sw5_val_tbl,
 331                   0x28, 0, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
 332         CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
 333                   CPCAP_BIT_SW6_SEL, unknown_val_tbl,
 334                   0, 0, 0, 0, 0, 0),
 335         CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
 336                   CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
 337                   0x87, 0x30, 4, 0x3, 0, 420),
 338         CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
 339                   CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
 340                   0x47, 0x10, 4, 0x43, 0x41, 350),
 341         CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
 342                   CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
 343                   0x87, 0x30, 4, 0x3, 0, 420),
 344         CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
 345                   CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
 346                   0x87, 0x30, 4, 0x82, 0, 420),
 347         CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
 348                   CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
 349                   0x80, 0xf, 0, 0x80, 0, 420),
 350         CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
 351                   CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
 352                   0x17, 0, 0, 0, 0x12, 0),
 353         CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
 354                   CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
 355                   0x87, 0x38, 3, 0x82, 0, 420),
 356         CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
 357                   CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
 358                   0x43, 0x18, 3, 0x2, 0, 420),
 359         CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
 360                   CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
 361                   0xac, 0x2, 1, 0x4, 0, 10),
 362         CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
 363                   CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
 364                   0x23, 0x8, 3, 0, 0, 10),
 365         CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
 366                   CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
 367                   0x23, 0x8, 3, 0, 0, 420),
 368         CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
 369                   CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
 370                   0x47, 0x10, 4, 0, 0, 420),
 371         CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
 372                   CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
 373                   0x20c, 0xc0, 6, 0x20c, 0, 420),
 374         CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
 375                   0xffff, vsim_val_tbl,
 376                   0x23, 0x8, 3, 0x3, 0, 420),
 377         CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
 378                   0xffff, vsimcard_val_tbl,
 379                   0x1e80, 0x8, 3, 0x1e00, 0, 420),
 380         CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
 381                   CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
 382                   0x1, 0xc, 2, 0x1, 0, 500),
 383         CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
 384                   CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
 385                   0x11c, 0x40, 6, 0xc, 0, 0),
 386         CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
 387                   CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
 388                   0x16, 0x1, 0, 0x4, 0, 0),
 389         { /* sentinel */ },
 390 };
 391
 392 static const struct of_device_id cpcap_regulator_id_table[] = {
 393         {
 394                 .compatible = "motorola,cpcap-regulator",
 395         },
 396         {
 397                 .compatible = "motorola,mapphone-cpcap-regulator",
 398                 .data = omap4_regulators,
 399         },
 400         {},
 401 };
 402 MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table);
 403
 404 static int cpcap_regulator_probe(struct platform_device *pdev)
 405 {
 406         struct cpcap_ddata *ddata;
 407         const struct of_device_id *match;
 408         struct regulator_config config;
 409         struct regulator_init_data init_data;
 410         int i;
 411
 412         match = of_match_device(of_match_ptr(cpcap_regulator_id_table),
 413                                 &pdev->dev);
 414         if (!match)
 415                 return -EINVAL;
 416
 417         if (!match->data) {
 418                 dev_err(&pdev->dev, "no configuration data found\n");
 419
 420                 return -ENODEV;
 421         }
 422
 423         ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
 424         if (!ddata)
 425                 return -ENOMEM;
 426
 427         ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
 428         if (!ddata->reg)
 429                 return -ENODEV;
 430
 431         ddata->dev = &pdev->dev;
 432         ddata->soc = match->data;
 433         platform_set_drvdata(pdev, ddata);
 434
 435         memset(&config, 0, sizeof(config));
 436         memset(&init_data, 0, sizeof(init_data));
 437         config.dev = &pdev->dev;
 438         config.regmap = ddata->reg;
 439         config.init_data = &init_data;
 440
 441         for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
 442                 const struct cpcap_regulator *regulator = &ddata->soc[i];
 443                 struct regulator_dev *rdev;
 444
 445                 if (!regulator->rdesc.name)
 446                         break;
 447
 448                 if (regulator->rdesc.volt_table == unknown_val_tbl)
 449                         continue;
 450
 451                 config.driver_data = (void *)regulator;
 452                 rdev = devm_regulator_register(&pdev->dev,
 453                                                &regulator->rdesc,
 454                                                &config);
 455                 if (IS_ERR(rdev)) {
 456                         dev_err(&pdev->dev, "failed to register regulator %s\n",
 457                                 regulator->rdesc.name);
 458
 459                         return PTR_ERR(rdev);
 460                 }
 461         }
 462
 463         return 0;
 464 }
 465
 466 static struct platform_driver cpcap_regulator_driver = {
 467         .probe          = cpcap_regulator_probe,
 468         .driver         = {
 469                 .name   = "cpcap-regulator",
 470                 .of_match_table = of_match_ptr(cpcap_regulator_id_table),
 471         },
 472 };
 473
 474 module_platform_driver(cpcap_regulator_driver);
 475
 476 MODULE_ALIAS("platform:cpcap-regulator");
 477 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
 478 MODULE_DESCRIPTION("CPCAP regulator driver");
 479 MODULE_LICENSE("GPL v2");