drivers/regulator/axp20x-regulator.c

   1 /*
   2  * AXP20x regulators driver.
   3  *
   4  * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General
   7  * Public License. See the file "COPYING" in the main directory of this
   8  * archive for more details.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/mfd/axp20x.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/regulator/driver.h>
  27 #include <linux/regulator/machine.h>
  28 #include <linux/regulator/of_regulator.h>
  29
  30 #define AXP20X_GPIO0_FUNC_MASK          GENMASK(3, 0)
  31 #define AXP20X_GPIO1_FUNC_MASK          GENMASK(3, 0)
  32
  33 #define AXP20X_IO_ENABLED               0x03
  34 #define AXP20X_IO_DISABLED              0x07
  35
  36 #define AXP20X_WORKMODE_DCDC2_MASK      BIT_MASK(2)
  37 #define AXP20X_WORKMODE_DCDC3_MASK      BIT_MASK(1)
  38
  39 #define AXP20X_FREQ_DCDC_MASK           GENMASK(3, 0)
  40
  41 #define AXP20X_VBUS_IPSOUT_MGMT_MASK    BIT_MASK(2)
  42
  43 #define AXP20X_DCDC2_V_OUT_MASK         GENMASK(5, 0)
  44 #define AXP20X_DCDC3_V_OUT_MASK         GENMASK(7, 0)
  45 #define AXP20X_LDO2_V_OUT_MASK          GENMASK(7, 4)
  46 #define AXP20X_LDO3_V_OUT_MASK          GENMASK(6, 0)
  47 #define AXP20X_LDO4_V_OUT_MASK          GENMASK(3, 0)
  48 #define AXP20X_LDO5_V_OUT_MASK          GENMASK(7, 4)
  49
  50 #define AXP20X_PWR_OUT_EXTEN_MASK       BIT_MASK(0)
  51 #define AXP20X_PWR_OUT_DCDC3_MASK       BIT_MASK(1)
  52 #define AXP20X_PWR_OUT_LDO2_MASK        BIT_MASK(2)
  53 #define AXP20X_PWR_OUT_LDO4_MASK        BIT_MASK(3)
  54 #define AXP20X_PWR_OUT_DCDC2_MASK       BIT_MASK(4)
  55 #define AXP20X_PWR_OUT_LDO3_MASK        BIT_MASK(6)
  56
  57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK        BIT_MASK(0)
  58 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
  59         ((x) << 0)
  60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK         BIT_MASK(1)
  61 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
  62         ((x) << 1)
  63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK          BIT_MASK(2)
  64 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN               BIT(2)
  65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK           BIT_MASK(3)
  66 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN                BIT(3)
  67
  68 #define AXP20X_LDO4_V_OUT_1250mV_START  0x0
  69 #define AXP20X_LDO4_V_OUT_1250mV_STEPS  0
  70 #define AXP20X_LDO4_V_OUT_1250mV_END    \
  71         (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
  72 #define AXP20X_LDO4_V_OUT_1300mV_START  0x1
  73 #define AXP20X_LDO4_V_OUT_1300mV_STEPS  7
  74 #define AXP20X_LDO4_V_OUT_1300mV_END    \
  75         (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
  76 #define AXP20X_LDO4_V_OUT_2500mV_START  0x9
  77 #define AXP20X_LDO4_V_OUT_2500mV_STEPS  0
  78 #define AXP20X_LDO4_V_OUT_2500mV_END    \
  79         (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
  80 #define AXP20X_LDO4_V_OUT_2700mV_START  0xa
  81 #define AXP20X_LDO4_V_OUT_2700mV_STEPS  1
  82 #define AXP20X_LDO4_V_OUT_2700mV_END    \
  83         (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
  84 #define AXP20X_LDO4_V_OUT_3000mV_START  0xc
  85 #define AXP20X_LDO4_V_OUT_3000mV_STEPS  3
  86 #define AXP20X_LDO4_V_OUT_3000mV_END    \
  87         (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
  88 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES  16
  89
  90 #define AXP22X_IO_ENABLED               0x03
  91 #define AXP22X_IO_DISABLED              0x04
  92
  93 #define AXP22X_WORKMODE_DCDCX_MASK(x)   BIT_MASK(x)
  94
  95 #define AXP22X_MISC_N_VBUSEN_FUNC       BIT(4)
  96
  97 #define AXP22X_DCDC1_V_OUT_MASK         GENMASK(4, 0)
  98 #define AXP22X_DCDC2_V_OUT_MASK         GENMASK(5, 0)
  99 #define AXP22X_DCDC3_V_OUT_MASK         GENMASK(5, 0)
 100 #define AXP22X_DCDC4_V_OUT_MASK         GENMASK(5, 0)
 101 #define AXP22X_DCDC5_V_OUT_MASK         GENMASK(4, 0)
 102 #define AXP22X_DC5LDO_V_OUT_MASK        GENMASK(2, 0)
 103 #define AXP22X_ALDO1_V_OUT_MASK         GENMASK(4, 0)
 104 #define AXP22X_ALDO2_V_OUT_MASK         GENMASK(4, 0)
 105 #define AXP22X_ALDO3_V_OUT_MASK         GENMASK(4, 0)
 106 #define AXP22X_DLDO1_V_OUT_MASK         GENMASK(4, 0)
 107 #define AXP22X_DLDO2_V_OUT_MASK         GENMASK(4, 0)
 108 #define AXP22X_DLDO3_V_OUT_MASK         GENMASK(4, 0)
 109 #define AXP22X_DLDO4_V_OUT_MASK         GENMASK(4, 0)
 110 #define AXP22X_ELDO1_V_OUT_MASK         GENMASK(4, 0)
 111 #define AXP22X_ELDO2_V_OUT_MASK         GENMASK(4, 0)
 112 #define AXP22X_ELDO3_V_OUT_MASK         GENMASK(4, 0)
 113 #define AXP22X_LDO_IO0_V_OUT_MASK       GENMASK(4, 0)
 114 #define AXP22X_LDO_IO1_V_OUT_MASK       GENMASK(4, 0)
 115
 116 #define AXP22X_PWR_OUT_DC5LDO_MASK      BIT_MASK(0)
 117 #define AXP22X_PWR_OUT_DCDC1_MASK       BIT_MASK(1)
 118 #define AXP22X_PWR_OUT_DCDC2_MASK       BIT_MASK(2)
 119 #define AXP22X_PWR_OUT_DCDC3_MASK       BIT_MASK(3)
 120 #define AXP22X_PWR_OUT_DCDC4_MASK       BIT_MASK(4)
 121 #define AXP22X_PWR_OUT_DCDC5_MASK       BIT_MASK(5)
 122 #define AXP22X_PWR_OUT_ALDO1_MASK       BIT_MASK(6)
 123 #define AXP22X_PWR_OUT_ALDO2_MASK       BIT_MASK(7)
 124
 125 #define AXP22X_PWR_OUT_SW_MASK          BIT_MASK(6)
 126 #define AXP22X_PWR_OUT_DC1SW_MASK       BIT_MASK(7)
 127
 128 #define AXP22X_PWR_OUT_ELDO1_MASK       BIT_MASK(0)
 129 #define AXP22X_PWR_OUT_ELDO2_MASK       BIT_MASK(1)
 130 #define AXP22X_PWR_OUT_ELDO3_MASK       BIT_MASK(2)
 131 #define AXP22X_PWR_OUT_DLDO1_MASK       BIT_MASK(3)
 132 #define AXP22X_PWR_OUT_DLDO2_MASK       BIT_MASK(4)
 133 #define AXP22X_PWR_OUT_DLDO3_MASK       BIT_MASK(5)
 134 #define AXP22X_PWR_OUT_DLDO4_MASK       BIT_MASK(6)
 135 #define AXP22X_PWR_OUT_ALDO3_MASK       BIT_MASK(7)
 136
 137 #define AXP803_PWR_OUT_DCDC1_MASK       BIT_MASK(0)
 138 #define AXP803_PWR_OUT_DCDC2_MASK       BIT_MASK(1)
 139 #define AXP803_PWR_OUT_DCDC3_MASK       BIT_MASK(2)
 140 #define AXP803_PWR_OUT_DCDC4_MASK       BIT_MASK(3)
 141 #define AXP803_PWR_OUT_DCDC5_MASK       BIT_MASK(4)
 142 #define AXP803_PWR_OUT_DCDC6_MASK       BIT_MASK(5)
 143
 144 #define AXP803_PWR_OUT_FLDO1_MASK       BIT_MASK(2)
 145 #define AXP803_PWR_OUT_FLDO2_MASK       BIT_MASK(3)
 146
 147 #define AXP803_DCDC1_V_OUT_MASK         GENMASK(4, 0)
 148 #define AXP803_DCDC2_V_OUT_MASK         GENMASK(6, 0)
 149 #define AXP803_DCDC3_V_OUT_MASK         GENMASK(6, 0)
 150 #define AXP803_DCDC4_V_OUT_MASK         GENMASK(6, 0)
 151 #define AXP803_DCDC5_V_OUT_MASK         GENMASK(6, 0)
 152 #define AXP803_DCDC6_V_OUT_MASK         GENMASK(6, 0)
 153
 154 #define AXP803_FLDO1_V_OUT_MASK         GENMASK(3, 0)
 155 #define AXP803_FLDO2_V_OUT_MASK         GENMASK(3, 0)
 156
 157 #define AXP803_DCDC23_POLYPHASE_DUAL    BIT(6)
 158 #define AXP803_DCDC56_POLYPHASE_DUAL    BIT(5)
 159
 160 #define AXP803_DCDC234_500mV_START      0x00
 161 #define AXP803_DCDC234_500mV_STEPS      70
 162 #define AXP803_DCDC234_500mV_END        \
 163         (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
 164 #define AXP803_DCDC234_1220mV_START     0x47
 165 #define AXP803_DCDC234_1220mV_STEPS     4
 166 #define AXP803_DCDC234_1220mV_END       \
 167         (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
 168 #define AXP803_DCDC234_NUM_VOLTAGES     76
 169
 170 #define AXP803_DCDC5_800mV_START        0x00
 171 #define AXP803_DCDC5_800mV_STEPS        32
 172 #define AXP803_DCDC5_800mV_END          \
 173         (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
 174 #define AXP803_DCDC5_1140mV_START       0x21
 175 #define AXP803_DCDC5_1140mV_STEPS       35
 176 #define AXP803_DCDC5_1140mV_END         \
 177         (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
 178 #define AXP803_DCDC5_NUM_VOLTAGES       69
 179
 180 #define AXP803_DCDC6_600mV_START        0x00
 181 #define AXP803_DCDC6_600mV_STEPS        50
 182 #define AXP803_DCDC6_600mV_END          \
 183         (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
 184 #define AXP803_DCDC6_1120mV_START       0x33
 185 #define AXP803_DCDC6_1120mV_STEPS       20
 186 #define AXP803_DCDC6_1120mV_END         \
 187         (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
 188 #define AXP803_DCDC6_NUM_VOLTAGES       72
 189
 190 #define AXP803_DLDO2_700mV_START        0x00
 191 #define AXP803_DLDO2_700mV_STEPS        26
 192 #define AXP803_DLDO2_700mV_END          \
 193         (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
 194 #define AXP803_DLDO2_3400mV_START       0x1b
 195 #define AXP803_DLDO2_3400mV_STEPS       4
 196 #define AXP803_DLDO2_3400mV_END         \
 197         (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
 198 #define AXP803_DLDO2_NUM_VOLTAGES       32
 199
 200 #define AXP806_DCDCA_V_CTRL_MASK        GENMASK(6, 0)
 201 #define AXP806_DCDCB_V_CTRL_MASK        GENMASK(4, 0)
 202 #define AXP806_DCDCC_V_CTRL_MASK        GENMASK(6, 0)
 203 #define AXP806_DCDCD_V_CTRL_MASK        GENMASK(5, 0)
 204 #define AXP806_DCDCE_V_CTRL_MASK        GENMASK(4, 0)
 205 #define AXP806_ALDO1_V_CTRL_MASK        GENMASK(4, 0)
 206 #define AXP806_ALDO2_V_CTRL_MASK        GENMASK(4, 0)
 207 #define AXP806_ALDO3_V_CTRL_MASK        GENMASK(4, 0)
 208 #define AXP806_BLDO1_V_CTRL_MASK        GENMASK(3, 0)
 209 #define AXP806_BLDO2_V_CTRL_MASK        GENMASK(3, 0)
 210 #define AXP806_BLDO3_V_CTRL_MASK        GENMASK(3, 0)
 211 #define AXP806_BLDO4_V_CTRL_MASK        GENMASK(3, 0)
 212 #define AXP806_CLDO1_V_CTRL_MASK        GENMASK(4, 0)
 213 #define AXP806_CLDO2_V_CTRL_MASK        GENMASK(4, 0)
 214 #define AXP806_CLDO3_V_CTRL_MASK        GENMASK(4, 0)
 215
 216 #define AXP806_PWR_OUT_DCDCA_MASK       BIT_MASK(0)
 217 #define AXP806_PWR_OUT_DCDCB_MASK       BIT_MASK(1)
 218 #define AXP806_PWR_OUT_DCDCC_MASK       BIT_MASK(2)
 219 #define AXP806_PWR_OUT_DCDCD_MASK       BIT_MASK(3)
 220 #define AXP806_PWR_OUT_DCDCE_MASK       BIT_MASK(4)
 221 #define AXP806_PWR_OUT_ALDO1_MASK       BIT_MASK(5)
 222 #define AXP806_PWR_OUT_ALDO2_MASK       BIT_MASK(6)
 223 #define AXP806_PWR_OUT_ALDO3_MASK       BIT_MASK(7)
 224 #define AXP806_PWR_OUT_BLDO1_MASK       BIT_MASK(0)
 225 #define AXP806_PWR_OUT_BLDO2_MASK       BIT_MASK(1)
 226 #define AXP806_PWR_OUT_BLDO3_MASK       BIT_MASK(2)
 227 #define AXP806_PWR_OUT_BLDO4_MASK       BIT_MASK(3)
 228 #define AXP806_PWR_OUT_CLDO1_MASK       BIT_MASK(4)
 229 #define AXP806_PWR_OUT_CLDO2_MASK       BIT_MASK(5)
 230 #define AXP806_PWR_OUT_CLDO3_MASK       BIT_MASK(6)
 231 #define AXP806_PWR_OUT_SW_MASK          BIT_MASK(7)
 232
 233 #define AXP806_DCDCAB_POLYPHASE_DUAL    0x40
 234 #define AXP806_DCDCABC_POLYPHASE_TRI    0x80
 235 #define AXP806_DCDCABC_POLYPHASE_MASK   GENMASK(7, 6)
 236
 237 #define AXP806_DCDCDE_POLYPHASE_DUAL    BIT(5)
 238
 239 #define AXP806_DCDCA_600mV_START        0x00
 240 #define AXP806_DCDCA_600mV_STEPS        50
 241 #define AXP806_DCDCA_600mV_END          \
 242         (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
 243 #define AXP806_DCDCA_1120mV_START       0x33
 244 #define AXP806_DCDCA_1120mV_STEPS       20
 245 #define AXP806_DCDCA_1120mV_END         \
 246         (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
 247 #define AXP806_DCDCA_NUM_VOLTAGES       72
 248
 249 #define AXP806_DCDCD_600mV_START        0x00
 250 #define AXP806_DCDCD_600mV_STEPS        45
 251 #define AXP806_DCDCD_600mV_END          \
 252         (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
 253 #define AXP806_DCDCD_1600mV_START       0x2e
 254 #define AXP806_DCDCD_1600mV_STEPS       17
 255 #define AXP806_DCDCD_1600mV_END         \
 256         (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
 257 #define AXP806_DCDCD_NUM_VOLTAGES       64
 258
 259 #define AXP809_DCDC4_600mV_START        0x00
 260 #define AXP809_DCDC4_600mV_STEPS        47
 261 #define AXP809_DCDC4_600mV_END          \
 262         (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
 263 #define AXP809_DCDC4_1800mV_START       0x30
 264 #define AXP809_DCDC4_1800mV_STEPS       8
 265 #define AXP809_DCDC4_1800mV_END         \
 266         (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
 267 #define AXP809_DCDC4_NUM_VOLTAGES       57
 268
 269 #define AXP813_DCDC7_V_OUT_MASK         GENMASK(6, 0)
 270
 271 #define AXP813_PWR_OUT_DCDC7_MASK       BIT_MASK(6)
 272
 273 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,    \
 274                     _vmask, _ereg, _emask, _enable_val, _disable_val)           \
 275         [_family##_##_id] = {                                                   \
 276                 .name           = (_match),                                     \
 277                 .supply_name    = (_supply),                                    \
 278                 .of_match       = of_match_ptr(_match),                         \
 279                 .regulators_node = of_match_ptr("regulators"),                  \
 280                 .type           = REGULATOR_VOLTAGE,                            \
 281                 .id             = _family##_##_id,                              \
 282                 .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
 283                 .owner          = THIS_MODULE,                                  \
 284                 .min_uV         = (_min) * 1000,                                \
 285                 .uV_step        = (_step) * 1000,                               \
 286                 .vsel_reg       = (_vreg),                                      \
 287                 .vsel_mask      = (_vmask),                                     \
 288                 .enable_reg     = (_ereg),                                      \
 289                 .enable_mask    = (_emask),                                     \
 290                 .enable_val     = (_enable_val),                                \
 291                 .disable_val    = (_disable_val),                               \
 292                 .ops            = &axp20x_ops,                                  \
 293         }
 294
 295 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,       \
 296                  _vmask, _ereg, _emask)                                         \
 297         [_family##_##_id] = {                                                   \
 298                 .name           = (_match),                                     \
 299                 .supply_name    = (_supply),                                    \
 300                 .of_match       = of_match_ptr(_match),                         \
 301                 .regulators_node = of_match_ptr("regulators"),                  \
 302                 .type           = REGULATOR_VOLTAGE,                            \
 303                 .id             = _family##_##_id,                              \
 304                 .n_voltages     = (((_max) - (_min)) / (_step) + 1),            \
 305                 .owner          = THIS_MODULE,                                  \
 306                 .min_uV         = (_min) * 1000,                                \
 307                 .uV_step        = (_step) * 1000,                               \
 308                 .vsel_reg       = (_vreg),                                      \
 309                 .vsel_mask      = (_vmask),                                     \
 310                 .enable_reg     = (_ereg),                                      \
 311                 .enable_mask    = (_emask),                                     \
 312                 .ops            = &axp20x_ops,                                  \
 313         }
 314
 315 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask)               \
 316         [_family##_##_id] = {                                                   \
 317                 .name           = (_match),                                     \
 318                 .supply_name    = (_supply),                                    \
 319                 .of_match       = of_match_ptr(_match),                         \
 320                 .regulators_node = of_match_ptr("regulators"),                  \
 321                 .type           = REGULATOR_VOLTAGE,                            \
 322                 .id             = _family##_##_id,                              \
 323                 .owner          = THIS_MODULE,                                  \
 324                 .enable_reg     = (_ereg),                                      \
 325                 .enable_mask    = (_emask),                                     \
 326                 .ops            = &axp20x_ops_sw,                               \
 327         }
 328
 329 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)                    \
 330         [_family##_##_id] = {                                                   \
 331                 .name           = (_match),                                     \
 332                 .supply_name    = (_supply),                                    \
 333                 .of_match       = of_match_ptr(_match),                         \
 334                 .regulators_node = of_match_ptr("regulators"),                  \
 335                 .type           = REGULATOR_VOLTAGE,                            \
 336                 .id             = _family##_##_id,                              \
 337                 .n_voltages     = 1,                                            \
 338                 .owner          = THIS_MODULE,                                  \
 339                 .min_uV         = (_volt) * 1000,                               \
 340                 .ops            = &axp20x_ops_fixed                             \
 341         }
 342
 343 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages,    \
 344                         _vreg, _vmask, _ereg, _emask)                           \
 345         [_family##_##_id] = {                                                   \
 346                 .name           = (_match),                                     \
 347                 .supply_name    = (_supply),                                    \
 348                 .of_match       = of_match_ptr(_match),                         \
 349                 .regulators_node = of_match_ptr("regulators"),                  \
 350                 .type           = REGULATOR_VOLTAGE,                            \
 351                 .id             = _family##_##_id,                              \
 352                 .n_voltages     = (_n_voltages),                                \
 353                 .owner          = THIS_MODULE,                                  \
 354                 .vsel_reg       = (_vreg),                                      \
 355                 .vsel_mask      = (_vmask),                                     \
 356                 .enable_reg     = (_ereg),                                      \
 357                 .enable_mask    = (_emask),                                     \
 358                 .linear_ranges  = (_ranges),                                    \
 359                 .n_linear_ranges = ARRAY_SIZE(_ranges),                         \
 360                 .ops            = &axp20x_ops_range,                            \
 361         }
 362
 363 static const int axp209_dcdc2_ldo3_slew_rates[] = {
 364         1600,
 365          800,
 366 };
 367
 368 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
 369 {
 370         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 371         int id = rdev_get_id(rdev);
 372         u8 reg, mask, enable, cfg = 0xff;
 373         const int *slew_rates;
 374         int rate_count = 0;
 375
 376         switch (axp20x->variant) {
 377         case AXP209_ID:
 378                 if (id == AXP20X_DCDC2) {
 379                         slew_rates = axp209_dcdc2_ldo3_slew_rates;
 380                         rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 381                         reg = AXP20X_DCDC2_LDO3_V_RAMP;
 382                         mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
 383                                AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
 384                         enable = (ramp > 0) ?
 385                                  AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN :
 386                                  !AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN;
 387                         break;
 388                 }
 389
 390                 if (id == AXP20X_LDO3) {
 391                         slew_rates = axp209_dcdc2_ldo3_slew_rates;
 392                         rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 393                         reg = AXP20X_DCDC2_LDO3_V_RAMP;
 394                         mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
 395                                AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
 396                         enable = (ramp > 0) ?
 397                                  AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN :
 398                                  !AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN;
 399                         break;
 400                 }
 401
 402                 if (rate_count > 0)
 403                         break;
 404
 405                 /* fall through */
 406         default:
 407                 /* Not supported for this regulator */
 408                 return -ENOTSUPP;
 409         }
 410
 411         if (ramp == 0) {
 412                 cfg = enable;
 413         } else {
 414                 int i;
 415
 416                 for (i = 0; i < rate_count; i++) {
 417                         if (ramp > slew_rates[i])
 418                                 break;
 419
 420                         if (id == AXP20X_DCDC2)
 421                                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
 422                         else
 423                                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
 424                 }
 425
 426                 if (cfg == 0xff) {
 427                         dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
 428                         return -EINVAL;
 429                 }
 430
 431                 cfg |= enable;
 432         }
 433
 434         return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
 435 }
 436
 437 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
 438 {
 439         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 440         int id = rdev_get_id(rdev);
 441
 442         switch (axp20x->variant) {
 443         case AXP209_ID:
 444                 if ((id == AXP20X_LDO3) &&
 445                     rdev->constraints && rdev->constraints->soft_start) {
 446                         int v_out;
 447                         int ret;
 448
 449                         /*
 450                          * On some boards, the LDO3 can be overloaded when
 451                          * turning on, causing the entire PMIC to shutdown
 452                          * without warning. Turning it on at the minimal voltage
 453                          * and then setting the voltage to the requested value
 454                          * works reliably.
 455                          */
 456                         if (regulator_is_enabled_regmap(rdev))
 457                                 break;
 458
 459                         v_out = regulator_get_voltage_sel_regmap(rdev);
 460                         if (v_out < 0)
 461                                 return v_out;
 462
 463                         if (v_out == 0)
 464                                 break;
 465
 466                         ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
 467                         /*
 468                          * A small pause is needed between
 469                          * setting the voltage and enabling the LDO to give the
 470                          * internal state machine time to process the request.
 471                          */
 472                         usleep_range(1000, 5000);
 473                         ret |= regulator_enable_regmap(rdev);
 474                         ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
 475
 476                         return ret;
 477                 }
 478                 break;
 479         default:
 480                 /* No quirks */
 481                 break;
 482         }
 483
 484         return regulator_enable_regmap(rdev);
 485 };
 486
 487 static const struct regulator_ops axp20x_ops_fixed = {
 488         .list_voltage           = regulator_list_voltage_linear,
 489 };
 490
 491 static const struct regulator_ops axp20x_ops_range = {
 492         .set_voltage_sel        = regulator_set_voltage_sel_regmap,
 493         .get_voltage_sel        = regulator_get_voltage_sel_regmap,
 494         .list_voltage           = regulator_list_voltage_linear_range,
 495         .enable                 = regulator_enable_regmap,
 496         .disable                = regulator_disable_regmap,
 497         .is_enabled             = regulator_is_enabled_regmap,
 498 };
 499
 500 static const struct regulator_ops axp20x_ops = {
 501         .set_voltage_sel        = regulator_set_voltage_sel_regmap,
 502         .get_voltage_sel        = regulator_get_voltage_sel_regmap,
 503         .list_voltage           = regulator_list_voltage_linear,
 504         .enable                 = axp20x_regulator_enable_regmap,
 505         .disable                = regulator_disable_regmap,
 506         .is_enabled             = regulator_is_enabled_regmap,
 507         .set_ramp_delay         = axp20x_set_ramp_delay,
 508 };
 509
 510 static const struct regulator_ops axp20x_ops_sw = {
 511         .enable                 = regulator_enable_regmap,
 512         .disable                = regulator_disable_regmap,
 513         .is_enabled             = regulator_is_enabled_regmap,
 514 };
 515
 516 static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
 517         REGULATOR_LINEAR_RANGE(1250000,
 518                                AXP20X_LDO4_V_OUT_1250mV_START,
 519                                AXP20X_LDO4_V_OUT_1250mV_END,
 520                                0),
 521         REGULATOR_LINEAR_RANGE(1300000,
 522                                AXP20X_LDO4_V_OUT_1300mV_START,
 523                                AXP20X_LDO4_V_OUT_1300mV_END,
 524                                100000),
 525         REGULATOR_LINEAR_RANGE(2500000,
 526                                AXP20X_LDO4_V_OUT_2500mV_START,
 527                                AXP20X_LDO4_V_OUT_2500mV_END,
 528                                0),
 529         REGULATOR_LINEAR_RANGE(2700000,
 530                                AXP20X_LDO4_V_OUT_2700mV_START,
 531                                AXP20X_LDO4_V_OUT_2700mV_END,
 532                                100000),
 533         REGULATOR_LINEAR_RANGE(3000000,
 534                                AXP20X_LDO4_V_OUT_3000mV_START,
 535                                AXP20X_LDO4_V_OUT_3000mV_END,
 536                                100000),
 537 };
 538
 539 static const struct regulator_desc axp20x_regulators[] = {
 540         AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
 541                  AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
 542                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
 543         AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
 544                  AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
 545                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
 546         AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
 547         AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
 548                  AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
 549                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
 550         AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
 551                  AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
 552                  AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
 553         AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
 554                         axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
 555                         AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
 556                         AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
 557         AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
 558                     AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
 559                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 560                     AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
 561 };
 562
 563 static const struct regulator_desc axp22x_regulators[] = {
 564         AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 565                  AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 566                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 567         AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 568                  AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 569                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 570         AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 571                  AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 572                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 573         AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
 574                  AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
 575                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 576         AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 577                  AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 578                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 579         /* secondary switchable output of DCDC1 */
 580         AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
 581                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 582         /* LDO regulator internally chained to DCDC5 */
 583         AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 584                  AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 585                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 586         AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 587                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 588                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 589         AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 590                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 591                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 592         AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 593                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 594                  AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
 595         AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 596                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 597                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 598         AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 599                  AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 600                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 601         AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 602                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 603                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 604         AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 605                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 606                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 607         AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 608                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 609                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 610         AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 611                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 612                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 613         AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 614                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 615                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 616         /* Note the datasheet only guarantees reliable operation up to
 617          * 3.3V, this needs to be enforced via dts provided constraints */
 618         AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 619                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 620                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 621                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 622         /* Note the datasheet only guarantees reliable operation up to
 623          * 3.3V, this needs to be enforced via dts provided constraints */
 624         AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 625                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 626                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 627                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 628         AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
 629 };
 630
 631 static const struct regulator_desc axp22x_drivevbus_regulator = {
 632         .name           = "drivevbus",
 633         .supply_name    = "drivevbus",
 634         .of_match       = of_match_ptr("drivevbus"),
 635         .regulators_node = of_match_ptr("regulators"),
 636         .type           = REGULATOR_VOLTAGE,
 637         .owner          = THIS_MODULE,
 638         .enable_reg     = AXP20X_VBUS_IPSOUT_MGMT,
 639         .enable_mask    = AXP20X_VBUS_IPSOUT_MGMT_MASK,
 640         .ops            = &axp20x_ops_sw,
 641 };
 642
 643 /* DCDC ranges shared with AXP813 */
 644 static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
 645         REGULATOR_LINEAR_RANGE(500000,
 646                                AXP803_DCDC234_500mV_START,
 647                                AXP803_DCDC234_500mV_END,
 648                                10000),
 649         REGULATOR_LINEAR_RANGE(1220000,
 650                                AXP803_DCDC234_1220mV_START,
 651                                AXP803_DCDC234_1220mV_END,
 652                                20000),
 653 };
 654
 655 static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
 656         REGULATOR_LINEAR_RANGE(800000,
 657                                AXP803_DCDC5_800mV_START,
 658                                AXP803_DCDC5_800mV_END,
 659                                10000),
 660         REGULATOR_LINEAR_RANGE(1140000,
 661                                AXP803_DCDC5_1140mV_START,
 662                                AXP803_DCDC5_1140mV_END,
 663                                20000),
 664 };
 665
 666 static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
 667         REGULATOR_LINEAR_RANGE(600000,
 668                                AXP803_DCDC6_600mV_START,
 669                                AXP803_DCDC6_600mV_END,
 670                                10000),
 671         REGULATOR_LINEAR_RANGE(1120000,
 672                                AXP803_DCDC6_1120mV_START,
 673                                AXP803_DCDC6_1120mV_END,
 674                                20000),
 675 };
 676
 677 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
 678 static const struct regulator_linear_range axp803_dldo2_ranges[] = {
 679         REGULATOR_LINEAR_RANGE(700000,
 680                                AXP803_DLDO2_700mV_START,
 681                                AXP803_DLDO2_700mV_END,
 682                                100000),
 683         REGULATOR_LINEAR_RANGE(3400000,
 684                                AXP803_DLDO2_3400mV_START,
 685                                AXP803_DLDO2_3400mV_END,
 686                                200000),
 687 };
 688
 689 static const struct regulator_desc axp803_regulators[] = {
 690         AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 691                  AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 692                  AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 693         AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
 694                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 695                         AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 696                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 697         AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
 698                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 699                         AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 700                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 701         AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
 702                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 703                         AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 704                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 705         AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
 706                         axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 707                         AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 708                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 709         AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
 710                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 711                         AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 712                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 713         /* secondary switchable output of DCDC1 */
 714         AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
 715                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 716         AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 717                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 718                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 719         AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 720                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 721                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 722         AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 723                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 724                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 725         AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 726                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 727                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 728         AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
 729                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 730                         AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 731                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 732         AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 733                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 734                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 735         AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 736                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 737                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 738         AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 739                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 740                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 741         AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 742                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 743                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 744         AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 745                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 746                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 747         AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 748                  AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 749                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 750         AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 751                  AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 752                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 753         AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
 754                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 755                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 756                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 757         AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
 758                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 759                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 760                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 761         AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
 762 };
 763
 764 static const struct regulator_linear_range axp806_dcdca_ranges[] = {
 765         REGULATOR_LINEAR_RANGE(600000,
 766                                AXP806_DCDCA_600mV_START,
 767                                AXP806_DCDCA_600mV_END,
 768                                10000),
 769         REGULATOR_LINEAR_RANGE(1120000,
 770                                AXP806_DCDCA_1120mV_START,
 771                                AXP806_DCDCA_1120mV_END,
 772                                20000),
 773 };
 774
 775 static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
 776         REGULATOR_LINEAR_RANGE(600000,
 777                                AXP806_DCDCD_600mV_START,
 778                                AXP806_DCDCD_600mV_END,
 779                                20000),
 780         REGULATOR_LINEAR_RANGE(1600000,
 781                                AXP806_DCDCD_1600mV_START,
 782                                AXP806_DCDCD_1600mV_END,
 783                                100000),
 784 };
 785
 786 static const struct regulator_desc axp806_regulators[] = {
 787         AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
 788                         axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 789                         AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
 790                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
 791         AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
 792                  AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
 793                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
 794         AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
 795                         axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 796                         AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
 797                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
 798         AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
 799                         axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
 800                         AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
 801                         AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
 802         AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
 803                  AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
 804                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
 805         AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 806                  AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
 807                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
 808         AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
 809                  AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
 810                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
 811         AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 812                  AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
 813                  AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
 814         AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
 815                  AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
 816                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
 817         AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
 818                  AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
 819                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
 820         AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
 821                  AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
 822                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
 823         AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
 824                  AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
 825                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
 826         AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
 827                  AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
 828                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
 829         AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
 830                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 831                         AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
 832                         AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
 833         AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
 834                  AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
 835                  AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
 836         AXP_DESC_SW(AXP806, SW, "sw", "swin",
 837                     AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
 838 };
 839
 840 static const struct regulator_linear_range axp809_dcdc4_ranges[] = {
 841         REGULATOR_LINEAR_RANGE(600000,
 842                                AXP809_DCDC4_600mV_START,
 843                                AXP809_DCDC4_600mV_END,
 844                                20000),
 845         REGULATOR_LINEAR_RANGE(1800000,
 846                                AXP809_DCDC4_1800mV_START,
 847                                AXP809_DCDC4_1800mV_END,
 848                                100000),
 849 };
 850
 851 static const struct regulator_desc axp809_regulators[] = {
 852         AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 853                  AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 854                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 855         AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 856                  AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 857                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 858         AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 859                  AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 860                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 861         AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
 862                         axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
 863                         AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
 864                         AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 865         AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 866                  AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 867                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 868         /* secondary switchable output of DCDC1 */
 869         AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
 870                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 871         /* LDO regulator internally chained to DCDC5 */
 872         AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 873                  AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 874                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 875         AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 876                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 877                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 878         AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 879                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 880                  AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 881         AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 882                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 883                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
 884         AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
 885                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 886                         AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 887                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 888         AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 889                  AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 890                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 891         AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 892                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 893                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 894         AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 895                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 896                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 897         AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 898                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 899                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 900         /*
 901          * Note the datasheet only guarantees reliable operation up to
 902          * 3.3V, this needs to be enforced via dts provided constraints
 903          */
 904         AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 905                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 906                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 907                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 908         /*
 909          * Note the datasheet only guarantees reliable operation up to
 910          * 3.3V, this needs to be enforced via dts provided constraints
 911          */
 912         AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 913                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 914                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 915                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 916         AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
 917         AXP_DESC_SW(AXP809, SW, "sw", "swin",
 918                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
 919 };
 920
 921 static const struct regulator_desc axp813_regulators[] = {
 922         AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 923                  AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 924                  AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 925         AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
 926                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 927                         AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 928                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 929         AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
 930                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 931                         AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 932                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 933         AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
 934                         axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 935                         AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 936                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 937         AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
 938                         axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 939                         AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 940                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 941         AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
 942                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 943                         AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 944                         AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 945         AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
 946                         axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 947                         AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
 948                         AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
 949         AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 950                  AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 951                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 952         AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 953                  AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 954                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 955         AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 956                  AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 957                  AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 958         AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 959                  AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 960                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 961         AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
 962                         axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 963                         AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 964                         AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 965         AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 966                  AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 967                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 968         AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 969                  AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 970                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 971         AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 972                  AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 973                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 974         AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 975                  AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 976                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 977         AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 978                  AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 979                  AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 980         /* to do / check ... */
 981         AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 982                  AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 983                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 984         AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 985                  AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 986                  AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 987         /*
 988          * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
 989          *
 990          * This means FLDO3 effectively switches supplies at runtime,
 991          * something the regulator subsystem does not support.
 992          */
 993         AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
 994         AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
 995                     AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 996                     AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 997                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 998         AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
 999                     AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1000                     AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1001                     AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1002         AXP_DESC_SW(AXP813, SW, "sw", "swin",
1003                     AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1004 };
1005
1006 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1007 {
1008         struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1009         unsigned int reg = AXP20X_DCDC_FREQ;
1010         u32 min, max, def, step;
1011
1012         switch (axp20x->variant) {
1013         case AXP202_ID:
1014         case AXP209_ID:
1015                 min = 750;
1016                 max = 1875;
1017                 def = 1500;
1018                 step = 75;
1019                 break;
1020         case AXP803_ID:
1021         case AXP813_ID:
1022                 /*
1023                  * AXP803/AXP813 DCDC work frequency setting has the same
1024                  * range and step as AXP22X, but at a different register.
1025                  * (See include/linux/mfd/axp20x.h)
1026                  */
1027                 reg = AXP803_DCDC_FREQ_CTRL;
1028                 /* Fall through - to the check below.*/
1029         case AXP806_ID:
1030                 /*
1031                  * AXP806 also have DCDC work frequency setting register at a
1032                  * different position.
1033                  */
1034                 if (axp20x->variant == AXP806_ID)
1035                         reg = AXP806_DCDC_FREQ_CTRL;
1036                 /* Fall through */
1037         case AXP221_ID:
1038         case AXP223_ID:
1039         case AXP809_ID:
1040                 min = 1800;
1041                 max = 4050;
1042                 def = 3000;
1043                 step = 150;
1044                 break;
1045         default:
1046                 dev_err(&pdev->dev,
1047                         "Setting DCDC frequency for unsupported AXP variant\n");
1048                 return -EINVAL;
1049         }
1050
1051         if (dcdcfreq == 0)
1052                 dcdcfreq = def;
1053
1054         if (dcdcfreq < min) {
1055                 dcdcfreq = min;
1056                 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1057                          min);
1058         }
1059
1060         if (dcdcfreq > max) {
1061                 dcdcfreq = max;
1062                 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1063                          max);
1064         }
1065
1066         dcdcfreq = (dcdcfreq - min) / step;
1067
1068         return regmap_update_bits(axp20x->regmap, reg,
1069                                   AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1070 }
1071
1072 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1073 {
1074         struct device_node *np, *regulators;
1075         int ret = 0;
1076         u32 dcdcfreq = 0;
1077
1078         np = of_node_get(pdev->dev.parent->of_node);
1079         if (!np)
1080                 return 0;
1081
1082         regulators = of_get_child_by_name(np, "regulators");
1083         if (!regulators) {
1084                 dev_warn(&pdev->dev, "regulators node not found\n");
1085         } else {
1086                 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1087                 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1088                 if (ret < 0) {
1089                         dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1090                 }
1091                 of_node_put(regulators);
1092         }
1093
1094         of_node_put(np);
1095         return ret;
1096 }
1097
1098 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1099 {
1100         struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1101         unsigned int reg = AXP20X_DCDC_MODE;
1102         unsigned int mask;
1103
1104         switch (axp20x->variant) {
1105         case AXP202_ID:
1106         case AXP209_ID:
1107                 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1108                         return -EINVAL;
1109
1110                 mask = AXP20X_WORKMODE_DCDC2_MASK;
1111                 if (id == AXP20X_DCDC3)
1112                         mask = AXP20X_WORKMODE_DCDC3_MASK;
1113
1114                 workmode <<= ffs(mask) - 1;
1115                 break;
1116
1117         case AXP806_ID:
1118                 /*
1119                  * AXP806 DCDC regulator IDs have the same range as AXP22X.
1120                  * (See include/linux/mfd/axp20x.h)
1121                  */
1122                 reg = AXP806_DCDC_MODE_CTRL2;
1123                  /* Fall through - to the check below. */
1124         case AXP221_ID:
1125         case AXP223_ID:
1126         case AXP809_ID:
1127                 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1128                         return -EINVAL;
1129
1130                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1131                 workmode <<= id - AXP22X_DCDC1;
1132                 break;
1133
1134         case AXP803_ID:
1135                 if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1136                         return -EINVAL;
1137
1138                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1139                 workmode <<= id - AXP803_DCDC1;
1140                 break;
1141
1142         case AXP813_ID:
1143                 if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1144                         return -EINVAL;
1145
1146                 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1147                 workmode <<= id - AXP813_DCDC1;
1148                 break;
1149
1150         default:
1151                 /* should not happen */
1152                 WARN_ON(1);
1153                 return -EINVAL;
1154         }
1155
1156         return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1157 }
1158
1159 /*
1160  * This function checks whether a regulator is part of a poly-phase
1161  * output setup based on the registers settings. Returns true if it is.
1162  */
1163 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1164 {
1165         u32 reg = 0;
1166
1167         /*
1168          * Currently in our supported AXP variants, only AXP803, AXP806,
1169          * and AXP813 have polyphase regulators.
1170          */
1171         switch (axp20x->variant) {
1172         case AXP803_ID:
1173         case AXP813_ID:
1174                 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
1175
1176                 switch (id) {
1177                 case AXP803_DCDC3:
1178                         return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1179                 case AXP803_DCDC6:
1180                         return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1181                 }
1182                 break;
1183
1184         case AXP806_ID:
1185                 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
1186
1187                 switch (id) {
1188                 case AXP806_DCDCB:
1189                         return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1190                                 AXP806_DCDCAB_POLYPHASE_DUAL) ||
1191                                 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1192                                 AXP806_DCDCABC_POLYPHASE_TRI));
1193                 case AXP806_DCDCC:
1194                         return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1195                                 AXP806_DCDCABC_POLYPHASE_TRI);
1196                 case AXP806_DCDCE:
1197                         return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1198                 }
1199                 break;
1200
1201         default:
1202                 return false;
1203         }
1204
1205         return false;
1206 }
1207
1208 static int axp20x_regulator_probe(struct platform_device *pdev)
1209 {
1210         struct regulator_dev *rdev;
1211         struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1212         const struct regulator_desc *regulators;
1213         struct regulator_config config = {
1214                 .dev = pdev->dev.parent,
1215                 .regmap = axp20x->regmap,
1216                 .driver_data = axp20x,
1217         };
1218         int ret, i, nregulators;
1219         u32 workmode;
1220         const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1221         const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1222         bool drivevbus = false;
1223
1224         switch (axp20x->variant) {
1225         case AXP202_ID:
1226         case AXP209_ID:
1227                 regulators = axp20x_regulators;
1228                 nregulators = AXP20X_REG_ID_MAX;
1229                 break;
1230         case AXP221_ID:
1231         case AXP223_ID:
1232                 regulators = axp22x_regulators;
1233                 nregulators = AXP22X_REG_ID_MAX;
1234                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1235                                                   "x-powers,drive-vbus-en");
1236                 break;
1237         case AXP803_ID:
1238                 regulators = axp803_regulators;
1239                 nregulators = AXP803_REG_ID_MAX;
1240                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1241                                                   "x-powers,drive-vbus-en");
1242                 break;
1243         case AXP806_ID:
1244                 regulators = axp806_regulators;
1245                 nregulators = AXP806_REG_ID_MAX;
1246                 break;
1247         case AXP809_ID:
1248                 regulators = axp809_regulators;
1249                 nregulators = AXP809_REG_ID_MAX;
1250                 break;
1251         case AXP813_ID:
1252                 regulators = axp813_regulators;
1253                 nregulators = AXP813_REG_ID_MAX;
1254                 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1255                                                   "x-powers,drive-vbus-en");
1256                 break;
1257         default:
1258                 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1259                         axp20x->variant);
1260                 return -EINVAL;
1261         }
1262
1263         /* This only sets the dcdc freq. Ignore any errors */
1264         axp20x_regulator_parse_dt(pdev);
1265
1266         for (i = 0; i < nregulators; i++) {
1267                 const struct regulator_desc *desc = &regulators[i];
1268                 struct regulator_desc *new_desc;
1269
1270                 /*
1271                  * If this regulator is a slave in a poly-phase setup,
1272                  * skip it, as its controls are bound to the master
1273                  * regulator and won't work.
1274                  */
1275                 if (axp20x_is_polyphase_slave(axp20x, i))
1276                         continue;
1277
1278                 /* Support for AXP813's FLDO3 is not implemented */
1279                 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1280                         continue;
1281
1282                 /*
1283                  * Regulators DC1SW and DC5LDO are connected internally,
1284                  * so we have to handle their supply names separately.
1285                  *
1286                  * We always register the regulators in proper sequence,
1287                  * so the supply names are correctly read. See the last
1288                  * part of this loop to see where we save the DT defined
1289                  * name.
1290                  */
1291                 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1292                     (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1293                     (regulators == axp809_regulators && i == AXP809_DC1SW)) {
1294                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1295                                                 GFP_KERNEL);
1296                         if (!new_desc)
1297                                 return -ENOMEM;
1298
1299                         *new_desc = regulators[i];
1300                         new_desc->supply_name = dcdc1_name;
1301                         desc = new_desc;
1302                 }
1303
1304                 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1305                     (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
1306                         new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1307                                                 GFP_KERNEL);
1308                         if (!new_desc)
1309                                 return -ENOMEM;
1310
1311                         *new_desc = regulators[i];
1312                         new_desc->supply_name = dcdc5_name;
1313                         desc = new_desc;
1314                 }
1315
1316                 rdev = devm_regulator_register(&pdev->dev, desc, &config);
1317                 if (IS_ERR(rdev)) {
1318                         dev_err(&pdev->dev, "Failed to register %s\n",
1319                                 regulators[i].name);
1320
1321                         return PTR_ERR(rdev);
1322                 }
1323
1324                 ret = of_property_read_u32(rdev->dev.of_node,
1325                                            "x-powers,dcdc-workmode",
1326                                            &workmode);
1327                 if (!ret) {
1328                         if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1329                                 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1330                                         rdev->desc->name);
1331                 }
1332
1333                 /*
1334                  * Save AXP22X DCDC1 / DCDC5 regulator names for later.
1335                  */
1336                 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1337                     (regulators == axp809_regulators && i == AXP809_DCDC1))
1338                         of_property_read_string(rdev->dev.of_node,
1339                                                 "regulator-name",
1340                                                 &dcdc1_name);
1341
1342                 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1343                     (regulators == axp809_regulators && i == AXP809_DCDC5))
1344                         of_property_read_string(rdev->dev.of_node,
1345                                                 "regulator-name",
1346                                                 &dcdc5_name);
1347         }
1348
1349         if (drivevbus) {
1350                 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1351                 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1352                                    AXP22X_MISC_N_VBUSEN_FUNC, 0);
1353                 rdev = devm_regulator_register(&pdev->dev,
1354                                                &axp22x_drivevbus_regulator,
1355                                                &config);
1356                 if (IS_ERR(rdev)) {
1357                         dev_err(&pdev->dev, "Failed to register drivevbus\n");
1358                         return PTR_ERR(rdev);
1359                 }
1360         }
1361
1362         return 0;
1363 }
1364
1365 static struct platform_driver axp20x_regulator_driver = {
1366         .probe  = axp20x_regulator_probe,
1367         .driver = {
1368                 .name           = "axp20x-regulator",
1369         },
1370 };
1371
1372 module_platform_driver(axp20x_regulator_driver);
1373
1374 MODULE_LICENSE("GPL v2");
1375 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1376 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1377 MODULE_ALIAS("platform:axp20x-regulator");