2 * Copyright (C) ST-Ericsson SA 2010
4 * License Terms: GNU General Public License v2
6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
10 * AB8500 peripheral regulators
12 * AB8500 supports the following regulators:
13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/abx500.h>
24 #include <linux/mfd/abx500/ab8500.h>
26 #include <linux/regulator/of_regulator.h>
27 #include <linux/regulator/driver.h>
28 #include <linux/regulator/machine.h>
29 #include <linux/regulator/ab8500.h>
30 #include <linux/slab.h>
33 * struct ab8500_shared_mode - is used when mode is shared between
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
38 struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
44 * struct ab8500_regulator_info - ab8500 regulator information
45 * @dev: device pointer
46 * @desc: regulator description
47 * @regulator_dev: regulator device
48 * @shared_mode: used when mode is shared between two regulators
49 * @load_lp_uA: maximum load in idle (low power) mode
50 * @update_bank: bank to control on/off
51 * @update_reg: register to control on/off
52 * @update_mask: mask to enable/disable and set mode of regulator
53 * @update_val: bits holding the regulator current mode
54 * @update_val_idle: bits to enable the regulator in idle (low power) mode
55 * @update_val_normal: bits to enable the regulator in normal (high power) mode
56 * @mode_bank: bank with location of mode register
57 * @mode_reg: mode register
58 * @mode_mask: mask for setting mode
59 * @mode_val_idle: mode setting for low power
60 * @mode_val_normal: mode setting for normal power
61 * @voltage_bank: bank to control regulator voltage
62 * @voltage_reg: register to control regulator voltage
63 * @voltage_mask: mask to control regulator voltage
65 struct ab8500_regulator_info {
67 struct regulator_desc desc;
68 struct regulator_dev *regulator;
69 struct ab8500_shared_mode *shared_mode;
93 /* voltage tables for the vauxn/vintcore supplies */
94 static const unsigned int ldo_vauxn_voltages[] = {
113 static const unsigned int ldo_vaux3_voltages[] = {
124 static const unsigned int ldo_vaux56_voltages[] = {
135 static const unsigned int ldo_vaux3_ab8540_voltages[] = {
147 static const unsigned int ldo_vaux56_ab8540_voltages[] = {
148 750000, 760000, 770000, 780000, 790000, 800000,
149 810000, 820000, 830000, 840000, 850000, 860000,
150 870000, 880000, 890000, 900000, 910000, 920000,
151 930000, 940000, 950000, 960000, 970000, 980000,
152 990000, 1000000, 1010000, 1020000, 1030000,
153 1040000, 1050000, 1060000, 1070000, 1080000,
154 1090000, 1100000, 1110000, 1120000, 1130000,
155 1140000, 1150000, 1160000, 1170000, 1180000,
156 1190000, 1200000, 1210000, 1220000, 1230000,
157 1240000, 1250000, 1260000, 1270000, 1280000,
158 1290000, 1300000, 1310000, 1320000, 1330000,
159 1340000, 1350000, 1360000, 1800000, 2790000,
162 static const unsigned int ldo_vintcore_voltages[] = {
172 static const unsigned int ldo_sdio_voltages[] = {
183 static const unsigned int fixed_1200000_voltage[] = {
187 static const unsigned int fixed_1800000_voltage[] = {
191 static const unsigned int fixed_2000000_voltage[] = {
195 static const unsigned int fixed_2050000_voltage[] = {
199 static const unsigned int fixed_3300000_voltage[] = {
203 static const unsigned int ldo_vana_voltages[] = {
214 static const unsigned int ldo_vaudio_voltages[] = {
222 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
225 static const unsigned int ldo_vdmic_voltages[] = {
232 static DEFINE_MUTEX(shared_mode_mutex);
233 static struct ab8500_shared_mode ldo_anamic1_shared;
234 static struct ab8500_shared_mode ldo_anamic2_shared;
235 static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
236 static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
238 static int ab8500_regulator_enable(struct regulator_dev *rdev)
241 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
244 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
248 ret = abx500_mask_and_set_register_interruptible(info->dev,
249 info->update_bank, info->update_reg,
250 info->update_mask, info->update_val);
252 dev_err(rdev_get_dev(rdev),
253 "couldn't set enable bits for regulator\n");
257 dev_vdbg(rdev_get_dev(rdev),
258 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
259 info->desc.name, info->update_bank, info->update_reg,
260 info->update_mask, info->update_val);
265 static int ab8500_regulator_disable(struct regulator_dev *rdev)
268 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
271 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
275 ret = abx500_mask_and_set_register_interruptible(info->dev,
276 info->update_bank, info->update_reg,
277 info->update_mask, 0x0);
279 dev_err(rdev_get_dev(rdev),
280 "couldn't set disable bits for regulator\n");
284 dev_vdbg(rdev_get_dev(rdev),
285 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
286 info->desc.name, info->update_bank, info->update_reg,
287 info->update_mask, 0x0);
292 static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
295 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
299 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
303 ret = abx500_get_register_interruptible(info->dev,
304 info->update_bank, info->update_reg, ®val);
306 dev_err(rdev_get_dev(rdev),
307 "couldn't read 0x%x register\n", info->update_reg);
311 dev_vdbg(rdev_get_dev(rdev),
312 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
314 info->desc.name, info->update_bank, info->update_reg,
315 info->update_mask, regval);
317 if (regval & info->update_mask)
323 static unsigned int ab8500_regulator_get_optimum_mode(
324 struct regulator_dev *rdev, int input_uV,
325 int output_uV, int load_uA)
329 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
332 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
336 if (load_uA <= info->load_lp_uA)
337 mode = REGULATOR_MODE_IDLE;
339 mode = REGULATOR_MODE_NORMAL;
344 static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
348 u8 bank, reg, mask, val;
349 bool lp_mode_req = false;
350 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
353 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
357 if (info->mode_mask) {
358 bank = info->mode_bank;
359 reg = info->mode_reg;
360 mask = info->mode_mask;
362 bank = info->update_bank;
363 reg = info->update_reg;
364 mask = info->update_mask;
367 if (info->shared_mode)
368 mutex_lock(&shared_mode_mutex);
371 case REGULATOR_MODE_NORMAL:
372 if (info->shared_mode)
376 val = info->mode_val_normal;
378 val = info->update_val_normal;
380 case REGULATOR_MODE_IDLE:
381 if (info->shared_mode) {
382 struct ab8500_regulator_info *shared_regulator;
384 shared_regulator = info->shared_mode->shared_regulator;
385 if (!shared_regulator->shared_mode->lp_mode_req) {
386 /* Other regulator prevent LP mode */
387 info->shared_mode->lp_mode_req = true;
395 val = info->mode_val_idle;
397 val = info->update_val_idle;
404 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) {
405 ret = abx500_mask_and_set_register_interruptible(info->dev,
406 bank, reg, mask, val);
408 dev_err(rdev_get_dev(rdev),
409 "couldn't set regulator mode\n");
413 dev_vdbg(rdev_get_dev(rdev),
414 "%s-set_mode (bank, reg, mask, value): "
415 "0x%x, 0x%x, 0x%x, 0x%x\n",
416 info->desc.name, bank, reg,
420 if (!info->mode_mask)
421 info->update_val = val;
423 if (info->shared_mode)
424 info->shared_mode->lp_mode_req = lp_mode_req;
427 if (info->shared_mode)
428 mutex_unlock(&shared_mode_mutex);
433 static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
435 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
442 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
446 /* Need special handling for shared mode */
447 if (info->shared_mode) {
448 if (info->shared_mode->lp_mode_req)
449 return REGULATOR_MODE_IDLE;
451 return REGULATOR_MODE_NORMAL;
454 if (info->mode_mask) {
455 /* Dedicated register for handling mode */
456 ret = abx500_get_register_interruptible(info->dev,
457 info->mode_bank, info->mode_reg, &val);
458 val = val & info->mode_mask;
460 val_normal = info->mode_val_normal;
461 val_idle = info->mode_val_idle;
463 /* Mode register same as enable register */
464 val = info->update_val;
465 val_normal = info->update_val_normal;
466 val_idle = info->update_val_idle;
469 if (val == val_normal)
470 ret = REGULATOR_MODE_NORMAL;
471 else if (val == val_idle)
472 ret = REGULATOR_MODE_IDLE;
479 static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
481 int ret, voltage_shift;
482 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
486 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
490 voltage_shift = ffs(info->voltage_mask) - 1;
492 ret = abx500_get_register_interruptible(info->dev,
493 info->voltage_bank, info->voltage_reg, ®val);
495 dev_err(rdev_get_dev(rdev),
496 "couldn't read voltage reg for regulator\n");
500 dev_vdbg(rdev_get_dev(rdev),
501 "%s-get_voltage (bank, reg, mask, shift, value): "
502 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
503 info->desc.name, info->voltage_bank,
504 info->voltage_reg, info->voltage_mask,
505 voltage_shift, regval);
507 return (regval & info->voltage_mask) >> voltage_shift;
510 static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
512 int ret, voltage_shift;
513 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
514 u8 regval, regval_expand;
517 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
521 ret = abx500_get_register_interruptible(info->dev,
522 info->expand_register.voltage_bank,
523 info->expand_register.voltage_reg, ®val_expand);
525 dev_err(rdev_get_dev(rdev),
526 "couldn't read voltage expand reg for regulator\n");
530 dev_vdbg(rdev_get_dev(rdev),
531 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
532 info->desc.name, info->expand_register.voltage_bank,
533 info->expand_register.voltage_reg,
534 info->expand_register.voltage_mask, regval_expand);
536 if (regval_expand & info->expand_register.voltage_mask)
537 return info->expand_register.voltage_limit;
539 ret = abx500_get_register_interruptible(info->dev,
540 info->voltage_bank, info->voltage_reg, ®val);
542 dev_err(rdev_get_dev(rdev),
543 "couldn't read voltage reg for regulator\n");
547 dev_vdbg(rdev_get_dev(rdev),
548 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
549 info->desc.name, info->voltage_bank, info->voltage_reg,
550 info->voltage_mask, regval);
552 voltage_shift = ffs(info->voltage_mask) - 1;
554 return (regval & info->voltage_mask) >> voltage_shift;
557 static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
560 int ret, voltage_shift;
561 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
565 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
569 voltage_shift = ffs(info->voltage_mask) - 1;
571 /* set the registers for the request */
572 regval = (u8)selector << voltage_shift;
573 ret = abx500_mask_and_set_register_interruptible(info->dev,
574 info->voltage_bank, info->voltage_reg,
575 info->voltage_mask, regval);
577 dev_err(rdev_get_dev(rdev),
578 "couldn't set voltage reg for regulator\n");
580 dev_vdbg(rdev_get_dev(rdev),
581 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
583 info->desc.name, info->voltage_bank, info->voltage_reg,
584 info->voltage_mask, regval);
589 static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
593 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
594 u8 regval, regval_expand;
597 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
601 if (selector < info->expand_register.voltage_limit) {
602 int voltage_shift = ffs(info->voltage_mask) - 1;
604 regval = (u8)selector << voltage_shift;
605 ret = abx500_mask_and_set_register_interruptible(info->dev,
606 info->voltage_bank, info->voltage_reg,
607 info->voltage_mask, regval);
609 dev_err(rdev_get_dev(rdev),
610 "couldn't set voltage reg for regulator\n");
614 dev_vdbg(rdev_get_dev(rdev),
615 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
616 info->desc.name, info->voltage_bank, info->voltage_reg,
617 info->voltage_mask, regval);
621 regval_expand = info->expand_register.voltage_mask;
624 ret = abx500_mask_and_set_register_interruptible(info->dev,
625 info->expand_register.voltage_bank,
626 info->expand_register.voltage_reg,
627 info->expand_register.voltage_mask,
630 dev_err(rdev_get_dev(rdev),
631 "couldn't set expand voltage reg for regulator\n");
635 dev_vdbg(rdev_get_dev(rdev),
636 "%s-set_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
637 info->desc.name, info->expand_register.voltage_bank,
638 info->expand_register.voltage_reg,
639 info->expand_register.voltage_mask, regval_expand);
644 static struct regulator_ops ab8500_regulator_volt_mode_ops = {
645 .enable = ab8500_regulator_enable,
646 .disable = ab8500_regulator_disable,
647 .is_enabled = ab8500_regulator_is_enabled,
648 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
649 .set_mode = ab8500_regulator_set_mode,
650 .get_mode = ab8500_regulator_get_mode,
651 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
652 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
653 .list_voltage = regulator_list_voltage_table,
656 static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
657 .enable = ab8500_regulator_enable,
658 .disable = ab8500_regulator_disable,
659 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
660 .set_mode = ab8500_regulator_set_mode,
661 .get_mode = ab8500_regulator_get_mode,
662 .is_enabled = ab8500_regulator_is_enabled,
663 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
664 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
665 .list_voltage = regulator_list_voltage_table,
668 static struct regulator_ops ab8500_regulator_volt_ops = {
669 .enable = ab8500_regulator_enable,
670 .disable = ab8500_regulator_disable,
671 .is_enabled = ab8500_regulator_is_enabled,
672 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
673 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
674 .list_voltage = regulator_list_voltage_table,
677 static struct regulator_ops ab8500_regulator_mode_ops = {
678 .enable = ab8500_regulator_enable,
679 .disable = ab8500_regulator_disable,
680 .is_enabled = ab8500_regulator_is_enabled,
681 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
682 .set_mode = ab8500_regulator_set_mode,
683 .get_mode = ab8500_regulator_get_mode,
684 .list_voltage = regulator_list_voltage_table,
687 static struct regulator_ops ab8500_regulator_ops = {
688 .enable = ab8500_regulator_enable,
689 .disable = ab8500_regulator_disable,
690 .is_enabled = ab8500_regulator_is_enabled,
691 .list_voltage = regulator_list_voltage_table,
694 static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
695 .enable = ab8500_regulator_enable,
696 .disable = ab8500_regulator_disable,
697 .is_enabled = ab8500_regulator_is_enabled,
698 .set_mode = ab8500_regulator_set_mode,
699 .get_mode = ab8500_regulator_get_mode,
700 .list_voltage = regulator_list_voltage_table,
703 /* AB8500 regulator information */
704 static struct ab8500_regulator_info
705 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
707 * Variable Voltage Regulators
708 * name, min mV, max mV,
709 * update bank, reg, mask, enable val
710 * volt bank, reg, mask
712 [AB8500_LDO_AUX1] = {
715 .ops = &ab8500_regulator_volt_mode_ops,
716 .type = REGULATOR_VOLTAGE,
717 .id = AB8500_LDO_AUX1,
718 .owner = THIS_MODULE,
719 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
720 .volt_table = ldo_vauxn_voltages,
722 .supply_name = "vin",
729 .update_val_idle = 0x03,
730 .update_val_normal = 0x01,
731 .voltage_bank = 0x04,
733 .voltage_mask = 0x0f,
735 [AB8500_LDO_AUX2] = {
738 .ops = &ab8500_regulator_volt_mode_ops,
739 .type = REGULATOR_VOLTAGE,
740 .id = AB8500_LDO_AUX2,
741 .owner = THIS_MODULE,
742 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
743 .volt_table = ldo_vauxn_voltages,
745 .supply_name = "vin",
752 .update_val_idle = 0x0c,
753 .update_val_normal = 0x04,
754 .voltage_bank = 0x04,
756 .voltage_mask = 0x0f,
758 [AB8500_LDO_AUX3] = {
761 .ops = &ab8500_regulator_volt_mode_ops,
762 .type = REGULATOR_VOLTAGE,
763 .id = AB8500_LDO_AUX3,
764 .owner = THIS_MODULE,
765 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
766 .volt_table = ldo_vaux3_voltages,
768 .supply_name = "vin",
775 .update_val_idle = 0x03,
776 .update_val_normal = 0x01,
777 .voltage_bank = 0x04,
779 .voltage_mask = 0x07,
781 [AB8500_LDO_INTCORE] = {
783 .name = "LDO-INTCORE",
784 .ops = &ab8500_regulator_volt_mode_ops,
785 .type = REGULATOR_VOLTAGE,
786 .id = AB8500_LDO_INTCORE,
787 .owner = THIS_MODULE,
788 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
789 .volt_table = ldo_vintcore_voltages,
797 .update_val_idle = 0x44,
798 .update_val_normal = 0x04,
799 .voltage_bank = 0x03,
801 .voltage_mask = 0x38,
805 * Fixed Voltage Regulators
807 * update bank, reg, mask, enable val
809 [AB8500_LDO_TVOUT] = {
812 .ops = &ab8500_regulator_mode_ops,
813 .type = REGULATOR_VOLTAGE,
814 .id = AB8500_LDO_TVOUT,
815 .owner = THIS_MODULE,
817 .volt_table = fixed_2000000_voltage,
825 .update_val_idle = 0x82,
826 .update_val_normal = 0x02,
828 [AB8500_LDO_AUDIO] = {
831 .ops = &ab8500_regulator_ops,
832 .type = REGULATOR_VOLTAGE,
833 .id = AB8500_LDO_AUDIO,
834 .owner = THIS_MODULE,
837 .volt_table = fixed_2000000_voltage,
844 [AB8500_LDO_ANAMIC1] = {
846 .name = "LDO-ANAMIC1",
847 .ops = &ab8500_regulator_ops,
848 .type = REGULATOR_VOLTAGE,
849 .id = AB8500_LDO_ANAMIC1,
850 .owner = THIS_MODULE,
853 .volt_table = fixed_2050000_voltage,
860 [AB8500_LDO_ANAMIC2] = {
862 .name = "LDO-ANAMIC2",
863 .ops = &ab8500_regulator_ops,
864 .type = REGULATOR_VOLTAGE,
865 .id = AB8500_LDO_ANAMIC2,
866 .owner = THIS_MODULE,
869 .volt_table = fixed_2050000_voltage,
876 [AB8500_LDO_DMIC] = {
879 .ops = &ab8500_regulator_ops,
880 .type = REGULATOR_VOLTAGE,
881 .id = AB8500_LDO_DMIC,
882 .owner = THIS_MODULE,
885 .volt_table = fixed_1800000_voltage,
894 * Regulators with fixed voltage and normal/idle modes
899 .ops = &ab8500_regulator_mode_ops,
900 .type = REGULATOR_VOLTAGE,
901 .id = AB8500_LDO_ANA,
902 .owner = THIS_MODULE,
905 .volt_table = fixed_1200000_voltage,
912 .update_val_idle = 0x0c,
913 .update_val_normal = 0x04,
917 /* AB8505 regulator information */
918 static struct ab8500_regulator_info
919 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
921 * Variable Voltage Regulators
922 * name, min mV, max mV,
923 * update bank, reg, mask, enable val
924 * volt bank, reg, mask
926 [AB8505_LDO_AUX1] = {
929 .ops = &ab8500_regulator_volt_mode_ops,
930 .type = REGULATOR_VOLTAGE,
931 .id = AB8505_LDO_AUX1,
932 .owner = THIS_MODULE,
933 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
934 .volt_table = ldo_vauxn_voltages,
941 .update_val_idle = 0x03,
942 .update_val_normal = 0x01,
943 .voltage_bank = 0x04,
945 .voltage_mask = 0x0f,
947 [AB8505_LDO_AUX2] = {
950 .ops = &ab8500_regulator_volt_mode_ops,
951 .type = REGULATOR_VOLTAGE,
952 .id = AB8505_LDO_AUX2,
953 .owner = THIS_MODULE,
954 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
955 .volt_table = ldo_vauxn_voltages,
962 .update_val_idle = 0x0c,
963 .update_val_normal = 0x04,
964 .voltage_bank = 0x04,
966 .voltage_mask = 0x0f,
968 [AB8505_LDO_AUX3] = {
971 .ops = &ab8500_regulator_volt_mode_ops,
972 .type = REGULATOR_VOLTAGE,
973 .id = AB8505_LDO_AUX3,
974 .owner = THIS_MODULE,
975 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
976 .volt_table = ldo_vaux3_voltages,
983 .update_val_idle = 0x03,
984 .update_val_normal = 0x01,
985 .voltage_bank = 0x04,
987 .voltage_mask = 0x07,
989 [AB8505_LDO_AUX4] = {
992 .ops = &ab8500_regulator_volt_mode_ops,
993 .type = REGULATOR_VOLTAGE,
994 .id = AB8505_LDO_AUX4,
995 .owner = THIS_MODULE,
996 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
997 .volt_table = ldo_vauxn_voltages,
1000 /* values for Vaux4Regu register */
1001 .update_bank = 0x04,
1003 .update_mask = 0x03,
1005 .update_val_idle = 0x03,
1006 .update_val_normal = 0x01,
1007 /* values for Vaux4SEL register */
1008 .voltage_bank = 0x04,
1009 .voltage_reg = 0x2f,
1010 .voltage_mask = 0x0f,
1012 [AB8505_LDO_AUX5] = {
1015 .ops = &ab8500_regulator_volt_mode_ops,
1016 .type = REGULATOR_VOLTAGE,
1017 .id = AB8505_LDO_AUX5,
1018 .owner = THIS_MODULE,
1019 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
1020 .volt_table = ldo_vaux56_voltages,
1023 /* values for CtrlVaux5 register */
1024 .update_bank = 0x01,
1026 .update_mask = 0x18,
1028 .update_val_idle = 0x18,
1029 .update_val_normal = 0x10,
1030 .voltage_bank = 0x01,
1031 .voltage_reg = 0x55,
1032 .voltage_mask = 0x07,
1034 [AB8505_LDO_AUX6] = {
1037 .ops = &ab8500_regulator_volt_mode_ops,
1038 .type = REGULATOR_VOLTAGE,
1039 .id = AB8505_LDO_AUX6,
1040 .owner = THIS_MODULE,
1041 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
1042 .volt_table = ldo_vaux56_voltages,
1045 /* values for CtrlVaux6 register */
1046 .update_bank = 0x01,
1048 .update_mask = 0x18,
1050 .update_val_idle = 0x18,
1051 .update_val_normal = 0x10,
1052 .voltage_bank = 0x01,
1053 .voltage_reg = 0x56,
1054 .voltage_mask = 0x07,
1056 [AB8505_LDO_INTCORE] = {
1058 .name = "LDO-INTCORE",
1059 .ops = &ab8500_regulator_volt_mode_ops,
1060 .type = REGULATOR_VOLTAGE,
1061 .id = AB8505_LDO_INTCORE,
1062 .owner = THIS_MODULE,
1063 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1064 .volt_table = ldo_vintcore_voltages,
1067 .update_bank = 0x03,
1069 .update_mask = 0x44,
1071 .update_val_idle = 0x44,
1072 .update_val_normal = 0x04,
1073 .voltage_bank = 0x03,
1074 .voltage_reg = 0x80,
1075 .voltage_mask = 0x38,
1079 * Fixed Voltage Regulators
1081 * update bank, reg, mask, enable val
1083 [AB8505_LDO_ADC] = {
1086 .ops = &ab8500_regulator_mode_ops,
1087 .type = REGULATOR_VOLTAGE,
1088 .id = AB8505_LDO_ADC,
1089 .owner = THIS_MODULE,
1091 .volt_table = fixed_2000000_voltage,
1092 .enable_time = 10000,
1095 .update_bank = 0x03,
1097 .update_mask = 0x82,
1099 .update_val_idle = 0x82,
1100 .update_val_normal = 0x02,
1102 [AB8505_LDO_AUDIO] = {
1104 .name = "LDO-AUDIO",
1105 .ops = &ab8500_regulator_volt_ops,
1106 .type = REGULATOR_VOLTAGE,
1107 .id = AB8505_LDO_AUDIO,
1108 .owner = THIS_MODULE,
1109 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1110 .volt_table = ldo_vaudio_voltages,
1112 .update_bank = 0x03,
1114 .update_mask = 0x02,
1116 .voltage_bank = 0x01,
1117 .voltage_reg = 0x57,
1118 .voltage_mask = 0x70,
1120 [AB8505_LDO_ANAMIC1] = {
1122 .name = "LDO-ANAMIC1",
1123 .ops = &ab8500_regulator_anamic_mode_ops,
1124 .type = REGULATOR_VOLTAGE,
1125 .id = AB8505_LDO_ANAMIC1,
1126 .owner = THIS_MODULE,
1128 .volt_table = fixed_2050000_voltage,
1130 .shared_mode = &ldo_anamic1_shared,
1131 .update_bank = 0x03,
1133 .update_mask = 0x08,
1138 .mode_val_idle = 0x04,
1139 .mode_val_normal = 0x00,
1141 [AB8505_LDO_ANAMIC2] = {
1143 .name = "LDO-ANAMIC2",
1144 .ops = &ab8500_regulator_anamic_mode_ops,
1145 .type = REGULATOR_VOLTAGE,
1146 .id = AB8505_LDO_ANAMIC2,
1147 .owner = THIS_MODULE,
1149 .volt_table = fixed_2050000_voltage,
1151 .shared_mode = &ldo_anamic2_shared,
1152 .update_bank = 0x03,
1154 .update_mask = 0x10,
1159 .mode_val_idle = 0x04,
1160 .mode_val_normal = 0x00,
1162 [AB8505_LDO_AUX8] = {
1165 .ops = &ab8500_regulator_ops,
1166 .type = REGULATOR_VOLTAGE,
1167 .id = AB8505_LDO_AUX8,
1168 .owner = THIS_MODULE,
1170 .volt_table = fixed_1800000_voltage,
1172 .update_bank = 0x03,
1174 .update_mask = 0x04,
1178 * Regulators with fixed voltage and normal/idle modes
1180 [AB8505_LDO_ANA] = {
1183 .ops = &ab8500_regulator_volt_mode_ops,
1184 .type = REGULATOR_VOLTAGE,
1185 .id = AB8505_LDO_ANA,
1186 .owner = THIS_MODULE,
1187 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1188 .volt_table = ldo_vana_voltages,
1191 .update_bank = 0x04,
1193 .update_mask = 0x0c,
1195 .update_val_idle = 0x0c,
1196 .update_val_normal = 0x04,
1197 .voltage_bank = 0x04,
1198 .voltage_reg = 0x29,
1199 .voltage_mask = 0x7,
1203 /* AB9540 regulator information */
1204 static struct ab8500_regulator_info
1205 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1207 * Variable Voltage Regulators
1208 * name, min mV, max mV,
1209 * update bank, reg, mask, enable val
1210 * volt bank, reg, mask
1212 [AB9540_LDO_AUX1] = {
1215 .ops = &ab8500_regulator_volt_mode_ops,
1216 .type = REGULATOR_VOLTAGE,
1217 .id = AB9540_LDO_AUX1,
1218 .owner = THIS_MODULE,
1219 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1220 .volt_table = ldo_vauxn_voltages,
1223 .update_bank = 0x04,
1225 .update_mask = 0x03,
1227 .update_val_idle = 0x03,
1228 .update_val_normal = 0x01,
1229 .voltage_bank = 0x04,
1230 .voltage_reg = 0x1f,
1231 .voltage_mask = 0x0f,
1233 [AB9540_LDO_AUX2] = {
1236 .ops = &ab8500_regulator_volt_mode_ops,
1237 .type = REGULATOR_VOLTAGE,
1238 .id = AB9540_LDO_AUX2,
1239 .owner = THIS_MODULE,
1240 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1241 .volt_table = ldo_vauxn_voltages,
1244 .update_bank = 0x04,
1246 .update_mask = 0x0c,
1248 .update_val_idle = 0x0c,
1249 .update_val_normal = 0x04,
1250 .voltage_bank = 0x04,
1251 .voltage_reg = 0x20,
1252 .voltage_mask = 0x0f,
1254 [AB9540_LDO_AUX3] = {
1257 .ops = &ab8500_regulator_volt_mode_ops,
1258 .type = REGULATOR_VOLTAGE,
1259 .id = AB9540_LDO_AUX3,
1260 .owner = THIS_MODULE,
1261 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
1262 .volt_table = ldo_vaux3_voltages,
1265 .update_bank = 0x04,
1267 .update_mask = 0x03,
1269 .update_val_idle = 0x03,
1270 .update_val_normal = 0x01,
1271 .voltage_bank = 0x04,
1272 .voltage_reg = 0x21,
1273 .voltage_mask = 0x07,
1275 [AB9540_LDO_AUX4] = {
1278 .ops = &ab8500_regulator_volt_mode_ops,
1279 .type = REGULATOR_VOLTAGE,
1280 .id = AB9540_LDO_AUX4,
1281 .owner = THIS_MODULE,
1282 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1283 .volt_table = ldo_vauxn_voltages,
1286 /* values for Vaux4Regu register */
1287 .update_bank = 0x04,
1289 .update_mask = 0x03,
1291 .update_val_idle = 0x03,
1292 .update_val_normal = 0x01,
1293 /* values for Vaux4SEL register */
1294 .voltage_bank = 0x04,
1295 .voltage_reg = 0x2f,
1296 .voltage_mask = 0x0f,
1298 [AB9540_LDO_INTCORE] = {
1300 .name = "LDO-INTCORE",
1301 .ops = &ab8500_regulator_volt_mode_ops,
1302 .type = REGULATOR_VOLTAGE,
1303 .id = AB9540_LDO_INTCORE,
1304 .owner = THIS_MODULE,
1305 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1306 .volt_table = ldo_vintcore_voltages,
1309 .update_bank = 0x03,
1311 .update_mask = 0x44,
1313 .update_val_idle = 0x44,
1314 .update_val_normal = 0x04,
1315 .voltage_bank = 0x03,
1316 .voltage_reg = 0x80,
1317 .voltage_mask = 0x38,
1321 * Fixed Voltage Regulators
1323 * update bank, reg, mask, enable val
1325 [AB9540_LDO_TVOUT] = {
1327 .name = "LDO-TVOUT",
1328 .ops = &ab8500_regulator_mode_ops,
1329 .type = REGULATOR_VOLTAGE,
1330 .id = AB9540_LDO_TVOUT,
1331 .owner = THIS_MODULE,
1333 .volt_table = fixed_2000000_voltage,
1334 .enable_time = 10000,
1337 .update_bank = 0x03,
1339 .update_mask = 0x82,
1341 .update_val_idle = 0x82,
1342 .update_val_normal = 0x02,
1344 [AB9540_LDO_USB] = {
1347 .ops = &ab8500_regulator_ops,
1348 .type = REGULATOR_VOLTAGE,
1349 .id = AB9540_LDO_USB,
1350 .owner = THIS_MODULE,
1352 .volt_table = fixed_3300000_voltage,
1354 .update_bank = 0x03,
1356 .update_mask = 0x03,
1358 .update_val_idle = 0x03,
1359 .update_val_normal = 0x01,
1361 [AB9540_LDO_AUDIO] = {
1363 .name = "LDO-AUDIO",
1364 .ops = &ab8500_regulator_ops,
1365 .type = REGULATOR_VOLTAGE,
1366 .id = AB9540_LDO_AUDIO,
1367 .owner = THIS_MODULE,
1369 .volt_table = fixed_2000000_voltage,
1371 .update_bank = 0x03,
1373 .update_mask = 0x02,
1376 [AB9540_LDO_ANAMIC1] = {
1378 .name = "LDO-ANAMIC1",
1379 .ops = &ab8500_regulator_ops,
1380 .type = REGULATOR_VOLTAGE,
1381 .id = AB9540_LDO_ANAMIC1,
1382 .owner = THIS_MODULE,
1384 .volt_table = fixed_2050000_voltage,
1386 .update_bank = 0x03,
1388 .update_mask = 0x08,
1391 [AB9540_LDO_ANAMIC2] = {
1393 .name = "LDO-ANAMIC2",
1394 .ops = &ab8500_regulator_ops,
1395 .type = REGULATOR_VOLTAGE,
1396 .id = AB9540_LDO_ANAMIC2,
1397 .owner = THIS_MODULE,
1399 .volt_table = fixed_2050000_voltage,
1401 .update_bank = 0x03,
1403 .update_mask = 0x10,
1406 [AB9540_LDO_DMIC] = {
1409 .ops = &ab8500_regulator_ops,
1410 .type = REGULATOR_VOLTAGE,
1411 .id = AB9540_LDO_DMIC,
1412 .owner = THIS_MODULE,
1414 .volt_table = fixed_1800000_voltage,
1416 .update_bank = 0x03,
1418 .update_mask = 0x04,
1423 * Regulators with fixed voltage and normal/idle modes
1425 [AB9540_LDO_ANA] = {
1428 .ops = &ab8500_regulator_mode_ops,
1429 .type = REGULATOR_VOLTAGE,
1430 .id = AB9540_LDO_ANA,
1431 .owner = THIS_MODULE,
1433 .volt_table = fixed_1200000_voltage,
1436 .update_bank = 0x04,
1438 .update_mask = 0x0c,
1440 .update_val_idle = 0x0c,
1441 .update_val_normal = 0x08,
1445 /* AB8540 regulator information */
1446 static struct ab8500_regulator_info
1447 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1449 * Variable Voltage Regulators
1450 * name, min mV, max mV,
1451 * update bank, reg, mask, enable val
1452 * volt bank, reg, mask
1454 [AB8540_LDO_AUX1] = {
1457 .ops = &ab8500_regulator_volt_mode_ops,
1458 .type = REGULATOR_VOLTAGE,
1459 .id = AB8540_LDO_AUX1,
1460 .owner = THIS_MODULE,
1461 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1462 .volt_table = ldo_vauxn_voltages,
1465 .update_bank = 0x04,
1467 .update_mask = 0x03,
1469 .update_val_idle = 0x03,
1470 .update_val_normal = 0x01,
1471 .voltage_bank = 0x04,
1472 .voltage_reg = 0x1f,
1473 .voltage_mask = 0x0f,
1475 [AB8540_LDO_AUX2] = {
1478 .ops = &ab8500_regulator_volt_mode_ops,
1479 .type = REGULATOR_VOLTAGE,
1480 .id = AB8540_LDO_AUX2,
1481 .owner = THIS_MODULE,
1482 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1483 .volt_table = ldo_vauxn_voltages,
1486 .update_bank = 0x04,
1488 .update_mask = 0x0c,
1490 .update_val_idle = 0x0c,
1491 .update_val_normal = 0x04,
1492 .voltage_bank = 0x04,
1493 .voltage_reg = 0x20,
1494 .voltage_mask = 0x0f,
1496 [AB8540_LDO_AUX3] = {
1499 .ops = &ab8540_aux3_regulator_volt_mode_ops,
1500 .type = REGULATOR_VOLTAGE,
1501 .id = AB8540_LDO_AUX3,
1502 .owner = THIS_MODULE,
1503 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
1504 .volt_table = ldo_vaux3_ab8540_voltages,
1507 .update_bank = 0x04,
1509 .update_mask = 0x03,
1511 .update_val_idle = 0x03,
1512 .update_val_normal = 0x01,
1513 .voltage_bank = 0x04,
1514 .voltage_reg = 0x21,
1515 .voltage_mask = 0x07,
1516 .expand_register = {
1518 .voltage_bank = 0x04,
1519 .voltage_reg = 0x01,
1520 .voltage_mask = 0x10,
1523 [AB8540_LDO_AUX4] = {
1526 .ops = &ab8500_regulator_volt_mode_ops,
1527 .type = REGULATOR_VOLTAGE,
1528 .id = AB8540_LDO_AUX4,
1529 .owner = THIS_MODULE,
1530 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1531 .volt_table = ldo_vauxn_voltages,
1534 /* values for Vaux4Regu register */
1535 .update_bank = 0x04,
1537 .update_mask = 0x03,
1539 .update_val_idle = 0x03,
1540 .update_val_normal = 0x01,
1541 /* values for Vaux4SEL register */
1542 .voltage_bank = 0x04,
1543 .voltage_reg = 0x2f,
1544 .voltage_mask = 0x0f,
1546 [AB8540_LDO_AUX5] = {
1549 .ops = &ab8500_regulator_volt_mode_ops,
1550 .type = REGULATOR_VOLTAGE,
1551 .id = AB8540_LDO_AUX5,
1552 .owner = THIS_MODULE,
1553 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1554 .volt_table = ldo_vaux56_ab8540_voltages,
1556 .load_lp_uA = 20000,
1557 /* values for Vaux5Regu register */
1558 .update_bank = 0x04,
1560 .update_mask = 0x03,
1562 .update_val_idle = 0x03,
1563 .update_val_normal = 0x01,
1564 /* values for Vaux5SEL register */
1565 .voltage_bank = 0x04,
1566 .voltage_reg = 0x33,
1567 .voltage_mask = 0x3f,
1569 [AB8540_LDO_AUX6] = {
1572 .ops = &ab8500_regulator_volt_mode_ops,
1573 .type = REGULATOR_VOLTAGE,
1574 .id = AB8540_LDO_AUX6,
1575 .owner = THIS_MODULE,
1576 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1577 .volt_table = ldo_vaux56_ab8540_voltages,
1579 .load_lp_uA = 20000,
1580 /* values for Vaux6Regu register */
1581 .update_bank = 0x04,
1583 .update_mask = 0x03,
1585 .update_val_idle = 0x03,
1586 .update_val_normal = 0x01,
1587 /* values for Vaux6SEL register */
1588 .voltage_bank = 0x04,
1589 .voltage_reg = 0x36,
1590 .voltage_mask = 0x3f,
1592 [AB8540_LDO_INTCORE] = {
1594 .name = "LDO-INTCORE",
1595 .ops = &ab8500_regulator_volt_mode_ops,
1596 .type = REGULATOR_VOLTAGE,
1597 .id = AB8540_LDO_INTCORE,
1598 .owner = THIS_MODULE,
1599 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1600 .volt_table = ldo_vintcore_voltages,
1603 .update_bank = 0x03,
1605 .update_mask = 0x44,
1607 .update_val_idle = 0x44,
1608 .update_val_normal = 0x04,
1609 .voltage_bank = 0x03,
1610 .voltage_reg = 0x80,
1611 .voltage_mask = 0x38,
1615 * Fixed Voltage Regulators
1617 * update bank, reg, mask, enable val
1619 [AB8540_LDO_TVOUT] = {
1621 .name = "LDO-TVOUT",
1622 .ops = &ab8500_regulator_mode_ops,
1623 .type = REGULATOR_VOLTAGE,
1624 .id = AB8540_LDO_TVOUT,
1625 .owner = THIS_MODULE,
1627 .volt_table = fixed_2000000_voltage,
1628 .enable_time = 10000,
1631 .update_bank = 0x03,
1633 .update_mask = 0x82,
1635 .update_val_idle = 0x82,
1636 .update_val_normal = 0x02,
1638 [AB8540_LDO_AUDIO] = {
1640 .name = "LDO-AUDIO",
1641 .ops = &ab8500_regulator_ops,
1642 .type = REGULATOR_VOLTAGE,
1643 .id = AB8540_LDO_AUDIO,
1644 .owner = THIS_MODULE,
1646 .volt_table = fixed_2000000_voltage,
1648 .update_bank = 0x03,
1650 .update_mask = 0x02,
1653 [AB8540_LDO_ANAMIC1] = {
1655 .name = "LDO-ANAMIC1",
1656 .ops = &ab8500_regulator_anamic_mode_ops,
1657 .type = REGULATOR_VOLTAGE,
1658 .id = AB8540_LDO_ANAMIC1,
1659 .owner = THIS_MODULE,
1661 .volt_table = fixed_2050000_voltage,
1663 .shared_mode = &ab8540_ldo_anamic1_shared,
1664 .update_bank = 0x03,
1666 .update_mask = 0x08,
1671 .mode_val_idle = 0x20,
1672 .mode_val_normal = 0x00,
1674 [AB8540_LDO_ANAMIC2] = {
1676 .name = "LDO-ANAMIC2",
1677 .ops = &ab8500_regulator_anamic_mode_ops,
1678 .type = REGULATOR_VOLTAGE,
1679 .id = AB8540_LDO_ANAMIC2,
1680 .owner = THIS_MODULE,
1682 .volt_table = fixed_2050000_voltage,
1684 .shared_mode = &ab8540_ldo_anamic2_shared,
1685 .update_bank = 0x03,
1687 .update_mask = 0x10,
1692 .mode_val_idle = 0x20,
1693 .mode_val_normal = 0x00,
1695 [AB8540_LDO_DMIC] = {
1698 .ops = &ab8500_regulator_volt_mode_ops,
1699 .type = REGULATOR_VOLTAGE,
1700 .id = AB8540_LDO_DMIC,
1701 .owner = THIS_MODULE,
1702 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
1703 .volt_table = ldo_vdmic_voltages,
1706 .update_bank = 0x03,
1708 .update_mask = 0x04,
1710 .voltage_bank = 0x03,
1711 .voltage_reg = 0x83,
1712 .voltage_mask = 0xc0,
1716 * Regulators with fixed voltage and normal/idle modes
1718 [AB8540_LDO_ANA] = {
1721 .ops = &ab8500_regulator_mode_ops,
1722 .type = REGULATOR_VOLTAGE,
1723 .id = AB8540_LDO_ANA,
1724 .owner = THIS_MODULE,
1726 .volt_table = fixed_1200000_voltage,
1729 .update_bank = 0x04,
1731 .update_mask = 0x0c,
1733 .update_val_idle = 0x0c,
1734 .update_val_normal = 0x04,
1736 [AB8540_LDO_SDIO] = {
1739 .ops = &ab8500_regulator_volt_mode_ops,
1740 .type = REGULATOR_VOLTAGE,
1741 .id = AB8540_LDO_SDIO,
1742 .owner = THIS_MODULE,
1743 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1744 .volt_table = ldo_sdio_voltages,
1747 .update_bank = 0x03,
1749 .update_mask = 0x30,
1751 .update_val_idle = 0x30,
1752 .update_val_normal = 0x10,
1753 .voltage_bank = 0x03,
1754 .voltage_reg = 0x88,
1755 .voltage_mask = 0x07,
1759 static struct ab8500_shared_mode ldo_anamic1_shared = {
1760 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1763 static struct ab8500_shared_mode ldo_anamic2_shared = {
1764 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1767 static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1768 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1771 static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1772 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1775 struct ab8500_reg_init {
1781 #define REG_INIT(_id, _bank, _addr, _mask) \
1788 /* AB8500 register init */
1789 static struct ab8500_reg_init ab8500_reg_init[] = {
1791 * 0x30, VanaRequestCtrl
1792 * 0xc0, VextSupply1RequestCtrl
1794 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
1796 * 0x03, VextSupply2RequestCtrl
1797 * 0x0c, VextSupply3RequestCtrl
1798 * 0x30, Vaux1RequestCtrl
1799 * 0xc0, Vaux2RequestCtrl
1801 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1803 * 0x03, Vaux3RequestCtrl
1806 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1808 * 0x08, VanaSysClkReq1HPValid
1809 * 0x20, Vaux1SysClkReq1HPValid
1810 * 0x40, Vaux2SysClkReq1HPValid
1811 * 0x80, Vaux3SysClkReq1HPValid
1813 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
1815 * 0x10, VextSupply1SysClkReq1HPValid
1816 * 0x20, VextSupply2SysClkReq1HPValid
1817 * 0x40, VextSupply3SysClkReq1HPValid
1819 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
1821 * 0x08, VanaHwHPReq1Valid
1822 * 0x20, Vaux1HwHPReq1Valid
1823 * 0x40, Vaux2HwHPReq1Valid
1824 * 0x80, Vaux3HwHPReq1Valid
1826 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
1828 * 0x01, VextSupply1HwHPReq1Valid
1829 * 0x02, VextSupply2HwHPReq1Valid
1830 * 0x04, VextSupply3HwHPReq1Valid
1832 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
1834 * 0x08, VanaHwHPReq2Valid
1835 * 0x20, Vaux1HwHPReq2Valid
1836 * 0x40, Vaux2HwHPReq2Valid
1837 * 0x80, Vaux3HwHPReq2Valid
1839 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
1841 * 0x01, VextSupply1HwHPReq2Valid
1842 * 0x02, VextSupply2HwHPReq2Valid
1843 * 0x04, VextSupply3HwHPReq2Valid
1845 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
1847 * 0x20, VanaSwHPReqValid
1848 * 0x80, Vaux1SwHPReqValid
1850 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
1852 * 0x01, Vaux2SwHPReqValid
1853 * 0x02, Vaux3SwHPReqValid
1854 * 0x04, VextSupply1SwHPReqValid
1855 * 0x08, VextSupply2SwHPReqValid
1856 * 0x10, VextSupply3SwHPReqValid
1858 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
1860 * 0x02, SysClkReq2Valid1
1861 * 0x04, SysClkReq3Valid1
1862 * 0x08, SysClkReq4Valid1
1863 * 0x10, SysClkReq5Valid1
1864 * 0x20, SysClkReq6Valid1
1865 * 0x40, SysClkReq7Valid1
1866 * 0x80, SysClkReq8Valid1
1868 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1870 * 0x02, SysClkReq2Valid2
1871 * 0x04, SysClkReq3Valid2
1872 * 0x08, SysClkReq4Valid2
1873 * 0x10, SysClkReq5Valid2
1874 * 0x20, SysClkReq6Valid2
1875 * 0x40, SysClkReq7Valid2
1876 * 0x80, SysClkReq8Valid2
1878 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1881 * 0x04, Vintcore12Ena
1882 * 0x38, Vintcore12Sel
1883 * 0x40, Vintcore12LP
1886 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1893 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1895 * 0x01, Vamic1_dzout
1896 * 0x02, Vamic2_dzout
1898 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1900 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1903 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1906 * 0x02, VrefDDRSleepMode
1908 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1910 * 0x03, VextSupply1Regu
1911 * 0x0c, VextSupply2Regu
1912 * 0x30, VextSupply3Regu
1913 * 0x40, ExtSupply2Bypass
1914 * 0x80, ExtSupply3Bypass
1916 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1921 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1925 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
1929 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1933 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1937 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
1939 * 0x01, VextSupply12LP
1941 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1946 * 0x20, Vintcore12Disch
1950 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1953 * 0x04, VdmicPullDownEna
1956 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1959 /* AB8505 register init */
1960 static struct ab8500_reg_init ab8505_reg_init[] = {
1962 * 0x03, VarmRequestCtrl
1963 * 0x0c, VsmpsCRequestCtrl
1964 * 0x30, VsmpsARequestCtrl
1965 * 0xc0, VsmpsBRequestCtrl
1967 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1969 * 0x03, VsafeRequestCtrl
1970 * 0x0c, VpllRequestCtrl
1971 * 0x30, VanaRequestCtrl
1973 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1975 * 0x30, Vaux1RequestCtrl
1976 * 0xc0, Vaux2RequestCtrl
1978 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1980 * 0x03, Vaux3RequestCtrl
1983 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1985 * 0x01, VsmpsASysClkReq1HPValid
1986 * 0x02, VsmpsBSysClkReq1HPValid
1987 * 0x04, VsafeSysClkReq1HPValid
1988 * 0x08, VanaSysClkReq1HPValid
1989 * 0x10, VpllSysClkReq1HPValid
1990 * 0x20, Vaux1SysClkReq1HPValid
1991 * 0x40, Vaux2SysClkReq1HPValid
1992 * 0x80, Vaux3SysClkReq1HPValid
1994 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1996 * 0x01, VsmpsCSysClkReq1HPValid
1997 * 0x02, VarmSysClkReq1HPValid
1998 * 0x04, VbbSysClkReq1HPValid
1999 * 0x08, VsmpsMSysClkReq1HPValid
2001 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2003 * 0x01, VsmpsAHwHPReq1Valid
2004 * 0x02, VsmpsBHwHPReq1Valid
2005 * 0x04, VsafeHwHPReq1Valid
2006 * 0x08, VanaHwHPReq1Valid
2007 * 0x10, VpllHwHPReq1Valid
2008 * 0x20, Vaux1HwHPReq1Valid
2009 * 0x40, Vaux2HwHPReq1Valid
2010 * 0x80, Vaux3HwHPReq1Valid
2012 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2014 * 0x08, VsmpsMHwHPReq1Valid
2016 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2018 * 0x01, VsmpsAHwHPReq2Valid
2019 * 0x02, VsmpsBHwHPReq2Valid
2020 * 0x04, VsafeHwHPReq2Valid
2021 * 0x08, VanaHwHPReq2Valid
2022 * 0x10, VpllHwHPReq2Valid
2023 * 0x20, Vaux1HwHPReq2Valid
2024 * 0x40, Vaux2HwHPReq2Valid
2025 * 0x80, Vaux3HwHPReq2Valid
2027 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2029 * 0x08, VsmpsMHwHPReq2Valid
2031 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2033 * 0x01, VsmpsCSwHPReqValid
2034 * 0x02, VarmSwHPReqValid
2035 * 0x04, VsmpsASwHPReqValid
2036 * 0x08, VsmpsBSwHPReqValid
2037 * 0x10, VsafeSwHPReqValid
2038 * 0x20, VanaSwHPReqValid
2039 * 0x40, VpllSwHPReqValid
2040 * 0x80, Vaux1SwHPReqValid
2042 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2044 * 0x01, Vaux2SwHPReqValid
2045 * 0x02, Vaux3SwHPReqValid
2046 * 0x20, VsmpsMSwHPReqValid
2048 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2050 * 0x02, SysClkReq2Valid1
2051 * 0x04, SysClkReq3Valid1
2052 * 0x08, SysClkReq4Valid1
2054 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2056 * 0x02, SysClkReq2Valid2
2057 * 0x04, SysClkReq3Valid2
2058 * 0x08, SysClkReq4Valid2
2060 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2062 * 0x01, Vaux4SwHPReqValid
2063 * 0x02, Vaux4HwHPReq2Valid
2064 * 0x04, Vaux4HwHPReq1Valid
2065 * 0x08, Vaux4SysClkReq1HPValid
2067 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2070 * 0x04, VintCore12Ena
2071 * 0x38, VintCore12Sel
2072 * 0x40, VintCore12LP
2075 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2082 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2084 * 0x01, Vamic1_dzout
2085 * 0x02, Vamic2_dzout
2087 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2090 * 0x0c, VsmpsASelCtrl
2091 * 0x10, VsmpsAAutoMode
2092 * 0x20, VsmpsAPWMMode
2094 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2097 * 0x0c, VsmpsBSelCtrl
2098 * 0x10, VsmpsBAutoMode
2099 * 0x20, VsmpsBPWMMode
2101 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2104 * 0x0c, VsafeSelCtrl
2105 * 0x10, VsafeAutoMode
2106 * 0x20, VsafePWMMode
2108 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2110 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2113 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2115 * 0x03, VextSupply1Regu
2116 * 0x0c, VextSupply2Regu
2117 * 0x30, VextSupply3Regu
2118 * 0x40, ExtSupply2Bypass
2119 * 0x80, ExtSupply3Bypass
2121 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2126 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2130 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2134 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2138 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2142 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2146 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2150 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2154 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2158 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2162 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2166 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2170 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2174 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2179 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2181 * 0x03, Vaux4RequestCtrl
2183 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2187 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2191 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2196 * 0x20, Vintcore12Disch
2200 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2203 * 0x04, VdmicPullDownEna
2206 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2210 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2216 * 0x40, Vaux5DisSfst
2217 * 0x80, Vaux5DisPulld
2219 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2224 * 0x80, Vaux6DisPulld
2226 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2229 /* AB9540 register init */
2230 static struct ab8500_reg_init ab9540_reg_init[] = {
2232 * 0x03, VarmRequestCtrl
2233 * 0x0c, VapeRequestCtrl
2234 * 0x30, Vsmps1RequestCtrl
2235 * 0xc0, Vsmps2RequestCtrl
2237 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2239 * 0x03, Vsmps3RequestCtrl
2240 * 0x0c, VpllRequestCtrl
2241 * 0x30, VanaRequestCtrl
2242 * 0xc0, VextSupply1RequestCtrl
2244 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2246 * 0x03, VextSupply2RequestCtrl
2247 * 0x0c, VextSupply3RequestCtrl
2248 * 0x30, Vaux1RequestCtrl
2249 * 0xc0, Vaux2RequestCtrl
2251 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2253 * 0x03, Vaux3RequestCtrl
2256 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2258 * 0x01, Vsmps1SysClkReq1HPValid
2259 * 0x02, Vsmps2SysClkReq1HPValid
2260 * 0x04, Vsmps3SysClkReq1HPValid
2261 * 0x08, VanaSysClkReq1HPValid
2262 * 0x10, VpllSysClkReq1HPValid
2263 * 0x20, Vaux1SysClkReq1HPValid
2264 * 0x40, Vaux2SysClkReq1HPValid
2265 * 0x80, Vaux3SysClkReq1HPValid
2267 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2269 * 0x01, VapeSysClkReq1HPValid
2270 * 0x02, VarmSysClkReq1HPValid
2271 * 0x04, VbbSysClkReq1HPValid
2272 * 0x08, VmodSysClkReq1HPValid
2273 * 0x10, VextSupply1SysClkReq1HPValid
2274 * 0x20, VextSupply2SysClkReq1HPValid
2275 * 0x40, VextSupply3SysClkReq1HPValid
2277 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2279 * 0x01, Vsmps1HwHPReq1Valid
2280 * 0x02, Vsmps2HwHPReq1Valid
2281 * 0x04, Vsmps3HwHPReq1Valid
2282 * 0x08, VanaHwHPReq1Valid
2283 * 0x10, VpllHwHPReq1Valid
2284 * 0x20, Vaux1HwHPReq1Valid
2285 * 0x40, Vaux2HwHPReq1Valid
2286 * 0x80, Vaux3HwHPReq1Valid
2288 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2290 * 0x01, VextSupply1HwHPReq1Valid
2291 * 0x02, VextSupply2HwHPReq1Valid
2292 * 0x04, VextSupply3HwHPReq1Valid
2293 * 0x08, VmodHwHPReq1Valid
2295 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2297 * 0x01, Vsmps1HwHPReq2Valid
2298 * 0x02, Vsmps2HwHPReq2Valid
2299 * 0x03, Vsmps3HwHPReq2Valid
2300 * 0x08, VanaHwHPReq2Valid
2301 * 0x10, VpllHwHPReq2Valid
2302 * 0x20, Vaux1HwHPReq2Valid
2303 * 0x40, Vaux2HwHPReq2Valid
2304 * 0x80, Vaux3HwHPReq2Valid
2306 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2308 * 0x01, VextSupply1HwHPReq2Valid
2309 * 0x02, VextSupply2HwHPReq2Valid
2310 * 0x04, VextSupply3HwHPReq2Valid
2311 * 0x08, VmodHwHPReq2Valid
2313 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2315 * 0x01, VapeSwHPReqValid
2316 * 0x02, VarmSwHPReqValid
2317 * 0x04, Vsmps1SwHPReqValid
2318 * 0x08, Vsmps2SwHPReqValid
2319 * 0x10, Vsmps3SwHPReqValid
2320 * 0x20, VanaSwHPReqValid
2321 * 0x40, VpllSwHPReqValid
2322 * 0x80, Vaux1SwHPReqValid
2324 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2326 * 0x01, Vaux2SwHPReqValid
2327 * 0x02, Vaux3SwHPReqValid
2328 * 0x04, VextSupply1SwHPReqValid
2329 * 0x08, VextSupply2SwHPReqValid
2330 * 0x10, VextSupply3SwHPReqValid
2331 * 0x20, VmodSwHPReqValid
2333 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2335 * 0x02, SysClkReq2Valid1
2337 * 0x80, SysClkReq8Valid1
2339 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2341 * 0x02, SysClkReq2Valid2
2343 * 0x80, SysClkReq8Valid2
2345 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2347 * 0x01, Vaux4SwHPReqValid
2348 * 0x02, Vaux4HwHPReq2Valid
2349 * 0x04, Vaux4HwHPReq1Valid
2350 * 0x08, Vaux4SysClkReq1HPValid
2352 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2355 * 0x04, Vintcore12Ena
2356 * 0x38, Vintcore12Sel
2357 * 0x40, Vintcore12LP
2360 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2367 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2369 * 0x01, Vamic1_dzout
2370 * 0x02, Vamic2_dzout
2372 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2375 * 0x0c, Vsmps1SelCtrl
2376 * 0x10, Vsmps1AutoMode
2377 * 0x20, Vsmps1PWMMode
2379 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2382 * 0x0c, Vsmps2SelCtrl
2383 * 0x10, Vsmps2AutoMode
2384 * 0x20, Vsmps2PWMMode
2386 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2389 * 0x0c, Vsmps3SelCtrl
2390 * NOTE! PRCMU register
2392 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2397 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2399 * 0x03, VextSupply1Regu
2400 * 0x0c, VextSupply2Regu
2401 * 0x30, VextSupply3Regu
2402 * 0x40, ExtSupply2Bypass
2403 * 0x80, ExtSupply3Bypass
2405 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2410 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2415 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2419 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2423 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2427 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2431 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2435 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2439 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2442 * NOTE! PRCMU register
2444 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2447 * NOTE! PRCMU register
2449 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2453 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2457 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2462 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2464 * 0x01, VextSupply12LP
2466 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2468 * 0x03, Vaux4RequestCtrl
2470 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2474 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2478 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2485 * 0x20, Vintcore12Disch
2489 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2493 * 0x04, VdmicPullDownEna
2494 * 0x08, VpllPullDownEna
2497 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2501 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2504 /* AB8540 register init */
2505 static struct ab8500_reg_init ab8540_reg_init[] = {
2507 * 0x01, VSimSycClkReq1Valid
2508 * 0x02, VSimSycClkReq2Valid
2509 * 0x04, VSimSycClkReq3Valid
2510 * 0x08, VSimSycClkReq4Valid
2511 * 0x10, VSimSycClkReq5Valid
2512 * 0x20, VSimSycClkReq6Valid
2513 * 0x40, VSimSycClkReq7Valid
2514 * 0x80, VSimSycClkReq8Valid
2516 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2518 * 0x03, VarmRequestCtrl
2519 * 0x0c, VapeRequestCtrl
2520 * 0x30, Vsmps1RequestCtrl
2521 * 0xc0, Vsmps2RequestCtrl
2523 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2525 * 0x03, Vsmps3RequestCtrl
2526 * 0x0c, VpllRequestCtrl
2527 * 0x30, VanaRequestCtrl
2528 * 0xc0, VextSupply1RequestCtrl
2530 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2532 * 0x03, VextSupply2RequestCtrl
2533 * 0x0c, VextSupply3RequestCtrl
2534 * 0x30, Vaux1RequestCtrl
2535 * 0xc0, Vaux2RequestCtrl
2537 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2539 * 0x03, Vaux3RequestCtrl
2542 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2544 * 0x01, Vsmps1SysClkReq1HPValid
2545 * 0x02, Vsmps2SysClkReq1HPValid
2546 * 0x04, Vsmps3SysClkReq1HPValid
2547 * 0x08, VanaSysClkReq1HPValid
2548 * 0x10, VpllSysClkReq1HPValid
2549 * 0x20, Vaux1SysClkReq1HPValid
2550 * 0x40, Vaux2SysClkReq1HPValid
2551 * 0x80, Vaux3SysClkReq1HPValid
2553 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2555 * 0x01, VapeSysClkReq1HPValid
2556 * 0x02, VarmSysClkReq1HPValid
2557 * 0x04, VbbSysClkReq1HPValid
2558 * 0x10, VextSupply1SysClkReq1HPValid
2559 * 0x20, VextSupply2SysClkReq1HPValid
2560 * 0x40, VextSupply3SysClkReq1HPValid
2562 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2564 * 0x01, Vsmps1HwHPReq1Valid
2565 * 0x02, Vsmps2HwHPReq1Valid
2566 * 0x04, Vsmps3HwHPReq1Valid
2567 * 0x08, VanaHwHPReq1Valid
2568 * 0x10, VpllHwHPReq1Valid
2569 * 0x20, Vaux1HwHPReq1Valid
2570 * 0x40, Vaux2HwHPReq1Valid
2571 * 0x80, Vaux3HwHPReq1Valid
2573 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2575 * 0x01, VextSupply1HwHPReq1Valid
2576 * 0x02, VextSupply2HwHPReq1Valid
2577 * 0x04, VextSupply3HwHPReq1Valid
2579 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2581 * 0x01, Vsmps1HwHPReq2Valid
2582 * 0x02, Vsmps2HwHPReq2Valid
2583 * 0x03, Vsmps3HwHPReq2Valid
2584 * 0x08, VanaHwHPReq2Valid
2585 * 0x10, VpllHwHPReq2Valid
2586 * 0x20, Vaux1HwHPReq2Valid
2587 * 0x40, Vaux2HwHPReq2Valid
2588 * 0x80, Vaux3HwHPReq2Valid
2590 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2592 * 0x01, VextSupply1HwHPReq2Valid
2593 * 0x02, VextSupply2HwHPReq2Valid
2594 * 0x04, VextSupply3HwHPReq2Valid
2596 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2598 * 0x01, VapeSwHPReqValid
2599 * 0x02, VarmSwHPReqValid
2600 * 0x04, Vsmps1SwHPReqValid
2601 * 0x08, Vsmps2SwHPReqValid
2602 * 0x10, Vsmps3SwHPReqValid
2603 * 0x20, VanaSwHPReqValid
2604 * 0x40, VpllSwHPReqValid
2605 * 0x80, Vaux1SwHPReqValid
2607 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2609 * 0x01, Vaux2SwHPReqValid
2610 * 0x02, Vaux3SwHPReqValid
2611 * 0x04, VextSupply1SwHPReqValid
2612 * 0x08, VextSupply2SwHPReqValid
2613 * 0x10, VextSupply3SwHPReqValid
2615 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2617 * 0x02, SysClkReq2Valid1
2619 * 0x80, SysClkReq8Valid1
2621 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2623 * 0x02, SysClkReq2Valid2
2625 * 0x80, SysClkReq8Valid2
2627 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2629 * 0x01, Vaux4SwHPReqValid
2630 * 0x02, Vaux4HwHPReq2Valid
2631 * 0x04, Vaux4HwHPReq1Valid
2632 * 0x08, Vaux4SysClkReq1HPValid
2634 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2636 * 0x01, Vaux5SwHPReqValid
2637 * 0x02, Vaux5HwHPReq2Valid
2638 * 0x04, Vaux5HwHPReq1Valid
2639 * 0x08, Vaux5SysClkReq1HPValid
2641 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2643 * 0x01, Vaux6SwHPReqValid
2644 * 0x02, Vaux6HwHPReq2Valid
2645 * 0x04, Vaux6HwHPReq1Valid
2646 * 0x08, Vaux6SysClkReq1HPValid
2648 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2650 * 0x01, VclkbSwHPReqValid
2651 * 0x02, VclkbHwHPReq2Valid
2652 * 0x04, VclkbHwHPReq1Valid
2653 * 0x08, VclkbSysClkReq1HPValid
2655 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2657 * 0x01, Vrf1SwHPReqValid
2658 * 0x02, Vrf1HwHPReq2Valid
2659 * 0x04, Vrf1HwHPReq1Valid
2660 * 0x08, Vrf1SysClkReq1HPValid
2662 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2665 * 0x04, Vintcore12Ena
2666 * 0x38, Vintcore12Sel
2667 * 0x40, Vintcore12LP
2670 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2679 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2681 * 0x01, Vamic1_dzout
2682 * 0x02, Vamic2_dzout
2684 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2687 * 0x08, VHSICOffState
2691 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2694 * 0x08, VSDIOOffState
2698 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2701 * 0x0c, Vsmps1SelCtrl
2702 * 0x10, Vsmps1AutoMode
2703 * 0x20, Vsmps1PWMMode
2705 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2708 * 0x0c, Vsmps2SelCtrl
2709 * 0x10, Vsmps2AutoMode
2710 * 0x20, Vsmps2PWMMode
2712 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2715 * 0x0c, Vsmps3SelCtrl
2716 * 0x10, Vsmps3AutoMode
2717 * 0x20, Vsmps3PWMMode
2718 * NOTE! PRCMU register
2720 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2725 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2727 * 0x03, VextSupply1Regu
2728 * 0x0c, VextSupply2Regu
2729 * 0x30, VextSupply3Regu
2730 * 0x40, ExtSupply2Bypass
2731 * 0x80, ExtSupply3Bypass
2733 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2738 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2743 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2747 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2751 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2755 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2759 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2763 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2767 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2770 * NOTE! PRCMU register
2772 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2775 * NOTE! PRCMU register
2777 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2781 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2785 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2790 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2792 * 0x01, VextSupply12LP
2794 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2799 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2801 * 0x03, Vaux4RequestCtrl
2803 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2807 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2811 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2813 * 0x03, Vaux5RequestCtrl
2815 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2819 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2823 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2825 * 0x03, Vaux6RequestCtrl
2827 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2831 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2835 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2837 * 0x03, VCLKBRequestCtrl
2839 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2843 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2847 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2849 * 0x03, Vrf1RequestCtrl
2851 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2858 * 0x20, Vintcore12Disch
2862 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2865 * 0x04, VdmicPullDownEna
2866 * 0x08, VpllPullDownEna
2869 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2873 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2879 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2882 static struct of_regulator_match ab8500_regulator_match[] = {
2883 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2884 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2885 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2886 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2887 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
2888 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2889 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2890 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2891 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2892 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
2895 static struct of_regulator_match ab8505_regulator_match[] = {
2896 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2897 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2898 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2899 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2900 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2901 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2902 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2903 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2904 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2905 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2906 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2907 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2908 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2911 static struct of_regulator_match ab8540_regulator_match[] = {
2912 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2913 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2914 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2915 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
2916 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2917 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
2918 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2919 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2920 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2921 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2922 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2923 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2924 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2925 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2928 static struct of_regulator_match ab9540_regulator_match[] = {
2929 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2930 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2931 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2932 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2933 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2934 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2935 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2936 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2937 { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2938 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2939 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2943 struct ab8500_regulator_info *info;
2945 struct ab8500_reg_init *init;
2947 struct of_regulator_match *match;
2951 static void abx500_get_regulator_info(struct ab8500 *ab8500)
2953 if (is_ab9540(ab8500)) {
2954 abx500_regulator.info = ab9540_regulator_info;
2955 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2956 abx500_regulator.init = ab9540_reg_init;
2957 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2958 abx500_regulator.match = ab9540_regulator_match;
2959 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2960 } else if (is_ab8505(ab8500)) {
2961 abx500_regulator.info = ab8505_regulator_info;
2962 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2963 abx500_regulator.init = ab8505_reg_init;
2964 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2965 abx500_regulator.match = ab8505_regulator_match;
2966 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2967 } else if (is_ab8540(ab8500)) {
2968 abx500_regulator.info = ab8540_regulator_info;
2969 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2970 abx500_regulator.init = ab8540_reg_init;
2971 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2972 abx500_regulator.match = ab8540_regulator_match;
2973 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
2975 abx500_regulator.info = ab8500_regulator_info;
2976 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
2977 abx500_regulator.init = ab8500_reg_init;
2978 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
2979 abx500_regulator.match = ab8500_regulator_match;
2980 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
2984 static int ab8500_regulator_register(struct platform_device *pdev,
2985 struct regulator_init_data *init_data,
2986 int id, struct device_node *np)
2988 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2989 struct ab8500_regulator_info *info = NULL;
2990 struct regulator_config config = { };
2992 /* assign per-regulator data */
2993 info = &abx500_regulator.info[id];
2994 info->dev = &pdev->dev;
2996 config.dev = &pdev->dev;
2997 config.init_data = init_data;
2998 config.driver_data = info;
2999 config.of_node = np;
3001 /* fix for hardware before ab8500v2.0 */
3002 if (is_ab8500_1p1_or_earlier(ab8500)) {
3003 if (info->desc.id == AB8500_LDO_AUX3) {
3004 info->desc.n_voltages =
3005 ARRAY_SIZE(ldo_vauxn_voltages);
3006 info->desc.volt_table = ldo_vauxn_voltages;
3007 info->voltage_mask = 0xf;
3011 /* register regulator with framework */
3012 info->regulator = devm_regulator_register(&pdev->dev, &info->desc,
3014 if (IS_ERR(info->regulator)) {
3015 dev_err(&pdev->dev, "failed to register regulator %s\n",
3017 return PTR_ERR(info->regulator);
3023 static int ab8500_regulator_probe(struct platform_device *pdev)
3025 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3026 struct device_node *np = pdev->dev.of_node;
3027 struct of_regulator_match *match;
3031 dev_err(&pdev->dev, "null mfd parent\n");
3035 abx500_get_regulator_info(ab8500);
3037 err = of_regulator_match(&pdev->dev, np,
3038 abx500_regulator.match,
3039 abx500_regulator.match_size);
3042 "Error parsing regulator init data: %d\n", err);
3046 match = abx500_regulator.match;
3047 for (i = 0; i < abx500_regulator.info_size; i++) {
3048 err = ab8500_regulator_register(pdev, match[i].init_data, i,
3057 static struct platform_driver ab8500_regulator_driver = {
3058 .probe = ab8500_regulator_probe,
3060 .name = "ab8500-regulator",
3064 static int __init ab8500_regulator_init(void)
3068 ret = platform_driver_register(&ab8500_regulator_driver);
3070 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3074 subsys_initcall(ab8500_regulator_init);
3076 static void __exit ab8500_regulator_exit(void)
3078 platform_driver_unregister(&ab8500_regulator_driver);
3080 module_exit(ab8500_regulator_exit);
3082 MODULE_LICENSE("GPL v2");
3083 MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
3084 MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
3085 MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
3086 MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3087 MODULE_ALIAS("platform:ab8500-regulator");