4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pwm.h>
25 #include <linux/err.h>
26 #include <linux/clk.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/of_device.h>
30 /* EHRPWM registers and bits definitions */
32 /* Time base module registers */
36 #define TBCTL_RUN_MASK (BIT(15) | BIT(14))
37 #define TBCTL_STOP_NEXT 0
38 #define TBCTL_STOP_ON_CYCLE BIT(14)
39 #define TBCTL_FREE_RUN (BIT(15) | BIT(14))
40 #define TBCTL_PRDLD_MASK BIT(3)
41 #define TBCTL_PRDLD_SHDW 0
42 #define TBCTL_PRDLD_IMDT BIT(3)
43 #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
45 #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
46 #define TBCTL_CTRMODE_UP 0
47 #define TBCTL_CTRMODE_DOWN BIT(0)
48 #define TBCTL_CTRMODE_UPDOWN BIT(1)
49 #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
51 #define TBCTL_HSPCLKDIV_SHIFT 7
52 #define TBCTL_CLKDIV_SHIFT 10
55 #define HSPCLKDIV_MAX 7
56 #define PERIOD_MAX 0xFFFF
58 /* compare module registers */
62 /* Action qualifier module registers */
68 #define AQCTL_CBU_MASK (BIT(9) | BIT(8))
69 #define AQCTL_CBU_FRCLOW BIT(8)
70 #define AQCTL_CBU_FRCHIGH BIT(9)
71 #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
72 #define AQCTL_CAU_MASK (BIT(5) | BIT(4))
73 #define AQCTL_CAU_FRCLOW BIT(4)
74 #define AQCTL_CAU_FRCHIGH BIT(5)
75 #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
76 #define AQCTL_PRD_MASK (BIT(3) | BIT(2))
77 #define AQCTL_PRD_FRCLOW BIT(2)
78 #define AQCTL_PRD_FRCHIGH BIT(3)
79 #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
80 #define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
81 #define AQCTL_ZRO_FRCLOW BIT(0)
82 #define AQCTL_ZRO_FRCHIGH BIT(1)
83 #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
85 #define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
87 #define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
89 #define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
91 #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
94 #define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
95 #define AQSFRC_RLDCSF_ZRO 0
96 #define AQSFRC_RLDCSF_PRD BIT(6)
97 #define AQSFRC_RLDCSF_ZROPRD BIT(7)
98 #define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
100 #define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
101 #define AQCSFRC_CSFB_FRCDIS 0
102 #define AQCSFRC_CSFB_FRCLOW BIT(2)
103 #define AQCSFRC_CSFB_FRCHIGH BIT(3)
104 #define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
105 #define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
106 #define AQCSFRC_CSFA_FRCDIS 0
107 #define AQCSFRC_CSFA_FRCLOW BIT(0)
108 #define AQCSFRC_CSFA_FRCHIGH BIT(1)
109 #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
111 #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
113 struct ehrpwm_context {
124 struct ehrpwm_pwm_chip {
125 struct pwm_chip chip;
126 unsigned int clk_rate;
127 void __iomem *mmio_base;
128 unsigned long period_cycles[NUM_PWM_CHANNEL];
129 enum pwm_polarity polarity[NUM_PWM_CHANNEL];
131 struct ehrpwm_context ctx;
134 static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
136 return container_of(chip, struct ehrpwm_pwm_chip, chip);
139 static inline u16 ehrpwm_read(void __iomem *base, int offset)
141 return readw(base + offset);
144 static inline void ehrpwm_write(void __iomem *base, int offset, unsigned int val)
146 writew(val & 0xFFFF, base + offset);
149 static void ehrpwm_modify(void __iomem *base, int offset,
150 unsigned short mask, unsigned short val)
152 unsigned short regval;
154 regval = readw(base + offset);
156 regval |= val & mask;
157 writew(regval, base + offset);
161 * set_prescale_div - Set up the prescaler divider function
162 * @rqst_prescaler: prescaler value min
163 * @prescale_div: prescaler value set
164 * @tb_clk_div: Time Base Control prescaler bits
166 static int set_prescale_div(unsigned long rqst_prescaler,
167 unsigned short *prescale_div, unsigned short *tb_clk_div)
169 unsigned int clkdiv, hspclkdiv;
171 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
172 for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
175 * calculations for prescaler value :
176 * prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
177 * HSPCLKDIVIDER = 2 ** hspclkdiv
178 * CLKDIVIDER = (1), if clkdiv == 0 *OR*
179 * (2 * clkdiv), if clkdiv != 0
181 * Configure prescale_div value such that period
182 * register value is less than 65535.
185 *prescale_div = (1 << clkdiv) *
186 (hspclkdiv ? (hspclkdiv * 2) : 1);
187 if (*prescale_div > rqst_prescaler) {
188 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
189 (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
197 static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
200 unsigned short aqctl_val, aqctl_mask;
203 * Configure PWM output to HIGH/LOW level on counter
204 * reaches compare register value and LOW/HIGH level
205 * on counter value reaches period register value and
206 * zero value on counter
210 aqctl_mask = AQCTL_CBU_MASK;
212 if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
213 aqctl_val = AQCTL_CHANB_POLINVERSED;
215 aqctl_val = AQCTL_CHANB_POLNORMAL;
218 aqctl_mask = AQCTL_CAU_MASK;
220 if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
221 aqctl_val = AQCTL_CHANA_POLINVERSED;
223 aqctl_val = AQCTL_CHANA_POLNORMAL;
226 aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
227 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
231 * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
232 * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
234 static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
235 int duty_ns, int period_ns)
237 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
238 unsigned long long c;
239 unsigned long period_cycles, duty_cycles;
240 unsigned short ps_divval, tb_divval;
243 if (period_ns > NSEC_PER_SEC)
248 do_div(c, NSEC_PER_SEC);
249 period_cycles = (unsigned long)c;
251 if (period_cycles < 1) {
257 do_div(c, NSEC_PER_SEC);
258 duty_cycles = (unsigned long)c;
262 * Period values should be same for multiple PWM channels as IP uses
263 * same period register for multiple channels.
265 for (i = 0; i < NUM_PWM_CHANNEL; i++) {
266 if (pc->period_cycles[i] &&
267 (pc->period_cycles[i] != period_cycles)) {
269 * Allow channel to reconfigure period if no other
270 * channels being configured.
275 dev_err(chip->dev, "Period value conflicts with channel %d\n",
281 pc->period_cycles[pwm->hwpwm] = period_cycles;
283 /* Configure clock prescaler to support Low frequency PWM wave */
284 if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
286 dev_err(chip->dev, "Unsupported values\n");
290 pm_runtime_get_sync(chip->dev);
292 /* Update clock prescaler values */
293 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
295 /* Update period & duty cycle with presacler division */
296 period_cycles = period_cycles / ps_divval;
297 duty_cycles = duty_cycles / ps_divval;
299 /* Configure shadow loading on Period register */
300 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
302 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
304 /* Configure ehrpwm counter for up-count mode */
305 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
309 /* Channel 1 configured with compare B register */
312 /* Channel 0 configured with compare A register */
315 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
317 pm_runtime_put_sync(chip->dev);
321 static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
322 struct pwm_device *pwm, enum pwm_polarity polarity)
324 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
326 /* Configuration of polarity in hardware delayed, do at enable */
327 pc->polarity[pwm->hwpwm] = polarity;
331 static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
333 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
334 unsigned short aqcsfrc_val, aqcsfrc_mask;
337 /* Leave clock enabled on enabling PWM */
338 pm_runtime_get_sync(chip->dev);
340 /* Disabling Action Qualifier on PWM output */
342 aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
343 aqcsfrc_mask = AQCSFRC_CSFB_MASK;
345 aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
346 aqcsfrc_mask = AQCSFRC_CSFA_MASK;
349 /* Changes to shadow mode */
350 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
353 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
355 /* Channels polarity can be configured from action qualifier module */
356 configure_polarity(pc, pwm->hwpwm);
358 /* Enable TBCLK before enabling PWM device */
359 ret = clk_enable(pc->tbclk);
361 dev_err(chip->dev, "Failed to enable TBCLK for %s\n",
362 dev_name(pc->chip.dev));
366 /* Enable time counter for free_run */
367 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN);
371 static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
373 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
374 unsigned short aqcsfrc_val, aqcsfrc_mask;
376 /* Action Qualifier puts PWM output low forcefully */
378 aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
379 aqcsfrc_mask = AQCSFRC_CSFB_MASK;
381 aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
382 aqcsfrc_mask = AQCSFRC_CSFA_MASK;
385 /* Update shadow register first before modifying active register */
386 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
388 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
390 * Changes to immediate action on Action Qualifier. This puts
391 * Action Qualifier control on PWM output from next TBCLK
393 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
396 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
398 /* Disabling TBCLK on PWM disable */
399 clk_disable(pc->tbclk);
401 /* Stop Time base counter */
402 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT);
404 /* Disable clock on PWM disable */
405 pm_runtime_put_sync(chip->dev);
408 static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
410 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
412 if (pwm_is_enabled(pwm)) {
413 dev_warn(chip->dev, "Removing PWM device without disabling\n");
414 pm_runtime_put_sync(chip->dev);
417 /* set period value to zero on free */
418 pc->period_cycles[pwm->hwpwm] = 0;
421 static const struct pwm_ops ehrpwm_pwm_ops = {
422 .free = ehrpwm_pwm_free,
423 .config = ehrpwm_pwm_config,
424 .set_polarity = ehrpwm_pwm_set_polarity,
425 .enable = ehrpwm_pwm_enable,
426 .disable = ehrpwm_pwm_disable,
427 .owner = THIS_MODULE,
430 static const struct of_device_id ehrpwm_of_match[] = {
431 { .compatible = "ti,am3352-ehrpwm" },
432 { .compatible = "ti,am33xx-ehrpwm" },
435 MODULE_DEVICE_TABLE(of, ehrpwm_of_match);
437 static int ehrpwm_pwm_probe(struct platform_device *pdev)
439 struct device_node *np = pdev->dev.of_node;
443 struct ehrpwm_pwm_chip *pc;
445 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
449 clk = devm_clk_get(&pdev->dev, "fck");
451 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
452 dev_warn(&pdev->dev, "Binding is obsolete.\n");
453 clk = devm_clk_get(pdev->dev.parent, "fck");
458 dev_err(&pdev->dev, "failed to get clock\n");
462 pc->clk_rate = clk_get_rate(clk);
464 dev_err(&pdev->dev, "failed to get clock rate\n");
468 pc->chip.dev = &pdev->dev;
469 pc->chip.ops = &ehrpwm_pwm_ops;
470 pc->chip.of_xlate = of_pwm_xlate_with_flags;
471 pc->chip.of_pwm_n_cells = 3;
473 pc->chip.npwm = NUM_PWM_CHANNEL;
475 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
476 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
477 if (IS_ERR(pc->mmio_base))
478 return PTR_ERR(pc->mmio_base);
480 /* Acquire tbclk for Time Base EHRPWM submodule */
481 pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
482 if (IS_ERR(pc->tbclk)) {
483 dev_err(&pdev->dev, "Failed to get tbclk\n");
484 return PTR_ERR(pc->tbclk);
487 ret = clk_prepare(pc->tbclk);
489 dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);
493 ret = pwmchip_add(&pc->chip);
495 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
499 pm_runtime_enable(&pdev->dev);
501 platform_set_drvdata(pdev, pc);
505 static int ehrpwm_pwm_remove(struct platform_device *pdev)
507 struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
509 clk_unprepare(pc->tbclk);
511 pm_runtime_put_sync(&pdev->dev);
512 pm_runtime_disable(&pdev->dev);
513 return pwmchip_remove(&pc->chip);
516 #ifdef CONFIG_PM_SLEEP
517 static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
519 pm_runtime_get_sync(pc->chip.dev);
520 pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
521 pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
522 pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
523 pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
524 pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
525 pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
526 pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
527 pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
528 pm_runtime_put_sync(pc->chip.dev);
531 static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
533 ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
534 ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
535 ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
536 ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
537 ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
538 ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
539 ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
540 ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
543 static int ehrpwm_pwm_suspend(struct device *dev)
545 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
548 ehrpwm_pwm_save_context(pc);
549 for (i = 0; i < pc->chip.npwm; i++) {
550 struct pwm_device *pwm = &pc->chip.pwms[i];
552 if (!pwm_is_enabled(pwm))
555 /* Disable explicitly if PWM is running */
556 pm_runtime_put_sync(dev);
561 static int ehrpwm_pwm_resume(struct device *dev)
563 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
566 for (i = 0; i < pc->chip.npwm; i++) {
567 struct pwm_device *pwm = &pc->chip.pwms[i];
569 if (!pwm_is_enabled(pwm))
572 /* Enable explicitly if PWM was running */
573 pm_runtime_get_sync(dev);
575 ehrpwm_pwm_restore_context(pc);
580 static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend,
583 static struct platform_driver ehrpwm_pwm_driver = {
586 .of_match_table = ehrpwm_of_match,
587 .pm = &ehrpwm_pwm_pm_ops,
589 .probe = ehrpwm_pwm_probe,
590 .remove = ehrpwm_pwm_remove,
593 module_platform_driver(ehrpwm_pwm_driver);
595 MODULE_DESCRIPTION("EHRPWM PWM driver");
596 MODULE_AUTHOR("Texas Instruments");
597 MODULE_LICENSE("GPL");