drivers/pwm/pwm-sifive.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2018 SiFive
   4  * For SiFive's PWM IP block documentation please refer Chapter 14 of
   5  * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
   6  *
   7  * Limitations:
   8  * - When changing both duty cycle and period, we cannot prevent in
   9  *   software that the output might produce a period with mixed
  10  *   settings (new period length and old duty cycle).
  11  * - The hardware cannot generate a 100% duty cycle.
  12  * - The hardware generates only inverted output.
  13  */
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/slab.h>
  20 #include <linux/bitfield.h>
  21
  22 /* Register offsets */
  23 #define PWM_SIFIVE_PWMCFG               0x0
  24 #define PWM_SIFIVE_PWMCOUNT             0x8
  25 #define PWM_SIFIVE_PWMS                 0x10
  26 #define PWM_SIFIVE_PWMCMP(i)            (0x20 + 4 * (i))
  27
  28 /* PWMCFG fields */
  29 #define PWM_SIFIVE_PWMCFG_SCALE         GENMASK(3, 0)
  30 #define PWM_SIFIVE_PWMCFG_STICKY        BIT(8)
  31 #define PWM_SIFIVE_PWMCFG_ZERO_CMP      BIT(9)
  32 #define PWM_SIFIVE_PWMCFG_DEGLITCH      BIT(10)
  33 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS     BIT(12)
  34 #define PWM_SIFIVE_PWMCFG_EN_ONCE       BIT(13)
  35 #define PWM_SIFIVE_PWMCFG_CENTER        BIT(16)
  36 #define PWM_SIFIVE_PWMCFG_GANG          BIT(24)
  37 #define PWM_SIFIVE_PWMCFG_IP            BIT(28)
  38
  39 #define PWM_SIFIVE_CMPWIDTH             16
  40 #define PWM_SIFIVE_DEFAULT_PERIOD       10000000
  41
  42 struct pwm_sifive_ddata {
  43         struct pwm_chip chip;
  44         struct mutex lock; /* lock to protect user_count */
  45         struct notifier_block notifier;
  46         struct clk *clk;
  47         void __iomem *regs;
  48         unsigned int real_period;
  49         unsigned int approx_period;
  50         int user_count;
  51 };
  52
  53 static inline
  54 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
  55 {
  56         return container_of(c, struct pwm_sifive_ddata, chip);
  57 }
  58
  59 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
  60 {
  61         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  62
  63         mutex_lock(&ddata->lock);
  64         ddata->user_count++;
  65         mutex_unlock(&ddata->lock);
  66
  67         return 0;
  68 }
  69
  70 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
  71 {
  72         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  73
  74         mutex_lock(&ddata->lock);
  75         ddata->user_count--;
  76         mutex_unlock(&ddata->lock);
  77 }
  78
  79 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
  80                                     unsigned long rate)
  81 {
  82         unsigned long long num;
  83         unsigned long scale_pow;
  84         int scale;
  85         u32 val;
  86         /*
  87          * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
  88          * period length is using pwmscale which provides the number of bits the
  89          * counter is shifted before being feed to the comparators. A period
  90          * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
  91          * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
  92          */
  93         scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
  94         scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
  95
  96         val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
  97               FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
  98         writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
  99
 100         /* As scale <= 15 the shift operation cannot overflow. */
 101         num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
 102         ddata->real_period = div64_ul(num, rate);
 103         dev_dbg(ddata->chip.dev,
 104                 "New real_period = %u ns\n", ddata->real_period);
 105 }
 106
 107 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 108                                  struct pwm_state *state)
 109 {
 110         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 111         u32 duty, val;
 112
 113         duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
 114
 115         state->enabled = duty > 0;
 116
 117         val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
 118         if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
 119                 state->enabled = false;
 120
 121         state->period = ddata->real_period;
 122         state->duty_cycle =
 123                 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
 124         state->polarity = PWM_POLARITY_INVERSED;
 125 }
 126
 127 static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
 128 {
 129         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 130         int ret;
 131
 132         if (enable) {
 133                 ret = clk_enable(ddata->clk);
 134                 if (ret) {
 135                         dev_err(ddata->chip.dev, "Enable clk failed\n");
 136                         return ret;
 137                 }
 138         }
 139
 140         if (!enable)
 141                 clk_disable(ddata->clk);
 142
 143         return 0;
 144 }
 145
 146 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 147                             const struct pwm_state *state)
 148 {
 149         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 150         struct pwm_state cur_state;
 151         unsigned int duty_cycle;
 152         unsigned long long num;
 153         bool enabled;
 154         int ret = 0;
 155         u32 frac;
 156
 157         if (state->polarity != PWM_POLARITY_INVERSED)
 158                 return -EINVAL;
 159
 160         ret = clk_enable(ddata->clk);
 161         if (ret) {
 162                 dev_err(ddata->chip.dev, "Enable clk failed\n");
 163                 return ret;
 164         }
 165
 166         mutex_lock(&ddata->lock);
 167         cur_state = pwm->state;
 168         enabled = cur_state.enabled;
 169
 170         duty_cycle = state->duty_cycle;
 171         if (!state->enabled)
 172                 duty_cycle = 0;
 173
 174         /*
 175          * The problem of output producing mixed setting as mentioned at top,
 176          * occurs here. To minimize the window for this problem, we are
 177          * calculating the register values first and then writing them
 178          * consecutively
 179          */
 180         num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
 181         frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
 182         /* The hardware cannot generate a 100% duty cycle */
 183         frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
 184
 185         if (state->period != ddata->approx_period) {
 186                 if (ddata->user_count != 1) {
 187                         ret = -EBUSY;
 188                         goto exit;
 189                 }
 190                 ddata->approx_period = state->period;
 191                 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
 192         }
 193
 194         writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
 195
 196         if (state->enabled != enabled)
 197                 pwm_sifive_enable(chip, state->enabled);
 198
 199 exit:
 200         clk_disable(ddata->clk);
 201         mutex_unlock(&ddata->lock);
 202         return ret;
 203 }
 204
 205 static const struct pwm_ops pwm_sifive_ops = {
 206         .request = pwm_sifive_request,
 207         .free = pwm_sifive_free,
 208         .get_state = pwm_sifive_get_state,
 209         .apply = pwm_sifive_apply,
 210         .owner = THIS_MODULE,
 211 };
 212
 213 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
 214                                      unsigned long event, void *data)
 215 {
 216         struct clk_notifier_data *ndata = data;
 217         struct pwm_sifive_ddata *ddata =
 218                 container_of(nb, struct pwm_sifive_ddata, notifier);
 219
 220         if (event == POST_RATE_CHANGE)
 221                 pwm_sifive_update_clock(ddata, ndata->new_rate);
 222
 223         return NOTIFY_OK;
 224 }
 225
 226 static int pwm_sifive_probe(struct platform_device *pdev)
 227 {
 228         struct device *dev = &pdev->dev;
 229         struct pwm_sifive_ddata *ddata;
 230         struct pwm_chip *chip;
 231         struct resource *res;
 232         int ret;
 233         u32 val;
 234         unsigned int enabled_pwms = 0, enabled_clks = 1;
 235
 236         ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 237         if (!ddata)
 238                 return -ENOMEM;
 239
 240         mutex_init(&ddata->lock);
 241         chip = &ddata->chip;
 242         chip->dev = dev;
 243         chip->ops = &pwm_sifive_ops;
 244         chip->of_xlate = of_pwm_xlate_with_flags;
 245         chip->of_pwm_n_cells = 3;
 246         chip->base = -1;
 247         chip->npwm = 4;
 248
 249         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 250         ddata->regs = devm_ioremap_resource(dev, res);
 251         if (IS_ERR(ddata->regs))
 252                 return PTR_ERR(ddata->regs);
 253
 254         ddata->clk = devm_clk_get(dev, NULL);
 255         if (IS_ERR(ddata->clk))
 256                 return dev_err_probe(dev, PTR_ERR(ddata->clk),
 257                                      "Unable to find controller clock\n");
 258
 259         ret = clk_prepare_enable(ddata->clk);
 260         if (ret) {
 261                 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
 262                 return ret;
 263         }
 264
 265         val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
 266         if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
 267                 unsigned int i;
 268
 269                 for (i = 0; i < chip->npwm; ++i) {
 270                         val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
 271                         if (val > 0)
 272                                 ++enabled_pwms;
 273                 }
 274         }
 275
 276         /* The clk should be on once for each running PWM. */
 277         if (enabled_pwms) {
 278                 while (enabled_clks < enabled_pwms) {
 279                         /* This is not expected to fail as the clk is already on */
 280                         ret = clk_enable(ddata->clk);
 281                         if (unlikely(ret)) {
 282                                 dev_err_probe(dev, ret, "Failed to enable clk\n");
 283                                 goto disable_clk;
 284                         }
 285                         ++enabled_clks;
 286                 }
 287         } else {
 288                 clk_disable(ddata->clk);
 289                 enabled_clks = 0;
 290         }
 291
 292         /* Watch for changes to underlying clock frequency */
 293         ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
 294         ret = clk_notifier_register(ddata->clk, &ddata->notifier);
 295         if (ret) {
 296                 dev_err(dev, "failed to register clock notifier: %d\n", ret);
 297                 goto disable_clk;
 298         }
 299
 300         ret = pwmchip_add(chip);
 301         if (ret < 0) {
 302                 dev_err(dev, "cannot register PWM: %d\n", ret);
 303                 goto unregister_clk;
 304         }
 305
 306         platform_set_drvdata(pdev, ddata);
 307         dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
 308
 309         return 0;
 310
 311 unregister_clk:
 312         clk_notifier_unregister(ddata->clk, &ddata->notifier);
 313 disable_clk:
 314         while (enabled_clks) {
 315                 clk_disable(ddata->clk);
 316                 --enabled_clks;
 317         }
 318         clk_unprepare(ddata->clk);
 319
 320         return ret;
 321 }
 322
 323 static int pwm_sifive_remove(struct platform_device *dev)
 324 {
 325         struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
 326         struct pwm_device *pwm;
 327         int ch;
 328
 329         pwmchip_remove(&ddata->chip);
 330         clk_notifier_unregister(ddata->clk, &ddata->notifier);
 331
 332         for (ch = 0; ch < ddata->chip.npwm; ch++) {
 333                 pwm = &ddata->chip.pwms[ch];
 334                 if (pwm->state.enabled)
 335                         clk_disable(ddata->clk);
 336         }
 337
 338         clk_unprepare(ddata->clk);
 339
 340         return 0;
 341 }
 342
 343 static const struct of_device_id pwm_sifive_of_match[] = {
 344         { .compatible = "sifive,pwm0" },
 345         {},
 346 };
 347 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
 348
 349 static struct platform_driver pwm_sifive_driver = {
 350         .probe = pwm_sifive_probe,
 351         .remove = pwm_sifive_remove,
 352         .driver = {
 353                 .name = "pwm-sifive",
 354                 .of_match_table = pwm_sifive_of_match,
 355         },
 356 };
 357 module_platform_driver(pwm_sifive_driver);
 358
 359 MODULE_DESCRIPTION("SiFive PWM driver");
 360 MODULE_LICENSE("GPL v2");