1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
14 #include <linux/clk.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 #include <linux/bitfield.h>
22 /* Register offsets */
23 #define PWM_SIFIVE_PWMCFG 0x0
24 #define PWM_SIFIVE_PWMCOUNT 0x8
25 #define PWM_SIFIVE_PWMS 0x10
26 #define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i))
29 #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
30 #define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
31 #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
32 #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
33 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
34 #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
35 #define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
36 #define PWM_SIFIVE_PWMCFG_GANG BIT(24)
37 #define PWM_SIFIVE_PWMCFG_IP BIT(28)
39 #define PWM_SIFIVE_CMPWIDTH 16
40 #define PWM_SIFIVE_DEFAULT_PERIOD 10000000
42 struct pwm_sifive_ddata {
44 struct mutex lock; /* lock to protect user_count and approx_period */
45 struct notifier_block notifier;
48 unsigned int real_period;
49 unsigned int approx_period;
54 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
56 return container_of(c, struct pwm_sifive_ddata, chip);
59 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
61 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
63 mutex_lock(&ddata->lock);
65 mutex_unlock(&ddata->lock);
70 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
72 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
74 mutex_lock(&ddata->lock);
76 mutex_unlock(&ddata->lock);
79 /* Called holding ddata->lock */
80 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
83 unsigned long long num;
84 unsigned long scale_pow;
88 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
89 * period length is using pwmscale which provides the number of bits the
90 * counter is shifted before being feed to the comparators. A period
91 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
92 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
94 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
95 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
97 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
98 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
99 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
101 /* As scale <= 15 the shift operation cannot overflow. */
102 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
103 ddata->real_period = div64_ul(num, rate);
104 dev_dbg(ddata->chip.dev,
105 "New real_period = %u ns\n", ddata->real_period);
108 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
109 struct pwm_state *state)
111 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
114 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
116 state->enabled = duty > 0;
118 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
119 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
120 state->enabled = false;
122 state->period = ddata->real_period;
124 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
125 state->polarity = PWM_POLARITY_INVERSED;
128 static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
130 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
134 ret = clk_enable(ddata->clk);
136 dev_err(ddata->chip.dev, "Enable clk failed\n");
142 clk_disable(ddata->clk);
147 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
148 const struct pwm_state *state)
150 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
151 struct pwm_state cur_state;
152 unsigned int duty_cycle;
153 unsigned long long num;
158 if (state->polarity != PWM_POLARITY_INVERSED)
161 ret = clk_enable(ddata->clk);
163 dev_err(ddata->chip.dev, "Enable clk failed\n");
167 cur_state = pwm->state;
168 enabled = cur_state.enabled;
170 duty_cycle = state->duty_cycle;
175 * The problem of output producing mixed setting as mentioned at top,
176 * occurs here. To minimize the window for this problem, we are
177 * calculating the register values first and then writing them
180 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
181 frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
182 /* The hardware cannot generate a 100% duty cycle */
183 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
185 mutex_lock(&ddata->lock);
186 if (state->period != ddata->approx_period) {
188 * Don't let a 2nd user change the period underneath the 1st user.
189 * However if ddate->approx_period == 0 this is the first time we set
190 * any period, so let whoever gets here first set the period so other
191 * users who agree on the period won't fail.
193 if (ddata->user_count != 1 && ddata->approx_period) {
194 mutex_unlock(&ddata->lock);
198 ddata->approx_period = state->period;
199 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
201 mutex_unlock(&ddata->lock);
203 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
205 if (state->enabled != enabled)
206 pwm_sifive_enable(chip, state->enabled);
209 clk_disable(ddata->clk);
213 static const struct pwm_ops pwm_sifive_ops = {
214 .request = pwm_sifive_request,
215 .free = pwm_sifive_free,
216 .get_state = pwm_sifive_get_state,
217 .apply = pwm_sifive_apply,
218 .owner = THIS_MODULE,
221 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
222 unsigned long event, void *data)
224 struct clk_notifier_data *ndata = data;
225 struct pwm_sifive_ddata *ddata =
226 container_of(nb, struct pwm_sifive_ddata, notifier);
228 if (event == POST_RATE_CHANGE) {
229 mutex_lock(&ddata->lock);
230 pwm_sifive_update_clock(ddata, ndata->new_rate);
231 mutex_unlock(&ddata->lock);
237 static int pwm_sifive_probe(struct platform_device *pdev)
239 struct device *dev = &pdev->dev;
240 struct pwm_sifive_ddata *ddata;
241 struct pwm_chip *chip;
242 struct resource *res;
245 unsigned int enabled_pwms = 0, enabled_clks = 1;
247 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
251 mutex_init(&ddata->lock);
254 chip->ops = &pwm_sifive_ops;
255 chip->of_xlate = of_pwm_xlate_with_flags;
256 chip->of_pwm_n_cells = 3;
260 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 ddata->regs = devm_ioremap_resource(dev, res);
262 if (IS_ERR(ddata->regs))
263 return PTR_ERR(ddata->regs);
265 ddata->clk = devm_clk_get(dev, NULL);
266 if (IS_ERR(ddata->clk))
267 return dev_err_probe(dev, PTR_ERR(ddata->clk),
268 "Unable to find controller clock\n");
270 ret = clk_prepare_enable(ddata->clk);
272 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
276 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
277 if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
280 for (i = 0; i < chip->npwm; ++i) {
281 val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
287 /* The clk should be on once for each running PWM. */
289 while (enabled_clks < enabled_pwms) {
290 /* This is not expected to fail as the clk is already on */
291 ret = clk_enable(ddata->clk);
293 dev_err_probe(dev, ret, "Failed to enable clk\n");
299 clk_disable(ddata->clk);
303 /* Watch for changes to underlying clock frequency */
304 ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
305 ret = clk_notifier_register(ddata->clk, &ddata->notifier);
307 dev_err(dev, "failed to register clock notifier: %d\n", ret);
311 ret = pwmchip_add(chip);
313 dev_err(dev, "cannot register PWM: %d\n", ret);
317 platform_set_drvdata(pdev, ddata);
318 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
323 clk_notifier_unregister(ddata->clk, &ddata->notifier);
325 while (enabled_clks) {
326 clk_disable(ddata->clk);
329 clk_unprepare(ddata->clk);
334 static int pwm_sifive_remove(struct platform_device *dev)
336 struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
337 struct pwm_device *pwm;
340 pwmchip_remove(&ddata->chip);
341 clk_notifier_unregister(ddata->clk, &ddata->notifier);
343 for (ch = 0; ch < ddata->chip.npwm; ch++) {
344 pwm = &ddata->chip.pwms[ch];
345 if (pwm->state.enabled)
346 clk_disable(ddata->clk);
349 clk_unprepare(ddata->clk);
354 static const struct of_device_id pwm_sifive_of_match[] = {
355 { .compatible = "sifive,pwm0" },
358 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
360 static struct platform_driver pwm_sifive_driver = {
361 .probe = pwm_sifive_probe,
362 .remove = pwm_sifive_remove,
364 .name = "pwm-sifive",
365 .of_match_table = pwm_sifive_of_match,
368 module_platform_driver(pwm_sifive_driver);
370 MODULE_DESCRIPTION("SiFive PWM driver");
371 MODULE_LICENSE("GPL v2");