1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
5 * Copyright (C) 2012 Renesas Solutions Corp.
11 #include <linux/init.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
22 #define TPU_CHANNEL_MAX 4
24 #define TPU_TSTR 0x00 /* Timer start register (shared) */
26 #define TPU_TCRn 0x00 /* Timer control register */
27 #define TPU_TCR_CCLR_NONE (0 << 5)
28 #define TPU_TCR_CCLR_TGRA (1 << 5)
29 #define TPU_TCR_CCLR_TGRB (2 << 5)
30 #define TPU_TCR_CCLR_TGRC (5 << 5)
31 #define TPU_TCR_CCLR_TGRD (6 << 5)
32 #define TPU_TCR_CKEG_RISING (0 << 3)
33 #define TPU_TCR_CKEG_FALLING (1 << 3)
34 #define TPU_TCR_CKEG_BOTH (2 << 3)
35 #define TPU_TMDRn 0x04 /* Timer mode register */
36 #define TPU_TMDR_BFWT (1 << 6)
37 #define TPU_TMDR_BFB (1 << 5)
38 #define TPU_TMDR_BFA (1 << 4)
39 #define TPU_TMDR_MD_NORMAL (0 << 0)
40 #define TPU_TMDR_MD_PWM (2 << 0)
41 #define TPU_TIORn 0x08 /* Timer I/O control register */
42 #define TPU_TIOR_IOA_0 (0 << 0)
43 #define TPU_TIOR_IOA_0_CLR (1 << 0)
44 #define TPU_TIOR_IOA_0_SET (2 << 0)
45 #define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
46 #define TPU_TIOR_IOA_1 (4 << 0)
47 #define TPU_TIOR_IOA_1_CLR (5 << 0)
48 #define TPU_TIOR_IOA_1_SET (6 << 0)
49 #define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
50 #define TPU_TIERn 0x0c /* Timer interrupt enable register */
51 #define TPU_TSRn 0x10 /* Timer status register */
52 #define TPU_TCNTn 0x14 /* Timer counter */
53 #define TPU_TGRAn 0x18 /* Timer general register A */
54 #define TPU_TGRBn 0x1c /* Timer general register B */
55 #define TPU_TGRCn 0x20 /* Timer general register C */
56 #define TPU_TGRDn 0x24 /* Timer general register D */
58 #define TPU_CHANNEL_OFFSET 0x10
59 #define TPU_CHANNEL_SIZE 0x40
62 TPU_PIN_INACTIVE, /* Pin is driven inactive */
63 TPU_PIN_PWM, /* Pin is driven by PWM */
64 TPU_PIN_ACTIVE, /* Pin is driven active */
69 struct tpu_pwm_device {
70 bool timer_on; /* Whether the timer is running */
72 struct tpu_device *tpu;
73 unsigned int channel; /* Channel number in the TPU */
75 enum pwm_polarity polarity;
76 unsigned int prescaler;
82 struct platform_device *pdev;
88 struct tpu_pwm_device tpd[TPU_CHANNEL_MAX];
91 #define to_tpu_device(c) container_of(c, struct tpu_device, chip)
93 static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
95 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
96 + tpd->channel * TPU_CHANNEL_SIZE;
98 iowrite16(value, base + reg_nr);
101 static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
102 enum tpu_pin_state state)
104 static const char * const states[] = { "inactive", "PWM", "active" };
106 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
107 tpd->channel, states[state]);
110 case TPU_PIN_INACTIVE:
111 tpu_pwm_write(tpd, TPU_TIORn,
112 tpd->polarity == PWM_POLARITY_INVERSED ?
113 TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
116 tpu_pwm_write(tpd, TPU_TIORn,
117 tpd->polarity == PWM_POLARITY_INVERSED ?
118 TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
121 tpu_pwm_write(tpd, TPU_TIORn,
122 tpd->polarity == PWM_POLARITY_INVERSED ?
123 TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
128 static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
133 spin_lock_irqsave(&tpd->tpu->lock, flags);
134 value = ioread16(tpd->tpu->base + TPU_TSTR);
137 value |= 1 << tpd->channel;
139 value &= ~(1 << tpd->channel);
141 iowrite16(value, tpd->tpu->base + TPU_TSTR);
142 spin_unlock_irqrestore(&tpd->tpu->lock, flags);
145 static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
149 if (!tpd->timer_on) {
150 /* Wake up device and enable clock. */
151 pm_runtime_get_sync(&tpd->tpu->pdev->dev);
152 ret = clk_prepare_enable(tpd->tpu->clk);
154 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
157 tpd->timer_on = true;
161 * Make sure the channel is stopped, as we need to reconfigure it
162 * completely. First drive the pin to the inactive state to avoid
165 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
166 tpu_pwm_start_stop(tpd, false);
169 * - Clear TCNT on TGRB match
170 * - Count on rising edge
172 * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
173 * - Output 1 until TGRA, output 0 until TGRB (active high polarity
176 tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
178 tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
179 tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
180 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
181 tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
183 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
184 tpd->channel, tpd->duty, tpd->period);
186 /* Start the channel. */
187 tpu_pwm_start_stop(tpd, true);
192 static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
197 /* Disable channel. */
198 tpu_pwm_start_stop(tpd, false);
200 /* Stop clock and mark device as idle. */
201 clk_disable_unprepare(tpd->tpu->clk);
202 pm_runtime_put(&tpd->tpu->pdev->dev);
204 tpd->timer_on = false;
207 /* -----------------------------------------------------------------------------
211 static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
213 struct tpu_device *tpu = to_tpu_device(chip);
214 struct tpu_pwm_device *tpd;
216 if (pwm->hwpwm >= TPU_CHANNEL_MAX)
219 tpd = &tpu->tpd[pwm->hwpwm];
222 tpd->channel = pwm->hwpwm;
223 tpd->polarity = PWM_POLARITY_NORMAL;
228 tpd->timer_on = false;
233 static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
235 struct tpu_device *tpu = to_tpu_device(chip);
236 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
238 tpu_pwm_timer_stop(tpd);
241 static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
242 u64 duty_ns, u64 period_ns, bool enabled)
244 struct tpu_device *tpu = to_tpu_device(chip);
245 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
246 unsigned int prescaler;
247 bool duty_only = false;
253 clk_rate = clk_get_rate(tpu->clk);
254 if (unlikely(clk_rate > NSEC_PER_SEC)) {
256 * This won't happen in the nearer future, so this is only a
257 * safeguard to prevent the following calculation from
258 * overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is
259 * not greater than period_ns and so fits into an u64.
264 period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC);
267 * Find the minimal prescaler in [0..3] such that
269 * period >> (2 * prescaler) < 0x10000
271 * This could be calculated using something like:
273 * prescaler = max(ilog2(period) / 2, 7) - 7;
275 * but given there are only four allowed results and that ilog2 isn't
276 * cheap on all platforms using a switch statement is more effective.
283 case 0x10000 ... 0x3ffff:
287 case 0x40000 ... 0xfffff:
291 case 0x100000 ... 0x3fffff:
299 period >>= 2 * prescaler;
302 duty = mul_u64_u64_div_u64(clk_rate, duty_ns,
303 (u64)NSEC_PER_SEC << (2 * prescaler));
307 dev_dbg(&tpu->pdev->dev,
308 "rate %u, prescaler %u, period %u, duty %u\n",
309 clk_rate, 1 << (2 * prescaler), (u32)period, duty);
311 if (tpd->prescaler == prescaler && tpd->period == period)
314 tpd->prescaler = prescaler;
315 tpd->period = period;
318 /* If the channel is disabled we're done. */
322 if (duty_only && tpd->timer_on) {
324 * If only the duty cycle changed and the timer is already
325 * running, there's no need to reconfigure it completely, Just
326 * modify the duty cycle.
328 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
329 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
332 /* Otherwise perform a full reconfiguration. */
333 ret = tpu_pwm_timer_start(tpd);
338 if (duty == 0 || duty == period) {
340 * To avoid running the timer when not strictly required, handle
341 * 0% and 100% duty cycles as fixed levels and stop the timer.
343 tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
344 tpu_pwm_timer_stop(tpd);
350 static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
351 enum pwm_polarity polarity)
353 struct tpu_device *tpu = to_tpu_device(chip);
354 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
356 tpd->polarity = polarity;
361 static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
363 struct tpu_device *tpu = to_tpu_device(chip);
364 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
367 ret = tpu_pwm_timer_start(tpd);
372 * To avoid running the timer when not strictly required, handle 0% and
373 * 100% duty cycles as fixed levels and stop the timer.
375 if (tpd->duty == 0 || tpd->duty == tpd->period) {
376 tpu_pwm_set_pin(tpd, tpd->duty ?
377 TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
378 tpu_pwm_timer_stop(tpd);
384 static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
386 struct tpu_device *tpu = to_tpu_device(chip);
387 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
389 /* The timer must be running to modify the pin output configuration. */
390 tpu_pwm_timer_start(tpd);
391 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
392 tpu_pwm_timer_stop(tpd);
395 static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
396 const struct pwm_state *state)
399 bool enabled = pwm->state.enabled;
401 if (state->polarity != pwm->state.polarity) {
403 tpu_pwm_disable(chip, pwm);
407 err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
412 if (!state->enabled) {
414 tpu_pwm_disable(chip, pwm);
419 err = tpu_pwm_config(pwm->chip, pwm,
420 state->duty_cycle, state->period, enabled);
425 err = tpu_pwm_enable(chip, pwm);
430 static const struct pwm_ops tpu_pwm_ops = {
431 .request = tpu_pwm_request,
432 .free = tpu_pwm_free,
433 .apply = tpu_pwm_apply,
436 /* -----------------------------------------------------------------------------
440 static int tpu_probe(struct platform_device *pdev)
442 struct tpu_device *tpu;
445 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
449 spin_lock_init(&tpu->lock);
452 /* Map memory, get clock and pin control. */
453 tpu->base = devm_platform_ioremap_resource(pdev, 0);
454 if (IS_ERR(tpu->base))
455 return PTR_ERR(tpu->base);
457 tpu->clk = devm_clk_get(&pdev->dev, NULL);
458 if (IS_ERR(tpu->clk))
459 return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
461 /* Initialize and register the device. */
462 platform_set_drvdata(pdev, tpu);
464 tpu->chip.dev = &pdev->dev;
465 tpu->chip.ops = &tpu_pwm_ops;
466 tpu->chip.npwm = TPU_CHANNEL_MAX;
468 ret = devm_pm_runtime_enable(&pdev->dev);
470 return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");
472 ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
474 return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");
480 static const struct of_device_id tpu_of_table[] = {
481 { .compatible = "renesas,tpu-r8a73a4", },
482 { .compatible = "renesas,tpu-r8a7740", },
483 { .compatible = "renesas,tpu-r8a7790", },
484 { .compatible = "renesas,tpu", },
488 MODULE_DEVICE_TABLE(of, tpu_of_table);
491 static struct platform_driver tpu_driver = {
494 .name = "renesas-tpu-pwm",
495 .of_match_table = of_match_ptr(tpu_of_table),
499 module_platform_driver(tpu_driver);
501 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
502 MODULE_DESCRIPTION("Renesas TPU PWM Driver");
503 MODULE_LICENSE("GPL v2");
504 MODULE_ALIAS("platform:renesas-tpu-pwm");