2 * MediaTek display pulse-width-modulation controller driver.
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YH Huang <yh.huang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/err.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/pwm.h>
24 #include <linux/slab.h>
26 #define DISP_PWM_EN 0x00
28 #define PWM_CLKDIV_SHIFT 16
29 #define PWM_CLKDIV_MAX 0x3ff
30 #define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
32 #define PWM_PERIOD_BIT_WIDTH 12
33 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
35 #define PWM_HIGH_WIDTH_SHIFT 16
36 #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
46 unsigned int commit_mask;
48 unsigned int bls_debug;
54 const struct mtk_pwm_data *data;
60 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
62 return container_of(chip, struct mtk_disp_pwm, chip);
65 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
68 void __iomem *address = mdp->base + offset;
71 value = readl(address);
74 writel(value, address);
77 static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
78 int duty_ns, int period_ns)
80 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
81 u32 clk_div, period, high_width, value;
85 err = clk_prepare_enable(mdp->clk_main);
87 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
91 err = clk_prepare_enable(mdp->clk_mm);
93 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
94 clk_disable_unprepare(mdp->clk_main);
99 * Find period, high_width and clk_div to suit duty_ns and period_ns.
100 * Calculate proper div value to keep period value in the bound.
102 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
103 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
105 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
106 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
108 rate = clk_get_rate(mdp->clk_main);
109 clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
110 PWM_PERIOD_BIT_WIDTH;
111 if (clk_div > PWM_CLKDIV_MAX) {
112 clk_disable_unprepare(mdp->clk_mm);
113 clk_disable_unprepare(mdp->clk_main);
117 div = NSEC_PER_SEC * (clk_div + 1);
118 period = div64_u64(rate * period_ns, div);
122 high_width = div64_u64(rate * duty_ns, div);
123 value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
125 if (mdp->data->bls_debug && !mdp->data->has_commit) {
127 * For MT2701, disable double buffer before writing register
128 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
130 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
131 mdp->data->bls_debug_mask,
132 mdp->data->bls_debug_mask);
133 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
135 mdp->data->con0_sel);
138 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
140 clk_div << PWM_CLKDIV_SHIFT);
141 mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
142 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
145 if (mdp->data->has_commit) {
146 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
147 mdp->data->commit_mask,
148 mdp->data->commit_mask);
149 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
150 mdp->data->commit_mask,
154 clk_disable_unprepare(mdp->clk_mm);
155 clk_disable_unprepare(mdp->clk_main);
160 static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
162 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
165 err = clk_prepare_enable(mdp->clk_main);
167 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
171 err = clk_prepare_enable(mdp->clk_mm);
173 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
174 clk_disable_unprepare(mdp->clk_main);
178 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
179 mdp->data->enable_mask);
184 static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
186 struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
188 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
191 clk_disable_unprepare(mdp->clk_mm);
192 clk_disable_unprepare(mdp->clk_main);
195 static const struct pwm_ops mtk_disp_pwm_ops = {
196 .config = mtk_disp_pwm_config,
197 .enable = mtk_disp_pwm_enable,
198 .disable = mtk_disp_pwm_disable,
199 .owner = THIS_MODULE,
202 static int mtk_disp_pwm_probe(struct platform_device *pdev)
204 struct mtk_disp_pwm *mdp;
208 mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
212 mdp->data = of_device_get_match_data(&pdev->dev);
214 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215 mdp->base = devm_ioremap_resource(&pdev->dev, r);
216 if (IS_ERR(mdp->base))
217 return PTR_ERR(mdp->base);
219 mdp->clk_main = devm_clk_get(&pdev->dev, "main");
220 if (IS_ERR(mdp->clk_main))
221 return PTR_ERR(mdp->clk_main);
223 mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
224 if (IS_ERR(mdp->clk_mm))
225 return PTR_ERR(mdp->clk_mm);
227 mdp->chip.dev = &pdev->dev;
228 mdp->chip.ops = &mtk_disp_pwm_ops;
232 ret = pwmchip_add(&mdp->chip);
234 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
238 platform_set_drvdata(pdev, mdp);
243 static int mtk_disp_pwm_remove(struct platform_device *pdev)
245 struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
247 pwmchip_remove(&mdp->chip);
252 static const struct mtk_pwm_data mt2701_pwm_data = {
253 .enable_mask = BIT(16),
259 .bls_debug_mask = 0x3,
262 static const struct mtk_pwm_data mt8173_pwm_data = {
263 .enable_mask = BIT(0),
272 static const struct of_device_id mtk_disp_pwm_of_match[] = {
273 { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
274 { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
275 { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
278 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
280 static struct platform_driver mtk_disp_pwm_driver = {
282 .name = "mediatek-disp-pwm",
283 .of_match_table = mtk_disp_pwm_of_match,
285 .probe = mtk_disp_pwm_probe,
286 .remove = mtk_disp_pwm_remove,
288 module_platform_driver(mtk_disp_pwm_driver);
290 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
291 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
292 MODULE_LICENSE("GPL v2");