1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/gpio.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/ingenic-tcu.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
24 unsigned int num_pwms;
27 struct jz4740_pwm_chip {
33 static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
35 return container_of(chip, struct jz4740_pwm_chip, chip);
38 static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
41 /* Enable all TCU channels for PWM use by default except channels 0/1 */
42 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
44 device_property_read_u32(jz->chip.dev->parent,
45 "ingenic,pwm-channels-mask",
48 return !!(pwm_channels_mask & BIT(channel));
51 static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
53 struct jz4740_pwm_chip *jz = to_jz4740(chip);
58 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
61 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
63 clk = clk_get(chip->dev, name);
65 dev_err(chip->dev, "error %pe: Failed to get clock\n", clk);
69 err = clk_prepare_enable(clk);
75 jz->clk[pwm->hwpwm] = clk;
80 static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
82 struct jz4740_pwm_chip *jz = to_jz4740(chip);
83 struct clk *clk = jz->clk[pwm->hwpwm];
85 clk_disable_unprepare(clk);
89 static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
91 struct jz4740_pwm_chip *jz = to_jz4740(chip);
93 /* Enable PWM output */
94 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
97 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
102 static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
104 struct jz4740_pwm_chip *jz = to_jz4740(chip);
107 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
108 * properly return to their init level.
110 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
111 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
114 * Disable PWM output.
115 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
116 * counter is stopped, while in TCU1 mode the order does not matter.
118 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
121 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
124 static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
125 const struct pwm_state *state)
127 struct jz4740_pwm_chip *jz = to_jz4740(pwm->chip);
128 unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
129 struct clk *clk = jz->clk[pwm->hwpwm];
130 unsigned long period, duty;
135 * Limit the clock to a maximum rate that still gives us a period value
136 * which fits in 16 bits.
138 do_div(tmp, state->period);
141 * /!\ IMPORTANT NOTE:
142 * -------------------
143 * This code relies on the fact that clk_round_rate() will always round
144 * down, which is not a valid assumption given by the clk API, but only
145 * happens to be true with the clk drivers used for Ingenic SoCs.
147 * Right now, there is no alternative as the clk API does not have a
148 * round-down function (and won't have one for a while), but if it ever
149 * comes to light, a round-down function should be used instead.
151 rate = clk_round_rate(clk, tmp);
153 dev_err(chip->dev, "Unable to round rate: %ld", rate);
157 /* Calculate period value */
158 tmp = (unsigned long long)rate * state->period;
159 do_div(tmp, NSEC_PER_SEC);
162 /* Calculate duty value */
163 tmp = (unsigned long long)rate * state->duty_cycle;
164 do_div(tmp, NSEC_PER_SEC);
170 jz4740_pwm_disable(chip, pwm);
172 err = clk_set_rate(clk, rate);
174 dev_err(chip->dev, "Unable to set rate: %d", err);
178 /* Reset counter to 0 */
179 regmap_write(jz->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
182 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
185 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), period);
187 /* Set abrupt shutdown */
188 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
194 * The PWM starts in inactive state until the internal timer reaches the
195 * duty value, then becomes active until the timer reaches the period
196 * value. In theory, we should then use (period - duty) as the real duty
197 * value, as a high duty value would otherwise result in the PWM pin
198 * being inactive most of the time.
200 * Here, we don't do that, and instead invert the polarity of the PWM
201 * when it is active. This trick makes the PWM start with its active
202 * state instead of its inactive state.
204 if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
205 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
206 TCU_TCSR_PWM_INITL_HIGH, 0);
208 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
209 TCU_TCSR_PWM_INITL_HIGH,
210 TCU_TCSR_PWM_INITL_HIGH);
213 jz4740_pwm_enable(chip, pwm);
218 static const struct pwm_ops jz4740_pwm_ops = {
219 .request = jz4740_pwm_request,
220 .free = jz4740_pwm_free,
221 .apply = jz4740_pwm_apply,
224 static int jz4740_pwm_probe(struct platform_device *pdev)
226 struct device *dev = &pdev->dev;
227 struct jz4740_pwm_chip *jz;
228 const struct soc_info *info;
230 info = device_get_match_data(dev);
234 jz = devm_kzalloc(dev, struct_size(jz, clk, info->num_pwms),
239 jz->map = device_node_to_regmap(dev->parent->of_node);
240 if (IS_ERR(jz->map)) {
241 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz->map));
242 return PTR_ERR(jz->map);
246 jz->chip.ops = &jz4740_pwm_ops;
247 jz->chip.npwm = info->num_pwms;
249 return devm_pwmchip_add(dev, &jz->chip);
252 static const struct soc_info jz4740_soc_info = {
256 static const struct soc_info jz4725b_soc_info = {
260 static const struct soc_info x1000_soc_info = {
264 static const struct of_device_id jz4740_pwm_dt_ids[] = {
265 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
266 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
267 { .compatible = "ingenic,x1000-pwm", .data = &x1000_soc_info },
270 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
272 static struct platform_driver jz4740_pwm_driver = {
274 .name = "jz4740-pwm",
275 .of_match_table = jz4740_pwm_dt_ids,
277 .probe = jz4740_pwm_probe,
279 module_platform_driver(jz4740_pwm_driver);
281 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
282 MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
283 MODULE_ALIAS("platform:jz4740-pwm");
284 MODULE_LICENSE("GPL");