drivers/pmdomain/rockchip/pm-domains.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Rockchip Generic power domain support.
   4  *
   5  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   6  */
   7
   8 #include <linux/io.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/err.h>
  11 #include <linux/mutex.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_clock.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/property.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_clk.h>
  19 #include <linux/clk.h>
  20 #include <linux/regmap.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <soc/rockchip/pm_domains.h>
  23 #include <dt-bindings/power/px30-power.h>
  24 #include <dt-bindings/power/rockchip,rv1126-power.h>
  25 #include <dt-bindings/power/rk3036-power.h>
  26 #include <dt-bindings/power/rk3066-power.h>
  27 #include <dt-bindings/power/rk3128-power.h>
  28 #include <dt-bindings/power/rk3188-power.h>
  29 #include <dt-bindings/power/rk3228-power.h>
  30 #include <dt-bindings/power/rk3288-power.h>
  31 #include <dt-bindings/power/rk3328-power.h>
  32 #include <dt-bindings/power/rk3366-power.h>
  33 #include <dt-bindings/power/rk3368-power.h>
  34 #include <dt-bindings/power/rk3399-power.h>
  35 #include <dt-bindings/power/rk3568-power.h>
  36 #include <dt-bindings/power/rk3588-power.h>
  37
  38 struct rockchip_domain_info {
  39         const char *name;
  40         int pwr_mask;
  41         int status_mask;
  42         int req_mask;
  43         int idle_mask;
  44         int ack_mask;
  45         bool active_wakeup;
  46         int pwr_w_mask;
  47         int req_w_mask;
  48         int mem_status_mask;
  49         int repair_status_mask;
  50         u32 pwr_offset;
  51         u32 mem_offset;
  52         u32 req_offset;
  53 };
  54
  55 struct rockchip_pmu_info {
  56         u32 pwr_offset;
  57         u32 status_offset;
  58         u32 req_offset;
  59         u32 idle_offset;
  60         u32 ack_offset;
  61         u32 mem_pwr_offset;
  62         u32 chain_status_offset;
  63         u32 mem_status_offset;
  64         u32 repair_status_offset;
  65
  66         u32 core_pwrcnt_offset;
  67         u32 gpu_pwrcnt_offset;
  68
  69         unsigned int core_power_transition_time;
  70         unsigned int gpu_power_transition_time;
  71
  72         int num_domains;
  73         const struct rockchip_domain_info *domain_info;
  74 };
  75
  76 #define MAX_QOS_REGS_NUM        5
  77 #define QOS_PRIORITY            0x08
  78 #define QOS_MODE                0x0c
  79 #define QOS_BANDWIDTH           0x10
  80 #define QOS_SATURATION          0x14
  81 #define QOS_EXTCONTROL          0x18
  82
  83 struct rockchip_pm_domain {
  84         struct generic_pm_domain genpd;
  85         const struct rockchip_domain_info *info;
  86         struct rockchip_pmu *pmu;
  87         int num_qos;
  88         struct regmap **qos_regmap;
  89         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  90         int num_clks;
  91         struct clk_bulk_data *clks;
  92 };
  93
  94 struct rockchip_pmu {
  95         struct device *dev;
  96         struct regmap *regmap;
  97         const struct rockchip_pmu_info *info;
  98         struct mutex mutex; /* mutex lock for pmu */
  99         struct genpd_onecell_data genpd_data;
 100         struct generic_pm_domain *domains[];
 101 };
 102
 103 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
 104
 105 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup)      \
 106 {                                                       \
 107         .name = _name,                          \
 108         .pwr_mask = (pwr),                              \
 109         .status_mask = (status),                        \
 110         .req_mask = (req),                              \
 111         .idle_mask = (idle),                            \
 112         .ack_mask = (ack),                              \
 113         .active_wakeup = (wakeup),                      \
 114 }
 115
 116 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup)    \
 117 {                                                       \
 118         .name = _name,                          \
 119         .pwr_w_mask = (pwr) << 16,                      \
 120         .pwr_mask = (pwr),                              \
 121         .status_mask = (status),                        \
 122         .req_w_mask = (req) << 16,                      \
 123         .req_mask = (req),                              \
 124         .idle_mask = (idle),                            \
 125         .ack_mask = (ack),                              \
 126         .active_wakeup = wakeup,                        \
 127 }
 128
 129 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup)      \
 130 {                                                       \
 131         .name = _name,                                  \
 132         .pwr_offset = p_offset,                         \
 133         .pwr_w_mask = (pwr) << 16,                      \
 134         .pwr_mask = (pwr),                              \
 135         .status_mask = (status),                        \
 136         .mem_offset = m_offset,                         \
 137         .mem_status_mask = (m_status),                  \
 138         .repair_status_mask = (r_status),               \
 139         .req_offset = r_offset,                         \
 140         .req_w_mask = (req) << 16,                      \
 141         .req_mask = (req),                              \
 142         .idle_mask = (idle),                            \
 143         .ack_mask = (ack),                              \
 144         .active_wakeup = wakeup,                        \
 145 }
 146
 147 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup)            \
 148 {                                                       \
 149         .name = _name,                          \
 150         .req_mask = (req),                              \
 151         .req_w_mask = (req) << 16,                      \
 152         .ack_mask = (ack),                              \
 153         .idle_mask = (idle),                            \
 154         .active_wakeup = wakeup,                        \
 155 }
 156
 157 #define DOMAIN_PX30(name, pwr, status, req, wakeup)             \
 158         DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
 159
 160 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup)             \
 161         DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
 162
 163 #define DOMAIN_RK3288(name, pwr, status, req, wakeup)           \
 164         DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
 165
 166 #define DOMAIN_RK3328(name, pwr, status, req, wakeup)           \
 167         DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
 168
 169 #define DOMAIN_RK3368(name, pwr, status, req, wakeup)           \
 170         DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
 171
 172 #define DOMAIN_RK3399(name, pwr, status, req, wakeup)           \
 173         DOMAIN(name, pwr, status, req, req, req, wakeup)
 174
 175 #define DOMAIN_RK3568(name, pwr, req, wakeup)           \
 176         DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
 177
 178 /*
 179  * Dynamic Memory Controller may need to coordinate with us -- see
 180  * rockchip_pmu_block().
 181  *
 182  * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
 183  * block() while we're initializing the PMU.
 184  */
 185 static DEFINE_MUTEX(dmc_pmu_mutex);
 186 static struct rockchip_pmu *dmc_pmu;
 187
 188 /*
 189  * Block PMU transitions and make sure they don't interfere with ARM Trusted
 190  * Firmware operations. There are two conflicts, noted in the comments below.
 191  *
 192  * Caller must unblock PMU transitions via rockchip_pmu_unblock().
 193  */
 194 int rockchip_pmu_block(void)
 195 {
 196         struct rockchip_pmu *pmu;
 197         struct generic_pm_domain *genpd;
 198         struct rockchip_pm_domain *pd;
 199         int i, ret;
 200
 201         mutex_lock(&dmc_pmu_mutex);
 202
 203         /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
 204         if (!dmc_pmu)
 205                 return 0;
 206         pmu = dmc_pmu;
 207
 208         /*
 209          * mutex blocks all idle transitions: we can't touch the
 210          * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
 211          * Firmware might be using it.
 212          */
 213         mutex_lock(&pmu->mutex);
 214
 215         /*
 216          * Power domain clocks: Per Rockchip, we *must* keep certain clocks
 217          * enabled for the duration of power-domain transitions. Most
 218          * transitions are handled by this driver, but some cases (in
 219          * particular, DRAM DVFS / memory-controller idle) must be handled by
 220          * firmware. Firmware can handle most clock management via a special
 221          * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
 222          * doesn't handle PLLs. We can assist this transition by doing the
 223          * clock management on behalf of firmware.
 224          */
 225         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 226                 genpd = pmu->genpd_data.domains[i];
 227                 if (genpd) {
 228                         pd = to_rockchip_pd(genpd);
 229                         ret = clk_bulk_enable(pd->num_clks, pd->clks);
 230                         if (ret < 0) {
 231                                 dev_err(pmu->dev,
 232                                         "failed to enable clks for domain '%s': %d\n",
 233                                         genpd->name, ret);
 234                                 goto err;
 235                         }
 236                 }
 237         }
 238
 239         return 0;
 240
 241 err:
 242         for (i = i - 1; i >= 0; i--) {
 243                 genpd = pmu->genpd_data.domains[i];
 244                 if (genpd) {
 245                         pd = to_rockchip_pd(genpd);
 246                         clk_bulk_disable(pd->num_clks, pd->clks);
 247                 }
 248         }
 249         mutex_unlock(&pmu->mutex);
 250         mutex_unlock(&dmc_pmu_mutex);
 251
 252         return ret;
 253 }
 254 EXPORT_SYMBOL_GPL(rockchip_pmu_block);
 255
 256 /* Unblock PMU transitions. */
 257 void rockchip_pmu_unblock(void)
 258 {
 259         struct rockchip_pmu *pmu;
 260         struct generic_pm_domain *genpd;
 261         struct rockchip_pm_domain *pd;
 262         int i;
 263
 264         if (dmc_pmu) {
 265                 pmu = dmc_pmu;
 266                 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 267                         genpd = pmu->genpd_data.domains[i];
 268                         if (genpd) {
 269                                 pd = to_rockchip_pd(genpd);
 270                                 clk_bulk_disable(pd->num_clks, pd->clks);
 271                         }
 272                 }
 273
 274                 mutex_unlock(&pmu->mutex);
 275         }
 276
 277         mutex_unlock(&dmc_pmu_mutex);
 278 }
 279 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
 280
 281 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)   \
 282         DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
 283
 284 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
 285 {
 286         struct rockchip_pmu *pmu = pd->pmu;
 287         const struct rockchip_domain_info *pd_info = pd->info;
 288         unsigned int val;
 289
 290         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
 291         return (val & pd_info->idle_mask) == pd_info->idle_mask;
 292 }
 293
 294 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
 295 {
 296         unsigned int val;
 297
 298         regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 299         return val;
 300 }
 301
 302 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 303                                          bool idle)
 304 {
 305         const struct rockchip_domain_info *pd_info = pd->info;
 306         struct generic_pm_domain *genpd = &pd->genpd;
 307         struct rockchip_pmu *pmu = pd->pmu;
 308         u32 pd_req_offset = pd_info->req_offset;
 309         unsigned int target_ack;
 310         unsigned int val;
 311         bool is_idle;
 312         int ret;
 313
 314         if (pd_info->req_mask == 0)
 315                 return 0;
 316         else if (pd_info->req_w_mask)
 317                 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
 318                              idle ? (pd_info->req_mask | pd_info->req_w_mask) :
 319                              pd_info->req_w_mask);
 320         else
 321                 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
 322                                    pd_info->req_mask, idle ? -1U : 0);
 323
 324         wmb();
 325
 326         /* Wait util idle_ack = 1 */
 327         target_ack = idle ? pd_info->ack_mask : 0;
 328         ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
 329                                         (val & pd_info->ack_mask) == target_ack,
 330                                         0, 10000);
 331         if (ret) {
 332                 dev_err(pmu->dev,
 333                         "failed to get ack on domain '%s', val=0x%x\n",
 334                         genpd->name, val);
 335                 return ret;
 336         }
 337
 338         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
 339                                         is_idle, is_idle == idle, 0, 10000);
 340         if (ret) {
 341                 dev_err(pmu->dev,
 342                         "failed to set idle on domain '%s', val=%d\n",
 343                         genpd->name, is_idle);
 344                 return ret;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
 351 {
 352         int i;
 353
 354         for (i = 0; i < pd->num_qos; i++) {
 355                 regmap_read(pd->qos_regmap[i],
 356                             QOS_PRIORITY,
 357                             &pd->qos_save_regs[0][i]);
 358                 regmap_read(pd->qos_regmap[i],
 359                             QOS_MODE,
 360                             &pd->qos_save_regs[1][i]);
 361                 regmap_read(pd->qos_regmap[i],
 362                             QOS_BANDWIDTH,
 363                             &pd->qos_save_regs[2][i]);
 364                 regmap_read(pd->qos_regmap[i],
 365                             QOS_SATURATION,
 366                             &pd->qos_save_regs[3][i]);
 367                 regmap_read(pd->qos_regmap[i],
 368                             QOS_EXTCONTROL,
 369                             &pd->qos_save_regs[4][i]);
 370         }
 371         return 0;
 372 }
 373
 374 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
 375 {
 376         int i;
 377
 378         for (i = 0; i < pd->num_qos; i++) {
 379                 regmap_write(pd->qos_regmap[i],
 380                              QOS_PRIORITY,
 381                              pd->qos_save_regs[0][i]);
 382                 regmap_write(pd->qos_regmap[i],
 383                              QOS_MODE,
 384                              pd->qos_save_regs[1][i]);
 385                 regmap_write(pd->qos_regmap[i],
 386                              QOS_BANDWIDTH,
 387                              pd->qos_save_regs[2][i]);
 388                 regmap_write(pd->qos_regmap[i],
 389                              QOS_SATURATION,
 390                              pd->qos_save_regs[3][i]);
 391                 regmap_write(pd->qos_regmap[i],
 392                              QOS_EXTCONTROL,
 393                              pd->qos_save_regs[4][i]);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 400 {
 401         struct rockchip_pmu *pmu = pd->pmu;
 402         unsigned int val;
 403
 404         if (pd->info->repair_status_mask) {
 405                 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
 406                 /* 1'b1: power on, 1'b0: power off */
 407                 return val & pd->info->repair_status_mask;
 408         }
 409
 410         /* check idle status for idle-only domains */
 411         if (pd->info->status_mask == 0)
 412                 return !rockchip_pmu_domain_is_idle(pd);
 413
 414         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 415
 416         /* 1'b0: power on, 1'b1: power off */
 417         return !(val & pd->info->status_mask);
 418 }
 419
 420 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
 421 {
 422         struct rockchip_pmu *pmu = pd->pmu;
 423         unsigned int val;
 424
 425         regmap_read(pmu->regmap,
 426                     pmu->info->mem_status_offset + pd->info->mem_offset, &val);
 427
 428         /* 1'b0: power on, 1'b1: power off */
 429         return !(val & pd->info->mem_status_mask);
 430 }
 431
 432 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
 433 {
 434         struct rockchip_pmu *pmu = pd->pmu;
 435         unsigned int val;
 436
 437         regmap_read(pmu->regmap,
 438                     pmu->info->chain_status_offset + pd->info->mem_offset, &val);
 439
 440         /* 1'b1: power on, 1'b0: power off */
 441         return val & pd->info->mem_status_mask;
 442 }
 443
 444 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
 445 {
 446         struct rockchip_pmu *pmu = pd->pmu;
 447         struct generic_pm_domain *genpd = &pd->genpd;
 448         bool is_on;
 449         int ret = 0;
 450
 451         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
 452                                         is_on == true, 0, 10000);
 453         if (ret) {
 454                 dev_err(pmu->dev,
 455                         "failed to get chain status '%s', target_on=1, val=%d\n",
 456                         genpd->name, is_on);
 457                 goto error;
 458         }
 459
 460         udelay(20);
 461
 462         regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
 463                      (pd->info->pwr_mask | pd->info->pwr_w_mask));
 464         wmb();
 465
 466         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
 467                                         is_on == false, 0, 10000);
 468         if (ret) {
 469                 dev_err(pmu->dev,
 470                         "failed to get mem status '%s', target_on=0, val=%d\n",
 471                         genpd->name, is_on);
 472                 goto error;
 473         }
 474
 475         regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
 476                      pd->info->pwr_w_mask);
 477         wmb();
 478
 479         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
 480                                         is_on == true, 0, 10000);
 481         if (ret) {
 482                 dev_err(pmu->dev,
 483                         "failed to get mem status '%s', target_on=1, val=%d\n",
 484                         genpd->name, is_on);
 485         }
 486
 487 error:
 488         return ret;
 489 }
 490
 491 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 492                                              bool on)
 493 {
 494         struct rockchip_pmu *pmu = pd->pmu;
 495         struct generic_pm_domain *genpd = &pd->genpd;
 496         u32 pd_pwr_offset = pd->info->pwr_offset;
 497         bool is_on, is_mem_on = false;
 498
 499         if (pd->info->pwr_mask == 0)
 500                 return;
 501
 502         if (on && pd->info->mem_status_mask)
 503                 is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
 504
 505         if (pd->info->pwr_w_mask)
 506                 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
 507                              on ? pd->info->pwr_w_mask :
 508                              (pd->info->pwr_mask | pd->info->pwr_w_mask));
 509         else
 510                 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
 511                                    pd->info->pwr_mask, on ? 0 : -1U);
 512
 513         wmb();
 514
 515         if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
 516                 return;
 517
 518         if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
 519                                       is_on == on, 0, 10000)) {
 520                 dev_err(pmu->dev,
 521                         "failed to set domain '%s', val=%d\n",
 522                         genpd->name, is_on);
 523                 return;
 524         }
 525 }
 526
 527 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 528 {
 529         struct rockchip_pmu *pmu = pd->pmu;
 530         int ret;
 531
 532         mutex_lock(&pmu->mutex);
 533
 534         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 535                 ret = clk_bulk_enable(pd->num_clks, pd->clks);
 536                 if (ret < 0) {
 537                         dev_err(pmu->dev, "failed to enable clocks\n");
 538                         mutex_unlock(&pmu->mutex);
 539                         return ret;
 540                 }
 541
 542                 if (!power_on) {
 543                         rockchip_pmu_save_qos(pd);
 544
 545                         /* if powering down, idle request to NIU first */
 546                         rockchip_pmu_set_idle_request(pd, true);
 547                 }
 548
 549                 rockchip_do_pmu_set_power_domain(pd, power_on);
 550
 551                 if (power_on) {
 552                         /* if powering up, leave idle mode */
 553                         rockchip_pmu_set_idle_request(pd, false);
 554
 555                         rockchip_pmu_restore_qos(pd);
 556                 }
 557
 558                 clk_bulk_disable(pd->num_clks, pd->clks);
 559         }
 560
 561         mutex_unlock(&pmu->mutex);
 562         return 0;
 563 }
 564
 565 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 566 {
 567         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 568
 569         return rockchip_pd_power(pd, true);
 570 }
 571
 572 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 573 {
 574         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 575
 576         return rockchip_pd_power(pd, false);
 577 }
 578
 579 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 580                                   struct device *dev)
 581 {
 582         struct clk *clk;
 583         int i;
 584         int error;
 585
 586         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 587
 588         error = pm_clk_create(dev);
 589         if (error) {
 590                 dev_err(dev, "pm_clk_create failed %d\n", error);
 591                 return error;
 592         }
 593
 594         i = 0;
 595         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 596                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 597                 error = pm_clk_add_clk(dev, clk);
 598                 if (error) {
 599                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 600                         clk_put(clk);
 601                         pm_clk_destroy(dev);
 602                         return error;
 603                 }
 604         }
 605
 606         return 0;
 607 }
 608
 609 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 610                                    struct device *dev)
 611 {
 612         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 613
 614         pm_clk_destroy(dev);
 615 }
 616
 617 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 618                                       struct device_node *node)
 619 {
 620         const struct rockchip_domain_info *pd_info;
 621         struct rockchip_pm_domain *pd;
 622         struct device_node *qos_node;
 623         int i, j;
 624         u32 id;
 625         int error;
 626
 627         error = of_property_read_u32(node, "reg", &id);
 628         if (error) {
 629                 dev_err(pmu->dev,
 630                         "%pOFn: failed to retrieve domain id (reg): %d\n",
 631                         node, error);
 632                 return -EINVAL;
 633         }
 634
 635         if (id >= pmu->info->num_domains) {
 636                 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
 637                         node, id);
 638                 return -EINVAL;
 639         }
 640         /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
 641         if (pmu->genpd_data.domains[id])
 642                 return 0;
 643
 644         pd_info = &pmu->info->domain_info[id];
 645         if (!pd_info) {
 646                 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
 647                         node, id);
 648                 return -EINVAL;
 649         }
 650
 651         pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
 652         if (!pd)
 653                 return -ENOMEM;
 654
 655         pd->info = pd_info;
 656         pd->pmu = pmu;
 657
 658         pd->num_clks = of_clk_get_parent_count(node);
 659         if (pd->num_clks > 0) {
 660                 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
 661                                         sizeof(*pd->clks), GFP_KERNEL);
 662                 if (!pd->clks)
 663                         return -ENOMEM;
 664         } else {
 665                 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
 666                         node, pd->num_clks);
 667                 pd->num_clks = 0;
 668         }
 669
 670         for (i = 0; i < pd->num_clks; i++) {
 671                 pd->clks[i].clk = of_clk_get(node, i);
 672                 if (IS_ERR(pd->clks[i].clk)) {
 673                         error = PTR_ERR(pd->clks[i].clk);
 674                         dev_err(pmu->dev,
 675                                 "%pOFn: failed to get clk at index %d: %d\n",
 676                                 node, i, error);
 677                         return error;
 678                 }
 679         }
 680
 681         error = clk_bulk_prepare(pd->num_clks, pd->clks);
 682         if (error)
 683                 goto err_put_clocks;
 684
 685         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
 686                                                  NULL);
 687
 688         if (pd->num_qos > 0) {
 689                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
 690                                               sizeof(*pd->qos_regmap),
 691                                               GFP_KERNEL);
 692                 if (!pd->qos_regmap) {
 693                         error = -ENOMEM;
 694                         goto err_unprepare_clocks;
 695                 }
 696
 697                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
 698                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
 699                                                             pd->num_qos,
 700                                                             sizeof(u32),
 701                                                             GFP_KERNEL);
 702                         if (!pd->qos_save_regs[j]) {
 703                                 error = -ENOMEM;
 704                                 goto err_unprepare_clocks;
 705                         }
 706                 }
 707
 708                 for (j = 0; j < pd->num_qos; j++) {
 709                         qos_node = of_parse_phandle(node, "pm_qos", j);
 710                         if (!qos_node) {
 711                                 error = -ENODEV;
 712                                 goto err_unprepare_clocks;
 713                         }
 714                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
 715                         if (IS_ERR(pd->qos_regmap[j])) {
 716                                 error = -ENODEV;
 717                                 of_node_put(qos_node);
 718                                 goto err_unprepare_clocks;
 719                         }
 720                         of_node_put(qos_node);
 721                 }
 722         }
 723
 724         if (pd->info->name)
 725                 pd->genpd.name = pd->info->name;
 726         else
 727                 pd->genpd.name = kbasename(node->full_name);
 728         pd->genpd.power_off = rockchip_pd_power_off;
 729         pd->genpd.power_on = rockchip_pd_power_on;
 730         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 731         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 732         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 733         if (pd_info->active_wakeup)
 734                 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
 735         pm_genpd_init(&pd->genpd, NULL,
 736                       !rockchip_pmu_domain_is_on(pd) ||
 737                       (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
 738
 739         pmu->genpd_data.domains[id] = &pd->genpd;
 740         return 0;
 741
 742 err_unprepare_clocks:
 743         clk_bulk_unprepare(pd->num_clks, pd->clks);
 744 err_put_clocks:
 745         clk_bulk_put(pd->num_clks, pd->clks);
 746         return error;
 747 }
 748
 749 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 750 {
 751         int ret;
 752
 753         /*
 754          * We're in the error cleanup already, so we only complain,
 755          * but won't emit another error on top of the original one.
 756          */
 757         ret = pm_genpd_remove(&pd->genpd);
 758         if (ret < 0)
 759                 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
 760                         pd->genpd.name, ret);
 761
 762         clk_bulk_unprepare(pd->num_clks, pd->clks);
 763         clk_bulk_put(pd->num_clks, pd->clks);
 764
 765         /* protect the zeroing of pm->num_clks */
 766         mutex_lock(&pd->pmu->mutex);
 767         pd->num_clks = 0;
 768         mutex_unlock(&pd->pmu->mutex);
 769
 770         /* devm will free our memory */
 771 }
 772
 773 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 774 {
 775         struct generic_pm_domain *genpd;
 776         struct rockchip_pm_domain *pd;
 777         int i;
 778
 779         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 780                 genpd = pmu->genpd_data.domains[i];
 781                 if (genpd) {
 782                         pd = to_rockchip_pd(genpd);
 783                         rockchip_pm_remove_one_domain(pd);
 784                 }
 785         }
 786
 787         /* devm will free our memory */
 788 }
 789
 790 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 791                                       u32 domain_reg_offset,
 792                                       unsigned int count)
 793 {
 794         /* First configure domain power down transition count ... */
 795         regmap_write(pmu->regmap, domain_reg_offset, count);
 796         /* ... and then power up count. */
 797         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 798 }
 799
 800 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 801                                      struct device_node *parent)
 802 {
 803         struct device_node *np;
 804         struct generic_pm_domain *child_domain, *parent_domain;
 805         int error;
 806
 807         for_each_child_of_node(parent, np) {
 808                 u32 idx;
 809
 810                 error = of_property_read_u32(parent, "reg", &idx);
 811                 if (error) {
 812                         dev_err(pmu->dev,
 813                                 "%pOFn: failed to retrieve domain id (reg): %d\n",
 814                                 parent, error);
 815                         goto err_out;
 816                 }
 817                 parent_domain = pmu->genpd_data.domains[idx];
 818
 819                 error = rockchip_pm_add_one_domain(pmu, np);
 820                 if (error) {
 821                         dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
 822                                 np, error);
 823                         goto err_out;
 824                 }
 825
 826                 error = of_property_read_u32(np, "reg", &idx);
 827                 if (error) {
 828                         dev_err(pmu->dev,
 829                                 "%pOFn: failed to retrieve domain id (reg): %d\n",
 830                                 np, error);
 831                         goto err_out;
 832                 }
 833                 child_domain = pmu->genpd_data.domains[idx];
 834
 835                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 836                 if (error) {
 837                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 838                                 parent_domain->name, child_domain->name, error);
 839                         goto err_out;
 840                 } else {
 841                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 842                                 parent_domain->name, child_domain->name);
 843                 }
 844
 845                 rockchip_pm_add_subdomain(pmu, np);
 846         }
 847
 848         return 0;
 849
 850 err_out:
 851         of_node_put(np);
 852         return error;
 853 }
 854
 855 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 856 {
 857         struct device *dev = &pdev->dev;
 858         struct device_node *np = dev->of_node;
 859         struct device_node *node;
 860         struct device *parent;
 861         struct rockchip_pmu *pmu;
 862         const struct rockchip_pmu_info *pmu_info;
 863         int error;
 864
 865         if (!np) {
 866                 dev_err(dev, "device tree node not found\n");
 867                 return -ENODEV;
 868         }
 869
 870         pmu_info = device_get_match_data(dev);
 871
 872         pmu = devm_kzalloc(dev,
 873                            struct_size(pmu, domains, pmu_info->num_domains),
 874                            GFP_KERNEL);
 875         if (!pmu)
 876                 return -ENOMEM;
 877
 878         pmu->dev = &pdev->dev;
 879         mutex_init(&pmu->mutex);
 880
 881         pmu->info = pmu_info;
 882
 883         pmu->genpd_data.domains = pmu->domains;
 884         pmu->genpd_data.num_domains = pmu_info->num_domains;
 885
 886         parent = dev->parent;
 887         if (!parent) {
 888                 dev_err(dev, "no parent for syscon devices\n");
 889                 return -ENODEV;
 890         }
 891
 892         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 893         if (IS_ERR(pmu->regmap)) {
 894                 dev_err(dev, "no regmap available\n");
 895                 return PTR_ERR(pmu->regmap);
 896         }
 897
 898         /*
 899          * Configure power up and down transition delays for CORE
 900          * and GPU domains.
 901          */
 902         if (pmu_info->core_power_transition_time)
 903                 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 904                                         pmu_info->core_power_transition_time);
 905         if (pmu_info->gpu_pwrcnt_offset)
 906                 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 907                                         pmu_info->gpu_power_transition_time);
 908
 909         error = -ENODEV;
 910
 911         /*
 912          * Prevent any rockchip_pmu_block() from racing with the remainder of
 913          * setup (clocks, register initialization).
 914          */
 915         mutex_lock(&dmc_pmu_mutex);
 916
 917         for_each_available_child_of_node(np, node) {
 918                 error = rockchip_pm_add_one_domain(pmu, node);
 919                 if (error) {
 920                         dev_err(dev, "failed to handle node %pOFn: %d\n",
 921                                 node, error);
 922                         of_node_put(node);
 923                         goto err_out;
 924                 }
 925
 926                 error = rockchip_pm_add_subdomain(pmu, node);
 927                 if (error < 0) {
 928                         dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
 929                                 node, error);
 930                         of_node_put(node);
 931                         goto err_out;
 932                 }
 933         }
 934
 935         if (error) {
 936                 dev_dbg(dev, "no power domains defined\n");
 937                 goto err_out;
 938         }
 939
 940         error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 941         if (error) {
 942                 dev_err(dev, "failed to add provider: %d\n", error);
 943                 goto err_out;
 944         }
 945
 946         /* We only expect one PMU. */
 947         if (!WARN_ON_ONCE(dmc_pmu))
 948                 dmc_pmu = pmu;
 949
 950         mutex_unlock(&dmc_pmu_mutex);
 951
 952         return 0;
 953
 954 err_out:
 955         rockchip_pm_domain_cleanup(pmu);
 956         mutex_unlock(&dmc_pmu_mutex);
 957         return error;
 958 }
 959
 960 static const struct rockchip_domain_info px30_pm_domains[] = {
 961         [PX30_PD_USB]           = DOMAIN_PX30("usb",      BIT(5),  BIT(5),  BIT(10), false),
 962         [PX30_PD_SDCARD]        = DOMAIN_PX30("sdcard",   BIT(8),  BIT(8),  BIT(9),  false),
 963         [PX30_PD_GMAC]          = DOMAIN_PX30("gmac",     BIT(10), BIT(10), BIT(6),  false),
 964         [PX30_PD_MMC_NAND]      = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5),  false),
 965         [PX30_PD_VPU]           = DOMAIN_PX30("vpu",      BIT(12), BIT(12), BIT(14), false),
 966         [PX30_PD_VO]            = DOMAIN_PX30("vo",       BIT(13), BIT(13), BIT(7),  false),
 967         [PX30_PD_VI]            = DOMAIN_PX30("vi",       BIT(14), BIT(14), BIT(8),  false),
 968         [PX30_PD_GPU]           = DOMAIN_PX30("gpu",      BIT(15), BIT(15), BIT(2),  false),
 969 };
 970
 971 static const struct rockchip_domain_info rv1126_pm_domains[] = {
 972         [RV1126_PD_VEPU]        = DOMAIN_RV1126("vepu", BIT(2),  BIT(9),  BIT(9), false),
 973         [RV1126_PD_VI]          = DOMAIN_RV1126("vi", BIT(4),  BIT(6),  BIT(6),  false),
 974         [RV1126_PD_VO]          = DOMAIN_RV1126("vo", BIT(5),  BIT(7),  BIT(7),  false),
 975         [RV1126_PD_ISPP]        = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8),  false),
 976         [RV1126_PD_VDPU]        = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
 977         [RV1126_PD_NVM]         = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11),  false),
 978         [RV1126_PD_SDIO]        = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13),  false),
 979         [RV1126_PD_USB]         = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15),  false),
 980 };
 981
 982 static const struct rockchip_domain_info rk3036_pm_domains[] = {
 983         [RK3036_PD_MSCH]        = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
 984         [RK3036_PD_CORE]        = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
 985         [RK3036_PD_PERI]        = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
 986         [RK3036_PD_VIO]         = DOMAIN_RK3036("vio",  BIT(11), BIT(19), BIT(26), false),
 987         [RK3036_PD_VPU]         = DOMAIN_RK3036("vpu",  BIT(10), BIT(20), BIT(27), false),
 988         [RK3036_PD_GPU]         = DOMAIN_RK3036("gpu",  BIT(9),  BIT(21), BIT(28), false),
 989         [RK3036_PD_SYS]         = DOMAIN_RK3036("sys",  BIT(8),  BIT(22), BIT(29), false),
 990 };
 991
 992 static const struct rockchip_domain_info rk3066_pm_domains[] = {
 993         [RK3066_PD_GPU]         = DOMAIN("gpu",   BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
 994         [RK3066_PD_VIDEO]       = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
 995         [RK3066_PD_VIO]         = DOMAIN("vio",   BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
 996         [RK3066_PD_PERI]        = DOMAIN("peri",  BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
 997         [RK3066_PD_CPU]         = DOMAIN("cpu",   0,      BIT(5), BIT(1), BIT(26), BIT(31), false),
 998 };
 999
1000 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1001         [RK3128_PD_CORE]        = DOMAIN_RK3288("core",  BIT(0), BIT(0), BIT(4), false),
1002         [RK3128_PD_MSCH]        = DOMAIN_RK3288("msch",  0,      0,      BIT(6), true),
1003         [RK3128_PD_VIO]         = DOMAIN_RK3288("vio",   BIT(3), BIT(3), BIT(2), false),
1004         [RK3128_PD_VIDEO]       = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1005         [RK3128_PD_GPU]         = DOMAIN_RK3288("gpu",   BIT(1), BIT(1), BIT(3), false),
1006 };
1007
1008 static const struct rockchip_domain_info rk3188_pm_domains[] = {
1009         [RK3188_PD_GPU]         = DOMAIN("gpu",   BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1010         [RK3188_PD_VIDEO]       = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1011         [RK3188_PD_VIO]         = DOMAIN("vio",   BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1012         [RK3188_PD_PERI]        = DOMAIN("peri",  BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1013         [RK3188_PD_CPU]         = DOMAIN("cpu",   BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1014 };
1015
1016 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1017         [RK3228_PD_CORE]        = DOMAIN_RK3036("core", BIT(0),  BIT(0),  BIT(16), true),
1018         [RK3228_PD_MSCH]        = DOMAIN_RK3036("msch", BIT(1),  BIT(1),  BIT(17), true),
1019         [RK3228_PD_BUS]         = DOMAIN_RK3036("bus",  BIT(2),  BIT(2),  BIT(18), true),
1020         [RK3228_PD_SYS]         = DOMAIN_RK3036("sys",  BIT(3),  BIT(3),  BIT(19), true),
1021         [RK3228_PD_VIO]         = DOMAIN_RK3036("vio",  BIT(4),  BIT(4),  BIT(20), false),
1022         [RK3228_PD_VOP]         = DOMAIN_RK3036("vop",  BIT(5),  BIT(5),  BIT(21), false),
1023         [RK3228_PD_VPU]         = DOMAIN_RK3036("vpu",  BIT(6),  BIT(6),  BIT(22), false),
1024         [RK3228_PD_RKVDEC]      = DOMAIN_RK3036("vdec", BIT(7),  BIT(7),  BIT(23), false),
1025         [RK3228_PD_GPU]         = DOMAIN_RK3036("gpu",  BIT(8),  BIT(8),  BIT(24), false),
1026         [RK3228_PD_PERI]        = DOMAIN_RK3036("peri", BIT(9),  BIT(9),  BIT(25), true),
1027         [RK3228_PD_GMAC]        = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1028 };
1029
1030 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1031         [RK3288_PD_VIO]         = DOMAIN_RK3288("vio",   BIT(7),  BIT(7),  BIT(4), false),
1032         [RK3288_PD_HEVC]        = DOMAIN_RK3288("hevc",  BIT(14), BIT(10), BIT(9), false),
1033         [RK3288_PD_VIDEO]       = DOMAIN_RK3288("video", BIT(8),  BIT(8),  BIT(3), false),
1034         [RK3288_PD_GPU]         = DOMAIN_RK3288("gpu",   BIT(9),  BIT(9),  BIT(2), false),
1035 };
1036
1037 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1038         [RK3328_PD_CORE]        = DOMAIN_RK3328("core",  0, BIT(0), BIT(0), false),
1039         [RK3328_PD_GPU]         = DOMAIN_RK3328("gpu",   0, BIT(1), BIT(1), false),
1040         [RK3328_PD_BUS]         = DOMAIN_RK3328("bus",   0, BIT(2), BIT(2), true),
1041         [RK3328_PD_MSCH]        = DOMAIN_RK3328("msch",  0, BIT(3), BIT(3), true),
1042         [RK3328_PD_PERI]        = DOMAIN_RK3328("peri",  0, BIT(4), BIT(4), true),
1043         [RK3328_PD_VIDEO]       = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1044         [RK3328_PD_HEVC]        = DOMAIN_RK3328("hevc",  0, BIT(6), BIT(6), false),
1045         [RK3328_PD_VIO]         = DOMAIN_RK3328("vio",   0, BIT(8), BIT(8), false),
1046         [RK3328_PD_VPU]         = DOMAIN_RK3328("vpu",   0, BIT(9), BIT(9), false),
1047 };
1048
1049 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1050         [RK3366_PD_PERI]        = DOMAIN_RK3368("peri",   BIT(10), BIT(10), BIT(6), true),
1051         [RK3366_PD_VIO]         = DOMAIN_RK3368("vio",    BIT(14), BIT(14), BIT(8), false),
1052         [RK3366_PD_VIDEO]       = DOMAIN_RK3368("video",  BIT(13), BIT(13), BIT(7), false),
1053         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368("vdec",   BIT(11), BIT(11), BIT(7), false),
1054         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368("wifibt", BIT(8),  BIT(8),  BIT(9), false),
1055         [RK3366_PD_VPU]         = DOMAIN_RK3368("vpu",    BIT(12), BIT(12), BIT(7), false),
1056         [RK3366_PD_GPU]         = DOMAIN_RK3368("gpu",    BIT(15), BIT(15), BIT(2), false),
1057 };
1058
1059 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1060         [RK3368_PD_PERI]        = DOMAIN_RK3368("peri",  BIT(13), BIT(12), BIT(6), true),
1061         [RK3368_PD_VIO]         = DOMAIN_RK3368("vio",   BIT(15), BIT(14), BIT(8), false),
1062         [RK3368_PD_VIDEO]       = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1063         [RK3368_PD_GPU_0]       = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1064         [RK3368_PD_GPU_1]       = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1065 };
1066
1067 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1068         [RK3399_PD_TCPD0]       = DOMAIN_RK3399("tcpd0",     BIT(8),  BIT(8),  0,       false),
1069         [RK3399_PD_TCPD1]       = DOMAIN_RK3399("tcpd1",     BIT(9),  BIT(9),  0,       false),
1070         [RK3399_PD_CCI]         = DOMAIN_RK3399("cci",       BIT(10), BIT(10), 0,       true),
1071         [RK3399_PD_CCI0]        = DOMAIN_RK3399("cci0",      0,       0,       BIT(15), true),
1072         [RK3399_PD_CCI1]        = DOMAIN_RK3399("cci1",      0,       0,       BIT(16), true),
1073         [RK3399_PD_PERILP]      = DOMAIN_RK3399("perilp",    BIT(11), BIT(11), BIT(1),  true),
1074         [RK3399_PD_PERIHP]      = DOMAIN_RK3399("perihp",    BIT(12), BIT(12), BIT(2),  true),
1075         [RK3399_PD_CENTER]      = DOMAIN_RK3399("center",    BIT(13), BIT(13), BIT(14), true),
1076         [RK3399_PD_VIO]         = DOMAIN_RK3399("vio",       BIT(14), BIT(14), BIT(17), false),
1077         [RK3399_PD_GPU]         = DOMAIN_RK3399("gpu",       BIT(15), BIT(15), BIT(0),  false),
1078         [RK3399_PD_VCODEC]      = DOMAIN_RK3399("vcodec",    BIT(16), BIT(16), BIT(3),  false),
1079         [RK3399_PD_VDU]         = DOMAIN_RK3399("vdu",       BIT(17), BIT(17), BIT(4),  false),
1080         [RK3399_PD_RGA]         = DOMAIN_RK3399("rga",       BIT(18), BIT(18), BIT(5),  false),
1081         [RK3399_PD_IEP]         = DOMAIN_RK3399("iep",       BIT(19), BIT(19), BIT(6),  false),
1082         [RK3399_PD_VO]          = DOMAIN_RK3399("vo",        BIT(20), BIT(20), 0,       false),
1083         [RK3399_PD_VOPB]        = DOMAIN_RK3399("vopb",      0,       0,       BIT(7),  false),
1084         [RK3399_PD_VOPL]        = DOMAIN_RK3399("vopl",      0,       0,       BIT(8),  false),
1085         [RK3399_PD_ISP0]        = DOMAIN_RK3399("isp0",      BIT(22), BIT(22), BIT(9),  false),
1086         [RK3399_PD_ISP1]        = DOMAIN_RK3399("isp1",      BIT(23), BIT(23), BIT(10), false),
1087         [RK3399_PD_HDCP]        = DOMAIN_RK3399("hdcp",      BIT(24), BIT(24), BIT(11), false),
1088         [RK3399_PD_GMAC]        = DOMAIN_RK3399("gmac",      BIT(25), BIT(25), BIT(23), true),
1089         [RK3399_PD_EMMC]        = DOMAIN_RK3399("emmc",      BIT(26), BIT(26), BIT(24), true),
1090         [RK3399_PD_USB3]        = DOMAIN_RK3399("usb3",      BIT(27), BIT(27), BIT(12), true),
1091         [RK3399_PD_EDP]         = DOMAIN_RK3399("edp",       BIT(28), BIT(28), BIT(22), false),
1092         [RK3399_PD_GIC]         = DOMAIN_RK3399("gic",       BIT(29), BIT(29), BIT(27), true),
1093         [RK3399_PD_SD]          = DOMAIN_RK3399("sd",        BIT(30), BIT(30), BIT(28), true),
1094         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1095 };
1096
1097 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1098         [RK3568_PD_NPU]         = DOMAIN_RK3568("npu",  BIT(1), BIT(2),  false),
1099         [RK3568_PD_GPU]         = DOMAIN_RK3568("gpu",  BIT(0), BIT(1),  false),
1100         [RK3568_PD_VI]          = DOMAIN_RK3568("vi",   BIT(6), BIT(3),  false),
1101         [RK3568_PD_VO]          = DOMAIN_RK3568("vo",   BIT(7), BIT(4),  false),
1102         [RK3568_PD_RGA]         = DOMAIN_RK3568("rga",  BIT(5), BIT(5),  false),
1103         [RK3568_PD_VPU]         = DOMAIN_RK3568("vpu",  BIT(2), BIT(6),  false),
1104         [RK3568_PD_RKVDEC]      = DOMAIN_RK3568("vdec", BIT(4), BIT(8),  false),
1105         [RK3568_PD_RKVENC]      = DOMAIN_RK3568("venc", BIT(3), BIT(7),  false),
1106         [RK3568_PD_PIPE]        = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1107 };
1108
1109 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1110         [RK3588_PD_GPU]         = DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       0x0, 0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),
1111         [RK3588_PD_NPU]         = DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0x0, 0,       0,       0x0, 0,       0,       false),
1112         [RK3588_PD_VCODEC]      = DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0x0, 0,       0,       0x0, 0,       0,       false),
1113         [RK3588_PD_NPUTOP]      = DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       0x0, BIT(11), BIT(2),  0x0, BIT(1),  BIT(1),  false),
1114         [RK3588_PD_NPU1]        = DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       0x0, BIT(12), BIT(3),  0x0, BIT(2),  BIT(2),  false),
1115         [RK3588_PD_NPU2]        = DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       0x0, BIT(13), BIT(4),  0x0, BIT(3),  BIT(3),  false),
1116         [RK3588_PD_VENC0]       = DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       0x0, BIT(14), BIT(5),  0x0, BIT(4),  BIT(4),  false),
1117         [RK3588_PD_VENC1]       = DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       0x0, BIT(15), BIT(6),  0x0, BIT(5),  BIT(5),  false),
1118         [RK3588_PD_RKVDEC0]     = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       0x0, BIT(16), BIT(7),  0x0, BIT(6),  BIT(6),  false),
1119         [RK3588_PD_RKVDEC1]     = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       0x0, BIT(17), BIT(8),  0x0, BIT(7),  BIT(7),  false),
1120         [RK3588_PD_VDPU]        = DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       0x0, BIT(18), BIT(9),  0x0, BIT(8),  BIT(8),  false),
1121         [RK3588_PD_RGA30]       = DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       0x0, BIT(19), BIT(10), 0x0, 0,       0,       false),
1122         [RK3588_PD_AV1]         = DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       0x0, BIT(20), BIT(11), 0x0, BIT(9),  BIT(9),  false),
1123         [RK3588_PD_VI]          = DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
1124         [RK3588_PD_FEC]         = DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       0x0, BIT(22), BIT(13), 0x0, 0,       0,       false),
1125         [RK3588_PD_ISP1]        = DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
1126         [RK3588_PD_RGA31]       = DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
1127         [RK3588_PD_VOP]         = DOMAIN_RK3588("vop",     0x4, BIT(1),  0,       0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
1128         [RK3588_PD_VO0]         = DOMAIN_RK3588("vo0",     0x4, BIT(2),  0,       0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
1129         [RK3588_PD_VO1]         = DOMAIN_RK3588("vo1",     0x4, BIT(3),  0,       0x0, BIT(27), BIT(18), 0x4, BIT(0),  BIT(16), false),
1130         [RK3588_PD_AUDIO]       = DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       0x0, BIT(28), BIT(19), 0x4, BIT(1),  BIT(17), false),
1131         [RK3588_PD_PHP]         = DOMAIN_RK3588("php",     0x4, BIT(5),  0,       0x0, BIT(29), BIT(20), 0x4, BIT(5),  BIT(21), false),
1132         [RK3588_PD_GMAC]        = DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       0x0, BIT(30), BIT(21), 0x0, 0,       0,       false),
1133         [RK3588_PD_PCIE]        = DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       0x0, BIT(31), BIT(22), 0x0, 0,       0,       true),
1134         [RK3588_PD_NVM]         = DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0x4, 0,       0,       0x4, BIT(2),  BIT(18), false),
1135         [RK3588_PD_NVM0]        = DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       0x4, BIT(1),  BIT(23), 0x0, 0,       0,       false),
1136         [RK3588_PD_SDIO]        = DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       0x4, BIT(2),  BIT(24), 0x4, BIT(3),  BIT(19), false),
1137         [RK3588_PD_USB]         = DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       0x4, BIT(3),  BIT(25), 0x4, BIT(4),  BIT(20), true),
1138         [RK3588_PD_SDMMC]       = DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       0x4, BIT(5),  BIT(26), 0x0, 0,       0,       false),
1139 };
1140
1141 static const struct rockchip_pmu_info px30_pmu = {
1142         .pwr_offset = 0x18,
1143         .status_offset = 0x20,
1144         .req_offset = 0x64,
1145         .idle_offset = 0x6c,
1146         .ack_offset = 0x6c,
1147
1148         .num_domains = ARRAY_SIZE(px30_pm_domains),
1149         .domain_info = px30_pm_domains,
1150 };
1151
1152 static const struct rockchip_pmu_info rk3036_pmu = {
1153         .req_offset = 0x148,
1154         .idle_offset = 0x14c,
1155         .ack_offset = 0x14c,
1156
1157         .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1158         .domain_info = rk3036_pm_domains,
1159 };
1160
1161 static const struct rockchip_pmu_info rk3066_pmu = {
1162         .pwr_offset = 0x08,
1163         .status_offset = 0x0c,
1164         .req_offset = 0x38, /* PMU_MISC_CON1 */
1165         .idle_offset = 0x0c,
1166         .ack_offset = 0x0c,
1167
1168         .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1169         .domain_info = rk3066_pm_domains,
1170 };
1171
1172 static const struct rockchip_pmu_info rk3128_pmu = {
1173         .pwr_offset = 0x04,
1174         .status_offset = 0x08,
1175         .req_offset = 0x0c,
1176         .idle_offset = 0x10,
1177         .ack_offset = 0x10,
1178
1179         .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1180         .domain_info = rk3128_pm_domains,
1181 };
1182
1183 static const struct rockchip_pmu_info rk3188_pmu = {
1184         .pwr_offset = 0x08,
1185         .status_offset = 0x0c,
1186         .req_offset = 0x38, /* PMU_MISC_CON1 */
1187         .idle_offset = 0x0c,
1188         .ack_offset = 0x0c,
1189
1190         .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1191         .domain_info = rk3188_pm_domains,
1192 };
1193
1194 static const struct rockchip_pmu_info rk3228_pmu = {
1195         .req_offset = 0x40c,
1196         .idle_offset = 0x488,
1197         .ack_offset = 0x488,
1198
1199         .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1200         .domain_info = rk3228_pm_domains,
1201 };
1202
1203 static const struct rockchip_pmu_info rk3288_pmu = {
1204         .pwr_offset = 0x08,
1205         .status_offset = 0x0c,
1206         .req_offset = 0x10,
1207         .idle_offset = 0x14,
1208         .ack_offset = 0x14,
1209
1210         .core_pwrcnt_offset = 0x34,
1211         .gpu_pwrcnt_offset = 0x3c,
1212
1213         .core_power_transition_time = 24, /* 1us */
1214         .gpu_power_transition_time = 24, /* 1us */
1215
1216         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1217         .domain_info = rk3288_pm_domains,
1218 };
1219
1220 static const struct rockchip_pmu_info rk3328_pmu = {
1221         .req_offset = 0x414,
1222         .idle_offset = 0x484,
1223         .ack_offset = 0x484,
1224
1225         .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1226         .domain_info = rk3328_pm_domains,
1227 };
1228
1229 static const struct rockchip_pmu_info rk3366_pmu = {
1230         .pwr_offset = 0x0c,
1231         .status_offset = 0x10,
1232         .req_offset = 0x3c,
1233         .idle_offset = 0x40,
1234         .ack_offset = 0x40,
1235
1236         .core_pwrcnt_offset = 0x48,
1237         .gpu_pwrcnt_offset = 0x50,
1238
1239         .core_power_transition_time = 24,
1240         .gpu_power_transition_time = 24,
1241
1242         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1243         .domain_info = rk3366_pm_domains,
1244 };
1245
1246 static const struct rockchip_pmu_info rk3368_pmu = {
1247         .pwr_offset = 0x0c,
1248         .status_offset = 0x10,
1249         .req_offset = 0x3c,
1250         .idle_offset = 0x40,
1251         .ack_offset = 0x40,
1252
1253         .core_pwrcnt_offset = 0x48,
1254         .gpu_pwrcnt_offset = 0x50,
1255
1256         .core_power_transition_time = 24,
1257         .gpu_power_transition_time = 24,
1258
1259         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1260         .domain_info = rk3368_pm_domains,
1261 };
1262
1263 static const struct rockchip_pmu_info rk3399_pmu = {
1264         .pwr_offset = 0x14,
1265         .status_offset = 0x18,
1266         .req_offset = 0x60,
1267         .idle_offset = 0x64,
1268         .ack_offset = 0x68,
1269
1270         /* ARM Trusted Firmware manages power transition times */
1271
1272         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1273         .domain_info = rk3399_pm_domains,
1274 };
1275
1276 static const struct rockchip_pmu_info rk3568_pmu = {
1277         .pwr_offset = 0xa0,
1278         .status_offset = 0x98,
1279         .req_offset = 0x50,
1280         .idle_offset = 0x68,
1281         .ack_offset = 0x60,
1282
1283         .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1284         .domain_info = rk3568_pm_domains,
1285 };
1286
1287 static const struct rockchip_pmu_info rk3588_pmu = {
1288         .pwr_offset = 0x14c,
1289         .status_offset = 0x180,
1290         .req_offset = 0x10c,
1291         .idle_offset = 0x120,
1292         .ack_offset = 0x118,
1293         .mem_pwr_offset = 0x1a0,
1294         .chain_status_offset = 0x1f0,
1295         .mem_status_offset = 0x1f8,
1296         .repair_status_offset = 0x290,
1297
1298         .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1299         .domain_info = rk3588_pm_domains,
1300 };
1301
1302 static const struct rockchip_pmu_info rv1126_pmu = {
1303         .pwr_offset = 0x110,
1304         .status_offset = 0x108,
1305         .req_offset = 0xc0,
1306         .idle_offset = 0xd8,
1307         .ack_offset = 0xd0,
1308
1309         .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1310         .domain_info = rv1126_pm_domains,
1311 };
1312
1313 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1314         {
1315                 .compatible = "rockchip,px30-power-controller",
1316                 .data = (void *)&px30_pmu,
1317         },
1318         {
1319                 .compatible = "rockchip,rk3036-power-controller",
1320                 .data = (void *)&rk3036_pmu,
1321         },
1322         {
1323                 .compatible = "rockchip,rk3066-power-controller",
1324                 .data = (void *)&rk3066_pmu,
1325         },
1326         {
1327                 .compatible = "rockchip,rk3128-power-controller",
1328                 .data = (void *)&rk3128_pmu,
1329         },
1330         {
1331                 .compatible = "rockchip,rk3188-power-controller",
1332                 .data = (void *)&rk3188_pmu,
1333         },
1334         {
1335                 .compatible = "rockchip,rk3228-power-controller",
1336                 .data = (void *)&rk3228_pmu,
1337         },
1338         {
1339                 .compatible = "rockchip,rk3288-power-controller",
1340                 .data = (void *)&rk3288_pmu,
1341         },
1342         {
1343                 .compatible = "rockchip,rk3328-power-controller",
1344                 .data = (void *)&rk3328_pmu,
1345         },
1346         {
1347                 .compatible = "rockchip,rk3366-power-controller",
1348                 .data = (void *)&rk3366_pmu,
1349         },
1350         {
1351                 .compatible = "rockchip,rk3368-power-controller",
1352                 .data = (void *)&rk3368_pmu,
1353         },
1354         {
1355                 .compatible = "rockchip,rk3399-power-controller",
1356                 .data = (void *)&rk3399_pmu,
1357         },
1358         {
1359                 .compatible = "rockchip,rk3568-power-controller",
1360                 .data = (void *)&rk3568_pmu,
1361         },
1362         {
1363                 .compatible = "rockchip,rk3588-power-controller",
1364                 .data = (void *)&rk3588_pmu,
1365         },
1366         {
1367                 .compatible = "rockchip,rv1126-power-controller",
1368                 .data = (void *)&rv1126_pmu,
1369         },
1370         { /* sentinel */ },
1371 };
1372
1373 static struct platform_driver rockchip_pm_domain_driver = {
1374         .probe = rockchip_pm_domain_probe,
1375         .driver = {
1376                 .name   = "rockchip-pm-domain",
1377                 .of_match_table = rockchip_pm_domain_dt_match,
1378                 /*
1379                  * We can't forcibly eject devices from the power
1380                  * domain, so we can't really remove power domains
1381                  * once they were added.
1382                  */
1383                 .suppress_bind_attrs = true,
1384         },
1385 };
1386
1387 static int __init rockchip_pm_domain_drv_register(void)
1388 {
1389         return platform_driver_register(&rockchip_pm_domain_driver);
1390 }
1391 postcore_initcall(rockchip_pm_domain_drv_register);