1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited
7 #include <linux/module.h>
9 #include <linux/debugfs.h>
10 #include <linux/string.h>
11 #include <linux/kernel.h>
12 #include <linux/list.h>
13 #include <linux/init.h>
15 #include <linux/bitops.h>
16 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_domain.h>
20 #include <linux/pm_opp.h>
21 #include <linux/interrupt.h>
22 #include <linux/regmap.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/clk.h>
26 #include <linux/nvmem-consumer.h>
28 /* Register Offsets for RB-CPR and Bit Definitions */
30 /* RBCPR Version Register */
31 #define REG_RBCPR_VERSION 0
32 #define RBCPR_VER_2 0x02
33 #define FLAGS_IGNORE_1ST_IRQ_STATUS BIT(0)
35 /* RBCPR Gate Count and Target Registers */
36 #define REG_RBCPR_GCNT_TARGET(n) (0x60 + 4 * (n))
38 #define RBCPR_GCNT_TARGET_TARGET_SHIFT 0
39 #define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0)
40 #define RBCPR_GCNT_TARGET_GCNT_SHIFT 12
41 #define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0)
43 /* RBCPR Timer Control */
44 #define REG_RBCPR_TIMER_INTERVAL 0x44
45 #define REG_RBIF_TIMER_ADJUST 0x4c
47 #define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0)
48 #define RBIF_TIMER_ADJ_CONS_UP_SHIFT 0
49 #define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0)
50 #define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4
51 #define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0)
52 #define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8
54 /* RBCPR Config Register */
55 #define REG_RBIF_LIMIT 0x48
56 #define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0)
57 #define RBIF_LIMIT_CEILING_SHIFT 6
58 #define RBIF_LIMIT_FLOOR_BITS 6
59 #define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0)
61 #define RBIF_LIMIT_CEILING_DEFAULT RBIF_LIMIT_CEILING_MASK
62 #define RBIF_LIMIT_FLOOR_DEFAULT 0
64 #define REG_RBIF_SW_VLEVEL 0x94
65 #define RBIF_SW_VLEVEL_DEFAULT 0x20
67 #define REG_RBCPR_STEP_QUOT 0x80
68 #define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0)
69 #define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0)
70 #define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8
72 /* RBCPR Control Register */
73 #define REG_RBCPR_CTL 0x90
75 #define RBCPR_CTL_LOOP_EN BIT(0)
76 #define RBCPR_CTL_TIMER_EN BIT(3)
77 #define RBCPR_CTL_SW_AUTO_CONT_ACK_EN BIT(5)
78 #define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN BIT(6)
79 #define RBCPR_CTL_COUNT_MODE BIT(10)
80 #define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0)
81 #define RBCPR_CTL_UP_THRESHOLD_SHIFT 24
82 #define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0)
83 #define RBCPR_CTL_DN_THRESHOLD_SHIFT 28
85 /* RBCPR Ack/Nack Response */
86 #define REG_RBIF_CONT_ACK_CMD 0x98
87 #define REG_RBIF_CONT_NACK_CMD 0x9c
89 /* RBCPR Result status Register */
90 #define REG_RBCPR_RESULT_0 0xa0
92 #define RBCPR_RESULT0_BUSY_SHIFT 19
93 #define RBCPR_RESULT0_BUSY_MASK BIT(RBCPR_RESULT0_BUSY_SHIFT)
94 #define RBCPR_RESULT0_ERROR_LT0_SHIFT 18
95 #define RBCPR_RESULT0_ERROR_SHIFT 6
96 #define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0)
97 #define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
98 #define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)
99 #define RBCPR_RESULT0_STEP_UP_SHIFT 1
101 /* RBCPR Interrupt Control Register */
102 #define REG_RBIF_IRQ_EN(n) (0x100 + 4 * (n))
103 #define REG_RBIF_IRQ_CLEAR 0x110
104 #define REG_RBIF_IRQ_STATUS 0x114
106 #define CPR_INT_DONE BIT(0)
107 #define CPR_INT_MIN BIT(1)
108 #define CPR_INT_DOWN BIT(2)
109 #define CPR_INT_MID BIT(3)
110 #define CPR_INT_UP BIT(4)
111 #define CPR_INT_MAX BIT(5)
112 #define CPR_INT_CLAMP BIT(6)
113 #define CPR_INT_ALL (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
114 CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
115 #define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN)
117 #define CPR_NUM_RING_OSC 8
119 /* CPR eFuse parameters */
120 #define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)
122 #define CPR_FUSE_MIN_QUOT_DIFF 50
124 #define FUSE_REVISION_UNKNOWN (-1)
126 enum voltage_change_dir {
136 char *quotient_offset;
139 struct fuse_corner_data {
149 /* fuse quot_offset */
150 int quot_offset_scale;
151 int quot_offset_adjust;
155 int init_voltage_step;
156 int init_voltage_width;
157 struct fuse_corner_data *fuse_corner_data;
161 unsigned int fuse_corner;
166 unsigned int num_fuse_corners;
170 unsigned int timer_delay_us;
171 unsigned int timer_cons_up;
172 unsigned int timer_cons_down;
173 unsigned int up_threshold;
174 unsigned int down_threshold;
175 unsigned int idle_clocks;
176 unsigned int gcnt_us;
177 unsigned int vdd_apc_step_up_limit;
178 unsigned int vdd_apc_step_down_limit;
179 unsigned int clamp_timer_interval;
181 struct cpr_fuses cpr_fuses;
182 bool reduce_to_fuse_uV;
183 bool reduce_to_corner_uV;
187 unsigned int enable_reg;
190 struct reg_sequence *config;
191 struct reg_sequence *settings;
192 int num_regs_per_fuse;
195 struct cpr_acc_desc {
196 const struct cpr_desc *cpr_desc;
197 const struct acc_desc *acc_desc;
206 const struct reg_sequence *accs;
208 unsigned long max_freq;
221 struct fuse_corner *fuse_corner;
225 unsigned int num_corners;
226 unsigned int ref_clk_khz;
228 struct generic_pm_domain pd;
230 struct device *attached_cpu_dev;
233 struct corner *corner;
234 struct regulator *vdd_apc;
241 struct fuse_corner *fuse_corners;
242 struct corner *corners;
244 const struct cpr_desc *desc;
245 const struct acc_desc *acc_desc;
246 const struct cpr_fuse *cpr_fuses;
248 struct dentry *debugfs;
251 static bool cpr_is_allowed(struct cpr_drv *drv)
253 return !drv->loop_disabled;
256 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
258 writel_relaxed(value, drv->base + offset);
261 static u32 cpr_read(struct cpr_drv *drv, u32 offset)
263 return readl_relaxed(drv->base + offset);
267 cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
271 val = readl_relaxed(drv->base + offset);
274 writel_relaxed(val, drv->base + offset);
277 static void cpr_irq_clr(struct cpr_drv *drv)
279 cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
282 static void cpr_irq_clr_nack(struct cpr_drv *drv)
285 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
288 static void cpr_irq_clr_ack(struct cpr_drv *drv)
291 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
294 static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
296 cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
299 static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
301 cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
304 static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
307 const struct cpr_desc *desc = drv->desc;
309 /* Program Consecutive Up & Down */
310 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
311 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
312 mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
313 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
314 cpr_masked_write(drv, REG_RBCPR_CTL,
315 RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
316 RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
318 cpr_irq_set(drv, corner->save_irq);
320 if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV)
321 val = RBCPR_CTL_LOOP_EN;
324 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
327 static void cpr_ctl_disable(struct cpr_drv *drv)
330 cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
331 RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
332 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
333 RBIF_TIMER_ADJ_CONS_UP_MASK |
334 RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
336 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
337 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
338 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
341 static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
345 reg_val = cpr_read(drv, REG_RBCPR_CTL);
346 return reg_val & RBCPR_CTL_LOOP_EN;
349 static bool cpr_ctl_is_busy(struct cpr_drv *drv)
353 reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
354 return reg_val & RBCPR_RESULT0_BUSY_MASK;
357 static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
359 corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
360 corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
363 static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
365 u32 gcnt, ctl, irq, ro_sel, step_quot;
366 struct fuse_corner *fuse = corner->fuse_corner;
367 const struct cpr_desc *desc = drv->desc;
370 ro_sel = fuse->ring_osc_idx;
372 gcnt |= fuse->quot - corner->quot_adjust;
374 /* Program the step quotient and idle clocks */
375 step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
376 step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
377 cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
379 /* Clear the target quotient value and gate count of all ROs */
380 for (i = 0; i < CPR_NUM_RING_OSC; i++)
381 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
383 cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
384 ctl = corner->save_ctl;
385 cpr_write(drv, REG_RBCPR_CTL, ctl);
386 irq = corner->save_irq;
387 cpr_irq_set(drv, irq);
388 dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt,
392 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
393 struct fuse_corner *end)
399 for (f += 1; f <= end; f++)
400 regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
402 for (f -= 1; f >= end; f--)
403 regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
407 static int cpr_pre_voltage(struct cpr_drv *drv,
408 struct fuse_corner *fuse_corner,
409 enum voltage_change_dir dir)
411 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
413 if (drv->tcsr && dir == DOWN)
414 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
419 static int cpr_post_voltage(struct cpr_drv *drv,
420 struct fuse_corner *fuse_corner,
421 enum voltage_change_dir dir)
423 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
425 if (drv->tcsr && dir == UP)
426 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
431 static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
432 int new_uV, enum voltage_change_dir dir)
435 struct fuse_corner *fuse_corner = corner->fuse_corner;
437 ret = cpr_pre_voltage(drv, fuse_corner, dir);
441 ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
443 dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
448 ret = cpr_post_voltage(drv, fuse_corner, dir);
455 static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv)
457 return drv->corner ? drv->corner - drv->corners + 1 : 0;
460 static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
462 u32 val, error_steps, reg_mask;
463 int last_uV, new_uV, step_uV, ret;
464 struct corner *corner;
465 const struct cpr_desc *desc = drv->desc;
467 if (dir != UP && dir != DOWN)
470 step_uV = regulator_get_linear_step(drv->vdd_apc);
474 corner = drv->corner;
476 val = cpr_read(drv, REG_RBCPR_RESULT_0);
478 error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
479 error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
480 last_uV = corner->last_uV;
483 if (desc->clamp_timer_interval &&
484 error_steps < desc->up_threshold) {
486 * Handle the case where another measurement started
487 * after the interrupt was triggered due to a core
488 * exiting from power collapse.
490 error_steps = max(desc->up_threshold,
491 desc->vdd_apc_step_up_limit);
494 if (last_uV >= corner->max_uV) {
495 cpr_irq_clr_nack(drv);
497 /* Maximize the UP threshold */
498 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
499 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
501 cpr_ctl_modify(drv, reg_mask, val);
503 /* Disable UP interrupt */
504 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
509 if (error_steps > desc->vdd_apc_step_up_limit)
510 error_steps = desc->vdd_apc_step_up_limit;
512 /* Calculate new voltage */
513 new_uV = last_uV + error_steps * step_uV;
514 new_uV = min(new_uV, corner->max_uV);
517 "UP: -> new_uV: %d last_uV: %d perf state: %u\n",
518 new_uV, last_uV, cpr_get_cur_perf_state(drv));
520 if (desc->clamp_timer_interval &&
521 error_steps < desc->down_threshold) {
523 * Handle the case where another measurement started
524 * after the interrupt was triggered due to a core
525 * exiting from power collapse.
527 error_steps = max(desc->down_threshold,
528 desc->vdd_apc_step_down_limit);
531 if (last_uV <= corner->min_uV) {
532 cpr_irq_clr_nack(drv);
534 /* Enable auto nack down */
535 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
536 val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
538 cpr_ctl_modify(drv, reg_mask, val);
540 /* Disable DOWN interrupt */
541 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
546 if (error_steps > desc->vdd_apc_step_down_limit)
547 error_steps = desc->vdd_apc_step_down_limit;
549 /* Calculate new voltage */
550 new_uV = last_uV - error_steps * step_uV;
551 new_uV = max(new_uV, corner->min_uV);
554 "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n",
555 new_uV, last_uV, cpr_get_cur_perf_state(drv));
558 ret = cpr_scale_voltage(drv, corner, new_uV, dir);
560 cpr_irq_clr_nack(drv);
563 drv->corner->last_uV = new_uV;
566 /* Disable auto nack down */
567 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
570 /* Restore default threshold for UP */
571 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
572 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
573 val = desc->up_threshold;
574 val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
577 cpr_ctl_modify(drv, reg_mask, val);
579 /* Re-enable default interrupts */
580 cpr_irq_set(drv, CPR_INT_DEFAULT);
583 cpr_irq_clr_ack(drv);
588 static irqreturn_t cpr_irq_handler(int irq, void *dev)
590 struct cpr_drv *drv = dev;
591 const struct cpr_desc *desc = drv->desc;
592 irqreturn_t ret = IRQ_HANDLED;
595 mutex_lock(&drv->lock);
597 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
598 if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
599 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
601 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
603 if (!cpr_ctl_is_enabled(drv)) {
604 dev_dbg(drv->dev, "CPR is disabled\n");
606 } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) {
607 dev_dbg(drv->dev, "CPR measurement is not ready\n");
608 } else if (!cpr_is_allowed(drv)) {
609 val = cpr_read(drv, REG_RBCPR_CTL);
610 dev_err_ratelimited(drv->dev,
611 "Interrupt broken? RBCPR_CTL = %#02x\n",
616 * Following sequence of handling is as per each IRQ's
619 if (val & CPR_INT_UP) {
621 } else if (val & CPR_INT_DOWN) {
622 cpr_scale(drv, DOWN);
623 } else if (val & CPR_INT_MIN) {
624 cpr_irq_clr_nack(drv);
625 } else if (val & CPR_INT_MAX) {
626 cpr_irq_clr_nack(drv);
627 } else if (val & CPR_INT_MID) {
628 /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
629 dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
632 "IRQ occurred for unknown flag (%#08x)\n", val);
635 /* Save register values for the corner */
636 cpr_corner_save(drv, drv->corner);
639 mutex_unlock(&drv->lock);
644 static int cpr_enable(struct cpr_drv *drv)
648 ret = regulator_enable(drv->vdd_apc);
652 mutex_lock(&drv->lock);
654 if (cpr_is_allowed(drv) && drv->corner) {
656 cpr_corner_restore(drv, drv->corner);
657 cpr_ctl_enable(drv, drv->corner);
660 mutex_unlock(&drv->lock);
665 static int cpr_disable(struct cpr_drv *drv)
667 mutex_lock(&drv->lock);
669 if (cpr_is_allowed(drv)) {
670 cpr_ctl_disable(drv);
674 mutex_unlock(&drv->lock);
676 return regulator_disable(drv->vdd_apc);
679 static int cpr_config(struct cpr_drv *drv)
683 struct corner *corner;
684 const struct cpr_desc *desc = drv->desc;
686 /* Disable interrupt and CPR */
687 cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
688 cpr_write(drv, REG_RBCPR_CTL, 0);
690 /* Program the default HW ceiling, floor and vlevel */
691 val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
692 << RBIF_LIMIT_CEILING_SHIFT;
693 val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
694 cpr_write(drv, REG_RBIF_LIMIT, val);
695 cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
698 * Clear the target quotient value and gate count of all
701 for (i = 0; i < CPR_NUM_RING_OSC; i++)
702 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
704 /* Init and save gcnt */
705 gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000;
706 gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
707 gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
710 /* Program the delay count for the timer */
711 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
712 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
713 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
714 desc->timer_delay_us);
716 /* Program Consecutive Up & Down */
717 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
718 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
719 val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
720 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
722 /* Program the control register */
723 val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
724 val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
725 val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
726 val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
727 cpr_write(drv, REG_RBCPR_CTL, val);
729 for (i = 0; i < drv->num_corners; i++) {
730 corner = &drv->corners[i];
731 corner->save_ctl = val;
732 corner->save_irq = CPR_INT_DEFAULT;
735 cpr_irq_set(drv, CPR_INT_DEFAULT);
737 val = cpr_read(drv, REG_RBCPR_VERSION);
738 if (val <= RBCPR_VER_2)
739 drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
744 static int cpr_set_performance_state(struct generic_pm_domain *domain,
747 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
748 struct corner *corner, *end;
749 enum voltage_change_dir dir;
752 mutex_lock(&drv->lock);
754 dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n",
755 __func__, state, cpr_get_cur_perf_state(drv));
758 * Determine new corner we're going to.
759 * Remove one since lowest performance state is 1.
761 corner = drv->corners + state - 1;
762 end = &drv->corners[drv->num_corners - 1];
763 if (corner > end || corner < drv->corners) {
768 /* Determine direction */
769 if (drv->corner > corner)
771 else if (drv->corner < corner)
776 if (cpr_is_allowed(drv))
777 new_uV = corner->last_uV;
781 if (cpr_is_allowed(drv))
782 cpr_ctl_disable(drv);
784 ret = cpr_scale_voltage(drv, corner, new_uV, dir);
788 if (cpr_is_allowed(drv)) {
790 if (drv->corner != corner)
791 cpr_corner_restore(drv, corner);
792 cpr_ctl_enable(drv, corner);
795 drv->corner = corner;
798 mutex_unlock(&drv->lock);
804 cpr_populate_ring_osc_idx(struct cpr_drv *drv)
806 struct fuse_corner *fuse = drv->fuse_corners;
807 struct fuse_corner *end = fuse + drv->desc->num_fuse_corners;
808 const struct cpr_fuse *fuses = drv->cpr_fuses;
812 for (; fuse < end; fuse++, fuses++) {
813 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data);
816 fuse->ring_osc_idx = data;
822 static int cpr_read_fuse_uV(const struct cpr_desc *desc,
823 const struct fuse_corner_data *fdata,
824 const char *init_v_efuse,
828 int step_size_uV, steps, uV;
832 ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits);
836 steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);
837 /* Not two's complement.. instead highest bit is sign bit */
838 if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1))
841 step_size_uV = desc->cpr_fuses.init_voltage_step;
843 uV = fdata->ref_uV + steps * step_size_uV;
844 return DIV_ROUND_UP(uV, step_volt) * step_volt;
847 static int cpr_fuse_corner_init(struct cpr_drv *drv)
849 const struct cpr_desc *desc = drv->desc;
850 const struct cpr_fuse *fuses = drv->cpr_fuses;
851 const struct acc_desc *acc_desc = drv->acc_desc;
853 unsigned int step_volt;
854 struct fuse_corner_data *fdata;
855 struct fuse_corner *fuse, *end;
857 const struct reg_sequence *accs;
860 accs = acc_desc->settings;
862 step_volt = regulator_get_linear_step(drv->vdd_apc);
866 /* Populate fuse_corner members */
867 fuse = drv->fuse_corners;
868 end = &fuse[desc->num_fuse_corners - 1];
869 fdata = desc->cpr_fuses.fuse_corner_data;
871 for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) {
873 * Update SoC voltages: platforms might choose a different
874 * regulators than the one used to characterize the algorithms
875 * (ie, init_voltage_step).
877 fdata->min_uV = roundup(fdata->min_uV, step_volt);
878 fdata->max_uV = roundup(fdata->max_uV, step_volt);
881 uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
886 fuse->min_uV = fdata->min_uV;
887 fuse->max_uV = fdata->max_uV;
888 fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
892 * Allow the highest fuse corner's PVS voltage to
893 * define the ceiling voltage for that corner in order
894 * to support SoC's in which variable ceiling values
897 end->max_uV = max(end->max_uV, end->uV);
900 /* Populate target quotient by scaling */
901 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot);
905 fuse->quot *= fdata->quot_scale;
906 fuse->quot += fdata->quot_offset;
907 fuse->quot += fdata->quot_adjust;
908 fuse->step_quot = desc->step_quot[fuse->ring_osc_idx];
910 /* Populate acc settings */
912 fuse->num_accs = acc_desc->num_regs_per_fuse;
913 accs += acc_desc->num_regs_per_fuse;
917 * Restrict all fuse corner PVS voltages based upon per corner
918 * ceiling and floor voltages.
920 for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
921 if (fuse->uV > fuse->max_uV)
922 fuse->uV = fuse->max_uV;
923 else if (fuse->uV < fuse->min_uV)
924 fuse->uV = fuse->min_uV;
926 ret = regulator_is_supported_voltage(drv->vdd_apc,
931 "min uV: %d (fuse corner: %d) not supported by regulator\n",
936 ret = regulator_is_supported_voltage(drv->vdd_apc,
941 "max uV: %d (fuse corner: %d) not supported by regulator\n",
947 "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n",
948 i, fuse->min_uV, fuse->uV, fuse->max_uV,
949 fuse->ring_osc_idx, fuse->quot, fuse->step_quot);
955 static int cpr_calculate_scaling(const char *quot_offset,
957 const struct fuse_corner_data *fdata,
958 const struct corner *corner)
961 unsigned long freq_diff;
963 const struct fuse_corner *fuse, *prev_fuse;
966 fuse = corner->fuse_corner;
967 prev_fuse = fuse - 1;
970 ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff);
974 quot_diff *= fdata->quot_offset_scale;
975 quot_diff += fdata->quot_offset_adjust;
977 quot_diff = fuse->quot - prev_fuse->quot;
980 freq_diff = fuse->max_freq - prev_fuse->max_freq;
981 freq_diff /= 1000000; /* Convert to MHz */
982 scaling = 1000 * quot_diff / freq_diff;
983 return min(scaling, fdata->max_quot_scale);
986 static int cpr_interpolate(const struct corner *corner, int step_volt,
987 const struct fuse_corner_data *fdata)
989 unsigned long f_high, f_low, f_diff;
990 int uV_high, uV_low, uV;
991 u64 temp, temp_limit;
992 const struct fuse_corner *fuse, *prev_fuse;
994 fuse = corner->fuse_corner;
995 prev_fuse = fuse - 1;
997 f_high = fuse->max_freq;
998 f_low = prev_fuse->max_freq;
1000 uV_low = prev_fuse->uV;
1001 f_diff = fuse->max_freq - corner->freq;
1004 * Don't interpolate in the wrong direction. This could happen
1005 * if the adjusted fuse voltage overlaps with the previous fuse's
1008 if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
1011 temp = f_diff * (uV_high - uV_low);
1012 temp = div64_ul(temp, f_high - f_low);
1015 * max_volt_scale has units of uV/MHz while freq values
1016 * have units of Hz. Divide by 1000000 to convert to.
1018 temp_limit = f_diff * fdata->max_volt_scale;
1019 do_div(temp_limit, 1000000);
1021 uV = uV_high - min(temp, temp_limit);
1022 return roundup(uV, step_volt);
1025 static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
1027 struct device_node *np;
1028 unsigned int fuse_corner = 0;
1030 np = dev_pm_opp_get_of_node(opp);
1031 if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner))
1032 pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
1040 static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref,
1041 struct device *cpu_dev)
1044 struct device_node *ref_np;
1045 struct device_node *desc_np;
1046 struct device_node *child_np = NULL;
1047 struct device_node *child_req_np = NULL;
1049 desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
1053 ref_np = dev_pm_opp_get_of_node(ref);
1058 of_node_put(child_req_np);
1059 child_np = of_get_next_available_child(desc_np, child_np);
1060 child_req_np = of_parse_phandle(child_np, "required-opps", 0);
1061 } while (child_np && child_req_np != ref_np);
1063 if (child_np && child_req_np == ref_np)
1064 of_property_read_u64(child_np, "opp-hz", &rate);
1066 of_node_put(child_req_np);
1067 of_node_put(child_np);
1068 of_node_put(ref_np);
1070 of_node_put(desc_np);
1072 return (unsigned long) rate;
1075 static int cpr_corner_init(struct cpr_drv *drv)
1077 const struct cpr_desc *desc = drv->desc;
1078 const struct cpr_fuse *fuses = drv->cpr_fuses;
1079 int i, level, scaling = 0;
1080 unsigned int fnum, fc;
1081 const char *quot_offset;
1082 struct fuse_corner *fuse, *prev_fuse;
1083 struct corner *corner, *end;
1084 struct corner_data *cdata;
1085 const struct fuse_corner_data *fdata;
1087 unsigned long freq_diff, freq_diff_mhz;
1089 int step_volt = regulator_get_linear_step(drv->vdd_apc);
1090 struct dev_pm_opp *opp;
1095 corner = drv->corners;
1096 end = &corner[drv->num_corners - 1];
1098 cdata = devm_kcalloc(drv->dev, drv->num_corners,
1099 sizeof(struct corner_data),
1105 * Store maximum frequency for each fuse corner based on the frequency
1108 for (level = 1; level <= drv->num_corners; level++) {
1109 opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level);
1112 fc = cpr_get_fuse_corner(opp);
1114 dev_pm_opp_put(opp);
1118 freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev);
1120 dev_pm_opp_put(opp);
1123 cdata[level - 1].fuse_corner = fnum;
1124 cdata[level - 1].freq = freq;
1126 fuse = &drv->fuse_corners[fnum];
1127 dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
1128 freq, dev_pm_opp_get_level(opp) - 1, fnum);
1129 if (freq > fuse->max_freq)
1130 fuse->max_freq = freq;
1131 dev_pm_opp_put(opp);
1135 * Get the quotient adjustment scaling factor, according to:
1137 * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
1138 * / (freq(corner_N) - freq(corner_N-1)), max_factor)
1140 * QUOT(corner_N): quotient read from fuse for fuse corner N
1141 * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1)
1142 * freq(corner_N): max frequency in MHz supported by fuse corner N
1143 * freq(corner_N-1): max frequency in MHz supported by fuse corner
1146 * Then walk through the corners mapped to each fuse corner
1147 * and calculate the quotient adjustment for each one using the
1148 * following formula:
1150 * quot_adjust = (freq_max - freq_corner) * scaling / 1000
1152 * freq_max: max frequency in MHz supported by the fuse corner
1153 * freq_corner: frequency in MHz corresponding to the corner
1154 * scaling: calculated from above equation
1165 * +--------------- +----------------
1166 * 0 1 2 3 4 5 6 0 1 2 3 4 5 6
1173 for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
1174 fnum = cdata[i].fuse_corner;
1175 fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
1176 quot_offset = fuses[fnum].quotient_offset;
1177 fuse = &drv->fuse_corners[fnum];
1179 prev_fuse = &drv->fuse_corners[fnum - 1];
1183 corner->fuse_corner = fuse;
1184 corner->freq = cdata[i].freq;
1185 corner->uV = fuse->uV;
1187 if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
1188 scaling = cpr_calculate_scaling(quot_offset, drv,
1193 apply_scaling = true;
1194 } else if (corner->freq == fuse->max_freq) {
1195 /* This is a fuse corner; don't scale anything */
1196 apply_scaling = false;
1199 if (apply_scaling) {
1200 freq_diff = fuse->max_freq - corner->freq;
1201 freq_diff_mhz = freq_diff / 1000000;
1202 corner->quot_adjust = scaling * freq_diff_mhz / 1000;
1204 corner->uV = cpr_interpolate(corner, step_volt, fdata);
1207 corner->max_uV = fuse->max_uV;
1208 corner->min_uV = fuse->min_uV;
1209 corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
1210 corner->last_uV = corner->uV;
1212 /* Reduce the ceiling voltage if needed */
1213 if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
1214 corner->max_uV = corner->uV;
1215 else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
1216 corner->max_uV = max(corner->min_uV, fuse->uV);
1218 dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
1219 corner->min_uV, corner->uV, corner->max_uV,
1220 fuse->quot - corner->quot_adjust);
1226 static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
1228 const struct cpr_desc *desc = drv->desc;
1229 struct cpr_fuse *fuses;
1232 fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners,
1233 sizeof(struct cpr_fuse),
1236 return ERR_PTR(-ENOMEM);
1238 for (i = 0; i < desc->num_fuse_corners; i++) {
1241 snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
1242 fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
1243 if (!fuses[i].ring_osc)
1244 return ERR_PTR(-ENOMEM);
1246 snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
1247 fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
1249 if (!fuses[i].init_voltage)
1250 return ERR_PTR(-ENOMEM);
1252 snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
1253 fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
1254 if (!fuses[i].quotient)
1255 return ERR_PTR(-ENOMEM);
1257 snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
1258 fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
1260 if (!fuses[i].quotient_offset)
1261 return ERR_PTR(-ENOMEM);
1267 static void cpr_set_loop_allowed(struct cpr_drv *drv)
1269 drv->loop_disabled = false;
1272 static int cpr_init_parameters(struct cpr_drv *drv)
1274 const struct cpr_desc *desc = drv->desc;
1277 clk = clk_get(drv->dev, "ref");
1279 return PTR_ERR(clk);
1281 drv->ref_clk_khz = clk_get_rate(clk) / 1000;
1284 if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK ||
1285 desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK ||
1286 desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK ||
1287 desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK ||
1288 desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK ||
1289 desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK)
1292 dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
1293 desc->up_threshold, desc->down_threshold);
1298 static int cpr_find_initial_corner(struct cpr_drv *drv)
1301 const struct corner *end;
1302 struct corner *iter;
1305 if (!drv->cpu_clk) {
1306 dev_err(drv->dev, "cannot get rate from NULL clk\n");
1310 end = &drv->corners[drv->num_corners - 1];
1311 rate = clk_get_rate(drv->cpu_clk);
1314 * Some bootloaders set a CPU clock frequency that is not defined
1315 * in the OPP table. When running at an unlisted frequency,
1316 * cpufreq_online() will change to the OPP which has the lowest
1317 * frequency, at or above the unlisted frequency.
1318 * Since cpufreq_online() always "rounds up" in the case of an
1319 * unlisted frequency, this function always "rounds down" in case
1320 * of an unlisted frequency. That way, when cpufreq_online()
1321 * triggers the first ever call to cpr_set_performance_state(),
1322 * it will correctly determine the direction as UP.
1324 for (iter = drv->corners; iter <= end; iter++) {
1325 if (iter->freq > rate)
1328 if (iter->freq == rate) {
1332 if (iter->freq < rate)
1337 dev_err(drv->dev, "boot up corner not found\n");
1341 dev_dbg(drv->dev, "boot up perf state: %u\n", i);
1346 static const struct cpr_desc qcs404_cpr_desc = {
1347 .num_fuse_corners = 3,
1348 .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
1349 .step_quot = (int []){ 25, 25, 25, },
1350 .timer_delay_us = 5000,
1352 .timer_cons_down = 2,
1354 .down_threshold = 3,
1357 .vdd_apc_step_up_limit = 1,
1358 .vdd_apc_step_down_limit = 1,
1360 .init_voltage_step = 8000,
1361 .init_voltage_width = 6,
1362 .fuse_corner_data = (struct fuse_corner_data[]){
1368 .max_volt_scale = 0,
1369 .max_quot_scale = 0,
1373 .quot_offset_scale = 5,
1374 .quot_offset_adjust = 0,
1381 .max_volt_scale = 2000,
1382 .max_quot_scale = 1400,
1386 .quot_offset_scale = 5,
1387 .quot_offset_adjust = 0,
1394 .max_volt_scale = 2000,
1395 .max_quot_scale = 1400,
1399 .quot_offset_scale = 5,
1400 .quot_offset_adjust = 0,
1406 static const struct acc_desc qcs404_acc_desc = {
1407 .settings = (struct reg_sequence[]){
1408 { 0xb120, 0x1041040 },
1415 .config = (struct reg_sequence[]){
1419 .num_regs_per_fuse = 2,
1422 static const struct cpr_acc_desc qcs404_cpr_acc_desc = {
1423 .cpr_desc = &qcs404_cpr_desc,
1424 .acc_desc = &qcs404_acc_desc,
1427 static int cpr_power_off(struct generic_pm_domain *domain)
1429 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
1431 return cpr_disable(drv);
1434 static int cpr_power_on(struct generic_pm_domain *domain)
1436 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
1438 return cpr_enable(drv);
1441 static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
1444 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
1445 const struct acc_desc *acc_desc = drv->acc_desc;
1448 mutex_lock(&drv->lock);
1450 dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
1453 * This driver only supports scaling voltage for a CPU cluster
1454 * where all CPUs in the cluster share a single regulator.
1455 * Therefore, save the struct device pointer only for the first
1456 * CPU device that gets attached. There is no need to do any
1457 * additional initialization when further CPUs get attached.
1459 if (drv->attached_cpu_dev)
1463 * cpr_scale_voltage() requires the direction (if we are changing
1464 * to a higher or lower OPP). The first time
1465 * cpr_set_performance_state() is called, there is no previous
1466 * performance state defined. Therefore, we call
1467 * cpr_find_initial_corner() that gets the CPU clock frequency
1468 * set by the bootloader, so that we can determine the direction
1469 * the first time cpr_set_performance_state() is called.
1471 drv->cpu_clk = devm_clk_get(dev, NULL);
1472 if (IS_ERR(drv->cpu_clk)) {
1473 ret = PTR_ERR(drv->cpu_clk);
1474 if (ret != -EPROBE_DEFER)
1475 dev_err(drv->dev, "could not get cpu clk: %d\n", ret);
1478 drv->attached_cpu_dev = dev;
1480 dev_dbg(drv->dev, "using cpu clk from: %s\n",
1481 dev_name(drv->attached_cpu_dev));
1484 * Everything related to (virtual) corners has to be initialized
1485 * here, when attaching to the power domain, since we need to know
1486 * the maximum frequency for each fuse corner, and this is only
1487 * available after the cpufreq driver has attached to us.
1488 * The reason for this is that we need to know the highest
1489 * frequency associated with each fuse corner.
1491 ret = dev_pm_opp_get_opp_count(&drv->pd.dev);
1493 dev_err(drv->dev, "could not get OPP count\n");
1496 drv->num_corners = ret;
1498 if (drv->num_corners < 2) {
1499 dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
1504 drv->corners = devm_kcalloc(drv->dev, drv->num_corners,
1505 sizeof(*drv->corners),
1507 if (!drv->corners) {
1512 ret = cpr_corner_init(drv);
1516 cpr_set_loop_allowed(drv);
1518 ret = cpr_init_parameters(drv);
1522 /* Configure CPR HW but keep it disabled */
1523 ret = cpr_config(drv);
1527 ret = cpr_find_initial_corner(drv);
1531 if (acc_desc->config)
1532 regmap_multi_reg_write(drv->tcsr, acc_desc->config,
1533 acc_desc->num_regs_per_fuse);
1535 /* Enable ACC if required */
1536 if (acc_desc->enable_mask)
1537 regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
1538 acc_desc->enable_mask,
1539 acc_desc->enable_mask);
1541 dev_info(drv->dev, "driver initialized with %u OPPs\n",
1545 mutex_unlock(&drv->lock);
1550 static int cpr_debug_info_show(struct seq_file *s, void *unused)
1552 u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
1553 u32 step_dn, step_up, error, error_lt0, busy;
1554 struct cpr_drv *drv = s->private;
1555 struct fuse_corner *fuse_corner;
1556 struct corner *corner;
1558 corner = drv->corner;
1559 fuse_corner = corner->fuse_corner;
1561 seq_printf(s, "corner, current_volt = %d uV\n",
1564 ro_sel = fuse_corner->ring_osc_idx;
1565 gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
1566 seq_printf(s, "rbcpr_gcnt_target (%u) = %#02X\n", ro_sel, gcnt);
1568 ctl = cpr_read(drv, REG_RBCPR_CTL);
1569 seq_printf(s, "rbcpr_ctl = %#02X\n", ctl);
1571 irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
1572 seq_printf(s, "rbcpr_irq_status = %#02X\n", irq_status);
1574 reg = cpr_read(drv, REG_RBCPR_RESULT_0);
1575 seq_printf(s, "rbcpr_result_0 = %#02X\n", reg);
1577 step_dn = reg & 0x01;
1578 step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
1579 seq_printf(s, " [step_dn = %u", step_dn);
1581 seq_printf(s, ", step_up = %u", step_up);
1583 error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
1584 & RBCPR_RESULT0_ERROR_STEPS_MASK;
1585 seq_printf(s, ", error_steps = %u", error_steps);
1587 error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
1588 seq_printf(s, ", error = %u", error);
1590 error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
1591 seq_printf(s, ", error_lt_0 = %u", error_lt0);
1593 busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
1594 seq_printf(s, ", busy = %u]\n", busy);
1598 DEFINE_SHOW_ATTRIBUTE(cpr_debug_info);
1600 static void cpr_debugfs_init(struct cpr_drv *drv)
1602 drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
1604 debugfs_create_file("debug_info", 0444, drv->debugfs,
1605 drv, &cpr_debug_info_fops);
1608 static int cpr_probe(struct platform_device *pdev)
1610 struct device *dev = &pdev->dev;
1611 struct cpr_drv *drv;
1613 const struct cpr_acc_desc *data;
1614 struct device_node *np;
1615 u32 cpr_rev = FUSE_REVISION_UNKNOWN;
1617 data = of_device_get_match_data(dev);
1618 if (!data || !data->cpr_desc || !data->acc_desc)
1621 drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
1625 drv->desc = data->cpr_desc;
1626 drv->acc_desc = data->acc_desc;
1628 drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners,
1629 sizeof(*drv->fuse_corners),
1631 if (!drv->fuse_corners)
1634 np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
1638 drv->tcsr = syscon_node_to_regmap(np);
1640 if (IS_ERR(drv->tcsr))
1641 return PTR_ERR(drv->tcsr);
1643 drv->base = devm_platform_ioremap_resource(pdev, 0);
1644 if (IS_ERR(drv->base))
1645 return PTR_ERR(drv->base);
1647 irq = platform_get_irq(pdev, 0);
1651 drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
1652 if (IS_ERR(drv->vdd_apc))
1653 return PTR_ERR(drv->vdd_apc);
1656 * Initialize fuse corners, since it simply depends
1657 * on data in efuses.
1658 * Everything related to (virtual) corners has to be
1659 * initialized after attaching to the power domain,
1660 * since it depends on the CPU's OPP table.
1662 ret = nvmem_cell_read_variable_le_u32(dev, "cpr_fuse_revision", &cpr_rev);
1666 drv->cpr_fuses = cpr_get_fuses(drv);
1667 if (IS_ERR(drv->cpr_fuses))
1668 return PTR_ERR(drv->cpr_fuses);
1670 ret = cpr_populate_ring_osc_idx(drv);
1674 ret = cpr_fuse_corner_init(drv);
1678 mutex_init(&drv->lock);
1680 ret = devm_request_threaded_irq(dev, irq, NULL,
1682 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
1687 drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
1692 drv->pd.power_off = cpr_power_off;
1693 drv->pd.power_on = cpr_power_on;
1694 drv->pd.set_performance_state = cpr_set_performance_state;
1695 drv->pd.attach_dev = cpr_pd_attach_dev;
1697 ret = pm_genpd_init(&drv->pd, NULL, true);
1701 ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
1703 goto err_remove_genpd;
1705 platform_set_drvdata(pdev, drv);
1706 cpr_debugfs_init(drv);
1711 pm_genpd_remove(&drv->pd);
1715 static void cpr_remove(struct platform_device *pdev)
1717 struct cpr_drv *drv = platform_get_drvdata(pdev);
1719 if (cpr_is_allowed(drv)) {
1720 cpr_ctl_disable(drv);
1721 cpr_irq_set(drv, 0);
1724 of_genpd_del_provider(pdev->dev.of_node);
1725 pm_genpd_remove(&drv->pd);
1727 debugfs_remove_recursive(drv->debugfs);
1730 static const struct of_device_id cpr_match_table[] = {
1731 { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
1734 MODULE_DEVICE_TABLE(of, cpr_match_table);
1736 static struct platform_driver cpr_driver = {
1738 .remove_new = cpr_remove,
1741 .of_match_table = cpr_match_table,
1744 module_platform_driver(cpr_driver);
1746 MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
1747 MODULE_LICENSE("GPL v2");