1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
7 #ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
8 #define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
10 #include "mtk-pm-domains.h"
11 #include <dt-bindings/power/mt8195-power.h>
14 * MT8195 power domain support
17 static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
18 [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = {
19 .name = "pcie_mac_p0",
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
24 .sram_pdn_bits = GENMASK(8, 8),
25 .sram_pdn_ack_bits = GENMASK(12, 12),
28 MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
29 MT8195_TOP_AXI_PROT_EN_VDNR_SET,
30 MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
31 MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
33 MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
34 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
35 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
36 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
39 [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = {
40 .name = "pcie_mac_p1",
43 .pwr_sta_offs = 0x174,
44 .pwr_sta2nd_offs = 0x178,
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
49 MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
50 MT8195_TOP_AXI_PROT_EN_VDNR_SET,
51 MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
52 MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
54 MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
55 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
56 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
57 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
60 [MT8195_POWER_DOMAIN_PCIE_PHY] = {
64 .pwr_sta_offs = 0x174,
65 .pwr_sta2nd_offs = 0x178,
66 .caps = MTK_SCPD_ACTIVE_WAKEUP,
68 [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = {
69 .name = "ssusb_pcie_phy",
72 .pwr_sta_offs = 0x174,
73 .pwr_sta2nd_offs = 0x178,
74 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_ALWAYS_ON,
76 [MT8195_POWER_DOMAIN_CSI_RX_TOP] = {
80 .pwr_sta_offs = 0x174,
81 .pwr_sta2nd_offs = 0x178,
82 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
84 [MT8195_POWER_DOMAIN_ETHER] = {
88 .pwr_sta_offs = 0x16c,
89 .pwr_sta2nd_offs = 0x170,
90 .sram_pdn_bits = GENMASK(8, 8),
91 .sram_pdn_ack_bits = GENMASK(12, 12),
92 .caps = MTK_SCPD_ACTIVE_WAKEUP,
94 [MT8195_POWER_DOMAIN_ADSP] = {
98 .pwr_sta_offs = 0x16c,
99 .pwr_sta2nd_offs = 0x170,
100 .sram_pdn_bits = GENMASK(8, 8),
101 .sram_pdn_ack_bits = GENMASK(12, 12),
104 MT8195_TOP_AXI_PROT_EN_2_ADSP,
105 MT8195_TOP_AXI_PROT_EN_2_SET,
106 MT8195_TOP_AXI_PROT_EN_2_CLR,
107 MT8195_TOP_AXI_PROT_EN_2_STA1),
109 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
111 [MT8195_POWER_DOMAIN_AUDIO] = {
115 .pwr_sta_offs = 0x16c,
116 .pwr_sta2nd_offs = 0x170,
117 .sram_pdn_bits = GENMASK(8, 8),
118 .sram_pdn_ack_bits = GENMASK(12, 12),
121 MT8195_TOP_AXI_PROT_EN_2_AUDIO,
122 MT8195_TOP_AXI_PROT_EN_2_SET,
123 MT8195_TOP_AXI_PROT_EN_2_CLR,
124 MT8195_TOP_AXI_PROT_EN_2_STA1),
127 [MT8195_POWER_DOMAIN_MFG0] = {
131 .pwr_sta_offs = 0x174,
132 .pwr_sta2nd_offs = 0x178,
133 .sram_pdn_bits = GENMASK(8, 8),
134 .sram_pdn_ack_bits = GENMASK(12, 12),
135 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
137 [MT8195_POWER_DOMAIN_MFG1] = {
141 .pwr_sta_offs = 0x174,
142 .pwr_sta2nd_offs = 0x178,
143 .sram_pdn_bits = GENMASK(8, 8),
144 .sram_pdn_ack_bits = GENMASK(12, 12),
147 MT8195_TOP_AXI_PROT_EN_MFG1,
148 MT8195_TOP_AXI_PROT_EN_SET,
149 MT8195_TOP_AXI_PROT_EN_CLR,
150 MT8195_TOP_AXI_PROT_EN_STA1),
152 MT8195_TOP_AXI_PROT_EN_2_MFG1,
153 MT8195_TOP_AXI_PROT_EN_2_SET,
154 MT8195_TOP_AXI_PROT_EN_2_CLR,
155 MT8195_TOP_AXI_PROT_EN_2_STA1),
157 MT8195_TOP_AXI_PROT_EN_1_MFG1,
158 MT8195_TOP_AXI_PROT_EN_1_SET,
159 MT8195_TOP_AXI_PROT_EN_1_CLR,
160 MT8195_TOP_AXI_PROT_EN_1_STA1),
162 MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
163 MT8195_TOP_AXI_PROT_EN_2_SET,
164 MT8195_TOP_AXI_PROT_EN_2_CLR,
165 MT8195_TOP_AXI_PROT_EN_2_STA1),
167 MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
168 MT8195_TOP_AXI_PROT_EN_SET,
169 MT8195_TOP_AXI_PROT_EN_CLR,
170 MT8195_TOP_AXI_PROT_EN_STA1),
172 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
173 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
174 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
175 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
177 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
179 [MT8195_POWER_DOMAIN_MFG2] = {
183 .pwr_sta_offs = 0x174,
184 .pwr_sta2nd_offs = 0x178,
185 .sram_pdn_bits = GENMASK(8, 8),
186 .sram_pdn_ack_bits = GENMASK(12, 12),
187 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
189 [MT8195_POWER_DOMAIN_MFG3] = {
193 .pwr_sta_offs = 0x174,
194 .pwr_sta2nd_offs = 0x178,
195 .sram_pdn_bits = GENMASK(8, 8),
196 .sram_pdn_ack_bits = GENMASK(12, 12),
197 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
199 [MT8195_POWER_DOMAIN_MFG4] = {
203 .pwr_sta_offs = 0x174,
204 .pwr_sta2nd_offs = 0x178,
205 .sram_pdn_bits = GENMASK(8, 8),
206 .sram_pdn_ack_bits = GENMASK(12, 12),
207 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
209 [MT8195_POWER_DOMAIN_MFG5] = {
213 .pwr_sta_offs = 0x174,
214 .pwr_sta2nd_offs = 0x178,
215 .sram_pdn_bits = GENMASK(8, 8),
216 .sram_pdn_ack_bits = GENMASK(12, 12),
217 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
219 [MT8195_POWER_DOMAIN_MFG6] = {
223 .pwr_sta_offs = 0x174,
224 .pwr_sta2nd_offs = 0x178,
225 .sram_pdn_bits = GENMASK(8, 8),
226 .sram_pdn_ack_bits = GENMASK(12, 12),
227 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
229 [MT8195_POWER_DOMAIN_VPPSYS0] = {
233 .pwr_sta_offs = 0x16c,
234 .pwr_sta2nd_offs = 0x170,
235 .sram_pdn_bits = GENMASK(8, 8),
236 .sram_pdn_ack_bits = GENMASK(12, 12),
239 MT8195_TOP_AXI_PROT_EN_VPPSYS0,
240 MT8195_TOP_AXI_PROT_EN_SET,
241 MT8195_TOP_AXI_PROT_EN_CLR,
242 MT8195_TOP_AXI_PROT_EN_STA1),
244 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
245 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
246 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
247 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
249 MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
250 MT8195_TOP_AXI_PROT_EN_SET,
251 MT8195_TOP_AXI_PROT_EN_CLR,
252 MT8195_TOP_AXI_PROT_EN_STA1),
254 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
255 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
256 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
257 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
259 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
260 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
261 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
262 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
265 [MT8195_POWER_DOMAIN_VDOSYS0] = {
269 .pwr_sta_offs = 0x16c,
270 .pwr_sta2nd_offs = 0x170,
271 .sram_pdn_bits = GENMASK(8, 8),
272 .sram_pdn_ack_bits = GENMASK(12, 12),
275 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
276 MT8195_TOP_AXI_PROT_EN_MM_SET,
277 MT8195_TOP_AXI_PROT_EN_MM_CLR,
278 MT8195_TOP_AXI_PROT_EN_MM_STA1),
280 MT8195_TOP_AXI_PROT_EN_VDOSYS0,
281 MT8195_TOP_AXI_PROT_EN_SET,
282 MT8195_TOP_AXI_PROT_EN_CLR,
283 MT8195_TOP_AXI_PROT_EN_STA1),
285 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
286 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
287 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
288 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
291 [MT8195_POWER_DOMAIN_VPPSYS1] = {
295 .pwr_sta_offs = 0x16c,
296 .pwr_sta2nd_offs = 0x170,
297 .sram_pdn_bits = GENMASK(8, 8),
298 .sram_pdn_ack_bits = GENMASK(12, 12),
301 MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
302 MT8195_TOP_AXI_PROT_EN_MM_SET,
303 MT8195_TOP_AXI_PROT_EN_MM_CLR,
304 MT8195_TOP_AXI_PROT_EN_MM_STA1),
306 MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
307 MT8195_TOP_AXI_PROT_EN_MM_SET,
308 MT8195_TOP_AXI_PROT_EN_MM_CLR,
309 MT8195_TOP_AXI_PROT_EN_MM_STA1),
311 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
312 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
313 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
314 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
317 [MT8195_POWER_DOMAIN_VDOSYS1] = {
321 .pwr_sta_offs = 0x16c,
322 .pwr_sta2nd_offs = 0x170,
323 .sram_pdn_bits = GENMASK(8, 8),
324 .sram_pdn_ack_bits = GENMASK(12, 12),
327 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
328 MT8195_TOP_AXI_PROT_EN_MM_SET,
329 MT8195_TOP_AXI_PROT_EN_MM_CLR,
330 MT8195_TOP_AXI_PROT_EN_MM_STA1),
332 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
333 MT8195_TOP_AXI_PROT_EN_MM_SET,
334 MT8195_TOP_AXI_PROT_EN_MM_CLR,
335 MT8195_TOP_AXI_PROT_EN_MM_STA1),
337 MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
338 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
339 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
340 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
343 [MT8195_POWER_DOMAIN_DP_TX] = {
347 .pwr_sta_offs = 0x16c,
348 .pwr_sta2nd_offs = 0x170,
349 .sram_pdn_bits = GENMASK(8, 8),
350 .sram_pdn_ack_bits = GENMASK(12, 12),
353 MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
354 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
355 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
356 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
358 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
360 [MT8195_POWER_DOMAIN_EPD_TX] = {
364 .pwr_sta_offs = 0x16c,
365 .pwr_sta2nd_offs = 0x170,
366 .sram_pdn_bits = GENMASK(8, 8),
367 .sram_pdn_ack_bits = GENMASK(12, 12),
370 MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
371 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
372 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
373 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
375 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
377 [MT8195_POWER_DOMAIN_HDMI_TX] = {
381 .pwr_sta_offs = 0x16c,
382 .pwr_sta2nd_offs = 0x170,
383 .sram_pdn_bits = GENMASK(8, 8),
384 .sram_pdn_ack_bits = GENMASK(12, 12),
385 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
387 [MT8195_POWER_DOMAIN_WPESYS] = {
391 .pwr_sta_offs = 0x16c,
392 .pwr_sta2nd_offs = 0x170,
393 .sram_pdn_bits = GENMASK(8, 8),
394 .sram_pdn_ack_bits = GENMASK(12, 12),
397 MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
398 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
399 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
400 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
402 MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
403 MT8195_TOP_AXI_PROT_EN_MM_SET,
404 MT8195_TOP_AXI_PROT_EN_MM_CLR,
405 MT8195_TOP_AXI_PROT_EN_MM_STA1),
407 MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
408 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
409 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
410 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
413 [MT8195_POWER_DOMAIN_VDEC0] = {
417 .pwr_sta_offs = 0x16c,
418 .pwr_sta2nd_offs = 0x170,
419 .sram_pdn_bits = GENMASK(8, 8),
420 .sram_pdn_ack_bits = GENMASK(12, 12),
423 MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
424 MT8195_TOP_AXI_PROT_EN_MM_SET,
425 MT8195_TOP_AXI_PROT_EN_MM_CLR,
426 MT8195_TOP_AXI_PROT_EN_MM_STA1),
428 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
429 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
430 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
431 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
433 MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
434 MT8195_TOP_AXI_PROT_EN_MM_SET,
435 MT8195_TOP_AXI_PROT_EN_MM_CLR,
436 MT8195_TOP_AXI_PROT_EN_MM_STA1),
438 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
439 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
440 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
441 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
443 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
445 [MT8195_POWER_DOMAIN_VDEC1] = {
449 .pwr_sta_offs = 0x16c,
450 .pwr_sta2nd_offs = 0x170,
451 .sram_pdn_bits = GENMASK(8, 8),
452 .sram_pdn_ack_bits = GENMASK(12, 12),
455 MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
456 MT8195_TOP_AXI_PROT_EN_MM_SET,
457 MT8195_TOP_AXI_PROT_EN_MM_CLR,
458 MT8195_TOP_AXI_PROT_EN_MM_STA1),
460 MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
461 MT8195_TOP_AXI_PROT_EN_MM_SET,
462 MT8195_TOP_AXI_PROT_EN_MM_CLR,
463 MT8195_TOP_AXI_PROT_EN_MM_STA1),
465 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
467 [MT8195_POWER_DOMAIN_VDEC2] = {
471 .pwr_sta_offs = 0x16c,
472 .pwr_sta2nd_offs = 0x170,
473 .sram_pdn_bits = GENMASK(8, 8),
474 .sram_pdn_ack_bits = GENMASK(12, 12),
477 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
478 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
479 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
480 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
482 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
483 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
484 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
485 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
487 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
489 [MT8195_POWER_DOMAIN_VENC] = {
493 .pwr_sta_offs = 0x16c,
494 .pwr_sta2nd_offs = 0x170,
495 .sram_pdn_bits = GENMASK(8, 8),
496 .sram_pdn_ack_bits = GENMASK(12, 12),
499 MT8195_TOP_AXI_PROT_EN_MM_VENC,
500 MT8195_TOP_AXI_PROT_EN_MM_SET,
501 MT8195_TOP_AXI_PROT_EN_MM_CLR,
502 MT8195_TOP_AXI_PROT_EN_MM_STA1),
504 MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
505 MT8195_TOP_AXI_PROT_EN_MM_SET,
506 MT8195_TOP_AXI_PROT_EN_MM_CLR,
507 MT8195_TOP_AXI_PROT_EN_MM_STA1),
509 MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
510 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
511 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
512 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
514 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
516 [MT8195_POWER_DOMAIN_VENC_CORE1] = {
517 .name = "venc_core1",
520 .pwr_sta_offs = 0x16c,
521 .pwr_sta2nd_offs = 0x170,
522 .sram_pdn_bits = GENMASK(8, 8),
523 .sram_pdn_ack_bits = GENMASK(12, 12),
526 MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
527 MT8195_TOP_AXI_PROT_EN_MM_SET,
528 MT8195_TOP_AXI_PROT_EN_MM_CLR,
529 MT8195_TOP_AXI_PROT_EN_MM_STA1),
531 MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
532 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
533 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
534 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
536 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
538 [MT8195_POWER_DOMAIN_IMG] = {
542 .pwr_sta_offs = 0x16c,
543 .pwr_sta2nd_offs = 0x170,
544 .sram_pdn_bits = GENMASK(8, 8),
545 .sram_pdn_ack_bits = GENMASK(12, 12),
548 MT8195_TOP_AXI_PROT_EN_MM_IMG,
549 MT8195_TOP_AXI_PROT_EN_MM_SET,
550 MT8195_TOP_AXI_PROT_EN_MM_CLR,
551 MT8195_TOP_AXI_PROT_EN_MM_STA1),
553 MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
554 MT8195_TOP_AXI_PROT_EN_MM_SET,
555 MT8195_TOP_AXI_PROT_EN_MM_CLR,
556 MT8195_TOP_AXI_PROT_EN_MM_STA1),
558 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
560 [MT8195_POWER_DOMAIN_DIP] = {
564 .pwr_sta_offs = 0x16c,
565 .pwr_sta2nd_offs = 0x170,
566 .sram_pdn_bits = GENMASK(8, 8),
567 .sram_pdn_ack_bits = GENMASK(12, 12),
568 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
570 [MT8195_POWER_DOMAIN_IPE] = {
574 .pwr_sta_offs = 0x16c,
575 .pwr_sta2nd_offs = 0x170,
576 .sram_pdn_bits = GENMASK(8, 8),
577 .sram_pdn_ack_bits = GENMASK(12, 12),
580 MT8195_TOP_AXI_PROT_EN_MM_IPE,
581 MT8195_TOP_AXI_PROT_EN_MM_SET,
582 MT8195_TOP_AXI_PROT_EN_MM_CLR,
583 MT8195_TOP_AXI_PROT_EN_MM_STA1),
585 MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
586 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
587 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
588 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
590 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
592 [MT8195_POWER_DOMAIN_CAM] = {
596 .pwr_sta_offs = 0x16c,
597 .pwr_sta2nd_offs = 0x170,
598 .sram_pdn_bits = GENMASK(8, 8),
599 .sram_pdn_ack_bits = GENMASK(12, 12),
602 MT8195_TOP_AXI_PROT_EN_2_CAM,
603 MT8195_TOP_AXI_PROT_EN_2_SET,
604 MT8195_TOP_AXI_PROT_EN_2_CLR,
605 MT8195_TOP_AXI_PROT_EN_2_STA1),
607 MT8195_TOP_AXI_PROT_EN_MM_CAM,
608 MT8195_TOP_AXI_PROT_EN_MM_SET,
609 MT8195_TOP_AXI_PROT_EN_MM_CLR,
610 MT8195_TOP_AXI_PROT_EN_MM_STA1),
612 MT8195_TOP_AXI_PROT_EN_1_CAM,
613 MT8195_TOP_AXI_PROT_EN_1_SET,
614 MT8195_TOP_AXI_PROT_EN_1_CLR,
615 MT8195_TOP_AXI_PROT_EN_1_STA1),
617 MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
618 MT8195_TOP_AXI_PROT_EN_MM_SET,
619 MT8195_TOP_AXI_PROT_EN_MM_CLR,
620 MT8195_TOP_AXI_PROT_EN_MM_STA1),
622 MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
623 MT8195_TOP_AXI_PROT_EN_MM_2_SET,
624 MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
625 MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
627 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
629 [MT8195_POWER_DOMAIN_CAM_RAWA] = {
633 .pwr_sta_offs = 0x16c,
634 .pwr_sta2nd_offs = 0x170,
635 .sram_pdn_bits = GENMASK(8, 8),
636 .sram_pdn_ack_bits = GENMASK(12, 12),
637 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
639 [MT8195_POWER_DOMAIN_CAM_RAWB] = {
643 .pwr_sta_offs = 0x16c,
644 .pwr_sta2nd_offs = 0x170,
645 .sram_pdn_bits = GENMASK(8, 8),
646 .sram_pdn_ack_bits = GENMASK(12, 12),
647 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
649 [MT8195_POWER_DOMAIN_CAM_MRAW] = {
653 .pwr_sta_offs = 0x16c,
654 .pwr_sta2nd_offs = 0x170,
655 .sram_pdn_bits = GENMASK(8, 8),
656 .sram_pdn_ack_bits = GENMASK(12, 12),
657 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
661 static const struct scpsys_soc_data mt8195_scpsys_data = {
662 .domains_data = scpsys_domain_data_mt8195,
663 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195),
666 #endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */