drivers/pmdomain/mediatek/mt8192-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mt8192-power.h>
   8
   9 /*
  10  * MT8192 power domain support
  11  */
  12
  13 static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
  14         [MT8192_POWER_DOMAIN_AUDIO] = {
  15                 .name = "audio",
  16                 .sta_mask = BIT(21),
  17                 .ctl_offs = 0x0354,
  18                 .pwr_sta_offs = 0x016c,
  19                 .pwr_sta2nd_offs = 0x0170,
  20                 .sram_pdn_bits = GENMASK(8, 8),
  21                 .sram_pdn_ack_bits = GENMASK(12, 12),
  22                 .bp_cfg = {
  23                         BUS_PROT_WR(INFRA,
  24                                     MT8192_TOP_AXI_PROT_EN_2_AUDIO,
  25                                     MT8192_TOP_AXI_PROT_EN_2_SET,
  26                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
  27                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
  28                 },
  29         },
  30         [MT8192_POWER_DOMAIN_CONN] = {
  31                 .name = "conn",
  32                 .sta_mask = PWR_STATUS_CONN,
  33                 .ctl_offs = 0x0304,
  34                 .pwr_sta_offs = 0x016c,
  35                 .pwr_sta2nd_offs = 0x0170,
  36                 .sram_pdn_bits = 0,
  37                 .sram_pdn_ack_bits = 0,
  38                 .bp_cfg = {
  39                         BUS_PROT_WR(INFRA,
  40                                     MT8192_TOP_AXI_PROT_EN_CONN,
  41                                     MT8192_TOP_AXI_PROT_EN_SET,
  42                                     MT8192_TOP_AXI_PROT_EN_CLR,
  43                                     MT8192_TOP_AXI_PROT_EN_STA1),
  44                         BUS_PROT_WR(INFRA,
  45                                     MT8192_TOP_AXI_PROT_EN_CONN_2ND,
  46                                     MT8192_TOP_AXI_PROT_EN_SET,
  47                                     MT8192_TOP_AXI_PROT_EN_CLR,
  48                                     MT8192_TOP_AXI_PROT_EN_STA1),
  49                         BUS_PROT_WR(INFRA,
  50                                     MT8192_TOP_AXI_PROT_EN_1_CONN,
  51                                     MT8192_TOP_AXI_PROT_EN_1_SET,
  52                                     MT8192_TOP_AXI_PROT_EN_1_CLR,
  53                                     MT8192_TOP_AXI_PROT_EN_1_STA1),
  54                 },
  55                 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
  56         },
  57         [MT8192_POWER_DOMAIN_MFG0] = {
  58                 .name = "mfg0",
  59                 .sta_mask = BIT(2),
  60                 .ctl_offs = 0x0308,
  61                 .pwr_sta_offs = 0x016c,
  62                 .pwr_sta2nd_offs = 0x0170,
  63                 .sram_pdn_bits = GENMASK(8, 8),
  64                 .sram_pdn_ack_bits = GENMASK(12, 12),
  65                 .caps = MTK_SCPD_DOMAIN_SUPPLY,
  66         },
  67         [MT8192_POWER_DOMAIN_MFG1] = {
  68                 .name = "mfg1",
  69                 .sta_mask = BIT(3),
  70                 .ctl_offs = 0x030c,
  71                 .pwr_sta_offs = 0x016c,
  72                 .pwr_sta2nd_offs = 0x0170,
  73                 .sram_pdn_bits = GENMASK(8, 8),
  74                 .sram_pdn_ack_bits = GENMASK(12, 12),
  75                 .bp_cfg = {
  76                         BUS_PROT_WR(INFRA,
  77                                     MT8192_TOP_AXI_PROT_EN_1_MFG1,
  78                                     MT8192_TOP_AXI_PROT_EN_1_SET,
  79                                     MT8192_TOP_AXI_PROT_EN_1_CLR,
  80                                     MT8192_TOP_AXI_PROT_EN_1_STA1),
  81                         BUS_PROT_WR(INFRA,
  82                                     MT8192_TOP_AXI_PROT_EN_2_MFG1,
  83                                     MT8192_TOP_AXI_PROT_EN_2_SET,
  84                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
  85                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
  86                         BUS_PROT_WR(INFRA,
  87                                     MT8192_TOP_AXI_PROT_EN_MFG1,
  88                                     MT8192_TOP_AXI_PROT_EN_SET,
  89                                     MT8192_TOP_AXI_PROT_EN_CLR,
  90                                     MT8192_TOP_AXI_PROT_EN_STA1),
  91                         BUS_PROT_WR(INFRA,
  92                                     MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
  93                                     MT8192_TOP_AXI_PROT_EN_2_SET,
  94                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
  95                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
  96                 },
  97                 .caps = MTK_SCPD_DOMAIN_SUPPLY,
  98         },
  99         [MT8192_POWER_DOMAIN_MFG2] = {
 100                 .name = "mfg2",
 101                 .sta_mask = BIT(4),
 102                 .ctl_offs = 0x0310,
 103                 .pwr_sta_offs = 0x016c,
 104                 .pwr_sta2nd_offs = 0x0170,
 105                 .sram_pdn_bits = GENMASK(8, 8),
 106                 .sram_pdn_ack_bits = GENMASK(12, 12),
 107         },
 108         [MT8192_POWER_DOMAIN_MFG3] = {
 109                 .name = "mfg3",
 110                 .sta_mask = BIT(5),
 111                 .ctl_offs = 0x0314,
 112                 .pwr_sta_offs = 0x016c,
 113                 .pwr_sta2nd_offs = 0x0170,
 114                 .sram_pdn_bits = GENMASK(8, 8),
 115                 .sram_pdn_ack_bits = GENMASK(12, 12),
 116         },
 117         [MT8192_POWER_DOMAIN_MFG4] = {
 118                 .name = "mfg4",
 119                 .sta_mask = BIT(6),
 120                 .ctl_offs = 0x0318,
 121                 .pwr_sta_offs = 0x016c,
 122                 .pwr_sta2nd_offs = 0x0170,
 123                 .sram_pdn_bits = GENMASK(8, 8),
 124                 .sram_pdn_ack_bits = GENMASK(12, 12),
 125         },
 126         [MT8192_POWER_DOMAIN_MFG5] = {
 127                 .name = "mfg5",
 128                 .sta_mask = BIT(7),
 129                 .ctl_offs = 0x031c,
 130                 .pwr_sta_offs = 0x016c,
 131                 .pwr_sta2nd_offs = 0x0170,
 132                 .sram_pdn_bits = GENMASK(8, 8),
 133                 .sram_pdn_ack_bits = GENMASK(12, 12),
 134         },
 135         [MT8192_POWER_DOMAIN_MFG6] = {
 136                 .name = "mfg6",
 137                 .sta_mask = BIT(8),
 138                 .ctl_offs = 0x0320,
 139                 .pwr_sta_offs = 0x016c,
 140                 .pwr_sta2nd_offs = 0x0170,
 141                 .sram_pdn_bits = GENMASK(8, 8),
 142                 .sram_pdn_ack_bits = GENMASK(12, 12),
 143         },
 144         [MT8192_POWER_DOMAIN_DISP] = {
 145                 .name = "disp",
 146                 .sta_mask = BIT(20),
 147                 .ctl_offs = 0x0350,
 148                 .pwr_sta_offs = 0x016c,
 149                 .pwr_sta2nd_offs = 0x0170,
 150                 .sram_pdn_bits = GENMASK(8, 8),
 151                 .sram_pdn_ack_bits = GENMASK(12, 12),
 152                 .bp_cfg = {
 153                         BUS_PROT_WR_IGN(INFRA,
 154                                         MT8192_TOP_AXI_PROT_EN_MM_DISP,
 155                                         MT8192_TOP_AXI_PROT_EN_MM_SET,
 156                                         MT8192_TOP_AXI_PROT_EN_MM_CLR,
 157                                         MT8192_TOP_AXI_PROT_EN_MM_STA1),
 158                         BUS_PROT_WR_IGN(INFRA,
 159                                         MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
 160                                         MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 161                                         MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 162                                         MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 163                         BUS_PROT_WR(INFRA,
 164                                     MT8192_TOP_AXI_PROT_EN_DISP,
 165                                     MT8192_TOP_AXI_PROT_EN_SET,
 166                                     MT8192_TOP_AXI_PROT_EN_CLR,
 167                                     MT8192_TOP_AXI_PROT_EN_STA1),
 168                         BUS_PROT_WR(INFRA,
 169                                     MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
 170                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 171                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 172                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 173                         BUS_PROT_WR(INFRA,
 174                                     MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
 175                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 176                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 177                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 178                 },
 179         },
 180         [MT8192_POWER_DOMAIN_IPE] = {
 181                 .name = "ipe",
 182                 .sta_mask = BIT(14),
 183                 .ctl_offs = 0x0338,
 184                 .pwr_sta_offs = 0x016c,
 185                 .pwr_sta2nd_offs = 0x0170,
 186                 .sram_pdn_bits = GENMASK(8, 8),
 187                 .sram_pdn_ack_bits = GENMASK(12, 12),
 188                 .bp_cfg = {
 189                         BUS_PROT_WR(INFRA,
 190                                     MT8192_TOP_AXI_PROT_EN_MM_IPE,
 191                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 192                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 193                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 194                         BUS_PROT_WR(INFRA,
 195                                     MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
 196                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 197                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 198                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 199                 },
 200         },
 201         [MT8192_POWER_DOMAIN_ISP] = {
 202                 .name = "isp",
 203                 .sta_mask = BIT(12),
 204                 .ctl_offs = 0x0330,
 205                 .pwr_sta_offs = 0x016c,
 206                 .pwr_sta2nd_offs = 0x0170,
 207                 .sram_pdn_bits = GENMASK(8, 8),
 208                 .sram_pdn_ack_bits = GENMASK(12, 12),
 209                 .bp_cfg = {
 210                         BUS_PROT_WR(INFRA,
 211                                     MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
 212                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 213                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 214                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 215                         BUS_PROT_WR(INFRA,
 216                                     MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
 217                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 218                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 219                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 220                 },
 221         },
 222         [MT8192_POWER_DOMAIN_ISP2] = {
 223                 .name = "isp2",
 224                 .sta_mask = BIT(13),
 225                 .ctl_offs = 0x0334,
 226                 .pwr_sta_offs = 0x016c,
 227                 .pwr_sta2nd_offs = 0x0170,
 228                 .sram_pdn_bits = GENMASK(8, 8),
 229                 .sram_pdn_ack_bits = GENMASK(12, 12),
 230                 .bp_cfg = {
 231                         BUS_PROT_WR(INFRA,
 232                                     MT8192_TOP_AXI_PROT_EN_MM_ISP2,
 233                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 234                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 235                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 236                         BUS_PROT_WR(INFRA,
 237                                     MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
 238                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 239                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 240                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 241                 },
 242         },
 243         [MT8192_POWER_DOMAIN_MDP] = {
 244                 .name = "mdp",
 245                 .sta_mask = BIT(19),
 246                 .ctl_offs = 0x034c,
 247                 .pwr_sta_offs = 0x016c,
 248                 .pwr_sta2nd_offs = 0x0170,
 249                 .sram_pdn_bits = GENMASK(8, 8),
 250                 .sram_pdn_ack_bits = GENMASK(12, 12),
 251                 .bp_cfg = {
 252                         BUS_PROT_WR(INFRA,
 253                                     MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
 254                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 255                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 256                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 257                         BUS_PROT_WR(INFRA,
 258                                     MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
 259                                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
 260                                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
 261                                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
 262                 },
 263         },
 264         [MT8192_POWER_DOMAIN_VENC] = {
 265                 .name = "venc",
 266                 .sta_mask = BIT(17),
 267                 .ctl_offs = 0x0344,
 268                 .pwr_sta_offs = 0x016c,
 269                 .pwr_sta2nd_offs = 0x0170,
 270                 .sram_pdn_bits = GENMASK(8, 8),
 271                 .sram_pdn_ack_bits = GENMASK(12, 12),
 272                 .bp_cfg = {
 273                         BUS_PROT_WR(INFRA,
 274                                     MT8192_TOP_AXI_PROT_EN_MM_VENC,
 275                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 276                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 277                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 278                         BUS_PROT_WR(INFRA,
 279                                     MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
 280                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 281                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 282                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 283                 },
 284         },
 285         [MT8192_POWER_DOMAIN_VDEC] = {
 286                 .name = "vdec",
 287                 .sta_mask = BIT(15),
 288                 .ctl_offs = 0x033c,
 289                 .pwr_sta_offs = 0x016c,
 290                 .pwr_sta2nd_offs = 0x0170,
 291                 .sram_pdn_bits = GENMASK(8, 8),
 292                 .sram_pdn_ack_bits = GENMASK(12, 12),
 293                 .bp_cfg = {
 294                         BUS_PROT_WR(INFRA,
 295                                     MT8192_TOP_AXI_PROT_EN_MM_VDEC,
 296                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 297                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 298                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 299                         BUS_PROT_WR(INFRA,
 300                                     MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
 301                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 302                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 303                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 304                 },
 305         },
 306         [MT8192_POWER_DOMAIN_VDEC2] = {
 307                 .name = "vdec2",
 308                 .sta_mask = BIT(16),
 309                 .ctl_offs = 0x0340,
 310                 .pwr_sta_offs = 0x016c,
 311                 .pwr_sta2nd_offs = 0x0170,
 312                 .sram_pdn_bits = GENMASK(8, 8),
 313                 .sram_pdn_ack_bits = GENMASK(12, 12),
 314         },
 315         [MT8192_POWER_DOMAIN_CAM] = {
 316                 .name = "cam",
 317                 .sta_mask = BIT(23),
 318                 .ctl_offs = 0x035c,
 319                 .pwr_sta_offs = 0x016c,
 320                 .pwr_sta2nd_offs = 0x0170,
 321                 .sram_pdn_bits = GENMASK(8, 8),
 322                 .sram_pdn_ack_bits = GENMASK(12, 12),
 323                 .bp_cfg = {
 324                         BUS_PROT_WR(INFRA,
 325                                     MT8192_TOP_AXI_PROT_EN_2_CAM,
 326                                     MT8192_TOP_AXI_PROT_EN_2_SET,
 327                                     MT8192_TOP_AXI_PROT_EN_2_CLR,
 328                                     MT8192_TOP_AXI_PROT_EN_2_STA1),
 329                         BUS_PROT_WR(INFRA,
 330                                     MT8192_TOP_AXI_PROT_EN_MM_CAM,
 331                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 332                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 333                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 334                         BUS_PROT_WR(INFRA,
 335                                     MT8192_TOP_AXI_PROT_EN_1_CAM,
 336                                     MT8192_TOP_AXI_PROT_EN_1_SET,
 337                                     MT8192_TOP_AXI_PROT_EN_1_CLR,
 338                                     MT8192_TOP_AXI_PROT_EN_1_STA1),
 339                         BUS_PROT_WR(INFRA,
 340                                     MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
 341                                     MT8192_TOP_AXI_PROT_EN_MM_SET,
 342                                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
 343                                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
 344                         BUS_PROT_WR(INFRA,
 345                                     MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
 346                                     MT8192_TOP_AXI_PROT_EN_VDNR_SET,
 347                                     MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
 348                                     MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
 349                 },
 350         },
 351         [MT8192_POWER_DOMAIN_CAM_RAWA] = {
 352                 .name = "cam_rawa",
 353                 .sta_mask = BIT(24),
 354                 .ctl_offs = 0x0360,
 355                 .pwr_sta_offs = 0x016c,
 356                 .pwr_sta2nd_offs = 0x0170,
 357                 .sram_pdn_bits = GENMASK(8, 8),
 358                 .sram_pdn_ack_bits = GENMASK(12, 12),
 359         },
 360         [MT8192_POWER_DOMAIN_CAM_RAWB] = {
 361                 .name = "cam_rawb",
 362                 .sta_mask = BIT(25),
 363                 .ctl_offs = 0x0364,
 364                 .pwr_sta_offs = 0x016c,
 365                 .pwr_sta2nd_offs = 0x0170,
 366                 .sram_pdn_bits = GENMASK(8, 8),
 367                 .sram_pdn_ack_bits = GENMASK(12, 12),
 368         },
 369         [MT8192_POWER_DOMAIN_CAM_RAWC] = {
 370                 .name = "cam_rawc",
 371                 .sta_mask = BIT(26),
 372                 .ctl_offs = 0x0368,
 373                 .pwr_sta_offs = 0x016c,
 374                 .pwr_sta2nd_offs = 0x0170,
 375                 .sram_pdn_bits = GENMASK(8, 8),
 376                 .sram_pdn_ack_bits = GENMASK(12, 12),
 377         },
 378 };
 379
 380 static const struct scpsys_soc_data mt8192_scpsys_data = {
 381         .domains_data = scpsys_domain_data_mt8192,
 382         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
 383 };
 384
 385 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */