1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
7 #ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
8 #define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
10 #include "mtk-pm-domains.h"
11 #include <dt-bindings/power/mt8186-power.h>
14 * MT8186 power domain support
17 static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
18 [MT8186_POWER_DOMAIN_MFG0] = {
22 .pwr_sta_offs = 0x16C,
23 .pwr_sta2nd_offs = 0x170,
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
28 [MT8186_POWER_DOMAIN_MFG1] = {
32 .pwr_sta_offs = 0x16C,
33 .pwr_sta2nd_offs = 0x170,
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
37 BUS_PROT_WR_IGN(INFRA,
38 MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
39 MT8186_TOP_AXI_PROT_EN_1_SET,
40 MT8186_TOP_AXI_PROT_EN_1_CLR,
41 MT8186_TOP_AXI_PROT_EN_1_STA),
42 BUS_PROT_WR_IGN(INFRA,
43 MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
44 MT8186_TOP_AXI_PROT_EN_SET,
45 MT8186_TOP_AXI_PROT_EN_CLR,
46 MT8186_TOP_AXI_PROT_EN_STA),
47 BUS_PROT_WR_IGN(INFRA,
48 MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
49 MT8186_TOP_AXI_PROT_EN_SET,
50 MT8186_TOP_AXI_PROT_EN_CLR,
51 MT8186_TOP_AXI_PROT_EN_STA),
52 BUS_PROT_WR_IGN(INFRA,
53 MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
54 MT8186_TOP_AXI_PROT_EN_1_SET,
55 MT8186_TOP_AXI_PROT_EN_1_CLR,
56 MT8186_TOP_AXI_PROT_EN_1_STA),
58 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
60 [MT8186_POWER_DOMAIN_MFG2] = {
64 .pwr_sta_offs = 0x16C,
65 .pwr_sta2nd_offs = 0x170,
66 .sram_pdn_bits = BIT(8),
67 .sram_pdn_ack_bits = BIT(12),
68 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
70 [MT8186_POWER_DOMAIN_MFG3] = {
74 .pwr_sta_offs = 0x16C,
75 .pwr_sta2nd_offs = 0x170,
76 .sram_pdn_bits = BIT(8),
77 .sram_pdn_ack_bits = BIT(12),
78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
80 [MT8186_POWER_DOMAIN_SSUSB] = {
84 .pwr_sta_offs = 0x16C,
85 .pwr_sta2nd_offs = 0x170,
86 .sram_pdn_bits = BIT(8),
87 .sram_pdn_ack_bits = BIT(12),
88 .caps = MTK_SCPD_ACTIVE_WAKEUP,
90 [MT8186_POWER_DOMAIN_SSUSB_P1] = {
94 .pwr_sta_offs = 0x16C,
95 .pwr_sta2nd_offs = 0x170,
96 .sram_pdn_bits = BIT(8),
97 .sram_pdn_ack_bits = BIT(12),
98 .caps = MTK_SCPD_ACTIVE_WAKEUP,
100 [MT8186_POWER_DOMAIN_DIS] = {
104 .pwr_sta_offs = 0x16C,
105 .pwr_sta2nd_offs = 0x170,
106 .sram_pdn_bits = BIT(8),
107 .sram_pdn_ack_bits = BIT(12),
109 BUS_PROT_WR_IGN(INFRA,
110 MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
111 MT8186_TOP_AXI_PROT_EN_1_SET,
112 MT8186_TOP_AXI_PROT_EN_1_CLR,
113 MT8186_TOP_AXI_PROT_EN_1_STA),
114 BUS_PROT_WR_IGN(INFRA,
115 MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
116 MT8186_TOP_AXI_PROT_EN_SET,
117 MT8186_TOP_AXI_PROT_EN_CLR,
118 MT8186_TOP_AXI_PROT_EN_STA),
121 [MT8186_POWER_DOMAIN_IMG] = {
125 .pwr_sta_offs = 0x16C,
126 .pwr_sta2nd_offs = 0x170,
127 .sram_pdn_bits = BIT(8),
128 .sram_pdn_ack_bits = BIT(12),
130 BUS_PROT_WR_IGN(INFRA,
131 MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
132 MT8186_TOP_AXI_PROT_EN_1_SET,
133 MT8186_TOP_AXI_PROT_EN_1_CLR,
134 MT8186_TOP_AXI_PROT_EN_1_STA),
135 BUS_PROT_WR_IGN(INFRA,
136 MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
137 MT8186_TOP_AXI_PROT_EN_1_SET,
138 MT8186_TOP_AXI_PROT_EN_1_CLR,
139 MT8186_TOP_AXI_PROT_EN_1_STA),
141 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
143 [MT8186_POWER_DOMAIN_IMG2] = {
147 .pwr_sta_offs = 0x16C,
148 .pwr_sta2nd_offs = 0x170,
149 .sram_pdn_bits = BIT(8),
150 .sram_pdn_ack_bits = BIT(12),
151 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
153 [MT8186_POWER_DOMAIN_IPE] = {
157 .pwr_sta_offs = 0x16C,
158 .pwr_sta2nd_offs = 0x170,
159 .sram_pdn_bits = BIT(8),
160 .sram_pdn_ack_bits = BIT(12),
162 BUS_PROT_WR_IGN(INFRA,
163 MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
164 MT8186_TOP_AXI_PROT_EN_1_SET,
165 MT8186_TOP_AXI_PROT_EN_1_CLR,
166 MT8186_TOP_AXI_PROT_EN_1_STA),
167 BUS_PROT_WR_IGN(INFRA,
168 MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
169 MT8186_TOP_AXI_PROT_EN_1_SET,
170 MT8186_TOP_AXI_PROT_EN_1_CLR,
171 MT8186_TOP_AXI_PROT_EN_1_STA),
173 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
175 [MT8186_POWER_DOMAIN_CAM] = {
179 .pwr_sta_offs = 0x16C,
180 .pwr_sta2nd_offs = 0x170,
181 .sram_pdn_bits = BIT(8),
182 .sram_pdn_ack_bits = BIT(12),
184 BUS_PROT_WR_IGN(INFRA,
185 MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
186 MT8186_TOP_AXI_PROT_EN_1_SET,
187 MT8186_TOP_AXI_PROT_EN_1_CLR,
188 MT8186_TOP_AXI_PROT_EN_1_STA),
189 BUS_PROT_WR_IGN(INFRA,
190 MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
191 MT8186_TOP_AXI_PROT_EN_1_SET,
192 MT8186_TOP_AXI_PROT_EN_1_CLR,
193 MT8186_TOP_AXI_PROT_EN_1_STA),
195 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
197 [MT8186_POWER_DOMAIN_CAM_RAWA] = {
201 .pwr_sta_offs = 0x16C,
202 .pwr_sta2nd_offs = 0x170,
203 .sram_pdn_bits = BIT(8),
204 .sram_pdn_ack_bits = BIT(12),
205 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
207 [MT8186_POWER_DOMAIN_CAM_RAWB] = {
211 .pwr_sta_offs = 0x16C,
212 .pwr_sta2nd_offs = 0x170,
213 .sram_pdn_bits = BIT(8),
214 .sram_pdn_ack_bits = BIT(12),
215 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
217 [MT8186_POWER_DOMAIN_VENC] = {
221 .pwr_sta_offs = 0x16C,
222 .pwr_sta2nd_offs = 0x170,
223 .sram_pdn_bits = BIT(8),
224 .sram_pdn_ack_bits = BIT(12),
226 BUS_PROT_WR_IGN(INFRA,
227 MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
228 MT8186_TOP_AXI_PROT_EN_1_SET,
229 MT8186_TOP_AXI_PROT_EN_1_CLR,
230 MT8186_TOP_AXI_PROT_EN_1_STA),
231 BUS_PROT_WR_IGN(INFRA,
232 MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
233 MT8186_TOP_AXI_PROT_EN_1_SET,
234 MT8186_TOP_AXI_PROT_EN_1_CLR,
235 MT8186_TOP_AXI_PROT_EN_1_STA),
237 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
239 [MT8186_POWER_DOMAIN_VDEC] = {
243 .pwr_sta_offs = 0x16C,
244 .pwr_sta2nd_offs = 0x170,
245 .sram_pdn_bits = BIT(8),
246 .sram_pdn_ack_bits = BIT(12),
248 BUS_PROT_WR_IGN(INFRA,
249 MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
250 MT8186_TOP_AXI_PROT_EN_1_SET,
251 MT8186_TOP_AXI_PROT_EN_1_CLR,
252 MT8186_TOP_AXI_PROT_EN_1_STA),
253 BUS_PROT_WR_IGN(INFRA,
254 MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
255 MT8186_TOP_AXI_PROT_EN_1_SET,
256 MT8186_TOP_AXI_PROT_EN_1_CLR,
257 MT8186_TOP_AXI_PROT_EN_1_STA),
259 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
261 [MT8186_POWER_DOMAIN_WPE] = {
265 .pwr_sta_offs = 0x16C,
266 .pwr_sta2nd_offs = 0x170,
267 .sram_pdn_bits = BIT(8),
268 .sram_pdn_ack_bits = BIT(12),
270 BUS_PROT_WR_IGN(INFRA,
271 MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
272 MT8186_TOP_AXI_PROT_EN_2_SET,
273 MT8186_TOP_AXI_PROT_EN_2_CLR,
274 MT8186_TOP_AXI_PROT_EN_2_STA),
275 BUS_PROT_WR_IGN(INFRA,
276 MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
277 MT8186_TOP_AXI_PROT_EN_2_SET,
278 MT8186_TOP_AXI_PROT_EN_2_CLR,
279 MT8186_TOP_AXI_PROT_EN_2_STA),
281 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
283 [MT8186_POWER_DOMAIN_CONN_ON] = {
287 .pwr_sta_offs = 0x16C,
288 .pwr_sta2nd_offs = 0x170,
290 BUS_PROT_WR_IGN(INFRA,
291 MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
292 MT8186_TOP_AXI_PROT_EN_1_SET,
293 MT8186_TOP_AXI_PROT_EN_1_CLR,
294 MT8186_TOP_AXI_PROT_EN_1_STA),
295 BUS_PROT_WR_IGN(INFRA,
296 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
297 MT8186_TOP_AXI_PROT_EN_SET,
298 MT8186_TOP_AXI_PROT_EN_CLR,
299 MT8186_TOP_AXI_PROT_EN_STA),
300 BUS_PROT_WR_IGN(INFRA,
301 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
302 MT8186_TOP_AXI_PROT_EN_SET,
303 MT8186_TOP_AXI_PROT_EN_CLR,
304 MT8186_TOP_AXI_PROT_EN_STA),
305 BUS_PROT_WR_IGN(INFRA,
306 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
307 MT8186_TOP_AXI_PROT_EN_SET,
308 MT8186_TOP_AXI_PROT_EN_CLR,
309 MT8186_TOP_AXI_PROT_EN_STA),
311 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
313 [MT8186_POWER_DOMAIN_CSIRX_TOP] = {
317 .pwr_sta_offs = 0x16C,
318 .pwr_sta2nd_offs = 0x170,
319 .sram_pdn_bits = BIT(8),
320 .sram_pdn_ack_bits = BIT(12),
321 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
323 [MT8186_POWER_DOMAIN_ADSP_AO] = {
327 .pwr_sta_offs = 0x16C,
328 .pwr_sta2nd_offs = 0x170,
330 [MT8186_POWER_DOMAIN_ADSP_INFRA] = {
331 .name = "adsp_infra",
334 .pwr_sta_offs = 0x16C,
335 .pwr_sta2nd_offs = 0x170,
337 [MT8186_POWER_DOMAIN_ADSP_TOP] = {
341 .pwr_sta_offs = 0x16C,
342 .pwr_sta2nd_offs = 0x170,
343 .sram_pdn_bits = BIT(8),
344 .sram_pdn_ack_bits = BIT(12),
346 BUS_PROT_WR_IGN(INFRA,
347 MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
348 MT8186_TOP_AXI_PROT_EN_3_SET,
349 MT8186_TOP_AXI_PROT_EN_3_CLR,
350 MT8186_TOP_AXI_PROT_EN_3_STA),
351 BUS_PROT_WR_IGN(INFRA,
352 MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
353 MT8186_TOP_AXI_PROT_EN_3_SET,
354 MT8186_TOP_AXI_PROT_EN_3_CLR,
355 MT8186_TOP_AXI_PROT_EN_3_STA),
357 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
361 static const struct scpsys_soc_data mt8186_scpsys_data = {
362 .domains_data = scpsys_domain_data_mt8186,
363 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186),
366 #endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */